WO2020026802A1 - Control method and plasma processing device - Google Patents
Control method and plasma processing device Download PDFInfo
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- WO2020026802A1 WO2020026802A1 PCT/JP2019/028024 JP2019028024W WO2020026802A1 WO 2020026802 A1 WO2020026802 A1 WO 2020026802A1 JP 2019028024 W JP2019028024 W JP 2019028024W WO 2020026802 A1 WO2020026802 A1 WO 2020026802A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
- H05H1/00—Generating plasma; Handling plasma
- H05H1/24—Generating plasma
- H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
Definitions
- the present disclosure relates to a control method and a plasma processing apparatus.
- the manufacturing process of a semiconductor device includes a step of forming holes and grooves by performing plasma etching on a film to be etched formed on a semiconductor wafer using a resist as a mask.
- a parallel plate type plasma processing apparatus it has been proposed to apply a DC voltage to an upper electrode in order to enhance a sputtering effect on a wafer surface (for example, Patent Documents 1 and 2). See).
- an object of the present invention is to control ion energy and prevent a decrease in etching rate.
- a method for controlling a plasma processing apparatus including a first electrode on which an object to be processed is placed, and a second electrode facing the first electrode, the method comprising: And supplying a negative DC voltage to the second electrode, wherein the negative DC voltage takes a first voltage value in a first state. And a second state in which an absolute value takes a second voltage value smaller than the first voltage value. The second state periodically repeats, and the first state is synchronized with a high-frequency cycle of the bias power. Or a partial period in each cycle of a periodically varying parameter measured in the transmission path of the bias power, so that the second state is continuous with the first state.
- a control method is provided that includes a first control step of performing and applying the voltage.
- FIG. 1 is a diagram illustrating an example of a plasma processing apparatus according to one embodiment.
- FIG. 2 is a diagram illustrating an example of a configuration of a control unit according to one embodiment. The figure which shows the case where it controls by the phase signal of the sensor attached to the electric power feeding system which concerns on one Embodiment, or the case where it controls by the signal synchronized with the high frequency period of bias power.
- FIG. 4 is a diagram illustrating an example of supply timing of DC and the like according to LF according to an embodiment.
- FIG. 4 is a diagram illustrating an example of an electrode potential and a plasma potential according to an embodiment.
- FIG. 9 is a diagram for explaining an effect of DC supply timing according to the embodiment.
- 9 is a timing chart showing a control method according to a modified example 1-1 of the embodiment.
- 9 is a timing chart showing a control method according to a modified example 1-2 of the embodiment.
- 6 is a timing chart showing a control method according to a modified example 1-3 of the embodiment.
- 9 is a timing chart showing a control method according to a modified example 1-4 of the embodiment.
- 9 is a timing chart showing a control method according to a second modification of the embodiment.
- 9 is a timing chart showing a control method according to a modification 3-1 of the embodiment.
- 13 is a timing chart showing a control method according to a modified example 3-2 of the embodiment.
- 9 is a timing chart illustrating a control method according to Modification 4 of the embodiment.
- 14 is a timing chart showing a control method according to a fifth modification of the embodiment.
- the high frequency as the source power is also referred to as HF, and the source power is also referred to as HF power.
- a high frequency as a bias power having a frequency lower than the frequency of the source power is also referred to as LF, and the bias power is also referred to as LF power.
- FIG. 1 is a diagram illustrating an example of a plasma processing apparatus according to one embodiment.
- the plasma processing apparatus 1 is a capacitively coupled parallel plate plasma processing apparatus, and has a cylindrical processing container 10 made of, for example, aluminum whose surface is anodized.
- the processing container 10 is grounded.
- a columnar support 14 is disposed at the bottom of the processing vessel 10 via an insulating plate 12 made of ceramics or the like, and a mounting table 16 made of, for example, aluminum is provided on the support 14.
- the mounting table 16 forms a lower electrode, on which a wafer W, which is an example of an object to be processed, is mounted via an electrostatic chuck 18.
- An electrostatic chuck 18 is provided on the upper surface of the mounting table 16 for holding the wafer W by electrostatic force.
- the electrostatic chuck 18 has a structure in which an electrode 20 made of a conductive film is sandwiched between a pair of insulating layers or sheets.
- a DC power supply 22 is connected to the electrode 20.
- the DC voltage output from the DC power supply 22 is applied to the electrode 20.
- the wafer W is attracted and held on the electrostatic chuck 18 by electrostatic force such as Coulomb force generated by this.
- a conductive edge ring 24 made of, for example, silicon is disposed on the mounting table 16 and on the periphery of the wafer W.
- the edge ring 24 is also called a focus ring.
- a cylindrical inner wall member 26 made of, for example, quartz is provided on the side surfaces of the mounting table 16 and the support table 14.
- a refrigerant chamber 28 is provided inside the support base 14, for example, in an annular shape.
- a coolant having a predetermined temperature for example, cooling water is circulated and supplied from the chiller unit provided outside to the coolant chamber 28 via the pipes 30a and 30b, and the processing temperature of the wafer W on the mounting table 16 is controlled by the temperature of the coolant. Is done.
- the refrigerant is an example of a medium for temperature adjustment circulated and supplied to the pipes 30a and 30b, and the medium for temperature adjustment may not only cool the mounting table 16 and the wafer W but also heat it. .
- a heat transfer gas, for example, He gas, from the heat transfer gas supply mechanism is supplied between the upper surface of the electrostatic chuck 18 and the back surface of the wafer W via the gas supply line 32.
- An upper electrode 34 is provided above and parallel to the mounting table 16 so as to face the mounting table 16.
- a space between the upper electrode 34 and the lower electrode is a plasma processing space.
- the upper electrode 34 forms a surface facing the wafer W on the mounting table 16 and in contact with the plasma processing space, that is, an upper surface.
- the upper electrode 34 is supported on the upper part of the processing container 10 via the insulating shielding member 42.
- the upper electrode 34 constitutes a surface facing the mounting table 16 and has an electrode plate 36 having a large number of gas discharge holes 37.
- the upper electrode 34 detachably supports the electrode plate 36, and is made of a conductive material such as an anodized surface.
- an electrode support 38 made of aluminum.
- the electrode plate 36 may be formed of, for example, silicon or SiC.
- a gas diffusion chamber 40 is provided inside the electrode support 38, and a large number of gas flow holes 41 communicating with the gas discharge holes 37 extend downward from the gas diffusion chamber 40.
- the electrode support 38 is provided with a gas inlet 62 for guiding the processing gas to the gas diffusion chamber 40.
- the gas inlet 62 is connected to a gas supply pipe 64, and the gas supply pipe 64 is connected to a processing gas supply source. 66 are connected.
- the gas supply pipe 64 is provided with a mass flow controller (MFC) 68 and an opening / closing valve 70 in order from the upstream side.
- MFC mass flow controller
- a processing gas for etching is supplied from the processing gas supply source 66.
- the processing gas reaches the gas diffusion chamber 40 from the gas supply pipe 64, and is discharged from the gas discharge hole 37 into the plasma processing space through the gas flow hole 41 in a shower shape.
- the upper electrode 34 functions as a shower head for supplying the processing gas.
- variable DC power supply 50 is connected to the upper electrode 34, and a DC voltage from the variable DC power supply 50 is applied to the upper electrode 34.
- the control of the polarity and current / voltage of the variable DC power supply 50 and the electronic switch for turning on / off the current and voltage are controlled by the control unit 200.
- a first high frequency power supply 48 is connected to the mounting table 16 via a power supply rod 47 and a matching unit 46.
- the first high frequency power supply 48 applies LF power to the mounting table 16. Thereby, ions are drawn into the wafer W on the mounting table 16.
- the first high-frequency power supply 48 outputs high-frequency power having a frequency in the range of 200 kHz to 13.56 MHz.
- the matching unit 46 matches the internal impedance of the first high-frequency power supply 48 with the load impedance.
- 2A second high frequency power supply 90 is connected to the mounting table 16 via a power supply rod 89 and a matching unit 88.
- the second high frequency power supply 90 applies HF power to the mounting table 16.
- the frequency of the HF is higher than the frequency of the LF, and HF power of a frequency of 13.56 MHz or higher is output from the second high frequency power supply 90.
- LF power of 400 kHz and HF power of 100 MHz may be output.
- the matching unit 88 matches the internal impedance of the second high-frequency power supply 90 with the load impedance.
- a filter 94 for passing a predetermined high frequency to the ground may be connected to the mounting table 16.
- the HF power supplied from the second high frequency power supply 90 may be applied to the upper electrode 34.
- An exhaust port 80 is provided at the bottom of the processing container 10, and an exhaust device 84 is connected to the exhaust port 80 via an exhaust pipe 82.
- the exhaust device 84 has a vacuum pump such as a turbo-molecular pump, and can reduce the pressure inside the processing container 10 to a desired degree of vacuum.
- a loading / unloading port 85 for the wafer W is provided on a side wall of the processing container 10, and the loading / unloading port 85 can be opened and closed by a gate valve 86.
- a deposition shield 11 for preventing an etching by-product (depot) from adhering to the processing container 10 along the inner wall of the processing container 10 is provided detachably. That is, the deposition shield 11 constitutes the wall of the processing container.
- the deposit shield 11 is also provided on the outer periphery of the inner wall member 26.
- An exhaust plate 83 is provided between the deposition shield 11 on the wall side of the processing container at the bottom of the processing container 10 and the deposition shield 11 on the inner wall member 26 side.
- an aluminum material coated with ceramics such as Y 2 O 3 can be used as the deposition shield 11 and the exhaust plate 83.
- the gate valve 86 is opened, and the wafer W to be etched is loaded into the processing chamber 10 through the loading / unloading port 85, and the mounting table is set. 16 is placed. Then, a processing gas for etching is supplied from the processing gas supply source 66 to the gas diffusion chamber 40 at a predetermined flow rate, and is supplied into the processing container 10 through the gas flow holes 41 and the gas discharge holes 37. Further, the inside of the processing container 10 is exhausted by the exhaust device 84, and the pressure therein is set to a set value within a range of, for example, 0.1 to 150 Pa.
- the processing gas various conventionally used gases can be adopted, and for example, a gas containing a halogen element such as a C 4 F 8 gas can be suitably used. Further, another gas such as Ar gas or O 2 gas may be contained.
- HF power is applied to the mounting table 16 from the second high-frequency power supply 90.
- LF power is applied to the mounting table 16 from the first high frequency power supply 48.
- a DC voltage is applied to the upper electrode 34 from the variable DC power supply 50.
- a DC voltage is applied from the DC power supply 22 to the electrode 20, and the wafer W is held on the mounting table 16.
- the processing gas discharged from the gas discharge holes 37 of the upper electrode 34 is dissociated and ionized mainly by HF electric power to generate plasma.
- the processing surface of the wafer W is etched by radicals and ions in the plasma.
- ions in the plasma are controlled, and etching of holes with a high aspect ratio can be performed, and the plasma control margin can be widened.
- the plasma processing apparatus 1 is provided with a control unit 200 for controlling the operation of the entire apparatus.
- the control unit 200 performs desired plasma processing such as etching in accordance with a recipe stored in a memory such as a ROM (Read Only Memory) and a RAM (Random Access Memory).
- the recipe includes process time, pressure (gas exhaust), high-frequency power and voltage, various gas flow rates, temperature inside the processing vessel (upper electrode temperature, side wall temperature of the processing vessel, temperature of wafer W, which are control information of the apparatus with respect to the process conditions). , The temperature of the electrostatic chuck, etc.), the temperature of the refrigerant output from the chiller, and the like.
- these programs and recipes indicating processing conditions may be stored in a hard disk or a semiconductor memory.
- the recipe may be set at a predetermined position in a state where the recipe is stored in a portable computer-readable storage medium such as a CD-ROM or a DVD, and may be read.
- control unit 200 measures the negative DC voltage output from the variable DC power supply 50 in a partial period in each cycle of the signal synchronized with the high-frequency cycle of the bias power, or in the transmission path of the bias power.
- a voltage, a current, an electromagnetic field, a light emission cycle of the generated plasma or a change in the sheath thickness of the plasma on the wafer W (lower electrode) is applied during a partial period within each cycle, and a negative DC voltage is alternately turned on and off. May be controlled to be repeated.
- a change in the voltage, current, electromagnetic field, emission cycle of the generated plasma, or change in the sheath thickness of the plasma on the wafer W (lower electrode), which is measured in the transmission path of the bias power is also referred to as a “parameter that varies periodically”.
- the HF voltage output from the second high frequency power supply 90 is applied to a partial period within each cycle of a signal synchronized with the high frequency cycle of the bias power or a partial period within each cycle of a periodically varying parameter.
- HF voltage may be controlled to be alternately turned on and off. Thereby, ion energy can be controlled and a decrease in the etching rate can be prevented.
- the transmission path of the bias power means the first high-frequency power supply 48 ⁇ the matching unit 46 ⁇ the power supply rod 47 ⁇ the mounting table 16 ⁇ the plasma ⁇ the upper electrode 34 ⁇ (ground).
- the voltage, current, and electromagnetic field measured on the transmission path of the bias power are generated by the upper electrode 34 and parts from the first high-frequency power supply 48 to the inside of the matching box 46 and from the power supply rod 47 to the mounting table 16.
- the negative DC voltage output from the variable DC power supply 50 periodically repeats a first state and a second state, which will be described later, and the first state corresponds to each of signals synchronized with the high-frequency cycle of the bias power. It is applied during a partial period within a cycle or a partial period within each cycle of a periodically varying parameter, and is controlled so as to apply the second state continuously with the first state.
- the periodically varying parameter is transmitted from the mounting table 16 to the power supply rod 47. It is preferably any one of the voltage, current, or electromagnetic field measured at any member up to the inside of the matching device connected via.
- a voltage sensor, a current sensor, or a BZ sensor (a sensor that measures an induced magnetic field) is installed near any part of the bias power transmission path.
- a method of measuring the voltage, current, or induced magnetic field of each part is given as an example.
- FIG. 2A shows the voltage sensor 300, the present invention is not limited to this, and may be a current sensor or a BZ sensor. Further, it is preferable that the arrangement of the respective sensors is connected to the power supply rod 47, but the arrangement is not limited to this.
- a signal from a sensor such as the voltage sensor 300 is input to the signal generation circuit 102 of the control unit 200, for example.
- FIG. 2B (a) shows an example in which a negative DC voltage is applied to a partial period in each cycle of a periodically varying parameter measured on a bias power transmission path.
- the processor 100 outputs any one of the HF voltage or current, the LF voltage or current, the HF phase signal or the LF phase signal from a sensor such as a VI probe attached to the bias power transmission path. Is input as an example of a parameter that fluctuates periodically.
- the processor 100 applies the negative DC voltage output from the variable DC power supply 50 to a partial period in each cycle of the input periodically varying parameter.
- the processor 100 may generate a signal synchronized with the high-frequency cycle of the bias power output from the first high-frequency power supply 48 without being based on the signal from the sensor. In this case, it is possible to omit the step of measuring the state of the parameter that periodically changes in the transmission path of the bias power.
- the processor 100 inputs an LF phase signal (small power waveform) or a signal relating to information of bias power from the first high frequency power supply 48, and based on the input signal, a high frequency cycle of bias power.
- Generate a signal synchronized with Processor 100 outputs the generated signal to variable DC power supply 50.
- the variable DC power supply 50 applies a negative DC voltage during a partial period within each cycle of this signal.
- the generated signal includes the modulation information of the source power, and the processor 100 may output the generated signal to the second high frequency power supply 90.
- the second high frequency power supply 90 applies source power during a partial period within each cycle of this signal.
- the processor 100 may generate a signal synchronized with the high-frequency cycle of the bias power without being based on the signal from the first high-frequency power supply 48.
- the processor 100 generates a signal having a period indicated by LF in FIG. 3, for example, and generates an on / off signal indicated by DC in FIG. 3, for example, in synchronization with the signal.
- the processor 100 outputs the generated signal to the first high-frequency power supply 48 and the variable DC power supply 50.
- the first high frequency power supply 48 outputs bias power based on this signal.
- the variable DC power supply 50 applies a negative DC voltage during a partial period within each cycle of this signal.
- the processor 100 may generate an on / off signal indicated by HF in FIG. 3 in synchronization with the generated signal having the cycle indicated by LF in FIG.
- the processor 100 outputs the generated signal to the second high frequency power supply 90.
- the second high frequency power supply 90 applies source power during a partial period within each cycle of this signal.
- the light emission period of the plasma and the change period of the sheath thickness of the plasma on the wafer W may be used as the index.
- the light emission period of the plasma can be detected by a photodiode, a photomicrosensor, or the like.
- a shutter is opened at an interval of nanoseconds (for example, 10 to 250 nsec) using an ICCD camera or the like, whereby a change in the sheath thickness can be measured.
- the mounting table 16 is an example of a first electrode on which the wafer W is mounted.
- the upper electrode is an example of a second electrode facing the first electrode.
- the first high-frequency power supply 48 is an example of a bias power supply that supplies LF power (bias power) to the first electrode.
- the second high-frequency power supply 90 is an example of a source power supply that supplies HF power (source power) having a higher frequency than LF power to the first electrode or the second electrode.
- the variable DC power supply 50 is an example of a DC power supply that supplies a DC voltage to the second electrode.
- the control unit 200 is an example of a control unit that controls a bias power supply, a source power supply, and a DC power supply.
- the potential of the lower electrode (mounting table 16) to which the bias power is applied is also referred to as an electrode potential.
- the control unit 200 includes a processor 100, a signal generation circuit 102, directional couplers 105 and 108, a power meter 111, and an oscilloscope 112. However, the power meter 111, the oscilloscope 112, and the directional coupler 108 need not be provided.
- a directional coupler 105 is connected between the first high-frequency power supply 48 and the matching box 46 to the power supply line of the first high-frequency power supply 48.
- a directional coupler 108 is connected to the power supply line of the second high-frequency power supply 90 between the second high-frequency power supply 90 and the matching unit 88.
- the -directional coupler 105 supplies a part of the LF traveling wave to the oscilloscope 112. Further, the directional coupler 108 gives a part of the traveling wave of the HF to the oscilloscope 112.
- the LF frequency displayed on the oscilloscope 112 is, for example, 400 kHz, and the HF frequency is, for example, 100 MHz.
- the oscilloscope 112 can observe the waveform of the LF traveling wave and the waveform of the HF traveling wave.
- the -directional coupler 108 supplies a part of the HF traveling wave to the power meter 111.
- the power meter 111 measures the amount of power of the HF traveling wave.
- the -directional coupler 105 supplies a part of the LF traveling wave to the processor 100.
- the processor 100 creates a DC synchronization signal synchronized with the traveling wave of the LF.
- the processor 100 may generate the DC synchronization signal in synchronization with the positive timing of the traveling wave of the LF.
- the LF waveform detected using a sensor such as a VI sensor may be provided to the processor 100.
- the processor 100 gives the created synchronization signal to the signal generation circuit 102.
- the signal generation circuit 102 generates a control signal synchronized with the LF traveling wave from the applied synchronization signal, and supplies the control signal to the variable DC power supply 50 and the first high-frequency power supply 48.
- the directional coupler 105 extracts a part of the LF voltage output from the first high frequency power supply 48 as a waveform and inputs the waveform to the processor 100.
- the processor 100 may directly input a part of the power of the LF or the like from the first high-frequency power supply 48.
- the processor 100 generates an ON signal having an arbitrary delay and an arbitrary width in synchronization with the input waveform signal or from the input signal, and transmits the ON signal to the signal generation circuit 102.
- the signal generation circuit 102 sends a command signal to the variable DC power supply 50 to generate a DC voltage during the ON signal.
- a command signal a control signal for generating a DC voltage during the ON signal or the ON signal itself is used depending on the input form of the variable DC power supply 50.
- the signal generation circuit 102 may send a command signal to the second high frequency power supply 90 to generate HF power during the ON signal.
- the signal from the directional coupler 105 is not used, and the signal generation circuit 102 outputs the LF output from the first high frequency power supply 48. May be extracted as a waveform, and an ON signal having an arbitrary delay and an arbitrary width may be created from the signal of the waveform.
- the signal generation circuit 102 transmits the waveform signal and the ON signal to the variable DC power supply 50. Similarly, the signal generation circuit 102 may transmit the waveform signal and the ON signal to the second high-frequency power supply 90.
- control signal generation method is an example, and the present invention is not limited to this.
- a negative DC voltage is applied to a partial period within each cycle of a signal synchronized with the high frequency cycle of the bias power or a partial period within each cycle of a given periodically varying parameter, and the DC voltage is turned on.
- a control signal for controlling so that the control signal is turned on and off can be generated, not only the circuit of the control unit 200 shown in FIGS. 2A and 2B but also other hardware or software can be used.
- the amplifier of the first high-frequency power supply 48 amplifies the amplitude (AM: amplitude modulation) of the LF modulation signal of 400 kHz and supplies it to the lower electrode.
- the amplifier of the second high frequency power supply 90 amplifies the amplitude of the HF modulation signal of 100 MHz and supplies it to the lower electrode.
- the signal generation circuit 102 applies a negative DC voltage during a partial period within each cycle of the periodically varying parameter measured on the bias power transmission path from the given synchronization signal, and turns on the negative DC voltage.
- a control signal may be generated for controlling so as to alternately repeat the operation and the OFF state, and the control signal may be supplied to the variable DC power supply 50.
- the signal generation circuit 102 applies a negative DC voltage during a partial period within each cycle of the signal synchronized with the high-frequency cycle of the bias power, and performs control so that ON and OFF of the negative DC voltage are alternately repeated.
- a control signal may be generated and supplied to the variable DC power supply 50. Instead of turning on and off the negative DC voltage, a control signal for controlling High and Low to be alternately repeated may be generated and supplied to the variable DC power supply 50.
- the signal generation circuit 102 applies HF power during a partial period within each cycle of the periodically varying parameter measured on the bias power transmission path from the given synchronization signal, and turns on the HF power.
- a control signal for performing control so that the power supply is repeatedly turned off may be generated and supplied to the second high-frequency power supply 90.
- the signal generation circuit 102 applies HF power during a partial period within each cycle of the signal synchronized with the high-frequency cycle of the bias power, and generates a control signal for controlling the HF power to be turned on and off alternately. Alternatively, it may be supplied to the variable DC power supply 50.
- a control signal may be generated to control the HF power so that High and Low are alternately repeated instead of turning on and off the HF power, and may be provided to the second high frequency power supply 90.
- FIG. 3 is a diagram showing an example of DC and HF voltages applied according to LF.
- LF positive
- the DC voltage is applied with a negative value and the HF voltage is off
- LF negative
- the HF voltage is applied with a positive value and the DC voltage is off.
- the electrode potential is determined by the voltage of LF.
- the processor 100 may generate a synchronization signal for controlling the DC voltage and the HF power in a time period including a timing when the electrode potential is positive.
- the processor 100 is not limited to this, and may generate a synchronization signal that controls the DC voltage and the HF power in a short time including the timing when the electrode potential becomes the deepest negative and at a timing when the electrode potential includes the negative. Good.
- FIG. 4 is a diagram showing an example of the potential of the upper electrode and the lower electrode and the plasma potential according to the present embodiment.
- FIG. 5 is a diagram for explaining the DC voltage supply timing and its effects according to the present embodiment.
- the LF current may be controlled instead of the LF voltage.
- the DC current may be controlled instead of the DC voltage.
- the electrode potential (wafer potential, lower electrode potential) when the LF voltage is negative becomes deeper than the electrode potential when the LF voltage is positive due to the so-called self-bias voltage Vdc.
- FIG. 4A shows the potential of each electrode and the plasma potential when LF power and HF power are supplied to the lower electrode.
- FIG. 4B shows the potential of each electrode and the plasma potential when the LF power and the HF power are supplied to the lower electrode and the negative DC voltage is further supplied to the upper electrode 34.
- the potential indicated by A in FIG. 4A is a plasma potential.
- the plasma potential is slightly higher than the highest potential in the processing container 10 as shown by the Plasma potential and the electrode potential in FIG. Therefore, when the electrode potential is positive, the plasma potential is slightly higher than the LF voltage, and when the LF voltage is negative, if the potential of the wall of the processing vessel 10 is 0, the plasma potential is slightly higher than the wall potential (0). growing.
- the speed of the electrons becomes 0 or close to 0 when or before the electrons reach the wafer W.
- the electrons adhere to the top surface of the hole or the side surface of the hole and do not reach the bottom of the hole.
- the ions are also drawn into the upper surface of the hole where the electrons are present or the side surface of the hole, and do not reach the bottom of the hole.
- Electrons whose velocity becomes 0 before reaching the wafer are accelerated in the opposite direction toward the plasma side by the plasma potential. That is, when a negative DC voltage is applied to the upper electrode 34, the range of the potential of the lower electrode where electrons accelerated by the sheath on the upper electrode 34 side can enter the wafer is the negative DC voltage shown in FIG.
- the range of the potential E is the same as the voltage, and in the range of F, the speed of the electrons becomes 0, and the electrons cannot reach the wafer. If the electrons do not reach the bottom of the hole, the bottom of the hole cannot be negatively charged up. As a result, positive charge-up at the bottom of the hole cannot be canceled by ions.
- the electrode potential when the electrode potential is positive, a negative DC voltage is applied to the upper electrode.
- a negative DC voltage is applied to the upper electrode.
- electrons are accelerated most, and since the sheath electric field on the wafer is low, deceleration at the sheath can be minimized and electrons can efficiently reach the bottom of the hole.
- ions can be drawn into the bottom of the hole, the perpendicularity of etching can be increased, and a decrease in etching rate can be prevented.
- a DC voltage of -1000 V is applied to the upper electrode 34 as a negative DC voltage indicated by D in FIG. 4B.
- the electrons are accelerated at a voltage of -1000 V and further accelerated by a plasma potential of about 10 V to 30 V.
- the accelerated electrons move in the plasma in the plasma processing space at a constant speed while keeping the straightness, then decelerate by the sheath on the wafer W, and are driven almost perpendicularly to the hole bottom of the film to be etched on the wafer. .
- the hole bottom is charged up negatively.
- ions having a larger mass than the electrons reach the bottom of the hole with a delay. This cancels the charge at the bottom of the hole.
- FIG. 5A shows an example of the supply timing of DC voltage and the operation of electrons and ions according to the comparative example.
- FIG. 5B shows an example of the supply timing of the DC voltage and the operation of electrons and ions according to the present embodiment.
- a DC voltage is continuously applied regardless of whether the electrode potential is positive or negative.
- the electrode potential is positive
- the DC voltage is applied, and when the electrode potential is negative, the application of the DC voltage is stopped.
- the LF voltage and the HF voltage are turned on / off at about 10 kHz and applied in a pulse form, and the DC voltage of about -1000 V is applied at the timing of turning off the pulses of the LF voltage and the HF voltage. Is applied to accelerate the electrons in the after-glow discharge, and bombard the electrons at the bottom of the hole, thereby facilitating the subsequent incidence of ions at the bottom of the hole.
- the number of electrons that are left during the afterglow discharge after the application of the HF voltage is stopped rapidly decreases, so that the number of electrons accelerated by a DC voltage of about ⁇ 1000 V decreases, and In some cases, the effect of driving into the hole bottom may not be sufficiently exhibited.
- a DC voltage is applied to the upper electrode at a timing when the electrode potential is positive, the acceleration of the electrons is increased, and the fastest electrons are made to enter the hole without decelerating as much as possible.
- electrons can reach the bottom of the hole and follow ions can be drawn into the bottom of the hole.
- the application of the DC voltage to the upper electrode is stopped when the electrode potential is negative.
- the number of electrons adhering to the surface or side surface of the hole can be reduced, so that the occurrence of bowing can be avoided and the etched shape can be made vertical.
- the ion energy can be controlled in synchronization with the change in the thickness of the sheath.
- ions can be attracted to the bottom of the hole and a decrease in the etching rate can be prevented.
- the etching shape can be made vertical.
- the frequency of the LF decreases, when the voltage of the LF having the same power is introduced from the first high frequency power supply 48, the effect of increasing the ion energy is higher than the effect of increasing the plasma density. Get higher. Thereby, ions can be drawn to the bottom of the hole and the perpendicularity of the etching can be improved. Therefore, in the control method according to the present embodiment, it is preferable that the frequency of the LF be 400 kHz or less. As a result, ions can be more efficiently drawn to the bottom of the hole, a decrease in the etching rate can be prevented, and the etching shape can be made vertical.
- the DC voltage is controlled to a negative value (hereinafter, also referred to as “ON”) when the electrode potential is positive, but the present invention is not limited to this, and the DC voltage is controlled to be ON during a time period including the positive timing. Alternatively, it may be turned on at a timing when the electrode potential includes a positive peak. Further, instead of turning on and off the DC voltage, the DC voltage may be controlled so that the absolute value becomes a high value and a low value with a negative value. In this case, instead of turning on the DC voltage, the DC voltage is controlled to be a negative value and the absolute value is set to be higher than Low, and instead of turning off the DC voltage, the DC voltage is set to a negative value. Control may be performed so as to be Low. At this time, it is preferable that the DC voltage is controlled to be High when the electrode potential is positive. However, the present invention is not limited to this, and control may be performed so that the electrode potential becomes High in a time zone including a positive timing.
- the DC voltage may be not only a rectangular wave whose electrode potential coincides with a positive timing but also a substantially rectangular wave including at least one of a rising slow-down and a falling slow-down.
- the DC voltage may be applied at least at a timing when the electrode potential is shifted by a predetermined time from the positive timing or at a timing when the electrode potential is shifted by a predetermined time.
- the waveform of the electrode potential may be distorted depending on the frequency of LF, gas type, and pressure.
- the DC voltage may be adjusted in the width of the application time so that the electrode potential is longer or shorter by a predetermined time than the positive timing.
- the power of the HF may be turned on during a time period including the timing when the electrode potential is positive. At this time, the power of the HF may be turned on when the electrode potential matches the positive timing, and the supply of the HF power may be turned off when the electrode potential matches the negative timing. Both the DC voltage and the HF power may be applied during a partial period of each cycle of the LF power, and both the DC voltage and the HF power may be turned off during the remaining period.
- the DC voltage and the power of the HF are controlled to be negative and high, and the DC voltage is turned off instead of turning off the DC voltage and the power of the HF.
- the power of the HF may be controlled to be negative values and low.
- the control method of the parallel plate type plasma processing apparatus 1 includes a step of supplying bias power to the lower electrode on which the wafer W is mounted, and a step of supplying a negative DC voltage to the upper electrode. And supplying to In the control method, as shown in FIG. 3 and FIG. 5 (b), the negative DC voltage has a first state in which it takes a first voltage value and a negative DC voltage in which a negative DC voltage has a smaller absolute value than the first voltage value. A second state having a voltage value of 2 and the first state is measured in a sub-period within each cycle of the signal synchronized with the high-frequency cycle of the bias power, or in a transmission path of the bias power.
- the periodically fluctuating parameter may be a voltage, a current, an electromagnetic field, a change in the emission of the generated plasma or a change in the sheath thickness of the plasma on the wafer.
- the state where the DC voltage is turned on (DC on, DC is applied negatively) is an example of the first state.
- the state where the DC voltage is off (DC off, DC is 0) is an example of the second state.
- the first state and the second state are repeated.
- a negative value and the absolute value may be controlled to High / Low.
- the state where the DC voltage is a negative value and the absolute value is controlled to High is an example of the first state.
- the state in which the DC voltage is a negative value and the absolute value is controlled to be lower than High is an example of the second state.
- the DC voltage in the second state may be 0, or may be a negative value whose absolute value is smaller than High.
- Modifications 1-1 to 1-4 Next, a control method of the plasma processing apparatus 1 according to modified examples 1-1 to 1-4 of the embodiment will be described. In the modified examples 1-1 to 1-4, control for intermittently stopping one or both of the bias power and the DC voltage is performed. 6A to 6D are timing charts illustrating control methods according to modified examples 1-1 to 1-4 of the embodiment.
- the DC voltage is independent of the period of a signal that is synchronized with the period of a periodically varying parameter or the high frequency of the bias power, which is shown by an example of the LF voltage.
- the LF voltage is applied in the same cycle in the first control step and the second control step.
- the DC voltage alternates between the first state and the second state at least once in the first control step, and is intermittently stopped in the second control step between the first control steps.
- the frequency of the LF may be, for example, 0.1 Hz to 100 kHz.
- An example of the third state is that the DC voltage synchronized with the LF voltage in the first control step at the positive timing takes the first state.
- the state of the DC voltage independent of the cycle of the LF voltage in the second control step is an example of a fourth state different from the third state.
- the control method according to the modified example 1-2 of FIG. 6B includes, in addition to the same first control step as the modified example 1-1, intermittently changing the bias power (LF voltage) at a cycle independent of the cycle of the DC voltage.
- a third control step of stopping is included.
- the state of the bias power in the third control step is an example of the fourth state.
- the first control step and the third control step are repeatedly executed.
- the DC voltage in the third control step is such that the first state and the second state are repeated in the same cycle as in the first control step.
- the control method according to the modified example 1-3 in FIG. 6C includes, in addition to the same first control step as the modified example 1-1, the DC control in the second control step of the modified example 1-1 and the control method of the modified example 1-2.
- the LF control in the third control step is performed. That is, the state where both the DC voltage and the bias power are intermittently stopped in the modified example 1-3 is an example of the fourth state.
- the cycle in which the bias power is intermittently stopped and the cycle in which the DC voltage is intermittently stopped may be synchronized.
- the cycle of intermittently stopping the DC and the bias power may be the same as shown in FIG. 6C, or the DC may be shifted behind the bias power as shown in FIG. 6D. , DC may be shifted before the bias power.
- the DC voltage in the third state, is turned on at a part of the timing when the bias power is positive, but the present invention is not limited to this. Further, instead of periodically turning on / off the DC voltage, the DC voltage may be controlled to be a negative value and the absolute value periodically becomes High / Low.
- FIG. 7 is a timing chart illustrating a control method according to Modification 2 of the embodiment.
- pulse-like power (hereinafter, also referred to as “LF pulse”) corresponding to the peak of the LF voltage is applied to the mounting table 16.
- a positive value of the LF pulse corresponds to a positive peak of the voltage of the LF
- a negative value of the LF pulse corresponds to a negative peak of the voltage of the LF.
- the negative DC voltage periodically repeats the first state and the second state, and applies the first state to a partial period in each cycle of the LF pulse. Then, the second state is applied continuously to the first state. This also controls the ion energy and can prevent a decrease in the etching rate.
- the DC voltage is negatively turned on or controlled to be a negative value and the absolute value becomes High during a part or all of the period when the LF pulse is positive.
- the DC voltage may be controlled to be off or a negative value and the absolute value thereof may be low in all or a part. According to this, since the LF pulse is binarized and the DC voltage is binarized and controlled in accordance with the binarization, the control becomes easy.
- FIG. 8A is a timing chart illustrating a control method according to Modification 3-1 of the embodiment.
- FIG. 8B is a timing chart illustrating a control method according to Modification 3-2 of the embodiment.
- the first state of the DC voltage is a signal that synchronizes with a periodically changing parameter, such as an electrode potential, or a high-frequency cycle of bias power. Is applied during a partial period including a positive value, and the second state is applied continuously to the first state.
- the first state of the DC voltage is a negative value and has two or more voltage values stepwise.
- the first state of the DC voltage is a negative value and smoothly has two or more voltage values.
- the first state of the DC voltage may be applied during a partial period in which the electrode potential includes a negative value.
- by controlling the DC voltage in the first state to a plurality of values, it is possible to more accurately control the ion energy and prevent a decrease in the etching rate.
- the first state of the DC voltage takes a pulse-like voltage value that repeats two or more voltage values.
- the first state of the DC voltage repeats a negative voltage value and a zero voltage value.
- the present invention is not limited to this, and two or more voltage values may be repeated, such as repeating three voltage values.
- the bias power may be a sine waveform or a pulse waveform power, or may be a tailored waveform power. That is, the bias voltage or current may be a sine waveform, an LF pulse waveform, or a tailored waveform shown in FIG. In the tailored waveform, the bias power may be modulated when DC shown in FIG. 10 is in the second state, or the bias power may be modulated when DC is in the first state.
- the DC waveform may be the tailored waveform shown in FIG. 10 in addition to the waveforms shown in FIGS. 8A, 8B, and 9. .
- the control of the control unit 200 will be additionally described.
- the control unit 200 may supply the source power during the first state. That is, the source power has a first state and a second state having different voltage values from each other, and the source state has a portion within each cycle of a signal synchronized with the high frequency cycle of the bias power.
- the second state may be applied continuously to the first state during a period or a partial period within each period of a periodically varying parameter measured in the bias power transmission path.
- the control unit 200 may supply at least one of the source power and the negative DC voltage when the electrode potential is positive.
- control method and the plasma processing apparatus have been described in the above embodiments.
- control method and the plasma processing apparatus according to the present disclosure are not limited to the above embodiments, and various modifications and improvements may be made within the scope of the present disclosure. Is possible.
- the matters described in the above embodiments can be combined within a range that does not contradict.
- one embodiment and a plurality of modified examples can be combined within a range not inconsistent.
- the plasma processing apparatus is Capacitively Coupled Plasma (CCP), Inductively Coupled Plasma (ICP), Radial Line Slot Slot Antenna (RLSA), Electron Cyclotron Resonance Plasma (ECR), any type of Helicon Wave Plasma (HWP) Applicable.
- CCP Capacitively Coupled Plasma
- ICP Inductively Coupled Plasma
- RLSA Radial Line Slot Slot Antenna
- ECR Electron Cyclotron Resonance Plasma
- HWP Helicon Wave Plasma Applicable.
- the wafer W has been described as an example of the object to be processed.
- the substrate is not limited to this, and may be various substrates used for LCD (Liquid Crystal Display), FPD (Flat Panel Display), a CD substrate, a printed substrate, or the like.
- Processing container 16 Mounting table (lower electrode) 34 upper electrode 47 power supply rod 46 matching device 48 first high frequency power supply 50 variable DC power supply 66 processing gas supply source 84 exhaust device 88 matching device 89 power supply rod 90 second high frequency power supply 91 ... GND block 100 ... processor 102 ... signal generation circuit 200 ... control unit
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Abstract
Provided is a control method for a plasma processing device having: a first electrode on which a to-be-processed body is placed; and a second electrode that opposes the first electrode. This control method has a step for supplying bias power to the first electrode and a step for supplying a negative direct-current voltage to the second electrode, the negative direct-current voltage periodically repeating a first state of having a first voltage value and a second state of having a lower absolute value than the first voltage value, and includes a first control step for applying the first state in a partial period in each of cycles of a signal synchronized with a high-frequency cycle of the bias power or a partial period in each of cycles of a parameter that varies periodically and that is measured in a transmission route of the bias power, and applying the second state in continuity with the first state.
Description
本開示は、制御方法及びプラズマ処理装置に関する。
The present disclosure relates to a control method and a plasma processing apparatus.
半導体デバイスの製造プロセスには、半導体ウェハに形成されたエッチング対象膜にレジストをマスクとしてプラズマエッチングを行い、ホールや溝を形成する工程がある。平行平板型のプラズマ処理装置を使用してプラズマエッチングを行う際、ウェハ表面へのスパッタ効果を高めるために、上部電極に直流電圧を印加することが提案されている(例えば、特許文献1、2を参照)。
製造 The manufacturing process of a semiconductor device includes a step of forming holes and grooves by performing plasma etching on a film to be etched formed on a semiconductor wafer using a resist as a mask. When performing plasma etching using a parallel plate type plasma processing apparatus, it has been proposed to apply a DC voltage to an upper electrode in order to enhance a sputtering effect on a wafer surface (for example, Patent Documents 1 and 2). See).
ところで、近年、プラズマエッチングにより高アスペクト比のパターンを形成する要求が高まっている。
In recent years, there has been an increasing demand for forming a pattern having a high aspect ratio by plasma etching.
しかしながら、特に高アスペクト比のホールをエッチングする際、エッチング途中でエッチングレートが下がる現象が生じる。これは、高アスペクト比のホールでは、エッチングが進むに従い、プラズマの電子をホール底に十分に叩き込むことが難しく、ホール底が電子によってチャージキャンセルされないために、イオンをホール底に引き込むことが困難になることが一因であると推定される。
However, particularly when etching a hole having a high aspect ratio, a phenomenon occurs in which the etching rate decreases during the etching. This is because, in a hole with a high aspect ratio, it is difficult to sufficiently strike plasma electrons into the hole bottom as etching proceeds, and it is difficult to draw ions into the hole bottom because the hole bottom is not canceled by electrons. It is presumed that this is one of the causes.
上記課題に対して、一側面では、イオンエネルギーを制御し、エッチングレートの低下を防ぐことを目的とする。
に 対 し て In one aspect, an object of the present invention is to control ion energy and prevent a decrease in etching rate.
本開示の一の態様によれば、被処理体を載置する第1の電極と、前記第1の電極と対向する第2の電極とを有するプラズマ処理装置の制御方法であって、バイアスパワーを前記第1の電極へ供給する工程と、負の直流電圧を前記第2の電極に供給する工程と、を有し、前記負の直流電圧は、第1の電圧値をとる第1の状態と、絶対値が前記第1の電圧値よりも小さい第2の電圧値をとる第2の状態とを周期的に繰り返し、前記第1の状態を、前記バイアスパワーの高周波の周期に同期する信号の各周期内の部分期間、又は前記バイアスパワーの伝達経路で測定された、周期的に変動するパラメータの各周期内の部分期間に印加し、前記第2の状態を前記第1の状態と連続して印加する第1制御工程を含む、制御方法が提供される。
According to one embodiment of the present disclosure, there is provided a method for controlling a plasma processing apparatus including a first electrode on which an object to be processed is placed, and a second electrode facing the first electrode, the method comprising: And supplying a negative DC voltage to the second electrode, wherein the negative DC voltage takes a first voltage value in a first state. And a second state in which an absolute value takes a second voltage value smaller than the first voltage value. The second state periodically repeats, and the first state is synchronized with a high-frequency cycle of the bias power. Or a partial period in each cycle of a periodically varying parameter measured in the transmission path of the bias power, so that the second state is continuous with the first state. A control method is provided that includes a first control step of performing and applying the voltage.
一の側面によれば、イオンエネルギーを制御し、エッチングレートの低下を防ぐことができる。
According to one aspect, it is possible to control ion energy and prevent a decrease in etching rate.
本開示を実施するための形態について図面を参照して説明する。なお、本明細書及び図面において、実質的に同一の構成については、同一の符号を付することにより重複した説明を省く。
形態 An embodiment for carrying out the present disclosure will be described with reference to the drawings. In the specification and the drawings, substantially the same configuration is denoted by the same reference numeral to omit redundant description.
以下、ソースパワーとしての高周波をHFともいい、ソースパワーをHF電力ともいう。また、ソースパワーの周波数よりも低い周波数のバイアスパワーとしての高周波をLFともいい、バイアスパワーをLF電力ともいう。
Hereinafter, the high frequency as the source power is also referred to as HF, and the source power is also referred to as HF power. Further, a high frequency as a bias power having a frequency lower than the frequency of the source power is also referred to as LF, and the bias power is also referred to as LF power.
[プラズマ処理装置の全体構成]
まず、プラズマ処理装置1の一例について、図1を参照しながら説明する。図1は、一実施形態に係るプラズマ処理装置の一例を示す図である。 [Overall configuration of plasma processing apparatus]
First, an example of theplasma processing apparatus 1 will be described with reference to FIG. FIG. 1 is a diagram illustrating an example of a plasma processing apparatus according to one embodiment.
まず、プラズマ処理装置1の一例について、図1を参照しながら説明する。図1は、一実施形態に係るプラズマ処理装置の一例を示す図である。 [Overall configuration of plasma processing apparatus]
First, an example of the
本実施形態にかかるプラズマ処理装置1は、容量結合型の平行平板プラズマ処理装置であり、例えば表面が陽極酸化処理されたアルミニウムからなる円筒状の処理容器10を有している。処理容器10は接地されている。
The plasma processing apparatus 1 according to the present embodiment is a capacitively coupled parallel plate plasma processing apparatus, and has a cylindrical processing container 10 made of, for example, aluminum whose surface is anodized. The processing container 10 is grounded.
処理容器10の底部には、セラミックス等からなる絶縁板12を介して円柱状の支持台14が配置され、この支持台14の上に例えばアルミニウムからなる載置台16が設けられている。載置台16は下部電極を構成し、その上に静電チャック18を介して被処理体の一例であるウェハWが載置される。
A columnar support 14 is disposed at the bottom of the processing vessel 10 via an insulating plate 12 made of ceramics or the like, and a mounting table 16 made of, for example, aluminum is provided on the support 14. The mounting table 16 forms a lower electrode, on which a wafer W, which is an example of an object to be processed, is mounted via an electrostatic chuck 18.
載置台16の上面には、ウェハWを静電力で吸着保持する静電チャック18が設けられている。静電チャック18は、導電膜からなる電極20を一対の絶縁層または絶縁シートで挟んだ構造を有する。電極20には直流電源22が接続されている。直流電源22から出力された直流電圧は、電極20に印加される。これにより生じたクーロン力等の静電力によってウェハWが静電チャック18に吸着保持される。
静電 An electrostatic chuck 18 is provided on the upper surface of the mounting table 16 for holding the wafer W by electrostatic force. The electrostatic chuck 18 has a structure in which an electrode 20 made of a conductive film is sandwiched between a pair of insulating layers or sheets. A DC power supply 22 is connected to the electrode 20. The DC voltage output from the DC power supply 22 is applied to the electrode 20. The wafer W is attracted and held on the electrostatic chuck 18 by electrostatic force such as Coulomb force generated by this.
載置台16上であってウェハWの周縁には、例えばシリコンからなる導電性のエッジリング24が配置されている。エッジリング24はフォーカスリングともいう。載置台16および支持台14の側面には、例えば石英からなる円筒状の内壁部材26が設けられている。
(4) A conductive edge ring 24 made of, for example, silicon is disposed on the mounting table 16 and on the periphery of the wafer W. The edge ring 24 is also called a focus ring. On the side surfaces of the mounting table 16 and the support table 14, a cylindrical inner wall member 26 made of, for example, quartz is provided.
支持台14の内部には、例えば環状に冷媒室28が設けられている。冷媒室28には、外部に設けられたチラーユニットより配管30a,30bを介して所定温度の冷媒、例えば冷却水が循環供給され、冷媒の温度によって載置台16上のウェハWの処理温度が制御される。なお、冷媒は、配管30a,30bに循環供給される温度調整用の媒体の一例であり、温度調整用の媒体は、載置台16及びウェハWを冷却するだけでなく、加熱する場合もあり得る。
冷媒 A refrigerant chamber 28 is provided inside the support base 14, for example, in an annular shape. A coolant having a predetermined temperature, for example, cooling water is circulated and supplied from the chiller unit provided outside to the coolant chamber 28 via the pipes 30a and 30b, and the processing temperature of the wafer W on the mounting table 16 is controlled by the temperature of the coolant. Is done. Note that the refrigerant is an example of a medium for temperature adjustment circulated and supplied to the pipes 30a and 30b, and the medium for temperature adjustment may not only cool the mounting table 16 and the wafer W but also heat it. .
さらに、伝熱ガス供給機構からの伝熱ガス、例えばHeガスがガス供給ライン32を介して静電チャック18の上面とウェハWの裏面との間に供給される。
{Circle around (2)} A heat transfer gas, for example, He gas, from the heat transfer gas supply mechanism is supplied between the upper surface of the electrostatic chuck 18 and the back surface of the wafer W via the gas supply line 32.
載置台16の上方には、載置台16と対向するように平行に上部電極34が設けられている。上部電極34と下部電極間の間はプラズマ処理空間となる。上部電極34は、載置台16上のウェハWと対向してプラズマ処理空間と接する面、つまり対向面を形成する。
上部 An upper electrode 34 is provided above and parallel to the mounting table 16 so as to face the mounting table 16. A space between the upper electrode 34 and the lower electrode is a plasma processing space. The upper electrode 34 forms a surface facing the wafer W on the mounting table 16 and in contact with the plasma processing space, that is, an upper surface.
上部電極34は、絶縁性の遮蔽部材42を介して、処理容器10の上部に支持されている。上部電極34は、載置台16との対向面を構成しかつ多数のガス吐出孔37を有する電極板36と、この電極板36を着脱自在に支持し、導電性材料、例えば表面が陽極酸化処理されたアルミニウムからなる電極支持体38とを有する。電極板36は、例えばシリコンやSiCにより形成されてもよい。電極支持体38の内部には、ガス拡散室40が設けられ、このガス拡散室40からはガス吐出孔37に連通する多数のガス通流孔41が下方に延びている。
The upper electrode 34 is supported on the upper part of the processing container 10 via the insulating shielding member 42. The upper electrode 34 constitutes a surface facing the mounting table 16 and has an electrode plate 36 having a large number of gas discharge holes 37. The upper electrode 34 detachably supports the electrode plate 36, and is made of a conductive material such as an anodized surface. And an electrode support 38 made of aluminum. The electrode plate 36 may be formed of, for example, silicon or SiC. A gas diffusion chamber 40 is provided inside the electrode support 38, and a large number of gas flow holes 41 communicating with the gas discharge holes 37 extend downward from the gas diffusion chamber 40.
電極支持体38にはガス拡散室40へ処理ガスを導くガス導入口62が形成されており、このガス導入口62にはガス供給管64が接続され、ガス供給管64には処理ガス供給源66が接続されている。ガス供給管64には、上流側から順にマスフローコントローラ(MFC)68および開閉バルブ70が設けられている。そして、処理ガス供給源66からエッチングのための処理ガスが供給される。処理ガスは、ガス供給管64からガス拡散室40に至り、ガス通流孔41を介してガス吐出孔37からシャワー状にプラズマ処理空間に吐出される。このようにして上部電極34は処理ガスを供給するためのシャワーヘッドとして機能する。
The electrode support 38 is provided with a gas inlet 62 for guiding the processing gas to the gas diffusion chamber 40. The gas inlet 62 is connected to a gas supply pipe 64, and the gas supply pipe 64 is connected to a processing gas supply source. 66 are connected. The gas supply pipe 64 is provided with a mass flow controller (MFC) 68 and an opening / closing valve 70 in order from the upstream side. Then, a processing gas for etching is supplied from the processing gas supply source 66. The processing gas reaches the gas diffusion chamber 40 from the gas supply pipe 64, and is discharged from the gas discharge hole 37 into the plasma processing space through the gas flow hole 41 in a shower shape. Thus, the upper electrode 34 functions as a shower head for supplying the processing gas.
上部電極34には、可変直流電源50が接続され、可変直流電源50からの直流電圧が上部電極34に印加される。可変直流電源50の極性および電流・電圧と、電流や電圧をオン・オフする電子スイッチの制御は、制御部200により制御される。
可 変 A variable DC power supply 50 is connected to the upper electrode 34, and a DC voltage from the variable DC power supply 50 is applied to the upper electrode 34. The control of the polarity and current / voltage of the variable DC power supply 50 and the electronic switch for turning on / off the current and voltage are controlled by the control unit 200.
載置台16には、給電棒47及び整合器46を介して第1の高周波電源48が接続されている。第1の高周波電源48は、載置台16にLF電力を印加する。これにより、載置台16上のウェハWにイオンが引き込まれる。第1の高周波電源48は、200kHz~13.56MHzの範囲内の周波数の高周波電力を出力する。整合器46は第1の高周波電源48の内部インピーダンスと負荷インピーダンスとを整合させる。
第 A first high frequency power supply 48 is connected to the mounting table 16 via a power supply rod 47 and a matching unit 46. The first high frequency power supply 48 applies LF power to the mounting table 16. Thereby, ions are drawn into the wafer W on the mounting table 16. The first high-frequency power supply 48 outputs high-frequency power having a frequency in the range of 200 kHz to 13.56 MHz. The matching unit 46 matches the internal impedance of the first high-frequency power supply 48 with the load impedance.
載置台16には、給電棒89及び整合器88を介して第2の高周波電源90が接続されている。第2の高周波電源90は、載置台16にHF電力を印加する。HFの周波数は、LFの周波数よりも高く、第2の高周波電源90から13.56MHz以上の周波数のHF電力が出力される。例えば400kHzのLF電力と100MHzのHF電力を出力してもよい。整合器88は、第2の高周波電源90の内部インピーダンスと負荷インピーダンスとを整合させる。載置台16には、所定の高周波をグランドに通すためのフィルタ94が接続されてもよい。なお、第2の高周波電源90から供給されるHF電力を、上部電極34に印加してもよい。
2A second high frequency power supply 90 is connected to the mounting table 16 via a power supply rod 89 and a matching unit 88. The second high frequency power supply 90 applies HF power to the mounting table 16. The frequency of the HF is higher than the frequency of the LF, and HF power of a frequency of 13.56 MHz or higher is output from the second high frequency power supply 90. For example, LF power of 400 kHz and HF power of 100 MHz may be output. The matching unit 88 matches the internal impedance of the second high-frequency power supply 90 with the load impedance. A filter 94 for passing a predetermined high frequency to the ground may be connected to the mounting table 16. The HF power supplied from the second high frequency power supply 90 may be applied to the upper electrode 34.
処理容器10の底部には排気口80が設けられ、この排気口80に排気管82を介して排気装置84が接続されている。排気装置84は、ターボ分子ポンプなどの真空ポンプを有しており、処理容器10内は所望の真空度まで減圧可能である。また、処理容器10の側壁にはウェハWの搬入出口85が設けられており、この搬入出口85はゲートバルブ86により開閉可能である。また、処理容器10の内壁に沿って処理容器10にエッチング副生物(デポ)が付着することを防止するためのデポシールド11が着脱自在に設けられている。すなわち、デポシールド11が処理容器の壁を構成している。また、デポシールド11は、内壁部材26の外周にも設けられている。処理容器10の底部の処理容器の壁側のデポシールド11と内壁部材26側のデポシールド11との間には排気プレート83が設けられている。デポシールド11および排気プレート83としては、アルミニウム材にY2O3等のセラミックスを被覆したものを用いることができる。
An exhaust port 80 is provided at the bottom of the processing container 10, and an exhaust device 84 is connected to the exhaust port 80 via an exhaust pipe 82. The exhaust device 84 has a vacuum pump such as a turbo-molecular pump, and can reduce the pressure inside the processing container 10 to a desired degree of vacuum. A loading / unloading port 85 for the wafer W is provided on a side wall of the processing container 10, and the loading / unloading port 85 can be opened and closed by a gate valve 86. In addition, a deposition shield 11 for preventing an etching by-product (depot) from adhering to the processing container 10 along the inner wall of the processing container 10 is provided detachably. That is, the deposition shield 11 constitutes the wall of the processing container. The deposit shield 11 is also provided on the outer periphery of the inner wall member 26. An exhaust plate 83 is provided between the deposition shield 11 on the wall side of the processing container at the bottom of the processing container 10 and the deposition shield 11 on the inner wall member 26 side. As the deposition shield 11 and the exhaust plate 83, an aluminum material coated with ceramics such as Y 2 O 3 can be used.
かかる構成のプラズマ処理装置1にてエッチング処理を行う際には、まず、ゲートバルブ86を開状態とし、搬入出口85を介してエッチング対象であるウェハWを処理容器10内に搬入し、載置台16上に載置する。そして、処理ガス供給源66からエッチングのための処理ガスを所定の流量でガス拡散室40へ供給し、ガス通流孔41およびガス吐出孔37を介して処理容器10内へ供給する。また、排気装置84により処理容器10内を排気し、その中の圧力を例えば0.1~150Paの範囲内の設定値とする。ここで、処理ガスとしては、従来用いられている種々のものを採用することができ、例えばC4F8ガス等のハロゲン元素を含有するガスを好適に用いることができる。さらに、ArガスやO2ガス等の他のガスが含まれていてもよい。
When performing an etching process in the plasma processing apparatus 1 having such a configuration, first, the gate valve 86 is opened, and the wafer W to be etched is loaded into the processing chamber 10 through the loading / unloading port 85, and the mounting table is set. 16 is placed. Then, a processing gas for etching is supplied from the processing gas supply source 66 to the gas diffusion chamber 40 at a predetermined flow rate, and is supplied into the processing container 10 through the gas flow holes 41 and the gas discharge holes 37. Further, the inside of the processing container 10 is exhausted by the exhaust device 84, and the pressure therein is set to a set value within a range of, for example, 0.1 to 150 Pa. Here, as the processing gas, various conventionally used gases can be adopted, and for example, a gas containing a halogen element such as a C 4 F 8 gas can be suitably used. Further, another gas such as Ar gas or O 2 gas may be contained.
このように処理容器10内にエッチングガスを導入した状態で、第2の高周波電源90からHF電力を載置台16に印加する。また、第1の高周波電源48からLF電力を載置台16に印加する。また、可変直流電源50から直流電圧を上部電極34に印加する。また、直流電源22から直流電圧を電極20に印加し、ウェハWを載置台16に保持する。
H With the etching gas introduced into the processing chamber 10 as described above, HF power is applied to the mounting table 16 from the second high-frequency power supply 90. Further, LF power is applied to the mounting table 16 from the first high frequency power supply 48. Further, a DC voltage is applied to the upper electrode 34 from the variable DC power supply 50. Further, a DC voltage is applied from the DC power supply 22 to the electrode 20, and the wafer W is held on the mounting table 16.
上部電極34のガス吐出孔37から吐出された処理ガスは、主にHF電力により解離及び電離しプラズマが生成される。プラズマ中のラジカルやイオンによってウェハWの被処理面がエッチングされる。また、載置台16にLF電力を印加することで、プラズマ中のイオンを制御し、高アスペクト比のホールのエッチングを可能とする等、プラズマの制御マージンを広くできる。
(4) The processing gas discharged from the gas discharge holes 37 of the upper electrode 34 is dissociated and ionized mainly by HF electric power to generate plasma. The processing surface of the wafer W is etched by radicals and ions in the plasma. In addition, by applying LF power to the mounting table 16, ions in the plasma are controlled, and etching of holes with a high aspect ratio can be performed, and the plasma control margin can be widened.
プラズマ処理装置1には、装置全体の動作を制御する制御部200が設けられている。制御部200は、ROM(Read Only Memory)及びRAM(Random Access Memory)等のメモリに格納されたレシピに従って、エッチング等の所望のプラズマ処理を実行する。レシピには、プロセス条件に対する装置の制御情報であるプロセス時間、圧力(ガスの排気)、高周波電力や電圧、各種ガス流量、処理容器内温度(上部電極温度、処理容器の側壁温度、ウェハW温度、静電チャック温度等)、チラーから出力される冷媒の温度などが設定されている。なお、これらのプログラムや処理条件を示すレシピは、ハードディスクや半導体メモリに記憶されてもよい。また、レシピは、CD-ROM、DVD等の可搬性のコンピュータにより読み取り可能な記憶媒体に収容された状態で所定位置にセットされ、読み出されるようにしてもよい。
(4) The plasma processing apparatus 1 is provided with a control unit 200 for controlling the operation of the entire apparatus. The control unit 200 performs desired plasma processing such as etching in accordance with a recipe stored in a memory such as a ROM (Read Only Memory) and a RAM (Random Access Memory). The recipe includes process time, pressure (gas exhaust), high-frequency power and voltage, various gas flow rates, temperature inside the processing vessel (upper electrode temperature, side wall temperature of the processing vessel, temperature of wafer W, which are control information of the apparatus with respect to the process conditions). , The temperature of the electrostatic chuck, etc.), the temperature of the refrigerant output from the chiller, and the like. Note that these programs and recipes indicating processing conditions may be stored in a hard disk or a semiconductor memory. Further, the recipe may be set at a predetermined position in a state where the recipe is stored in a portable computer-readable storage medium such as a CD-ROM or a DVD, and may be read.
例えば、制御部200は、可変直流電源50から出力する負の直流電圧を、前記バイアスパワーの高周波の周期に同期する信号の各周期内の部分期間、又はバイアスパワーの伝達経路で測定された、電圧、電流、電磁界、発生したプラズマの発光周期又はウェハW(下部電極)上のプラズマのシース厚の変化の各周期内の部分期間に印加し、負の直流電圧のオンとオフとを交互に繰り返すように制御してもよい。以下、バイアスパワーの伝達経路で測定された、電圧、電流、電磁界、発生したプラズマの発光周期又はウェハW(下部電極)上のプラズマのシース厚の変化を「周期的に変動するパラメータ」ともいう。第2の高周波電源90から出力するHFの電圧を、前記バイアスパワーの高周波の周期に同期する信号の各周期内の部分期間、又は周期的に変動するパラメータの各周期内の部分期間に印加し、HFの電圧のオンとオフとを交互に繰り返すように制御してもよい。これにより、イオンエネルギーを制御し、エッチングレートの低下を防ぐことができる。
For example, the control unit 200 measures the negative DC voltage output from the variable DC power supply 50 in a partial period in each cycle of the signal synchronized with the high-frequency cycle of the bias power, or in the transmission path of the bias power. A voltage, a current, an electromagnetic field, a light emission cycle of the generated plasma or a change in the sheath thickness of the plasma on the wafer W (lower electrode) is applied during a partial period within each cycle, and a negative DC voltage is alternately turned on and off. May be controlled to be repeated. Hereinafter, a change in the voltage, current, electromagnetic field, emission cycle of the generated plasma, or change in the sheath thickness of the plasma on the wafer W (lower electrode), which is measured in the transmission path of the bias power, is also referred to as a “parameter that varies periodically”. Say. The HF voltage output from the second high frequency power supply 90 is applied to a partial period within each cycle of a signal synchronized with the high frequency cycle of the bias power or a partial period within each cycle of a periodically varying parameter. , HF voltage may be controlled to be alternately turned on and off. Thereby, ion energy can be controlled and a decrease in the etching rate can be prevented.
バイアスパワーの伝達経路とは、第1の高周波電源48→整合器46→給電棒47→載置台16→プラズマ→上部電極34→(グランド)をいう。バイアスパワーの伝達経路で測定された電圧、電流、電磁界とは、第1の高周波電源48から整合器46の内部及び給電棒47を介して載置台16に至るまでのパーツと上部電極34で測定された電圧、電流、電磁界、又は、プラズマで測定された電磁界をいう。
The transmission path of the bias power means the first high-frequency power supply 48 → the matching unit 46 → the power supply rod 47 → the mounting table 16 → the plasma → the upper electrode 34 → (ground). The voltage, current, and electromagnetic field measured on the transmission path of the bias power are generated by the upper electrode 34 and parts from the first high-frequency power supply 48 to the inside of the matching box 46 and from the power supply rod 47 to the mounting table 16. A measured voltage, current, electromagnetic field, or electromagnetic field measured in plasma.
可変直流電源50から出力する負の直流電圧は、後述する第1の状態と第2の状態とを周期的に繰り返し、第1の状態は、前記バイアスパワーの高周波の周期に同期する信号の各周期内の部分期間、又は周期的に変動するパラメータの各周期内の部分期間に印加され、第2の状態を第1の状態と連続して印加するように制御される。
The negative DC voltage output from the variable DC power supply 50 periodically repeats a first state and a second state, which will be described later, and the first state corresponds to each of signals synchronized with the high-frequency cycle of the bias power. It is applied during a partial period within a cycle or a partial period within each cycle of a periodically varying parameter, and is controlled so as to apply the second state continuously with the first state.
負の直流電圧を、バイアスパワーの伝達経路で測定された、周期的に変動するパラメータの各周期内の部分期間に印加する場合、周期的に変動するパラメータは、載置台16から給電棒47を介して接続される整合器の内部までのいずれかの部材において測定された電圧、電流又は電磁界のいずれかであることが好ましい。
When a negative DC voltage is applied in a partial period within each cycle of the periodically varying parameter measured on the bias power transmission path, the periodically varying parameter is transmitted from the mounting table 16 to the power supply rod 47. It is preferably any one of the voltage, current, or electromagnetic field measured at any member up to the inside of the matching device connected via.
バイアスパワーの伝達経路で周期的に変動するパラメータを測定する方法としては、バイアスパワーの伝達経路のいずれかのパーツの近傍に電圧センサ、電流センサ又はBZセンサ(誘導磁場を測るセンサ)を設置することで各パーツの電圧、電流又は誘導磁場を計測する方法が一例として挙げられる。なお、図2Aには、電圧センサ300を示したが、これに限られず、電流センサ又はBZセンサであってもよい。また、上記各センサの配置は、給電棒47に接続されることが好ましいが、これに限られない。電圧センサ300等のセンサからの信号は、例えば制御部200の信号発生回路102に入力される。
As a method of measuring a parameter that fluctuates periodically in a bias power transmission path, a voltage sensor, a current sensor, or a BZ sensor (a sensor that measures an induced magnetic field) is installed near any part of the bias power transmission path. For example, a method of measuring the voltage, current, or induced magnetic field of each part is given as an example. Although FIG. 2A shows the voltage sensor 300, the present invention is not limited to this, and may be a current sensor or a BZ sensor. Further, it is preferable that the arrangement of the respective sensors is connected to the power supply rod 47, but the arrangement is not limited to this. A signal from a sensor such as the voltage sensor 300 is input to the signal generation circuit 102 of the control unit 200, for example.
例えば図2B(a)は、負の直流電圧を、バイアスパワーの伝達経路で測定された、周期的に変動するパラメータの各周期内の部分期間に印加する場合の一例である。図2B(a)では、プロセッサ100が、バイアスパワーの伝達経路に取り付けられたVIプローブ等のセンサからHFの電圧又は電流、LFの電圧又は電流、HFの位相信号又はLFの位相信号のいずれかを周期的に変動するパラメータの一例として入力する。プロセッサ100は、可変直流電源50から出力する負の直流電圧を、入力した周期的に変動するパラメータの各周期内の部分期間に印加する。
{For example, FIG. 2B (a) shows an example in which a negative DC voltage is applied to a partial period in each cycle of a periodically varying parameter measured on a bias power transmission path. In FIG. 2B (a), the processor 100 outputs any one of the HF voltage or current, the LF voltage or current, the HF phase signal or the LF phase signal from a sensor such as a VI probe attached to the bias power transmission path. Is input as an example of a parameter that fluctuates periodically. The processor 100 applies the negative DC voltage output from the variable DC power supply 50 to a partial period in each cycle of the input periodically varying parameter.
プロセッサ100は、センサからの信号に基づかずに第1の高周波電源48から出力されるバイアスパワーの高周波の周期に同期する信号を生成してもよい。この場合、バイアスパワーの伝達経路で周期的に変動するパラメータの状態を測定する工程を省くことができる。例えば図2B(b)では、プロセッサ100が、第1の高周波電源48からLFの位相信号(小電力波形)又はバイアスパワーの情報に関する信号を入力し、この入力信号に基づきバイアスパワーの高周波の周期に同期する信号を生成する。プロセッサ100は、生成した信号を可変直流電源50に出力する。可変直流電源50は、この信号の各周期内の部分期間に負の直流電圧を印加する。生成した信号は、ソースパワーの変調情報を含み、プロセッサ100は、生成した信号を第2の高周波電源90に出力してもよい。第2の高周波電源90は、この信号の各周期内の部分期間にソースパワーを印加する。
The processor 100 may generate a signal synchronized with the high-frequency cycle of the bias power output from the first high-frequency power supply 48 without being based on the signal from the sensor. In this case, it is possible to omit the step of measuring the state of the parameter that periodically changes in the transmission path of the bias power. For example, in FIG. 2B (b), the processor 100 inputs an LF phase signal (small power waveform) or a signal relating to information of bias power from the first high frequency power supply 48, and based on the input signal, a high frequency cycle of bias power. Generate a signal synchronized with Processor 100 outputs the generated signal to variable DC power supply 50. The variable DC power supply 50 applies a negative DC voltage during a partial period within each cycle of this signal. The generated signal includes the modulation information of the source power, and the processor 100 may output the generated signal to the second high frequency power supply 90. The second high frequency power supply 90 applies source power during a partial period within each cycle of this signal.
なお、プロセッサ100は、第1の高周波電源48からの信号に基づかずにバイアスパワーの高周波の周期に同期する信号を生成してもよい。この場合、プロセッサ100は、例えば図3のLFに示す周期を有する信号を生成すると共に、この信号に同期する、例えば図3のDCに示すオン・オフ信号を生成する。プロセッサ100は、生成した信号を第1の高周波電源48及び可変直流電源50に出力する。第1の高周波電源48は、この信号に基づきバイアスパワーを出力する。可変直流電源50は、この信号の各周期内の部分期間に負の直流電圧を印加する。
Note that the processor 100 may generate a signal synchronized with the high-frequency cycle of the bias power without being based on the signal from the first high-frequency power supply 48. In this case, the processor 100 generates a signal having a period indicated by LF in FIG. 3, for example, and generates an on / off signal indicated by DC in FIG. 3, for example, in synchronization with the signal. The processor 100 outputs the generated signal to the first high-frequency power supply 48 and the variable DC power supply 50. The first high frequency power supply 48 outputs bias power based on this signal. The variable DC power supply 50 applies a negative DC voltage during a partial period within each cycle of this signal.
更に、プロセッサ100は、生成した図3のLFに示す周期を有する信号に同期する、例えば図3のHFに示すオン・オフ信号を生成してもよい。プロセッサ100は、生成した信号を第2の高周波電源90に出力する。第2の高周波電源90は、この信号の各周期内の部分期間にソースパワーを印加する。
Further, the processor 100 may generate an on / off signal indicated by HF in FIG. 3 in synchronization with the generated signal having the cycle indicated by LF in FIG. The processor 100 outputs the generated signal to the second high frequency power supply 90. The second high frequency power supply 90 applies source power during a partial period within each cycle of this signal.
更に、プラズマの発光周期、ウェハW上のプラズマのシース厚の変化の周期を指標にしても良い。プラズマの発光周期は、フォトダイオード、フォトマイクロセンサ等で検出できる。シース厚については、ICCDカメラなどを用いてナノsecの間隔(例えば10~250nsec)でシャッターを切り、これにより、シース厚の変化を測定できる。
Furthermore, the light emission period of the plasma and the change period of the sheath thickness of the plasma on the wafer W may be used as the index. The light emission period of the plasma can be detected by a photodiode, a photomicrosensor, or the like. Regarding the sheath thickness, a shutter is opened at an interval of nanoseconds (for example, 10 to 250 nsec) using an ICCD camera or the like, whereby a change in the sheath thickness can be measured.
なお、載置台16は、ウェハWを載置する第1の電極の一例である。上部電極は、第1の電極と対向する第2の電極の一例である。第1の高周波電源48は、第1の電極にLF電力(バイアスパワー)を供給するバイアス電源の一例である。第2の高周波電源90は、第1の電極又は第2の電極にLF電力よりも高い周波数のHF電力(ソースパワー)を供給するソース電源の一例である。可変直流電源50は、直流電圧を第2の電極に供給する直流電源の一例である。制御部200は、バイアス電源、ソース電源及び直流電源を制御する制御部の一例である。バイアスパワーを印加する下部電極(載置台16)の電位を、電極電位ともいう。
The mounting table 16 is an example of a first electrode on which the wafer W is mounted. The upper electrode is an example of a second electrode facing the first electrode. The first high-frequency power supply 48 is an example of a bias power supply that supplies LF power (bias power) to the first electrode. The second high-frequency power supply 90 is an example of a source power supply that supplies HF power (source power) having a higher frequency than LF power to the first electrode or the second electrode. The variable DC power supply 50 is an example of a DC power supply that supplies a DC voltage to the second electrode. The control unit 200 is an example of a control unit that controls a bias power supply, a source power supply, and a DC power supply. The potential of the lower electrode (mounting table 16) to which the bias power is applied is also referred to as an electrode potential.
[制御部の構成]
制御部200の具体的構成について、図2Aを参照して説明する。制御部200は、プロセッサ100、信号発生回路102、方向性結合器105,108、電力メータ111、オシロスコープ112を有する。ただし、電力メータ111、オシロスコープ112、方向性結合器108は設けなくてもよい。 [Configuration of control unit]
The specific configuration of thecontrol unit 200 will be described with reference to FIG. 2A. The control unit 200 includes a processor 100, a signal generation circuit 102, directional couplers 105 and 108, a power meter 111, and an oscilloscope 112. However, the power meter 111, the oscilloscope 112, and the directional coupler 108 need not be provided.
制御部200の具体的構成について、図2Aを参照して説明する。制御部200は、プロセッサ100、信号発生回路102、方向性結合器105,108、電力メータ111、オシロスコープ112を有する。ただし、電力メータ111、オシロスコープ112、方向性結合器108は設けなくてもよい。 [Configuration of control unit]
The specific configuration of the
第1の高周波電源48の給電ラインには、第1の高周波電源48と整合器46の間に方向性結合器105が接続されている。第2の高周波電源90の給電ラインには、第2の高周波電源90と整合器88の間に方向性結合器108が接続されている。
A directional coupler 105 is connected between the first high-frequency power supply 48 and the matching box 46 to the power supply line of the first high-frequency power supply 48. A directional coupler 108 is connected to the power supply line of the second high-frequency power supply 90 between the second high-frequency power supply 90 and the matching unit 88.
方向性結合器105は、LFの進行波の一部をオシロスコープ112に与える。また、方向性結合器108は、HFの進行波の一部をオシロスコープ112に与える。
The -directional coupler 105 supplies a part of the LF traveling wave to the oscilloscope 112. Further, the directional coupler 108 gives a part of the traveling wave of the HF to the oscilloscope 112.
一実施形態において、オシロスコープ112に表示されるLFの周波数は、例えば400kHzであり、HFの周波数は、例えば100MHzである。これにより、オシロスコープ112では、LFの進行波の波形と、HFの進行波の波形を観察できる。
In one embodiment, the LF frequency displayed on the oscilloscope 112 is, for example, 400 kHz, and the HF frequency is, for example, 100 MHz. Thus, the oscilloscope 112 can observe the waveform of the LF traveling wave and the waveform of the HF traveling wave.
方向性結合器108は、HFの進行波の一部を電力メータ111に与える。電力メータ111は、HFの進行波の電力量を計量する。
The -directional coupler 108 supplies a part of the HF traveling wave to the power meter 111. The power meter 111 measures the amount of power of the HF traveling wave.
方向性結合器105は、LFの進行波の一部をプロセッサ100に与える。プロセッサ100は、LFの進行波に同期させるDC用の同期信号を作成する。例えば、プロセッサ100は、LFの進行波の正のタイミングに同期させてDC用の同期信号を作成してもよい。なお、方向性結合器105の替わりに、VIセンサ等のセンサを用いて検出したLFの波形をプロセッサ100に与えてもよい。
The -directional coupler 105 supplies a part of the LF traveling wave to the processor 100. The processor 100 creates a DC synchronization signal synchronized with the traveling wave of the LF. For example, the processor 100 may generate the DC synchronization signal in synchronization with the positive timing of the traveling wave of the LF. Note that, instead of the directional coupler 105, the LF waveform detected using a sensor such as a VI sensor may be provided to the processor 100.
プロセッサ100は、作成した同期信号を信号発生回路102に与える。信号発生回路102は、与えられた同期信号からLFの進行波に同期する制御信号を発生し、可変直流電源50及び第1の高周波電源48に与える。
(4) The processor 100 gives the created synchronization signal to the signal generation circuit 102. The signal generation circuit 102 generates a control signal synchronized with the LF traveling wave from the applied synchronization signal, and supplies the control signal to the variable DC power supply 50 and the first high-frequency power supply 48.
制御信号の生成方法には、以下の2通りがある。第1の高周波電源48が一般的な電源の場合、方向性結合器105が第1の高周波電源48から出力されるLFの電圧の一部を波形として取り出し、プロセッサ100に入力する。ただし、これに限られず、プロセッサ100が、第1の高周波電源48から直接、LFの電力等の一部を入力してもよい。プロセッサ100は、入力した波形の信号に同期させて又は該信号から任意の遅延と任意の幅を有するオン信号を作成し、信号発生回路102に送信する。
There are the following two methods for generating the control signal. When the first high frequency power supply 48 is a general power supply, the directional coupler 105 extracts a part of the LF voltage output from the first high frequency power supply 48 as a waveform and inputs the waveform to the processor 100. However, the present invention is not limited thereto, and the processor 100 may directly input a part of the power of the LF or the like from the first high-frequency power supply 48. The processor 100 generates an ON signal having an arbitrary delay and an arbitrary width in synchronization with the input waveform signal or from the input signal, and transmits the ON signal to the signal generation circuit 102.
信号発生回路102は、オン信号の間、直流電圧を発生させるために可変直流電源50に指令信号を送る。指令信号には、可変直流電源50の入力形態に応じて、オン信号の間、直流電圧を発生させる制御信号又はオン信号そのものが使用される。同様に、信号発生回路102は、オン信号の間、HFの電力を発生させるために第2の高周波電源90に指令信号を送るようにしてもよい。
The signal generation circuit 102 sends a command signal to the variable DC power supply 50 to generate a DC voltage during the ON signal. As the command signal, a control signal for generating a DC voltage during the ON signal or the ON signal itself is used depending on the input form of the variable DC power supply 50. Similarly, the signal generation circuit 102 may send a command signal to the second high frequency power supply 90 to generate HF power during the ON signal.
第1の高周波電源48がLFの電力、電圧又は電流を増幅するアンプの場合、方向性結合器105からの信号は使用せず、信号発生回路102が第1の高周波電源48から出力されるLFの電力等の一部を波形として取り出し、該波形の信号から任意の遅延と任意の幅を有するオン信号を作成してもよい。信号発生回路102は、該波形の信号及びオン信号を可変直流電源50に送信する。同様にして、信号発生回路102は、該波形の信号及びオン信号を第2の高周波電源90に送信してもよい。
When the first high frequency power supply 48 is an amplifier that amplifies the power, voltage or current of the LF, the signal from the directional coupler 105 is not used, and the signal generation circuit 102 outputs the LF output from the first high frequency power supply 48. May be extracted as a waveform, and an ON signal having an arbitrary delay and an arbitrary width may be created from the signal of the waveform. The signal generation circuit 102 transmits the waveform signal and the ON signal to the variable DC power supply 50. Similarly, the signal generation circuit 102 may transmit the waveform signal and the ON signal to the second high-frequency power supply 90.
ただし、以上の制御信号の生成方法は一例であり、これに限らない。負の直流電圧を、前記バイアスパワーの高周波の周期に同期する信号の各周期内の部分期間、又は与えられた周期的に変動するパラメータの各周期内の部分期間に印加し、直流電圧のオンとオフとが交互に繰り返されるように制御する制御信号を生成できれば、図2A及び図2Bに示す制御部200の回路に限られず、他のハードウェア又はソフトウェアを使用できる。
However, the above-described control signal generation method is an example, and the present invention is not limited to this. A negative DC voltage is applied to a partial period within each cycle of a signal synchronized with the high frequency cycle of the bias power or a partial period within each cycle of a given periodically varying parameter, and the DC voltage is turned on. As long as a control signal for controlling so that the control signal is turned on and off can be generated, not only the circuit of the control unit 200 shown in FIGS. 2A and 2B but also other hardware or software can be used.
第1の高周波電源48のアンプは、400kHzのLFの変調信号の振幅(AM:amplitude modulation)を増幅し、下部電極に供給する。第2の高周波電源90のアンプは、100MHzのHFの変調信号の振幅を増幅し、下部電極に供給する。
The amplifier of the first high-frequency power supply 48 amplifies the amplitude (AM: amplitude modulation) of the LF modulation signal of 400 kHz and supplies it to the lower electrode. The amplifier of the second high frequency power supply 90 amplifies the amplitude of the HF modulation signal of 100 MHz and supplies it to the lower electrode.
信号発生回路102は、与えられた同期信号からバイアスパワーの伝達経路で測定された、周期的に変動するパラメータの各周期内の部分期間に負の直流電圧を印加し、負の直流電圧のオンとオフとが交互に繰り返されるように制御する制御信号を発生し、可変直流電源50に与えてもよい。信号発生回路102は、バイアスパワーの高周波の周期に同期する信号の各周期内の部分期間に負の直流電圧を印加し、負の直流電圧のオンとオフとが交互に繰り返されるように制御する制御信号を発生し、可変直流電源50に与えてもよい。負の直流電圧のオンとオフに替えてHighとLowとが交互に繰り返されるように制御する制御信号を発生し、可変直流電源50に与えてもよい。
The signal generation circuit 102 applies a negative DC voltage during a partial period within each cycle of the periodically varying parameter measured on the bias power transmission path from the given synchronization signal, and turns on the negative DC voltage. Alternatively, a control signal may be generated for controlling so as to alternately repeat the operation and the OFF state, and the control signal may be supplied to the variable DC power supply 50. The signal generation circuit 102 applies a negative DC voltage during a partial period within each cycle of the signal synchronized with the high-frequency cycle of the bias power, and performs control so that ON and OFF of the negative DC voltage are alternately repeated. A control signal may be generated and supplied to the variable DC power supply 50. Instead of turning on and off the negative DC voltage, a control signal for controlling High and Low to be alternately repeated may be generated and supplied to the variable DC power supply 50.
また、信号発生回路102は、与えられた同期信号からバイアスパワーの伝達経路で測定された、周期的に変動するパラメータの各周期内の部分期間にHF電力を印加し、HFの電力のオンとオフとが交互に繰り返されるように制御する制御信号を発生し、第2の高周波電源90に与えてもよい。信号発生回路102は、バイアスパワーの高周波の周期に同期する信号の各周期内の部分期間にHF電力を印加し、HF電力のオンとオフとが交互に繰り返されるように制御する制御信号を発生し、可変直流電源50に与えてもよい。HF電力のオンとオフに替えてHighとLowとが交互に繰り返されるように制御する制御信号を発生し、第2の高周波電源90に与えてもよい。
Further, the signal generation circuit 102 applies HF power during a partial period within each cycle of the periodically varying parameter measured on the bias power transmission path from the given synchronization signal, and turns on the HF power. A control signal for performing control so that the power supply is repeatedly turned off may be generated and supplied to the second high-frequency power supply 90. The signal generation circuit 102 applies HF power during a partial period within each cycle of the signal synchronized with the high-frequency cycle of the bias power, and generates a control signal for controlling the HF power to be turned on and off alternately. Alternatively, it may be supplied to the variable DC power supply 50. A control signal may be generated to control the HF power so that High and Low are alternately repeated instead of turning on and off the HF power, and may be provided to the second high frequency power supply 90.
図3は、LFに応じて印加するDC及びHFの電圧の一例を示す図である。LFが正のとき、DCの電圧は負の値で印加され、HFの電圧はオフであり、LFが負のとき、HFの電圧は正の値で印加され、DCの電圧はオフである。LFの電圧によって電極電位が決まる。
FIG. 3 is a diagram showing an example of DC and HF voltages applied according to LF. When LF is positive, the DC voltage is applied with a negative value and the HF voltage is off, and when LF is negative, the HF voltage is applied with a positive value and the DC voltage is off. The electrode potential is determined by the voltage of LF.
プロセッサ100は、電極電位が正のタイミングを含む時間帯にDCの電圧及びHFの電力を制御する同期信号を作成してもよい。ただし、プロセッサ100は、これに限られず、電極電位が負に最も深くなるタイミングを含む短時間や電極電位が負を含むタイミングにDCの電圧及びHFの電力を制御する同期信号を作成してもよい。
The processor 100 may generate a synchronization signal for controlling the DC voltage and the HF power in a time period including a timing when the electrode potential is positive. However, the processor 100 is not limited to this, and may generate a synchronization signal that controls the DC voltage and the HF power in a short time including the timing when the electrode potential becomes the deepest negative and at a timing when the electrode potential includes the negative. Good.
[DCの電圧の供給タイミング]
次に、本実施形態におけるDCの電圧の供給タイミングの効果について、図4及び図5を参照しながら説明する。図4は、本実施形態に係る上部電極及び下部電極の電位とプラズマ電位の一例を示す図である。図5は、本実施形態に係る直流電圧の供給タイミングとその効果を説明するための図である。 [DC voltage supply timing]
Next, the effect of the supply timing of the DC voltage in the present embodiment will be described with reference to FIGS. FIG. 4 is a diagram showing an example of the potential of the upper electrode and the lower electrode and the plasma potential according to the present embodiment. FIG. 5 is a diagram for explaining the DC voltage supply timing and its effects according to the present embodiment.
次に、本実施形態におけるDCの電圧の供給タイミングの効果について、図4及び図5を参照しながら説明する。図4は、本実施形態に係る上部電極及び下部電極の電位とプラズマ電位の一例を示す図である。図5は、本実施形態に係る直流電圧の供給タイミングとその効果を説明するための図である。 [DC voltage supply timing]
Next, the effect of the supply timing of the DC voltage in the present embodiment will be described with reference to FIGS. FIG. 4 is a diagram showing an example of the potential of the upper electrode and the lower electrode and the plasma potential according to the present embodiment. FIG. 5 is a diagram for explaining the DC voltage supply timing and its effects according to the present embodiment.
以下では、主にLFの電圧及びDCの電圧を制御したときの、上部電極及び下部電極の電位とプラズマ電位、電子とイオンの動作について、図4を参照して説明する。なお、LFの電圧に替えてLFの電流を制御してもよい。また、DCの電圧に替えてDCの電流を制御してもよい。
Hereinafter, the operations of the potentials of the upper electrode and the lower electrode, the plasma potential, and the electrons and ions when the LF voltage and the DC voltage are controlled will be described with reference to FIG. The LF current may be controlled instead of the LF voltage. Further, the DC current may be controlled instead of the DC voltage.
LFの電圧が負のときの電極電位(ウェハの電位、下部電極電位)は、いわゆる自己バイアス電圧VdcによりLFの電圧が正のときの電極電位よりも負に深くなる。
The electrode potential (wafer potential, lower electrode potential) when the LF voltage is negative becomes deeper than the electrode potential when the LF voltage is positive due to the so-called self-bias voltage Vdc.
図4(a)及び図4(b)のそれぞれの左側の縦軸には、上部電極34の電位が示され、右側の縦軸には下部電極(載置台16)の電位が示され、その間はプラズマ処理空間におけるプラズマ電位が示されている。図4(a)は、LF電力及びHF電力を下部電極に供給した場合の各電極の電位及びプラズマ電位を示す。図4(b)は、LF電力及びHF電力を下部電極に供給し、更に負のDC電圧を上部電極34に供給した場合の各電極の電位及びプラズマ電位を示す。
4A and 4B, the left vertical axis indicates the potential of the upper electrode 34, and the right vertical axis indicates the potential of the lower electrode (mounting table 16). Indicates the plasma potential in the plasma processing space. FIG. 4A shows the potential of each electrode and the plasma potential when LF power and HF power are supplied to the lower electrode. FIG. 4B shows the potential of each electrode and the plasma potential when the LF power and the HF power are supplied to the lower electrode and the negative DC voltage is further supplied to the upper electrode 34.
図4(a)のAに示す電位は、プラズマ電位である。プラズマ電位は、図3のPlasma電位と電極電位に示すように、処理容器10内の最も高い電位よりもわずかに高くなる。よって、電極電位が正のときにはプラズマ電位はLFの電圧よりもわずかに大きくなり、LFの電圧が負のときには処理容器10の壁の電位を0とすると、壁の電位(0)よりもわずかに大きくなる。
電位 The potential indicated by A in FIG. 4A is a plasma potential. The plasma potential is slightly higher than the highest potential in the processing container 10 as shown by the Plasma potential and the electrode potential in FIG. Therefore, when the electrode potential is positive, the plasma potential is slightly higher than the LF voltage, and when the LF voltage is negative, if the potential of the wall of the processing vessel 10 is 0, the plasma potential is slightly higher than the wall potential (0). growing.
図4(a)に示すように、LF電力及びHF電力を下部電極に印加する場合、電極電位が正のときにはプラズマ電位はHF電圧の振幅B及びLF電圧の振幅CによってB+Cだけ押し上げられる。これに対して、電極電位が負のときには下部電極の電位は、自己バイアス電圧Vdcによって負電位側に深くなる。
As shown in FIG. 4A, when LF power and HF power are applied to the lower electrode, when the electrode potential is positive, the plasma potential is boosted by B + C by the amplitude B of the HF voltage and the amplitude C of the LF voltage. On the other hand, when the electrode potential is negative, the potential of the lower electrode becomes deeper toward the negative potential due to the self-bias voltage Vdc.
上部電極に負の直流電圧を印加していない図4(a)の場合、上部電極の電位は0である。このとき、電子は上部電極にできたシース、すなわち上部電極の電位0とプラズマ電位とのわずかな電位差により加速した後、等速に移動し、下部電極の電位が正のときにはウェハW上のシースの電圧に応じて減速しながら、ウェハWに入射する。よって、下部電極の電位が正のときには、プラズマ電位と下部電極の電位との差が小さいため、入射できる電子のエネルギーも低い。よって、様々なエネルギーを持った電子がウェハWに入射される。一方、下部電極の電位が負のときには、電子はウェハWに入射できない。つまり、下部電極が正の電位のときには下部電極には電子が流入し、負の電位のときには下部電極にはイオンが流入する。
(4) In the case of FIG. 4A where no negative DC voltage is applied to the upper electrode, the potential of the upper electrode is 0. At this time, the electrons are accelerated by a small potential difference between the potential 0 of the upper electrode and the plasma potential, and then move at a constant speed. When the potential of the lower electrode is positive, the electrons on the wafer W Incident on the wafer W while decelerating in accordance with the voltage of. Therefore, when the potential of the lower electrode is positive, the difference between the plasma potential and the potential of the lower electrode is small, so that the energy of electrons that can be incident is also low. Therefore, electrons having various energies are incident on the wafer W. On the other hand, when the potential of the lower electrode is negative, electrons cannot enter the wafer W. That is, when the lower electrode has a positive potential, electrons flow into the lower electrode, and when the lower electrode has a negative potential, ions flow into the lower electrode.
図4(b)に示すように、LF電力及びHF電力を下部電極に印加し、かつ上部電極に負の直流電圧を印加したとき、電子は、負の直流電圧を印加しなかったときと比べて、上部電極の電位とプラズマ電位との電位差が大きくなり、その電位差によって電子はさらに加速する。その結果、電子は、プラズマ処理空間から下部電極へより直線的に高速に移動する。その結果、電子は、負の直流電圧を印加しなかったときと比べて、ウェハWに入射できる可能性が高まる。
As shown in FIG. 4B, when the LF power and the HF power are applied to the lower electrode and a negative DC voltage is applied to the upper electrode, the electrons are compared with the case where no negative DC voltage is applied. As a result, the potential difference between the potential of the upper electrode and the plasma potential increases, and the potential difference further accelerates the electrons. As a result, the electrons move more linearly and faster from the plasma processing space to the lower electrode. As a result, the possibility that electrons can be incident on the wafer W is increased as compared to when no negative DC voltage is applied.
ただし、下部電極の電位によっては、電子がウェハWに到達したときに又は到達する前に、電子の速度が0又は0に近くなってしまう。この場合、電子はホールの上面やホールの側面に付着し、ホール底に到達しない。そうすると、イオンも同様に電子が存在するホールの上面やホールの側面に引き込まれ、ホール底に到達しない。
However, depending on the potential of the lower electrode, the speed of the electrons becomes 0 or close to 0 when or before the electrons reach the wafer W. In this case, the electrons adhere to the top surface of the hole or the side surface of the hole and do not reach the bottom of the hole. Then, the ions are also drawn into the upper surface of the hole where the electrons are present or the side surface of the hole, and do not reach the bottom of the hole.
ウェハに到達する前に速度が0となった電子は、プラズマ電位によりプラズマ側に向かって逆方向に加速する。つまり、上部電極34に負の直流電圧を印加した場合、上部電極34側のシースで加速された電子がウェハに入射可能な下部電極の電位の範囲は、図4(b)に示す負の直流電圧と同じ大きさの電位Eの範囲となり、Fの範囲では電子の速度が0になって、電子はウェハに到達できない。電子がホール底まで到達しないと、ホール底を負にチャージアップさせることができない。この結果、ホール底におけるプラスのチャージアップをイオンによりキャンセルできない。
電子 Electrons whose velocity becomes 0 before reaching the wafer are accelerated in the opposite direction toward the plasma side by the plasma potential. That is, when a negative DC voltage is applied to the upper electrode 34, the range of the potential of the lower electrode where electrons accelerated by the sheath on the upper electrode 34 side can enter the wafer is the negative DC voltage shown in FIG. The range of the potential E is the same as the voltage, and in the range of F, the speed of the electrons becomes 0, and the electrons cannot reach the wafer. If the electrons do not reach the bottom of the hole, the bottom of the hole cannot be negatively charged up. As a result, positive charge-up at the bottom of the hole cannot be canceled by ions.
そこで、本実施形態の制御方法の一例としては、電極電位が正のときに、負の直流電圧を上部電極に印加する。これにより、電子が最も加速されるようにし、さらに、ウェハ上のシース電界は低い為に、シースでの減速を最小限に抑え、ホール底に効率よく電子を到達させる事ができる。これにより、イオンをホール底へ引き込み、かつ、エッチングの垂直性を高め、さらに、エッチングレートの低下を防ぐことができる。
Therefore, as an example of the control method of the present embodiment, when the electrode potential is positive, a negative DC voltage is applied to the upper electrode. As a result, electrons are accelerated most, and since the sheath electric field on the wafer is low, deceleration at the sheath can be minimized and electrons can efficiently reach the bottom of the hole. As a result, ions can be drawn into the bottom of the hole, the perpendicularity of etching can be increased, and a decrease in etching rate can be prevented.
例えば、上部電極34に図4(b)のDに示す負のDC電圧として-1000Vの直流電圧を印加したとする。この場合、電子は、-1000Vの電圧で加速され、さらに10V~30V程度のプラズマ電位の加速を受ける。加速された電子はプラズマ処理空間にてプラズマ中を、直進性を保ちながら等速で移動後、ウェハW上のシースにて減速し、ウェハ上のエッチング対象膜のホール底にほぼ垂直に打ち込まれる。これにより、ホール底は負にチャージアップされる。その後、ホール底に電子よりも質量の大きいイオンが遅れて到達する。これによりホール底はチャージキャンセルされる。
(4) For example, it is assumed that a DC voltage of -1000 V is applied to the upper electrode 34 as a negative DC voltage indicated by D in FIG. 4B. In this case, the electrons are accelerated at a voltage of -1000 V and further accelerated by a plasma potential of about 10 V to 30 V. The accelerated electrons move in the plasma in the plasma processing space at a constant speed while keeping the straightness, then decelerate by the sheath on the wafer W, and are driven almost perpendicularly to the hole bottom of the film to be etched on the wafer. . As a result, the hole bottom is charged up negatively. Thereafter, ions having a larger mass than the electrons reach the bottom of the hole with a delay. This cancels the charge at the bottom of the hole.
図5(a)は、比較例に係るDCの電圧の供給タイミングと電子及びイオンの動作の一例を示す。図5(b)は、本実施形態に係るDCの電圧の供給タイミングと電子及びイオンの動作の一例を示す。図5(a)の比較例では、電極電位の正負にかかわらず連続して直流電圧を印加する。これに対して、図5(b)の本実施形態では、電極電位が正のとき直流電圧を印加し、負のとき直流電圧の印加を停止する。
FIG. 5A shows an example of the supply timing of DC voltage and the operation of electrons and ions according to the comparative example. FIG. 5B shows an example of the supply timing of the DC voltage and the operation of electrons and ions according to the present embodiment. In the comparative example of FIG. 5A, a DC voltage is continuously applied regardless of whether the electrode potential is positive or negative. On the other hand, in the embodiment of FIG. 5B, when the electrode potential is positive, the DC voltage is applied, and when the electrode potential is negative, the application of the DC voltage is stopped.
図5(a)(b)の制御では、図5の下段の枠内に示すように、電極電位が正のときにはウェハ上のシースは薄くなる。よって、電極電位が正のときには、電子は、薄いシースを通過する際に減速が少なく、ウェハWに概ね垂直に到達しウェハWに入射する。この結果、図5(a)(b)の左側のホール内に示すように電子がホール底まで到達できる。
In the control of FIGS. 5A and 5B, as shown in the lower frame of FIG. 5, when the electrode potential is positive, the sheath on the wafer becomes thin. Therefore, when the electrode potential is positive, the electrons have little deceleration when passing through the thin sheath, reach the wafer W almost perpendicularly, and enter the wafer W. As a result, electrons can reach the bottom of the hole as shown in the hole on the left side of FIGS.
電極電位が負のときには、電極電位が正のときよりもウェハ上に厚いシースが形成される。よって、電極電位が負のときに直流電圧を印加すると、電子は、厚いシースを通過する際に減速し、図5(a)の下段右側のホール内に示すようにウェハWへ到着しないか、到着してもホールの上面や側面に付着し、電子のほとんどはホール底まで到達できない。ホールの側面に付着した電子は、イオンを引き入れ、ボーイングの発生要因の一つになる。
(4) When the electrode potential is negative, a thicker sheath is formed on the wafer than when the electrode potential is positive. Therefore, when a DC voltage is applied when the electrode potential is negative, the electrons decelerate when passing through the thick sheath and do not reach the wafer W as shown in the lower right hole of FIG. Even when they arrive, they adhere to the top and side surfaces of the hole, and most of the electrons cannot reach the bottom of the hole. Electrons attached to the side surface of the hole attract ions and become one of the causes of bowing.
一方、電極電位が負のときに直流電圧の印加を停止すると、電子は、厚いシースを通過する際にさらに減速し、図5(b)の下段右側のホール内に示すようにほとんどの電子の速度がウェハWへ到達できる前に0になる。その結果、ホールの上面や側面に付着する電子の数を少なくすることができる。
On the other hand, when the application of the DC voltage is stopped when the electrode potential is negative, the electrons further decelerate when passing through the thick sheath, and as shown in the lower right hole of FIG. The speed becomes zero before the wafer can reach the wafer W. As a result, the number of electrons adhering to the top and side surfaces of the hole can be reduced.
他の比較例では、LFの電圧とHFの電圧とを10kHz程度でオン・オフさせてパルス状に印加し、LFの電圧とHFの電圧のパルスのオフのタイミングで、-1000V程度の直流電圧を印加し、アフターグロー放電中の電子を加速させ、電子をホール底に打ち込み、その後のホール底へのイオン入射をし易くする。
In another comparative example, the LF voltage and the HF voltage are turned on / off at about 10 kHz and applied in a pulse form, and the DC voltage of about -1000 V is applied at the timing of turning off the pulses of the LF voltage and the HF voltage. Is applied to accelerate the electrons in the after-glow discharge, and bombard the electrons at the bottom of the hole, thereby facilitating the subsequent incidence of ions at the bottom of the hole.
しかし、この方法では、HFの電圧の印加を停止した後のアフターグロー放電中に残された電子は急激に減少するため、-1000V程度の直流電圧により加速される電子そのものが少なくなり、上記電子のホール底への打ち込み効果を十分に発揮できない場合がある。
However, in this method, the number of electrons that are left during the afterglow discharge after the application of the HF voltage is stopped rapidly decreases, so that the number of electrons accelerated by a DC voltage of about −1000 V decreases, and In some cases, the effect of driving into the hole bottom may not be sufficiently exhibited.
そこで、本実施形態では、電極電位が正のタイミングに上部電極に直流電圧をオンし、電子の加速を上げ、最速の電子を極力減速させずにホール内に入射させる。これにより、電子をホール底まで到達させ、追従するイオンをホール底へ引き込むことができる。また、電極電位が負のタイミングに上部電極への直流電圧の印加を止める。これにより、ホールの表面や側面に付着する電子の数を少なくすることができ、ボーイングの発生を回避し、エッチング形状の垂直にすることができる。
Therefore, in this embodiment, a DC voltage is applied to the upper electrode at a timing when the electrode potential is positive, the acceleration of the electrons is increased, and the fastest electrons are made to enter the hole without decelerating as much as possible. As a result, electrons can reach the bottom of the hole and follow ions can be drawn into the bottom of the hole. Further, the application of the DC voltage to the upper electrode is stopped when the electrode potential is negative. As a result, the number of electrons adhering to the surface or side surface of the hole can be reduced, so that the occurrence of bowing can be avoided and the etched shape can be made vertical.
このようにして、電極電位の正負に応じて直流電圧の供給タイミングを制御することでシースの厚さの変化に同期させ、イオンエネルギーを制御することができる。これにより、ホール底にイオンを引き込み、エッチングレートの低下を防ぐことができる。また、エッチング形状を垂直にすることができる。
Thus, by controlling the supply timing of the DC voltage according to the polarity of the electrode potential, the ion energy can be controlled in synchronization with the change in the thickness of the sheath. As a result, ions can be attracted to the bottom of the hole and a decrease in the etching rate can be prevented. Further, the etching shape can be made vertical.
なお、周波数の適正値については、LFの周波数が下がると、第1の高周波電源48から同じパワーのLFの電圧を導入したときに、プラズマ密度を高くする効果よりもイオンエネルギーを大きくする効果が高くなる。これにより、イオンをホール底へ引き込み、かつ、エッチングの垂直性を高めることができる。そこで、本実施形態に係る制御方法では、LFの周波数を400kHz又はそれ以下の周波数にすることが好ましい。これにより、さらに効率よくイオンをホール底へ引き込み、エッチングレートの低下を防ぐことができ、エッチング形状を垂直にすることができる。
Regarding the appropriate value of the frequency, when the frequency of the LF decreases, when the voltage of the LF having the same power is introduced from the first high frequency power supply 48, the effect of increasing the ion energy is higher than the effect of increasing the plasma density. Get higher. Thereby, ions can be drawn to the bottom of the hole and the perpendicularity of the etching can be improved. Therefore, in the control method according to the present embodiment, it is preferable that the frequency of the LF be 400 kHz or less. As a result, ions can be more efficiently drawn to the bottom of the hole, a decrease in the etching rate can be prevented, and the etching shape can be made vertical.
直流電圧は、電極電位が正のタイミングに負の値(以下、オンともいう。)に制御することが好ましいが、これに限られず、電極電位が正のタイミングを含む時間帯にオンに制御してもよいし、電極電位が正のピークを含むタイミングにオンに制御してもよい。また、直流電圧をオン及びオフする替わりに直流電圧を負の値で絶対値がHigh及びLowになるように制御してもよい。この場合、直流電圧をオンする替わりに直流電圧を負の値であって絶対値がLowよりも大きいHighになるように制御し、直流電圧をオフする替わりに直流電圧を負の値であってLowになるように制御してもよい。このとき、直流電圧は、電極電位が正のタイミングにHighに制御することが好ましい。ただし、これに限られず、電極電位が正のタイミングを含む時間帯にHighになるように制御してもよい。
It is preferable that the DC voltage is controlled to a negative value (hereinafter, also referred to as “ON”) when the electrode potential is positive, but the present invention is not limited to this, and the DC voltage is controlled to be ON during a time period including the positive timing. Alternatively, it may be turned on at a timing when the electrode potential includes a positive peak. Further, instead of turning on and off the DC voltage, the DC voltage may be controlled so that the absolute value becomes a high value and a low value with a negative value. In this case, instead of turning on the DC voltage, the DC voltage is controlled to be a negative value and the absolute value is set to be higher than Low, and instead of turning off the DC voltage, the DC voltage is set to a negative value. Control may be performed so as to be Low. At this time, it is preferable that the DC voltage is controlled to be High when the electrode potential is positive. However, the present invention is not limited to this, and control may be performed so that the electrode potential becomes High in a time zone including a positive timing.
また、直流電圧は、電極電位が正のタイミングに一致させた矩形波だけでなく、立ち上がりのスローアップ又は立ち下がりのスローダウンの少なくともいずれかを含む略矩形波を印加してもよい。また、直流電圧は、電極電位が正のタイミングから所定時間だけ後にずらしたタイミング又は所定時間だけ前にずらしたタイミングの少なくともいずれかに印加してもよい。
The DC voltage may be not only a rectangular wave whose electrode potential coincides with a positive timing but also a substantially rectangular wave including at least one of a rising slow-down and a falling slow-down. The DC voltage may be applied at least at a timing when the electrode potential is shifted by a predetermined time from the positive timing or at a timing when the electrode potential is shifted by a predetermined time.
電極電位の特に正側の波形は、LFの周波数やガス種や圧力に依存して歪む場合がある。このような場合は、電極電位が正のタイミングから所定時間だけずらして、よりシースが薄く電子が入りやすいタイミングを選定して直流電圧を印加することが好ましい。
特 に The waveform of the electrode potential, especially on the positive side, may be distorted depending on the frequency of LF, gas type, and pressure. In such a case, it is preferable to apply a DC voltage by shifting the electrode potential by a predetermined time from the positive timing and selecting a timing at which the sheath is thinner and electrons easily enter.
また、直流電圧は、電極電位が正のタイミングに対して所定時間だけ長く又は短くするように印加時間の幅を調整してもよい。また、直流電圧の制御とともに、電極電位が正のタイミングを含む時間帯、HFの電力をオンしてもよい。このとき、電極電位が正のタイミングに一致させてHFの電力をオンし、電極電位が負のタイミングに一致させてHFの電力の供給をオフしてもよい。LFの電力の各周期内の部分期間に、直流電圧とHFの電力との両方印加し、残りの期間で直流電圧とHFの電力との両方をオフにしてもよい。また、直流電圧とHFの電力とをオンする替わりに直流電圧とHFの電力とを負の値であってHighになるように制御し、直流電圧とHFの電力とをオフする替わりに直流電圧とHFの電力とを負の値であってLowになるように制御してもよい。
The DC voltage may be adjusted in the width of the application time so that the electrode potential is longer or shorter by a predetermined time than the positive timing. In addition to the control of the DC voltage, the power of the HF may be turned on during a time period including the timing when the electrode potential is positive. At this time, the power of the HF may be turned on when the electrode potential matches the positive timing, and the supply of the HF power may be turned off when the electrode potential matches the negative timing. Both the DC voltage and the HF power may be applied during a partial period of each cycle of the LF power, and both the DC voltage and the HF power may be turned off during the remaining period. Further, instead of turning on the DC voltage and the power of the HF, the DC voltage and the power of the HF are controlled to be negative and high, and the DC voltage is turned off instead of turning off the DC voltage and the power of the HF. And the power of the HF may be controlled to be negative values and low.
[制御方法]
以上に説明したように、一実施形態に係る平行平板型のプラズマ処理装置1の制御方法は、バイアスパワーを、ウェハWを載置する下部電極に供給する工程と、負の直流電圧を上部電極に供給する工程とを含む。該制御方法では、図3及び図5(b)に示すように、負の直流電圧は、第1の電圧値をとる第1の状態と、絶対値が前記第1の電圧値よりも小さい第2の電圧値をとる第2の状態とを有し、第1の状態を、前記バイアスパワーの高周波の周期に同期する信号の各周期内の部分期間、又はバイアスパワーの伝達経路で測定された、周期的に変動するパラメータの各周期内の部分期間に印加し、第2の状態を第1の状態と連続して印加する第1制御工程を含む。周期的に変動するパラメータは、電圧、電流、電磁界、発生したプラズマの発光の変化又はウェハ上のプラズマのシース厚の変化であってもよい。 [Control method]
As described above, the control method of the parallel plate typeplasma processing apparatus 1 according to one embodiment includes a step of supplying bias power to the lower electrode on which the wafer W is mounted, and a step of supplying a negative DC voltage to the upper electrode. And supplying to In the control method, as shown in FIG. 3 and FIG. 5 (b), the negative DC voltage has a first state in which it takes a first voltage value and a negative DC voltage in which a negative DC voltage has a smaller absolute value than the first voltage value. A second state having a voltage value of 2 and the first state is measured in a sub-period within each cycle of the signal synchronized with the high-frequency cycle of the bias power, or in a transmission path of the bias power. A first control step of applying a periodically varying parameter during a partial period within each cycle and applying the second state continuously with the first state. The periodically fluctuating parameter may be a voltage, a current, an electromagnetic field, a change in the emission of the generated plasma or a change in the sheath thickness of the plasma on the wafer.
以上に説明したように、一実施形態に係る平行平板型のプラズマ処理装置1の制御方法は、バイアスパワーを、ウェハWを載置する下部電極に供給する工程と、負の直流電圧を上部電極に供給する工程とを含む。該制御方法では、図3及び図5(b)に示すように、負の直流電圧は、第1の電圧値をとる第1の状態と、絶対値が前記第1の電圧値よりも小さい第2の電圧値をとる第2の状態とを有し、第1の状態を、前記バイアスパワーの高周波の周期に同期する信号の各周期内の部分期間、又はバイアスパワーの伝達経路で測定された、周期的に変動するパラメータの各周期内の部分期間に印加し、第2の状態を第1の状態と連続して印加する第1制御工程を含む。周期的に変動するパラメータは、電圧、電流、電磁界、発生したプラズマの発光の変化又はウェハ上のプラズマのシース厚の変化であってもよい。 [Control method]
As described above, the control method of the parallel plate type
図5(b)に示すように、直流電圧がオン(DC on、DCが負に印加)されている状態は、第1の状態の一例である。直流電圧がオフ(DC off、DCが0)されている状態は、第2の状態の一例である。第1制御工程では、第1の状態と第2の状態とが繰り返される。
状態 As shown in FIG. 5B, the state where the DC voltage is turned on (DC on, DC is applied negatively) is an example of the first state. The state where the DC voltage is off (DC off, DC is 0) is an example of the second state. In the first control step, the first state and the second state are repeated.
DCの電圧をオン・オフする替わりに、負の値であって絶対値がHigh・Lowに制御されてもよい。この場合、DCの電圧が負の値であって絶対値がHighに制御されている状態は、第1の状態の一例である。DCの電圧が負の値であって絶対値がHighよりも小さいLowに制御されている状態は、第2の状態の一例である。例えば、第2の状態のDCの電圧は0であってもよいし、負の値であって絶対値がHighよりも小さい値であってもよい。
Instead of turning on / off the DC voltage, a negative value and the absolute value may be controlled to High / Low. In this case, the state where the DC voltage is a negative value and the absolute value is controlled to High is an example of the first state. The state in which the DC voltage is a negative value and the absolute value is controlled to be lower than High is an example of the second state. For example, the DC voltage in the second state may be 0, or may be a negative value whose absolute value is smaller than High.
[変形例1-1~1-4]
次に、一実施形態の変形例1-1~1-4に係るプラズマ処理装置1の制御方法について説明する。変形例1-1~1-4では、バイアスパワーとDCの電圧とのいずれか又は両方を間欠的に停止する制御を行う。図6A~図6Dは、一実施形態の変形例1-1~1-4に係る制御方法を示すタイミングチャートである。 [Modifications 1-1 to 1-4]
Next, a control method of theplasma processing apparatus 1 according to modified examples 1-1 to 1-4 of the embodiment will be described. In the modified examples 1-1 to 1-4, control for intermittently stopping one or both of the bias power and the DC voltage is performed. 6A to 6D are timing charts illustrating control methods according to modified examples 1-1 to 1-4 of the embodiment.
次に、一実施形態の変形例1-1~1-4に係るプラズマ処理装置1の制御方法について説明する。変形例1-1~1-4では、バイアスパワーとDCの電圧とのいずれか又は両方を間欠的に停止する制御を行う。図6A~図6Dは、一実施形態の変形例1-1~1-4に係る制御方法を示すタイミングチャートである。 [Modifications 1-1 to 1-4]
Next, a control method of the
図6Aの変形例1-1では、第1制御工程に加えて、DCの電圧を、LF電圧により一例を示す周期的に変動するパラメータ又はバイアスパワーの高周波の周期に同期する信号の周期と独立した周期で間欠的に停止する第2制御工程を含む。第1制御工程と第2制御工程とは繰り返し実行される。
In the modified example 1-1 of FIG. 6A, in addition to the first control step, the DC voltage is independent of the period of a signal that is synchronized with the period of a periodically varying parameter or the high frequency of the bias power, which is shown by an example of the LF voltage. A second control step of intermittently stopping at the set cycle. The first control step and the second control step are repeatedly executed.
変形例1-1では、LF電圧は、第1制御工程及び第2制御工程において同じ周期で印加される。一方、DCの電圧は、第1制御工程において第1の状態と第2の状態とを交互に1回以上繰り返し、第2制御工程において第1制御工程の間で間欠的に停止される。
In the modification 1-1, the LF voltage is applied in the same cycle in the first control step and the second control step. On the other hand, the DC voltage alternates between the first state and the second state at least once in the first control step, and is intermittently stopped in the second control step between the first control steps.
第1制御工程及び第2制御工程では、LFの周波数は、例えば0.1Hz~100kHzであってもよい。なお、DCの電圧のDuty比(=第4の状態/(第3の状態+第4の状態))は、1%~99%の範囲内であればよい。
で は In the first control step and the second control step, the frequency of the LF may be, for example, 0.1 Hz to 100 kHz. The duty ratio of the DC voltage (= fourth state / (third state + fourth state)) may be in the range of 1% to 99%.
第1制御工程におけるLF電圧が正のタイミングで同期したDCの電圧が第1の状態をとるのが、第3の状態の一例である。第2制御工程におけるLF電圧の周期と独立したDCの電圧の状態は、第3の状態と異なる第4の状態の一例である。
DC An example of the third state is that the DC voltage synchronized with the LF voltage in the first control step at the positive timing takes the first state. The state of the DC voltage independent of the cycle of the LF voltage in the second control step is an example of a fourth state different from the third state.
図6Bの変形例1-2にかかる制御方法は、変形例1-1と同じ第1制御工程に加えて、バイアスパワー(LF電圧)をDCの電圧の周期とは独立した周期で間欠的に停止する第3制御工程を含む。第3制御工程におけるバイアスパワーの状態は、第4の状態の一例である。
The control method according to the modified example 1-2 of FIG. 6B includes, in addition to the same first control step as the modified example 1-1, intermittently changing the bias power (LF voltage) at a cycle independent of the cycle of the DC voltage. A third control step of stopping is included. The state of the bias power in the third control step is an example of the fourth state.
変形例1-2では、第1制御工程と第3制御工程とが繰り返し実行される。変形例1-2では、第3制御工程におけるDCの電圧は、第1制御工程と同じ周期で第1の状態と第2の状態とが繰り返される。
In the modification 1-2, the first control step and the third control step are repeatedly executed. In the modified example 1-2, the DC voltage in the third control step is such that the first state and the second state are repeated in the same cycle as in the first control step.
なお、第1制御工程においてLFの周波数は、例えば0.1Hz~100Hzであってもよく、LFの電圧のDuty比(=第4の状態/(第3の状態+第4の状態))は、1%~90%の範囲内であればよい。
In the first control step, the frequency of the LF may be, for example, 0.1 Hz to 100 Hz, and the duty ratio of the voltage of the LF (= the fourth state / (the third state + the fourth state)) , May be in the range of 1% to 90%.
図6Cの変形例1-3にかかる制御方法は、変形例1-1と同じ第1制御工程に加えて、変形例1-1の第2制御工程のDCの制御と変形例1-2の第3制御工程のLFの制御が行われる。つまり、変形例1-3におけるDCの電圧及びバイアスパワーの両方を間欠的に停止した状態は、第4の状態の一例である。
The control method according to the modified example 1-3 in FIG. 6C includes, in addition to the same first control step as the modified example 1-1, the DC control in the second control step of the modified example 1-1 and the control method of the modified example 1-2. The LF control in the third control step is performed. That is, the state where both the DC voltage and the bias power are intermittently stopped in the modified example 1-3 is an example of the fourth state.
バイアスパワーを間欠的に停止する周期とDCの電圧を間欠的に停止する周期とは同期させてもよい。この場合、DC及びバイアスパワーを間欠的に停止する周期は、図6Cに示すように一致してもよいし、図6Dに示すように、DCがバイアスパワーよりも後ろにずれていてもよいし、DCがバイアスパワーよりも前にずれていてもよい。
The cycle in which the bias power is intermittently stopped and the cycle in which the DC voltage is intermittently stopped may be synchronized. In this case, the cycle of intermittently stopping the DC and the bias power may be the same as shown in FIG. 6C, or the DC may be shifted behind the bias power as shown in FIG. 6D. , DC may be shifted before the bias power.
なお、図6A~図6Dでは、第3の状態において、バイアスパワーが正の一部のタイミングに、DCの電圧をオンしているが、これに限られない。また、DCの電圧を周期的にオン・オフする替わりに、DCの電圧を負の値であって周期的に絶対値がHigh・Lowになるように制御してもよい。
6A to 6D, in the third state, the DC voltage is turned on at a part of the timing when the bias power is positive, but the present invention is not limited to this. Further, instead of periodically turning on / off the DC voltage, the DC voltage may be controlled to be a negative value and the absolute value periodically becomes High / Low.
[変形例2]
次に、一実施形態の変形例2に係る制御方法について、図7を参照して説明する。図7は、一実施形態の変形例2に係る制御方法を示すタイミングチャートである。 [Modification 2]
Next, a control method according to a second modification of the embodiment will be described with reference to FIG. FIG. 7 is a timing chart illustrating a control method according to Modification 2 of the embodiment.
次に、一実施形態の変形例2に係る制御方法について、図7を参照して説明する。図7は、一実施形態の変形例2に係る制御方法を示すタイミングチャートである。 [Modification 2]
Next, a control method according to a second modification of the embodiment will be described with reference to FIG. FIG. 7 is a timing chart illustrating a control method according to Modification 2 of the embodiment.
例えば、変形例2に係る制御方法では、図7に示すようにLFの電圧のピークに対応するパルス状の電力(以下、「LFパルス」ともいう。)が載置台16に印加される。LFパルスの正の値は、LFの電圧の正のピークに一致し、LFパルスの負の値は、LFの電圧の負のピークに一致する。
For example, in the control method according to the second modification, as shown in FIG. 7, pulse-like power (hereinafter, also referred to as “LF pulse”) corresponding to the peak of the LF voltage is applied to the mounting table 16. A positive value of the LF pulse corresponds to a positive peak of the voltage of the LF, and a negative value of the LF pulse corresponds to a negative peak of the voltage of the LF.
この場合、変形例2に係る制御方法では、負の直流電圧は第1の状態と第2の状態とを周期的に繰り返し、第1の状態を、LFパルスの各周期内の部分期間に印加し、第2の状態を第1の状態と連続して印加する。これによっても、イオンエネルギーを制御し、エッチングレートの低下を防ぐことができる。
In this case, in the control method according to the second modification, the negative DC voltage periodically repeats the first state and the second state, and applies the first state to a partial period in each cycle of the LF pulse. Then, the second state is applied continuously to the first state. This also controls the ion energy and can prevent a decrease in the etching rate.
具体的には、LFパルスが正の間の一部又は全部においてDCの電圧を負にオンまたは負の値であって絶対値がHighになるように制御し、LFパルスが負の間の一部又は全部においてDCの電圧をオフ又は負の値であって絶対値がLowになるように制御してもよい。これによれば、LFパルスが2値化されており、これに応じてDCの電圧を2値化して制御するため、制御が容易になる。
More specifically, the DC voltage is negatively turned on or controlled to be a negative value and the absolute value becomes High during a part or all of the period when the LF pulse is positive. The DC voltage may be controlled to be off or a negative value and the absolute value thereof may be low in all or a part. According to this, since the LF pulse is binarized and the DC voltage is binarized and controlled in accordance with the binarization, the control becomes easy.
[変形例3-1、3-2]
次に、一実施形態の変形例3-1、3-2に係る制御方法について、図8A及び図8Bを参照して説明する。図8Aは、一実施形態の変形例3-1に係る制御方法を示すタイミングチャートである。図8Bは、一実施形態の変形例3-2に係る制御方法を示すタイミングチャートである。 [Modifications 3-1 and 3-2]
Next, a control method according to modified examples 3-1 and 3-2 of the embodiment will be described with reference to FIGS. 8A and 8B. FIG. 8A is a timing chart illustrating a control method according to Modification 3-1 of the embodiment. FIG. 8B is a timing chart illustrating a control method according to Modification 3-2 of the embodiment.
次に、一実施形態の変形例3-1、3-2に係る制御方法について、図8A及び図8Bを参照して説明する。図8Aは、一実施形態の変形例3-1に係る制御方法を示すタイミングチャートである。図8Bは、一実施形態の変形例3-2に係る制御方法を示すタイミングチャートである。 [Modifications 3-1 and 3-2]
Next, a control method according to modified examples 3-1 and 3-2 of the embodiment will be described with reference to FIGS. 8A and 8B. FIG. 8A is a timing chart illustrating a control method according to Modification 3-1 of the embodiment. FIG. 8B is a timing chart illustrating a control method according to Modification 3-2 of the embodiment.
例えば、変形例3-1、3-2に係る制御方法では、DCの電圧の第1の状態を、電極電位を一例とする周期的に変動するパラメータ又はバイアスパワーの高周波の周期に同期する信号が正の値を含む部分期間に印加し、第2の状態を第1の状態と連続して印加する。変形例3-1では、DCの電圧の第1の状態が、負の値であって段階的に2つ以上の電圧値を有する。また、変形例3-2では、DCの電圧の第1の状態が、負の値であって滑らかに2つ以上の電圧値を有する。ただし、DCの電圧の第1の状態は、電極電位が負の値を含む部分期間に印加してもよい。変形例3-1、3-2では、第1の状態におけるDCの電圧を複数の値に制御することで、より精度良くイオンエネルギーを制御し、エッチングレートの低下を防ぐことができる。
For example, in the control methods according to Modification Examples 3-1 and 3-2, the first state of the DC voltage is a signal that synchronizes with a periodically changing parameter, such as an electrode potential, or a high-frequency cycle of bias power. Is applied during a partial period including a positive value, and the second state is applied continuously to the first state. In the modified example 3-1, the first state of the DC voltage is a negative value and has two or more voltage values stepwise. In the modified example 3-2, the first state of the DC voltage is a negative value and smoothly has two or more voltage values. However, the first state of the DC voltage may be applied during a partial period in which the electrode potential includes a negative value. In the modified examples 3-1 and 3-2, by controlling the DC voltage in the first state to a plurality of values, it is possible to more accurately control the ion energy and prevent a decrease in the etching rate.
[変形例4]
変形例4では、DCの電圧の第1の状態が、2つ以上の電圧値を繰り返すパルス状の電圧値をとる。図9の例では、DCの電圧の第1の状態は、負の値の電圧値と0の電圧値とを繰り返す。ただし、これに限られず、3つの電圧値を繰り返す等、2つ以上の電圧値を繰り返してもよい。 [Modification 4]
In the fourth modification, the first state of the DC voltage takes a pulse-like voltage value that repeats two or more voltage values. In the example of FIG. 9, the first state of the DC voltage repeats a negative voltage value and a zero voltage value. However, the present invention is not limited to this, and two or more voltage values may be repeated, such as repeating three voltage values.
変形例4では、DCの電圧の第1の状態が、2つ以上の電圧値を繰り返すパルス状の電圧値をとる。図9の例では、DCの電圧の第1の状態は、負の値の電圧値と0の電圧値とを繰り返す。ただし、これに限られず、3つの電圧値を繰り返す等、2つ以上の電圧値を繰り返してもよい。 [Modification 4]
In the fourth modification, the first state of the DC voltage takes a pulse-like voltage value that repeats two or more voltage values. In the example of FIG. 9, the first state of the DC voltage repeats a negative voltage value and a zero voltage value. However, the present invention is not limited to this, and two or more voltage values may be repeated, such as repeating three voltage values.
[変形例5]
バイアスパワーは、サイン波形又はパルス波形のパワーであってもよいし、テイラード波形のパワーであってもよい。つまり、バイアスの電圧又は電流は、サイン波形であってもよいし、LFパルス波形であってもよいし、図10に示すテイラード波形でもよい。テイラード波形では、図10に示すDCが第2の状態のときにバイアスのパワーを変調してもよいし、第1の状態のときにバイアスのパワーを変調してもよい。 [Modification 5]
The bias power may be a sine waveform or a pulse waveform power, or may be a tailored waveform power. That is, the bias voltage or current may be a sine waveform, an LF pulse waveform, or a tailored waveform shown in FIG. In the tailored waveform, the bias power may be modulated when DC shown in FIG. 10 is in the second state, or the bias power may be modulated when DC is in the first state.
バイアスパワーは、サイン波形又はパルス波形のパワーであってもよいし、テイラード波形のパワーであってもよい。つまり、バイアスの電圧又は電流は、サイン波形であってもよいし、LFパルス波形であってもよいし、図10に示すテイラード波形でもよい。テイラード波形では、図10に示すDCが第2の状態のときにバイアスのパワーを変調してもよいし、第1の状態のときにバイアスのパワーを変調してもよい。 [Modification 5]
The bias power may be a sine waveform or a pulse waveform power, or may be a tailored waveform power. That is, the bias voltage or current may be a sine waveform, an LF pulse waveform, or a tailored waveform shown in FIG. In the tailored waveform, the bias power may be modulated when DC shown in FIG. 10 is in the second state, or the bias power may be modulated when DC is in the first state.
なお、同様にして、DCの第1の状態が2つ以上の電圧値をとる場合、DCの波形は、図8A、図8B、図9に示す波形の他、図10に示すテイラード波形でもよい。
(その他)
制御部200の制御について付記する。
(付記1)
制御部200は、前記第1の状態の期間にソースパワーを供給してもよい。すなわち、ソースパワーは、互いに異なる電圧値をとる第1の状態と第2の状態とを有し、前記第1の状態を、前記バイアスパワーの高周波の周期に同期する信号の各周期内の部分期間、又は前記バイアスパワーの伝達経路で測定された、周期的に変動するパラメータの各周期内の部分期間に印加し、第2の状態を前記第1の状態と連続して印加してもよい。
(付記2)
制御部200は、前記電極電位が正のタイミングにソースパワー及び負の直流電圧の少なくともいずれかを供給してもよい。 Similarly, when the first state of DC takes two or more voltage values, the DC waveform may be the tailored waveform shown in FIG. 10 in addition to the waveforms shown in FIGS. 8A, 8B, and 9. .
(Other)
The control of thecontrol unit 200 will be additionally described.
(Appendix 1)
Thecontrol unit 200 may supply the source power during the first state. That is, the source power has a first state and a second state having different voltage values from each other, and the source state has a portion within each cycle of a signal synchronized with the high frequency cycle of the bias power. The second state may be applied continuously to the first state during a period or a partial period within each period of a periodically varying parameter measured in the bias power transmission path. .
(Appendix 2)
Thecontrol unit 200 may supply at least one of the source power and the negative DC voltage when the electrode potential is positive.
(その他)
制御部200の制御について付記する。
(付記1)
制御部200は、前記第1の状態の期間にソースパワーを供給してもよい。すなわち、ソースパワーは、互いに異なる電圧値をとる第1の状態と第2の状態とを有し、前記第1の状態を、前記バイアスパワーの高周波の周期に同期する信号の各周期内の部分期間、又は前記バイアスパワーの伝達経路で測定された、周期的に変動するパラメータの各周期内の部分期間に印加し、第2の状態を前記第1の状態と連続して印加してもよい。
(付記2)
制御部200は、前記電極電位が正のタイミングにソースパワー及び負の直流電圧の少なくともいずれかを供給してもよい。 Similarly, when the first state of DC takes two or more voltage values, the DC waveform may be the tailored waveform shown in FIG. 10 in addition to the waveforms shown in FIGS. 8A, 8B, and 9. .
(Other)
The control of the
(Appendix 1)
The
(Appendix 2)
The
以上、制御方法及びプラズマ処理装置を上記実施形態により説明したが、本開示にかかる制御方法及びプラズマ処理装置は上記実施形態に限定されるものではなく、本開示の範囲内で種々の変形及び改良が可能である。上記複数の実施形態に記載された事項は、矛盾しない範囲で組み合わせることができる。また、一実施形態及び複数の変形例は、矛盾しない範囲で組み合わせることができる。
As described above, the control method and the plasma processing apparatus have been described in the above embodiments. However, the control method and the plasma processing apparatus according to the present disclosure are not limited to the above embodiments, and various modifications and improvements may be made within the scope of the present disclosure. Is possible. The matters described in the above embodiments can be combined within a range that does not contradict. In addition, one embodiment and a plurality of modified examples can be combined within a range not inconsistent.
本開示に係るプラズマ処理装置は、Capacitively Coupled Plasma(CCP)、Inductively Coupled Plasma(ICP)、Radial Line Slot Antenna(RLSA)、Electron Cyclotron Resonance Plasma(ECR)、Helicon Wave Plasma(HWP)のどのタイプにも適用可能である。
The plasma processing apparatus according to the present disclosure is Capacitively Coupled Plasma (CCP), Inductively Coupled Plasma (ICP), Radial Line Slot Slot Antenna (RLSA), Electron Cyclotron Resonance Plasma (ECR), any type of Helicon Wave Plasma (HWP) Applicable.
本明細書では、被処理体の一例としてウェハWを挙げて説明した。しかし、基板は、これに限らず、LCD(Liquid Crystal Display)、FPD(Flat Panel Display)に用いられる各種基板、CD基板、プリント基板等であっても良い。
で は In this specification, the wafer W has been described as an example of the object to be processed. However, the substrate is not limited to this, and may be various substrates used for LCD (Liquid Crystal Display), FPD (Flat Panel Display), a CD substrate, a printed substrate, or the like.
本国際出願は、2018年7月30日に出願された日本国特許出願2018-142855号に基づく優先権及び2019年6月10日に出願された日本国特許出願2019-108223号に基づく優先権を主張するものであり、その全内容を本国際出願に援用する。
This international application filed a priority based on Japanese Patent Application No. 2018-142855 filed on July 30, 2018 and a priority based on Japanese Patent Application No. 2019-108223 filed on June 10, 2018. , The entire contents of which are incorporated into this International Application.
10…処理容器
16…載置台(下部電極)
34…上部電極
47…給電棒
46…整合器
48…第1の高周波電源
50…可変直流電源
66…処理ガス供給源
84…排気装置
88…整合器
89…給電棒
90…第2の高周波電源
91…GNDブロック
100…プロセッサ
102…信号発生回路
200…制御部 10Processing container 16 Mounting table (lower electrode)
34upper electrode 47 power supply rod 46 matching device 48 first high frequency power supply 50 variable DC power supply 66 processing gas supply source 84 exhaust device 88 matching device 89 power supply rod 90 second high frequency power supply 91 ... GND block 100 ... processor 102 ... signal generation circuit 200 ... control unit
16…載置台(下部電極)
34…上部電極
47…給電棒
46…整合器
48…第1の高周波電源
50…可変直流電源
66…処理ガス供給源
84…排気装置
88…整合器
89…給電棒
90…第2の高周波電源
91…GNDブロック
100…プロセッサ
102…信号発生回路
200…制御部 10
34
Claims (12)
- 被処理体を載置する第1の電極と、前記第1の電極に対向する第2の電極とを有するプラズマ処理装置の制御方法であって、
バイアスパワーを前記第1の電極へ供給する工程と、
負の直流電圧を前記第2の電極に供給する工程と、
を有し、
前記負の直流電圧は、第1の電圧値をとる第1の状態と、絶対値が前記第1の電圧値よりも小さい第2の電圧値をとる第2の状態とを周期的に繰り返し、
前記第1の状態を、前記バイアスパワーの高周波の周期に同期する信号の各周期内の部分期間、又は前記バイアスパワーの伝達経路で測定された、周期的に変動するパラメータの各周期内の部分期間に印加し、前記第2の状態を前記第1の状態と連続して印加する第1制御工程を含む、制御方法。 A method for controlling a plasma processing apparatus, comprising: a first electrode on which an object to be processed is placed, and a second electrode facing the first electrode,
Supplying bias power to the first electrode;
Supplying a negative DC voltage to the second electrode;
Has,
The negative DC voltage periodically repeats a first state having a first voltage value and a second state having an absolute value having a second voltage value smaller than the first voltage value,
Changing the first state to a sub-period within each period of a signal synchronized with a high-frequency period of the bias power, or a sub-period within each period of a periodically fluctuating parameter measured on a transmission path of the bias power. A control method, comprising: a first control step of applying the voltage during a period and applying the second state continuously with the first state. - 前記周期的に変動するパラメータは、電圧、電流、電磁界、発生したプラズマの発光の変化又は被処理体上のプラズマのシース厚の変化である、
請求項1に記載の制御方法。 The periodically fluctuating parameter is a voltage, a current, an electromagnetic field, a change in the emission of the generated plasma or a change in the sheath thickness of the plasma on the object to be processed.
The control method according to claim 1. - 前記部分期間は、前記バイアスパワーの高周波の周期に同期する信号又は前記周期的に変動するパラメータが正のピークとなるタイミングを含む、
請求項1又は2のいずれか一項に記載の制御方法。 The partial period includes a signal synchronized with a high-frequency cycle of the bias power or a timing at which the periodically fluctuating parameter has a positive peak,
The control method according to claim 1. - 前記負の直流電圧を、前記バイアスパワーの高周波の周期に同期する信号又は前記周期的に変動するパラメータの周期とは独立した周期で間欠的に停止する第2制御工程をさらに含む、
請求項1~3のいずれか一項に記載の制御方法。 The negative DC voltage further includes a second control step of intermittently stopping at a cycle independent of a cycle of the signal or the periodically varying parameter synchronized with a cycle of a high frequency of the bias power.
The control method according to any one of claims 1 to 3. - 前記バイアスパワーを前記負の直流電圧の周期とは独立した周期で間欠的に停止する第3制御工程を含む、
請求項1~4のいずれか一項に記載の制御方法。 A third control step of intermittently stopping the bias power at a cycle independent of a cycle of the negative DC voltage,
The control method according to any one of claims 1 to 4. - 前記負の直流電圧を、前記バイアスパワーの高周波の周期に同期する信号又は前記周期的に変動するパラメータの周期とは独立した周期で間欠的に停止する第2制御工程と、
前記バイアスパワーを前記負の直流電圧の周期とは独立した周期で間欠的に停止する第3制御工程とを含み、
前記第2制御工程と前記第3制御工程とは同期する、
請求項1~3のいずれか一項に記載の制御方法。 A second control step of intermittently stopping the negative DC voltage at a cycle independent of the cycle of the signal or the periodically varying parameter synchronized with the cycle of the high frequency of the bias power;
A third control step of intermittently stopping the bias power at a cycle independent of a cycle of the negative DC voltage,
The second control step and the third control step are synchronized with each other;
The control method according to any one of claims 1 to 3. - 前記バイアスパワーは、サイン波形、パルス波形又はテイラード波形のパワーである、
請求項1~6のいずれか一項に記載の制御方法。 The bias power is a sine waveform, a pulse waveform or a tailored waveform power,
The control method according to any one of claims 1 to 6. - 前記第1の状態が2つ以上の電圧値をとる、
請求項1~7のいずれか一項に記載の制御方法。 The first state has two or more voltage values;
The control method according to any one of claims 1 to 7. - 前記第2の状態が2つ以上の電圧値をとる、
請求項1~8のいずれか一項に記載の制御方法。 The second state has two or more voltage values;
The control method according to any one of claims 1 to 8. - 前記第2の状態の電圧値は0である、
請求項1~9のいずれか一項に記載の制御方法。 The voltage value in the second state is 0,
The control method according to any one of claims 1 to 9. - 被処理体を載置する第1の電極と、
前記第1の電極と対向する第2の電極と、
前記第1の電極にバイアスパワーを供給するバイアス電源と、
前記第2の電極に負の直流電圧を供給する直流電源と、
前記バイアスパワー及び前記直流電圧を制御する制御部と、を有するプラズマ処理装置であって、
前記負の直流電圧は、第1の電圧値をとる第1の状態と、絶対値が前記第1の電圧値よりも小さい第2の電圧値をとる第2の状態とを周期的に繰り返し、
前記制御部は、
前記第1の状態を、前記バイアスパワーの高周波の周期に同期する信号の各周期内の部分期間、又は前記バイアスパワーの伝達経路で測定された、周期的に変動するパラメータの各周期内の部分期間に印加し、前記第2の状態を前記第1の状態と連続して印加するように制御する、
プラズマ処理装置。 A first electrode on which the object is placed;
A second electrode facing the first electrode;
A bias power supply for supplying a bias power to the first electrode;
A DC power supply for supplying a negative DC voltage to the second electrode;
A control unit for controlling the bias power and the DC voltage,
The negative DC voltage periodically repeats a first state that takes a first voltage value and a second state that takes a second voltage value whose absolute value is smaller than the first voltage value,
The control unit includes:
Changing the first state to a sub-period within each period of a signal synchronized with the high-frequency period of the bias power, or a sub-period within each period of a periodically varying parameter measured on the transmission path of the bias power. Control during the period, so that the second state is continuously applied to the first state.
Plasma processing equipment. - 前記制御部が、
前記バイアスパワーの高周波の周期に同期する信号又は前記周期的に変動するパラメータに同期する同期信号を作成し、該同期信号から前記直流電圧を出力する直流電源用の制御信号を生成し、前記直流電源に送信する、
請求項11に記載のプラズマ処理装置。 The control unit includes:
A signal synchronizing with a high-frequency cycle of the bias power or a synchronizing signal synchronizing with the periodically fluctuating parameter is generated, and a control signal for a DC power supply that outputs the DC voltage is generated from the synchronizing signal. Send to power,
A plasma processing apparatus according to claim 11.
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