WO2020024570A1 - 相位调整装置以及太赫兹信号的提取系统 - Google Patents

相位调整装置以及太赫兹信号的提取系统 Download PDF

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Publication number
WO2020024570A1
WO2020024570A1 PCT/CN2019/073337 CN2019073337W WO2020024570A1 WO 2020024570 A1 WO2020024570 A1 WO 2020024570A1 CN 2019073337 W CN2019073337 W CN 2019073337W WO 2020024570 A1 WO2020024570 A1 WO 2020024570A1
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Prior art keywords
signal
phase
counter
frequency
output
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PCT/CN2019/073337
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English (en)
French (fr)
Inventor
邓仕发
潘奕
丁庆
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深圳市太赫兹科技创新研究院
雄安华讯方舟科技有限公司
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Publication of WO2020024570A1 publication Critical patent/WO2020024570A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider

Definitions

  • the invention relates to the field of electronic circuits, in particular to a phase adjustment device and a terahertz signal extraction system.
  • the terahertz signal currently has a wide range of applications in many fields.
  • the traditional terahertz signal acquisition process generally uses an antenna as the signal receiving end.
  • the received signal is then amplified by the preamplifier for data acquisition.
  • Such a collection process will be accompanied by relatively large noise and interference signals, and it is difficult to capture the terahertz signal from the signal masked by the noise.
  • a phase adjustment device includes:
  • a phase-locked loop module for receiving a reference signal to output an oscillator signal and a demodulator signal
  • a frequency division module configured to receive the oscillator signal to output a phase shift signal and a frequency division signal
  • a frequency tracking module configured to receive the demodulator signal to output a capture range signal
  • the phase-locked loop module is further configured to receive the frequency-divided signal and the capture range signal.
  • the phase adjustment device can control the operation of the phase-locked loop module by outputting the capture range signal through the frequency tracking module, so that the phase-locked loop module can automatically capture and lock a wide range of terahertz signals, so that the output has high accuracy and stability. Phase shift signal.
  • the phase-locked loop module includes:
  • a detection unit configured to receive the reference signal and the frequency-divided signal, and perform phase detection and frequency detection on the reference signal and the frequency-divided signal;
  • a tri-state output unit which is communicatively connected to the detection unit and is configured to control an output state according to a phase and a frequency of the reference signal and the frequency-divided signal;
  • a first output unit which is communicatively connected to the tri-state output unit, and the first output unit includes a loop filter, an oscillator, and a demodulator for outputting the oscillator signal and the demodulator signal;
  • the first output unit is further configured to receive the capture range signal to control a working frequency of the oscillator.
  • the detection unit includes at least one of a buffer, a flip-flop, and a logic gate circuit; and the tri-state output unit includes at least one of an N field effect transistor and a P field effect transistor.
  • the frequency division module includes:
  • An addition counter for receiving the oscillator signal to output the frequency-divided signal
  • a control switch which is communicatively connected to the addition counter and is used to control a preset value of the adder counter
  • a second output unit is communicatively connected to the addition counter, and the second output unit includes a multiplexer and a logic gate circuit for outputting the phase shift signal.
  • the addition counter includes a first counter, a second counter, a third counter, and a fourth counter
  • the logic gate circuit includes a first XOR gate, a second XOR gate, and a third XOR.
  • the phase shift signal includes a first phase shift signal and a second phase shift signal
  • the control switch is communicatively connected to the first counter, the second counter, the third counter, and the fourth counter, and the control switch controls the first counter and the second counter.
  • the preset value of the multiplexer is communicatively connected to the second counter, the first XOR gate, and the second XOR gate, respectively, and the first XOR gate is in communication with the second XOR gate.
  • Exclusive-OR gates are respectively used to output the first phase-shifted signal and the second phase-shifted signal; the third counter and the fourth counter are cascaded in phase, and the third counter also passes the third XOR
  • An OR gate is cascaded with the second counter, and the third counter is used to output the frequency-divided signal.
  • the first phase shift signal is a 0 ° phase shift signal
  • the second phase shift signal is a 90 ° phase shift signal
  • the frequency tracking module includes:
  • a reverse bias unit configured to receive the demodulator signal to output a reverse bias signal
  • a third output unit is communicatively connected to the reverse bias unit and configured to output the capture range signal according to the reverse bias signal.
  • the reverse bias unit includes a resistor, a capacitor, and an operational amplifier; and the third output unit includes a low-pass filter and a transistor.
  • a terahertz signal extraction system includes:
  • a signal generating device configured to generate the reference signal and a driving signal
  • a signal transmitting device configured to generate a modulated terahertz signal under the driving of the driving signal
  • a signal conversion device for receiving the modulated terahertz signal and converting it into a voltage signal
  • phase adjustment device configured to phase adjust the reference signal to obtain a phase-shifted signal
  • a phase-sensitive detection device configured to perform phase-sensitive detection processing on the voltage signal and the phase-shifted signal to obtain a phase-sensitive detection signal
  • a filtering device is configured to filter the phase-sensitive detection signal to obtain an original terahertz signal.
  • the above terahertz signal extraction system uses a phase-sensitive detection method for weak signal processing.
  • the phase adjustment device in the phase-locked loop mode can lock signals in a wide frequency range, thereby achieving low noise and high dynamic range from signals covered by noise. Extract the original terahertz signal.
  • the signal conversion device includes:
  • a photoconductive receiver for receiving the modulated terahertz signal and converting it into a current signal
  • An amplifier for receiving the current signal. And convert it into a voltage signal.
  • FIG. 1 is a schematic structural diagram of a phase adjustment device according to an embodiment
  • FIG. 2 is a schematic structural diagram of a phase-locked loop module according to an embodiment
  • FIG. 3 is a schematic structural diagram of a frequency division module in an embodiment
  • FIG. 4 is a schematic structural diagram of a frequency tracking module according to an embodiment
  • FIG. 5 is a schematic diagram showing a relationship between a demodulator signal voltage and an oscillator signal voltage in an embodiment
  • FIG. 6 is a schematic diagram of an amplitude-frequency characteristic curve of a loop filter in an embodiment
  • FIG. 7 is a schematic structural diagram of a terahertz signal extraction system in an embodiment.
  • FIG. 1 is a schematic structural diagram of a phase adjustment device according to an embodiment.
  • a phase adjustment device 50 includes a phase-locked loop module 100 for receiving a reference signal to output an oscillator signal and a demodulator. Signals; a frequency division module 200 for receiving an oscillator signal to output a phase shift signal and a frequency division signal; a frequency tracking module 300 for receiving a demodulator signal to output a capture range signal; wherein the phase locked loop module 100 also Used to receive crossover signals and capture range signals.
  • the phase adjustment device 50 uses a phase-locked loop mode to adjust the phase of the reference signal.
  • the phase-locked loop module 100 is communicatively connected to the frequency division module 200 and the frequency tracking module 300. After the phase-locked loop module 100 receives the reference signal, it outputs an oscillation. To the frequency division module 200.
  • the frequency division module 200 outputs the frequency division signal to the phase locked loop module 100 as a comparison signal.
  • the phase locked loop module 100 also outputs a demodulator signal to the frequency tracking module 300.
  • the frequency tracking module 300 captures the range The signal is output to the PLL module 100.
  • the capture range signal can determine the operating frequency of the oscillator in the PLL module 100, so that the PLL module 100 can automatically capture and lock a wide range of terahertz signals and control the frequency division module. 200 outputs a phase-adjusted phase shift signal.
  • the phase adjustment device can control the operation of the phase-locked loop module by outputting the capture range signal through the frequency tracking module, so that the phase-locked loop module can automatically capture and lock a wide range of terahertz signals, so that the output has high accuracy and stability. Phase shift signal.
  • FIG. 2 is a schematic structural diagram of a phase-locked loop module according to an embodiment.
  • the phase-locked loop module 100 includes a detection unit 120 for receiving a reference signal and a frequency-divided signal, and The reference signal and the frequency-divided signal perform phase detection and frequency detection; the tri-state output unit 140 is communicatively connected to the detection unit 120 and is used to control the output state according to the phase and frequency of the reference signal and the frequency-divided signal; the first output unit 160, and The tri-state output unit 140 is communicatively connected.
  • the first output unit 160 includes a loop filter 162, an oscillator 164, and a demodulator 166, and is configured to output an oscillator signal and a demodulator signal.
  • the first output unit is further configured to: A capture range signal is received to control the operating frequency of the oscillator 164.
  • the input terminal 1202 is communicatively connected to the terahertz signal generating device for receiving a reference signal, and the input terminal 1204 is connected to the frequency-dividing signal output terminal of the frequency-dividing module 200 for receiving frequency-dividing signals.
  • the signals, reference signals and frequency-divided signals undergo phase and frequency detection by the detection unit 120, and then output two signals through the tri-state output unit 140.
  • One of the signals is buffered and output to the lock monitoring end 1254, and one is passed through a loop filter.
  • 162 is input to the oscillator 164 after processing, and a signal is input to the demodulator 166.
  • the input terminal 1628 is connected to the capture range signal output terminal of the frequency tracking module 300 for receiving the capture range signal, and the capture range signal is used to determine the oscillation.
  • the operating frequency of the modulator 164 enables the phase-locked loop module 100 to automatically capture and lock a wide range of terahertz signals.
  • the detection unit 120 includes at least one of a buffer, a flip-flop, and a logic gate circuit; and the tri-state output unit 140 includes at least one of an N-FET and a P-FET.
  • the detection unit 120 may include structures such as a buffer, a flip-flop, and a logic gate circuit.
  • the detection unit 120 Including buffer 1206, buffer 1208, flip-flop 1212, flip-flop 1214, NAND gate 1222, NAND gate 1232, NAND gate 1234, NAND gate 1236, NOR gate 1242, NOR gate 1244, and NOR Door 1246.
  • the buffer 1206 and the buffer 1208 perform buffer isolation on the input signal to reduce the influence of the front-end circuit on the back-end logic circuit.
  • the tri-state output unit 140 is a push-pull tri-state output circuit composed of an N-FET 142 and a P-FET 144.
  • the input terminal 1602 is a capture range setting terminal of the phase-locked circuit, and is connected to the frequency tracking module 300.
  • the input terminal 1612 is a reference voltage setting terminal, and the input terminal 1628 is connected to the frequency tracking module 300 for automatic frequency tracking processing.
  • the loop filter 162 is a biased loop filter composed of a resistor 1622, a resistor 1624, and a capacitor 1626.
  • the oscillator 164 may be a VCO voltage-controlled oscillator.
  • the output terminal 1642 of the oscillator signal is connected to the frequency divider.
  • the oscillator signal input terminal and the demodulator signal output terminal 166 of the module 200 are connected to the demodulator signal input terminal of the frequency tracking module 300.
  • two signals are output through the tri-state output unit 140.
  • One of the signals is directly output to the lock monitoring end 1254 after being buffered by the output buffer 1252, and the other signal passes through the loop.
  • the channel filter 162 After being processed by the channel filter 162, it is input to the operational amplifier 1616 and fed back to the oscillator 164.
  • a follower composed of the operational amplifier 1618 is output to the demodulator signal output terminal 166.
  • V DEM V VCO
  • the power supply voltage is V CC
  • the reference signal is SIG REF
  • the frequency is
  • the frequency-divided signal is SIG COMP
  • its frequency is Phase difference
  • the transfer function is
  • the V DEM end output reflects the phase difference between SIG REF and SIG COMP , and the relationship between them is linear.
  • the logic gate circuit will make the P field effect transistor 144 in a conductive state for a certain period of time, and the corresponding phase difference is ⁇ DEM .
  • SIG REF When SIG REF When lagging behind SIG COMP , the N-FET 142 is in a conducting state.
  • the P FET 144 remains on for most of the input signal period, and for the remaining periods, the N FET 142 and the P FET 144 They are both in the off state and in the tri-state state.
  • the N-FET 142 When the SIG REF frequency is lower than the SIG COMP frequency, the N-FET 142 is on for most of the period. From the above relationship, it can be known that the phase difference and frequency change will be fed back to the loop filter 162, so that the capacitor 1626 The voltage of the capacitor changes until the signal and the comparator input are equal in phase and frequency. At this stable point, the voltage on the capacitor 1644 remains unchanged, and the output is in a tri-state.
  • FIG. 6 is a schematic diagram of the amplitude-frequency characteristic curve of the loop filter in one embodiment.
  • the resistance value R 1 of the resistor 1624 in the loop filter 162 may be 51 K ⁇ , and the capacitance of the capacitor 1626
  • the value of C 1 can be 470 nF, and the value of resistor R 2 of resistor 1622 can be 100 K ⁇ .
  • the amplitude-frequency characteristic curve of the loop filter 162 is shown in FIG. 6.
  • the frequency range of the oscillator 164 is determined by the equivalent resistance of the capture range signal input terminal 1602 and the capacitor 1644.
  • the value of the equivalent resistance of the capture range signal input terminal 1602 is determined by the frequency tracking module 300.
  • FIG. 3 is a schematic structural diagram of a frequency division module in an embodiment.
  • the frequency division module 200 includes: an addition counter 220 for receiving an oscillator signal to output a frequency division signal;
  • the switch 240 is communicatively connected to the adder counter and is used to control the preset value of the adder counter.
  • the second output unit 260 is communicatively connected to the adder counter.
  • the second output unit includes a multiplexer 262 and a logic gate circuit 264. To output a phase shift signal.
  • the addition counter 220 may be a four-bit binary presettable synchronous addition counter.
  • the addition counter 220 may include a plurality of cascaded counters.
  • the control switch 240 is used to select preset values for controlling the addition counter 220 respectively.
  • the addition counter 220 is used for phase shift control as an output signal and an output frequency division signal as an auxiliary frequency division count of the phase-locked loop module 100.
  • the input terminal 202 is connected to the oscillator signal output terminal 1642 in the phase-locked loop module 100 for receiving the oscillator signal, and the output terminal 286 is connected to the input terminal 1204 of the phase-locked loop module 100 for outputting to the phase-locked loop module 100. Divided signal.
  • the above-mentioned addition counter 220 includes a first counter 221, a second counter 222, a third counter 223, and a fourth counter 224
  • the logic gate circuit includes a first XOR gate, a second XOR gate, and a third XOR gate
  • the phase shift signal includes a first phase shift signal and a second phase shift signal
  • the control switch 240 is communicatively connected to the first counter 221, the second counter 222, the third counter 223, and the fourth counter 224, respectively.
  • the control switch 240 controls the preset values of the first counter 221 and the second counter 222.
  • the multiplexer 262 is communicatively connected with the second counter 222, the first XOR gate 264, and the second XOR gate 266, respectively.
  • the first XOR gate 264 and the second XOR gate 266 are respectively used to output a first phase shift signal and The second phase shift signal; the third counter 223 and the fourth counter 224 are cascaded.
  • the third counter 223 is also cascaded with the second counter 222 through a third XOR gate 268.
  • the third counter 223 is used to output a frequency division signal. .
  • the first counter 221, the second counter 222, the third counter 223, and the fourth counter 224 are connected in a cascade manner.
  • the preset values of the third counter 223 and the fourth counter 224 may also be set to 15, which The preset values of the two counters are fixed and cannot be adjusted.
  • the TC carry output of the fourth counter 224 is connected to the CET enable terminal of the third counter 223, thereby cascading the third counter 223 and the fourth counter 224 into one counter.
  • the circuit thus formed is at the edge of the signal change output from the oscillator 164 of the phase-locked loop module 100.
  • the fourth counter 224 generates a high-level carry signal every 16 CLK cycles of the carry terminal TC, which is input to the CET of the third counter 223 Control (gating) the output of the counter.
  • the third counter 223 counts data only once when the carry signal of the fourth counter 224 is generated, and is in an inhibit state at other times.
  • the QD output pin of the third counter 223 generates a signal change every 8 TC cycles, so that it is output to the frequency-divided signal through the output terminal 286 and fed back to the phase-locked loop module 100.
  • the frequency-divided signal is a frequency-divided 128 signal of the oscillator signal, and is used as a feedback comparison signal of the phase-locked loop module 100.
  • the TC carry output of the third counter 223 is connected to the enable terminal PE of the first counter 221 and the second counter 222 after passing through the third XOR gate 268.
  • the first counter 221 and the second counter respectively set preset values through the control switch 240.
  • Set to N1, N2, N1 is the fine adjustment setting of the output phase
  • N2 is the coarse adjustment setting of the output signal phase.
  • fine adjustment N1 can be set to 16 gears, each gear step is 1.4 °
  • coarse adjustment N2 is set to 16 gears, each gear step is 22.5 °
  • the output signal can be 0 ⁇ 360 Any adjustment between 0 to 255 gears.
  • the three outputs QB, QC, and QD of the first counter 221 are respectively connected to the input terminals 1A, 1B, 2A, and 2B of the multiplexer 262, and then the output terminals 1Y and 2Y of the multiplexer 262 respectively output two
  • the channel signal is XORed by the first XOR gate 264, and the 2Y output signal is XORed with the ground by the second XOR gate 266.
  • the first phase shift signal and the second phase shift signal are respectively output through the output terminal 282 and the output terminal 284, where the first phase shift signal and the second phase shift signal are 90 ° out of phase with the same frequency as the reference signal, and the first phase
  • the phase shift of the shift signal and the second phase shift signal from the reference signal can be adjusted by controlling the switch 240.
  • the first phase shift signal is a 0 ° phase shift signal
  • the second phase shift signal is a 90 ° phase shift signal.
  • FIG. 4 is a schematic structural diagram of a frequency tracking module according to an embodiment.
  • the frequency tracking module 300 includes a reverse bias unit 320 for receiving demodulation.
  • a third output unit 340 is communicatively connected to the reverse bias unit, and is configured to output a capture range signal according to the reverse bias signal.
  • the input terminal 302 is connected to the demodulator signal output terminal of the phase-locked loop module 100 for receiving a demodulator signal, and the demodulator signal passes through the reverse bias unit 320 to output a value.
  • the third output unit 340 generates a capture range signal after processing by the third output unit 340, and the capture range signal is output to the phase-locked loop module 100 through the output terminal 362.
  • the reverse biasing unit 320 includes a resistor, a capacitor, and an operational amplifier; the third output unit 340 includes a low-pass filter and a transistor 348.
  • the reverse bias unit 320 may specifically include a resistor 321, a resistor 322, a capacitor 324, a resistor 326, and an operational amplifier 328.
  • the third output unit is composed of a low-pass filter and a transistor 348.
  • the low-pass filter may specifically include a resistor 341 and a capacitor 346, and the transistor 348 may be an NPN transistor.
  • the demodulator signal of the phase locked loop module 100 is input to the frequency tracking module 300 through the input terminal 302.
  • the resistance value R 5 of the resistor 321 may be 10K ⁇
  • the resistance value R of the resistor 322 may be The value of 6 can be 15K ⁇
  • the value of resistor R F of resistor 326 can be 47K ⁇
  • the value of capacitance C F of capacitor 324 can be 1pF
  • the value of resistor R7 of resistor 341 can be 10M ⁇
  • resistor 342 The value of the resistance R 8 can be 47K ⁇
  • the value of the resistance R 9 of the resistor 343 can be 1M ⁇
  • the capacitance C 3 of the capacitor 346 can be 1uF.
  • the resistor 321, the resistor 322, the capacitor 324, the resistor 326, and the operational amplifier 328 constitute a reverse bias unit 320.
  • FIG. 7 is a schematic structural diagram of a terahertz signal extraction system in an embodiment.
  • a terahertz signal extraction system 10 includes a signal generating device 20 for generating a reference. Signals and driving signals; a signal transmitting device 30 for generating a modulated terahertz signal under the driving of a driving signal; a signal conversion device 40 for receiving a modulated terahertz signal and converting it into a voltage signal; the phase adjusting device 50 described above For phase-adjusting the reference signal to obtain a phase-shifted signal; phase-sensitive detection device 60 for performing phase-sensitive detection processing on the voltage signal and the phase-shifted signal to obtain a phase-sensitive detection signal; and filtering device 70 for The phase-sensitive detection signal is filtered to obtain the original terahertz signal.
  • the signal generating device 10 is a terahertz reference signal source generating circuit.
  • the signal generating device 10 generates a reference signal for phase-sensitive detection, and simultaneously generates a driving signal of the terahertz source.
  • the signal generating device 20 may be a terahertz transmitting antenna.
  • the signal generating device 20 generates a modulated terahertz signal after driving signals generated by the laser and the signal generating device 10.
  • the signal conversion device 40 receives the modulated terahertz signal from the signal generating device 20 and converts the modulated terahertz signal into a voltage signal.
  • the phase adjustment device 50 adjusts the phase of the reference signal generated by the signal generation device 10 with respect to the modulated terahertz signal to output a phase-shifted signal.
  • the phase-sensitive detection device 60 receives the voltage signal output from the signal conversion device 40 and the phase-shifted signal output from the phase adjustment device 50, and performs phase-sensitive detection processing on the voltage signal and the phase-shifted signal.
  • the filter circuit device 70 applies the phase-sensitive detection device 60
  • the output phase-sensitive detection signal is filtered to obtain the original terahertz signal.
  • the above-mentioned terahertz signal extraction system 10 uses a phase-sensitive detection method for weak signal processing.
  • the phase adjustment device in the phase-locked loop mode can lock signals in a wide frequency range, thereby achieving low noise and high dynamic range.
  • the signal is extracted from the original terahertz signal.
  • the signal conversion device 40 includes: a photoconductive receiver for receiving a modulated terahertz signal and converting it into a current signal; and an amplifier for receiving a current signal. And convert it into a voltage signal.
  • the signal conversion device 40 may include a photoconductive receiver and an amplifier.
  • the photoconductive receiver can be a photoconductive dipole antenna, which is used to couple terahertz electromagnetic waves to form high-speed carrier movement, thereby generating instantaneous current.
  • LT-GaAs low-temperature-grown gallium arsenide
  • the amplifier may be a preamplifier, which converts a current signal generated by the photoconductive receiver into a voltage signal, and outputs the voltage signal to the phase-sensitive detection device 60 for phase-sensitive detection processing.

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Abstract

本申请涉及一种相位调整装置以及一种太赫兹信号的提取系统，一种相位调整装置，其特征在于，包括：锁相环模块，用于接收参考信号，以输出振荡器信号以及解调器信号；分频模块，用于用于接收所述振荡器信号，以输出相移信号以及分频信号；频率跟踪模块，用于接收所述解调器信号以输出捕获范围信号；其中，所述锁相环模块还用于接收所述分频信号以及所述捕获范围信号。上述相位调整装置，通过频率跟踪模块输出捕获范围信号可以控制锁相环模块的工作，从而使锁相环模块能过自动捕获并锁定宽范围的太赫兹信号，从而输出却精度和稳定性较高的相移信号。

Description

相位调整装置以及太赫兹信号的提取系统 技术领域
本发明涉及电子电路领域，特别是涉及一种相位调整装置以及太赫兹信号的提取系统。
背景技术
太赫兹信号目前在很多领域有着广泛的应用前景，传统的太赫兹信号采集过程一般采用天线作为信号接受端，接收到的信号再经过前置放大器的放大处理后进行数据采集。这样的采集过程将会伴随着比较大的噪声和干扰信号，很难从被噪声掩盖的信号中捕获到太赫兹信号。
发明内容
基于此，有必要针对上述技术问题，提供一种相位调整装置以及太赫兹信号提取系统，可以自动捕获并锁定宽范围的太赫兹信号，并输出却精度和稳定性较高的相移信号。
一种相位调整装置，包括：
锁相环模块，用于接收参考信号，以输出振荡器信号以及解调器信号；
分频模块，用于接收所述振荡器信号，以输出相移信号以及分频信号；
频率跟踪模块，用于接收所述解调器信号以输出捕获范围信号；
其中，所述锁相环模块还用于接收所述分频信号以及所述捕获范围信号。
上述相位调整装置，通过频率跟踪模块输出捕获范围信号可以控制锁相环模块的工作，从而使锁相环模块能过自动捕获并锁定宽范围的太赫兹信号，从而输出却精度和稳定性较高的相移信号。
在其中一个实施例中，所述锁相环模块包括：
检测单元，用于接收所述参考信号和所述分频信号，并对所述参考信号和所述分频信号进行相位检测和频率检测；
三态输出单元，与所述检测单元通信连接，用于根据所述参考信号和所述 分频信号的相位和频率控制输出状态；
第一输出单元，与所述三态输出单元通信连接，所述第一输出单元包括环路滤波器、振荡器以及解调器，用于输出所述振荡器信号以及所述解调器信号；
其中，所述第一输出单元还用于接收所述捕获范围信号，以控制所述振荡器的工作频率。
在其中一个实施例中，所述检测单元包括缓冲器、触发器以及逻辑门电路中的至少一中；所述三态输出单元包括N场效应管以及P场效应管中的至少一种。
在其中一个实施例中，所述分频模块包括：
加法计数器，用于接收所述振荡器信号，以输出所述分频信号；
控制开关，与所述加法计数器通信连接，用于控制所述加法器计数器的预设值；
第二输出单元，与所述加法计数器通信连接，所述第二输出单元包括多路复用器与逻辑门电路，用于输出所述相移信号。
在其中一个实施例中，所述加法计数器包括第一计数器、第二计数器、第三计数器以及第四计数器，所述逻辑门电路包括第一异或门、第二异或门以及第三异或门，所述相移信号包括第一相移信号以及第二相移信号；
其中，所述控制开关分别与所述第一计数器、所述第二计数器、所述第三计数器以及所述第四计数器通信连接，所述控制开关控制所述第一计数器与所述第二计数器的预设值，所述多路复用器分别与所述第二计数器、所述第一异或门以及所述第二异或门通信连接，所述第一异或门与所述第二异或门分别用于输出所述第一相移信号以及所述第二相移信号；所述第三计数器和所述第四计数器相级联，所述第三计数器还通过所述第三异或门与所述第二计数器相级联，所述第三计数器用于输出所述分频信号。
在其中一个实施例中，所述第一相移信号为0°相移信号，所述第二相移信号为90°相移信号。
在其中一个实施例中，所述频率跟踪模块包括：
反向偏置单元，用于接收所述解调器信号，以输出反向偏置信号；
第三输出单元，与所述反向偏置单元通信连接，用于根据所述反向偏置信号输出所述捕获范围信号。
在其中一个实施例中，所述反向偏置单元包括电阻器、电容器以及运算放大器；所述第三输出单元包括低通滤波器以及晶体管。
一种太赫兹信号的提取系统，包括：
信号生成装置，用于生成所述参考信号以及驱动信号；
信号发射装置，用于在所述驱动信号的驱动下生成调制太赫兹信号；
信号转换装置，用于接收所述调制太赫兹信号，并将其转化为电压信号；
权利要求1至8中任意一项所述的相位调整装置，用于将所述参考信号进行相位调整以得到相移信号；
相敏检波装置，用于将所述电压信号和所述移相信号进行相敏检波处理，以得到相敏检波信号；
滤波装置，用于将所述相敏检波信号进行滤波处理，以得到原始太赫兹信号。
上述太赫兹信号的提取系统，采用相敏检波的方式进行微弱信号处理，通过锁相环模式的相位调整装置能够锁定宽频率范围的信号，从而实现低噪声高动态范围的从被噪声掩盖的信号中提取原始太赫兹信号。
在其中一个实施例中，所述信号转换装置包括：
光电导接收器，用于接收所述调制太赫兹信号，并将其转化为电流信号；
放大器，用于接收所述电流信号。并将其转化为电压信号。
附图说明
图1为一个实施例中相位调整装置的结构示意图；
图2为一个实施例中锁相环模块的结构示意图；
图3为一个实施例中分频模块的结构示意图；
图4为一个实施例中频率跟踪模块的结构示意图；
图5为一个实施例中解调器信号电压与振荡器信号电压的关系示意图；
图6为一个实施例中环路滤波器的幅频特性曲线的示意图；
图7为一个实施例中太赫兹信号的提取系统的结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
图1为一个实施例中相位调整装置的结构示意图，如图1所示，一种相位调整装置50，包括：锁相环模块100，用于接收参考信号，以输出振荡器信号以及解调器信号；分频模块200，用于接收振荡器信号，以输出相移信号以及分频信号；频率跟踪模块300，用于接收解调器信号以输出捕获范围信号；其中，锁相环模块100还用于接收分频信号以及捕获范围信号。
具体地，相位调整装置50采用锁相环模式对参考信号进行相位调整，锁相环模块100分别与分频模块200以及频率跟踪模块300通信连接，锁相环模块100接收参考信号后，输出振荡器信号至分频模块200，分频模块200输出分频信号给锁相环模块100作为比较信号，锁相环模块100还输出解调器信号至频率跟踪模块300，频率跟踪模块300将捕获范围信号输出至锁相环模块100，捕获范围信号可以确定锁相环模块100中振荡器的工作频率，从而使锁相环模块100能够自动捕获并锁定宽范围的太赫兹信号，并控制分频模块200输出经过相位调整的相移信号。
上述相位调整装置，通过频率跟踪模块输出捕获范围信号可以控制锁相环模块的工作，从而使锁相环模块能过自动捕获并锁定宽范围的太赫兹信号，从而输出却精度和稳定性较高的相移信号。
图2为一个实施例中锁相环模块的结构示意图，如图2所示，在一个实施例中，锁相环模块100包括：检测单元120，用于接收参考信号和分频信号，并对参考信号和分频信号进行相位检测和频率检测；三态输出单元140，与检测单元120通信连接，用于根据参考信号和分频信号的相位和频率控制输出状 态；第一输出单元160，与三态输出单元140通信连接，第一输出单元160包括环路滤波器162、振荡器164以及解调器166，用于输出振荡器信号以及解调器信号；其中，第一输出单元还用于接收捕获范围信号，以控制振荡器164的工作频率。
具体地，在锁相环模块100中，输入端1202与太赫兹信号生成装置通信连接，用于接收参考信号，输入端1204连接至分频模块200的分频信号输出端，用于接收分频信号，参考信号和分频信号经过检测单元120进行相位和频率的检测后，经过三态输出单元140输出两路信号，其中一路信号经缓冲后输出至锁定监测端1254，一路经过环路滤波器162处理后输入至振荡器164，同时引出一路信号输入至解调器166，输入端1628连接至频率跟踪模块300的捕获范围信号输出端，用于接收捕获范围信号，捕获范围信号用于决定振荡器164的工作频率，从而使锁相环模块100能自动捕获并锁定宽范围的太赫兹信号。
在一个实施例中，上述检测单元120包括缓冲器、触发器以及逻辑门电路中的至少一中；上述三态输出单元140包括N场效应管以及P场效应管中的至少一种。
具体地，检测单元120可以包括缓冲器、触发器以及逻辑门电路等结构，例如在图2所示的实施例中，检测单元120为一个正边沿触发的相位和频率检测电路后，检测单元120具体包括缓冲器1206、缓冲器1208、触发器1212、触发器1214，与非门1222、为非门1232、为非门1234、为非门1236、或非门1242、或非门1244以及或非门1246。其中，缓冲器1206和缓冲器1208对输入信号进行缓冲隔离，减少前端电路对后端逻辑电路的影响。三态输出单元140由N场效应管142以及P场效应管144组成的推挽三态输出电路。输入端1602为锁相电路捕获范围设置端，连接至频率跟踪模块300，输入端1612为参考电压设置端，输入端1628连接至频率跟踪模块300进行频率自动跟踪处理。环路滤波器162为由电阻器1622、电阻器1624以及电容器1626组成的带偏置型环路滤波器，振荡器164可以为VCO压控振荡器，振荡器信号的输出端1642连接至分频模块200的振荡器信号输入端，解调器信号输出端166连 接至频率跟踪模块300的解调器信号输入端。
进一步地，参考信号和分频信号经过检测单元120后，经过三态输出单元140输出两路信号，其中一路信号经输出缓冲器1252的缓冲之后直接输出至锁定监测端1254，另一路信号经环路滤波器162处理后，输入至运放1616，反馈给振荡器164，同时引出一路信号由运放1618构成的跟随器后输出至解调器信号输出端166。图5为一个实施例中解调器信号电压与振荡器信号电压的关系示意图，如图5所示，解调器信号的输出电压V DEM与VCO压控振荡器的输出电压V VCO的关系为V DEM＝V VCO。
在本实施例中电源电压为V CC，参考信号为SIG REF，其频率为
Figure PCTCN2019073337-appb-000001
分频信号为SIG COMP，其频率为
Figure PCTCN2019073337-appb-000002
相位差
Figure PCTCN2019073337-appb-000003
传递函数为
Figure PCTCN2019073337-appb-000004
V DEM端输出反映的是SIG REF和SIG COMP之间的相位差，他们之间的关系成线性。
当SIG REF和SIG COMP的频率相等，但SIG REF相位超前于SIG COMP时，逻辑门电路将使P场效应管144在一定时间内处于导通状态，对应的相位差为φ DEM，当SIG REF滞后于SIG COMP时，N场效应管142处于导通状态。当SIG REF的频率高于SIG COMP的频率时，P场效应管144在输入信号周期的大部分时间内保持为导通状态，而对于余下的周期，N场效应管142和P场效应管144均为断开状态即处于三态状态。当SIG REF频率低于SIG COMP频率，在大部分周期内N场效应管142处于导通状态，由上述关系式可知，相位差及频率的变化将反馈至环路滤波器162上，使得电容器1626的电压发生变化，直到信号和比较器输入在相位和频率上都相等，在该稳定点，电容器1644上的电压保持不变，输出处于三态。
图6为一个实施例中环路滤波器的幅频特性曲线的示意图，在一个实施例中，环路滤波器162中的电阻器1624的阻值R 1取值可以为51KΩ，电容器1626的电容量C 1取值可以为470nF，电阻器1622的阻值R 2取值可以为100KΩ。对应的滤波器时间常数τ 1、τ 2以及τ 3分别为τ 1＝R 2·C 1、τ 2＝R 1·C 1以及τ 3＝(R 1+R 2)·C 1，衰减比m为
Figure PCTCN2019073337-appb-000005
则环路滤波器162的幅频特性曲线如图6所示。振荡器164的频率范围由捕获范围信号输入端1602 的等效电阻以及电容器1644决定，其中捕获范围信号输入端1602的等效电阻的取值由频率跟踪模块300确定。
图3为一个实施例中分频模块的结构示意图，如图3所示，在一个实施例中，分频模块200包括：加法计数器220，用于接收振荡器信号，以输出分频信号；控制开关240，与加法计数器通信连接，用于控制加法器计数器的预设值；第二输出单元260，与加法计数器通信连接，第二输出单元包括多路复用器262与逻辑门电路264，用于输出相移信号。
具体地，加法计数器220可以为四位二进制可预置的同步加法计数器，加法计数器220可以包括扩多个级联的计数器，通过控制开关240选择分别控制加计数器法器220的预设值。从而使加法计数器220用于作为输出信号的移相控制以及输出分频信号作为锁相环模块100的辅助分频计数。输入端202连接至锁相环模块100中的振荡器信号输出端1642，用于接收振荡器信号，输出端286连接至锁相环模块100的输入端1204，用于向锁相环模块100输出分频信号。
在一个实施例中，上述加法计数器220包括第一计数器221、第二计数器222、第三计数器223以及第四计数器224，上述逻辑门电路包括第一异或门、第二异或门以及第三异或门，上述相移信号包括第一相移信号以及第二相移信号；
其中，控制开关240分别与第一计数器221、第二计数222器、第三计数器223以及第四计数器224通信连接，控制开关240控制第一计数器221与第二计数器222的预设值，多路复用器262分别与第二计数器222、第一异或门264以及第二异或门266通信连接，第一异或门264与第二异或门266分别用于输出第一相移信号以及第二相移信号；第三计数器223和第四计数器224相级联，第三计数器223还通过第三异或门268与第二计数器222相级联，第三计数器223用于输出分频信号。
具体地，第一计数器221、第二计数器222、第三计数器223以及第四计数器224采用级联的方式进行连接，第三计数器223和第四计数器224的预设值可以也设置为15，这两个计数器的预设值为固定值，不可调整。同时将第四 计数器224的TC进位输出连接到第三计数器223的CET使能端，从而将第三计数器223和第四计数器224级联成一个计数器。由此组成的电路在锁相环模块100的振荡器164输出的信号变化边缘，第四计数器224每16个CLK周期进位端TC产生一个高电平的进位信号，输入至第三计数器223的CET端，对计数器的输出进行控制(门控)。只有当第四计数器224的进位信号产生的时候第三计数器223才进行一次数据计数，其他时间处于禁止(inhibit)状态。第三计数器223的QD输出脚每8个TC周期产生一次信号的变化，从而通过输出端286输出至分频信号反馈给锁相环模块100。分频信号为振荡器信号的128分频信号，作为锁相环模块100的反馈比较信号。
第三计数器223的TC进位输出经过第三异或门268之后连接至第一计数器221和第二计数器222的使能端PE，第一计数器221和第二计数器通过控制开关240分别将预设值设为N1、N2，N1为输出相位的微调设置，N2为输出信号相位的粗调设置。例如，微调N1可设置为16个档位，每个档位步进为1.4°，粗调N2设置为16个档位，每个档位步进为22.5°，则输出信号可在0～360°之间进行0～255个档位之间的任何调整。第一计数器221的三个输出QB、QC、QD输出分别接至多路复用器262的输入端1A、1B、2A、2B，然后多路复用器262的通过输出端1Y、2Y分别输出两路信号通过第一异或门264进行异或，及2Y输出信号与地通过第二异或门266进行异或。然后通过输出端282和输出端284分别输出第一相移信号和第二相移信号，其中，第一相移信号和第二相移信号相位相差90°且与参考信号频率相同，第一相移信号及第二相移信号与参考信号的相位偏移可通过控制开关240来调节。例如在一个实施例中，上述第一相移信号为0°相移信号，上述第二相移信号为90°相移信号。
在一个实施例中，图4为一个实施例中频率跟踪模块的结构示意图，如图4所示，在一个实施例中，频率跟踪模块300包括：反向偏置单元320，用于接收解调器信号，以输出反向偏置信号；第三输出单元340，与反向偏置单元通信连接，用于根据反向偏置信号输出捕获范围信号。
具体地，在频率跟踪模块300中，输入端302连接至锁相环模块100的解 调器信号输出端，用于接收解调器信号，解调器信号经过反向偏置单元320后输出值第三输出单元340，经过第三输出单元340的处理后生成捕获范围信号，捕获范围信号通过输出端362输出至锁相环模块100。
在一个实施例中，上述反向偏置单元320包括电阻器、电容器以及运算放大器；上述第三输出单元340包括低通滤波器以及晶体管348。
具体地，反向偏置单元320具体可以包括电阻器321、电阻器322、电容器324、电阻器326以及运算放大器328。第三输出单元由低通滤波器及晶体管348组成，低通滤波器具体可以包括电阻器341以及电容器346，晶体管348可以为NPN型晶体管。
进一步地，锁相环模块100的解调器信号通过输入端302输入至频率跟踪模块300中，本实施例中电阻器321的阻值R 5取值可以为10KΩ，电阻器322的阻值R 6取值可以为15KΩ，电阻器326的阻值R F取值可以为47KΩ，电容器324的电容量C F取值可以为1pF，电阻器341的阻值R7取值可以为10MΩ，电阻器342的阻值R 8取值可以为47KΩ，电阻器343的阻值R 9取值可以为1MΩ，电容器346的电容量C 3取值可以为1uF。电阻器321、电阻器322、电容器324、电阻器326以及运算放大器328构成了反向偏置单元320，运算
Figure PCTCN2019073337-appb-000006
管的控制，使捕获范围信号输出端362的等效电阻R g发生变化，具体为R g＝R 9或
Figure PCTCN2019073337-appb-000007
根据振荡器164的特性，捕获范围信号输出端362的等效电阻R g和电容器1644共同决定振荡器164的工作频率，从而使相位调整装置能够自动捕获并锁定宽范围的信号
图7为一个实施例中太赫兹信号的提取系统的结构示意图，如图7所示，在一个实施例中，一种太赫兹信号的提取系统10，包括：信号生成装置20，用于生成参考信号以及驱动信号；信号发射装置30，用于在驱动信号的驱动下生成调制太赫兹信号；信号转换装置40，用于接收调制太赫兹信号，并将其转化为电压信号；上述相位调整装置50，用于将参考信号进行相位调整以得到相移信号；相敏检波装置60，用于将电压信号和移相信号进行相敏检波处理，以 得到相敏检波信号；滤波装置70，用于将相敏检波信号进行滤波处理，以得到原始太赫兹信号。
具体地，信号生成装置10为太赫兹参考信号源产生电路，信号生成装置10产生用于相敏检波的参考信号，同时产生太赫兹源的驱动信号。信号生成装置20可以为太赫兹发射天线，信号生成装置20经激光和信号生成装置10产生的驱动信号后生成调制太赫兹信号。信号转换装置40接收信号生成装置20发出的调制太赫兹信号，并将调制太赫兹信号转换成电压信号。相位调整装置50将信号生成装置10产生的参考信号相对于调制太赫兹信号进行相位调整以输出相移信号。相敏检波装置60分别接收信号转换装置40输出的电压信号以及相位调整装置50输出的相移信号，并将电压信号和相移信号进行相敏检波处理，滤波电路装置70将相敏检波装置60输出的相敏检波信号进行滤波处理，从而得到原始的太赫兹信号。
上述太赫兹信号的提取系统10，采用相敏检波的方式进行微弱信号处理，通过锁相环模式的相位调整装置能够锁定宽频率范围的信号，从而实现低噪声高动态范围的从被噪声掩盖的信号中提取原始太赫兹信号。
在一个实施例中，上述信号转换装置40包括：光电导接收器，用于接收调制太赫兹信号，并将其转化为电流信号；放大器，用于接收电流信号。并将其转化为电压信号。
具体地，信号转换装置40可以包括光电导接收器以及放大器。光电导接收器可以为光电导偶极天线，用于耦合太赫兹电磁波，形成载流子高速运动，从而产生瞬间电流，一般可以采用低温生长的砷化镓(LT-GaAs)材质。将太赫兹信号转换成电流信号。放大器可以为前置放大器，将光电导接收器产生的电流信号转换成电压信号，从而输出给相敏检波装置60进行相敏检波处理。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领 域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种相位调整装置，其特征在于，包括：
    锁相环模块，用于接收参考信号，以输出振荡器信号以及解调器信号；
    分频模块，用于接收所述振荡器信号，以输出相移信号以及分频信号；
    频率跟踪模块，用于接收所述解调器信号以输出捕获范围信号；
    其中，所述锁相环模块还用于接收所述分频信号以及所述捕获范围信号。
  2. 根据权利要求1所述的装置，其特征在于，所述锁相环模块包括：
    检测单元，用于接收所述参考信号和所述分频信号，并对所述参考信号和所述分频信号进行相位检测和频率检测；
    三态输出单元，与所述检测单元通信连接，用于根据所述参考信号和所述分频信号的相位和频率控制输出状态；
    第一输出单元，与所述三态输出单元通信连接，所述第一输出单元包括环路滤波器、振荡器以及解调器，用于输出所述振荡器信号以及所述解调器信号；
    其中，所述第一输出单元还用于接收所述捕获范围信号，以控制所述振荡器的工作频率。
  3. 根据权利要求2所述的装置，其特征在于，所述检测单元包括缓冲器、触发器以及逻辑门电路中的至少一中；所述三态输出单元包括N场效应管以及P场效应管中的至少一种。
  4. 根据权利要求1所述的装置，其特征在于，所述分频模块包括：
    加法计数器，用于接收所述振荡器信号，以输出所述分频信号；
    控制开关，与所述加法计数器通信连接，用于控制所述加法器计数器的预设值；
    第二输出单元，与所述加法计数器通信连接，所述第二输出单元包括多路复用器与逻辑门电路，用于输出所述相移信号。
  5. 根据权利要求4所述的装置，其特征在于，所述加法计数器包括第一计数器、第二计数器、第三计数器以及第四计数器，所述逻辑门电路包括第一异或门、第二异或门以及第三异或门，所述相移信号包括第一相移信号以及第二相移信号；
    其中，所述控制开关分别与所述第一计数器、所述第二计数器、所述第三 计数器以及所述第四计数器通信连接，所述控制开关控制所述第一计数器与所述第二计数器的预设值，所述多路复用器分别与所述第二计数器、所述第一异或门以及所述第二异或门通信连接，所述第一异或门与所述第二异或门分别用于输出所述第一相移信号以及所述第二相移信号；所述第三计数器和所述第四计数器相级联，所述第三计数器还通过所述第三异或门与所述第二计数器相级联，所述第三计数器用于输出所述分频信号。
  6. 根据权利要求5所述的装置，其特征在于，所述第一相移信号为0°相移信号，所述第二相移信号为90°相移信号。
  7. 根据权利要求1所述的装置，其特征在于，所述频率跟踪模块包括：
    反向偏置单元，用于接收所述解调器信号，以输出反向偏置信号；
    第三输出单元，与所述反向偏置单元通信连接，用于根据所述反向偏置信号输出所述捕获范围信号。
  8. 根据权利要求7所述的装置，其特征在于，所述反向偏置单元包括电阻器、电容器以及运算放大器；所述第三输出单元包括低通滤波器以及晶体管。
  9. 一种太赫兹信号的提取系统，其特征在于，包括：
    信号生成装置，用于生成所述参考信号以及驱动信号；
    信号发射装置，用于在所述驱动信号的驱动下生成调制太赫兹信号；
    信号转换装置，用于接收所述调制太赫兹信号，并将其转化为电压信号；
    权利要求1至8中任意一项所述的相位调整装置，用于将所述参考信号进行相位调整以得到相移信号；
    相敏检波装置，用于将所述电压信号和所述移相信号进行相敏检波处理，以得到相敏检波信号；
    滤波装置，用于将所述相敏检波信号进行滤波处理，以得到原始太赫兹信号。
  10. 根据权利要求9所述的系统，其特征在于，所述信号转换装置包括：
    光电导接收器，用于接收所述调制太赫兹信号，并将其转化为电流信号；
    放大器，用于接收所述电流信号。并将其转化为电压信号。
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