WO2020019312A1

WO2020019312A1 - Multi-layer composite semiconductor substrate structure and method for preparing same

Info

Publication number: WO2020019312A1
Application number: PCT/CN2018/097478
Authority: WO
Inventors: 母凤文; 须贺唯知
Original assignee: 无锡艾克柏国际微电子科技有限公司
Priority date: 2018-07-27
Filing date: 2018-07-27
Publication date: 2020-01-30
Also published as: CN111226314B; CN111226314A

Abstract

Disclosed are a multi-layer composite semiconductor substrate structure and a method for preparing same. The structure comprises: a high-heat-conductivity material layer, a bonding interface layer, a dielectric material layer, a device functional layer and a support substrate, wherein the bonding interface layer is formed between the high-heat-conductivity material layer and the dielectric material layer, and the high-heat-conductivity material layer is bonded with the dielectric material layer by means of the bonding interface layer; and the dielectric material layer is formed above the device functional layer supported by the support substrate. The preparation method is a low-temperature process, in which a growth start face of the high-heat-conductivity material layer is bonded with the dielectric material layer, or a growth stop face of the high-heat-conductivity material layer is bonded with the dielectric material layer. According to the multi-layer composite semiconductor substrate structure and the method for preparing same in the present disclosure, the heat dissipation effect of a device is improved, the problem of the device functional layer being subjected to thermal damage and stress as a result of a direct high-temperature deposition process of the high-heat-conductivity material layer is avoided, and material costs and grinding processing costs are saved on.

Description

Multilayer composite semiconductor substrate structure and preparation method thereof

Technical field

The present disclosure relates to the technical field of semiconductor processes and semiconductor packaging, and in particular, to a high-heat-dissipation multilayer composite semiconductor substrate structure for manufacturing high-power devices and a preparation method thereof.

Background technique

At present, high-power, high-frequency electronic devices have great prospects in weather radar and 5G communication applications, but the heat dissipation problems of high-power, high-frequency devices have severely limited device reliability and service life. At present, one of the methods to solve the heat dissipation problem of the above devices is to integrate the above devices with high thermal conductivity materials. The integration methods mainly include:

(1) A device functional layer is grown on a high thermal conductivity material such as diamond. This method generally requires single crystal high thermal conductivity materials, but single crystal high thermal conductivity materials are difficult to prepare, small in size, extremely expensive, and have very serious thermal mismatch problems.

(2) Grow high thermal conductivity materials on the device functional layer, such as diamond on gallium nitride. The epitaxial growth of high thermal conductivity materials usually requires high-temperature processes (about 700 ° C and above) and the reducing atmosphere will erode the functional layer of the device, so substrate warpage and device functional layer damage are likely to occur during the growth of high thermal conductivity materials. In addition, if the initial support substrate needs to be removed if growing on the back of the device layer, the material cost and processing cost are greatly increased.

(3) The self-supporting high thermal conductivity substrate is bonded to the device functional layer or the device layer.

Self-supporting high-thermal-conductivity substrates such as diamond need to be ground to provide surface smoothness, and then bonded to the device functional layer or device layer, but grinding self-supporting high-thermal-conductivity substrates are usually thick, warping, and material costs And the processing cost is very high; also, this method also needs to remove the initial support substrate, which greatly increases the cost.

Therefore, the existing heat dissipation solutions for high-power and high-frequency electronic devices are difficult to implement and costly.

Summary of the Invention

(1) Technical problems to be solved

The present disclosure provides a highly exothermic multilayer composite semiconductor substrate structure that can be used to fabricate high-power devices and a method for manufacturing the same, in order to at least partially solve the above-mentioned technical problems.

(Two) technical solutions

According to an aspect of the present disclosure, there is provided a multilayer composite semiconductor substrate structure including: a high thermal conductivity material layer, a bonding interface layer, a dielectric material layer, a device functional layer, and a supporting substrate, wherein :

The bonding interface layer is formed between the high thermal conductivity material layer and the dielectric material layer, and the high thermal conductivity material layer is bonded to the dielectric material layer through the bonding interface layer;

The dielectric material layer is formed on the device functional layer supported by the supporting substrate.

In some embodiments, the thermal conductivity of the high thermal conductivity material layer is not lower than that of silicon, and the thickness is between 200 nanometers and 50 micrometers; the material is diamond, silicon carbide, multi-layer graphene, and carbon nanometers. One or a combination of tubes, aluminum nitride, boron arsenide, and boron nitride.

In some embodiments, the thickness of the bonding interface layer is between 0.1 and 50 nanometers; and it is prepared by using one or more stacked combinations of the following materials: silicon oxide, aluminum oxide, silicon nitride, Aluminum nitride, silicon, silicon carbide, beryllium oxide, boron nitride, titanium oxide, nitrogen-carbon chemicals, modified diamond surface layer, modified dielectric material surface layer, hafnium oxide, hafnium oxide, and zirconia; the crystal form is amorphous, single Crystalline or polycrystalline.

In some embodiments, the thickness of the dielectric material layer is between 2 and 50 nanometers, and is prepared by using one or more stacked combinations of the following materials: silicon oxide, aluminum oxide, silicon nitride, and nitrogen. Aluminium, amorphous silicon, amorphous silicon carbide, titanium oxide, nitrogen-carbon chemicals, hafnium oxide, hafnium oxide, and zirconia.

In some embodiments, the material of the device functional layer is one or a combination of gallium nitride, aluminum gallium nitride, aluminum nitride, gallium oxide, silicon, silicon carbide, and diamond; and the thickness is between 10 nanometers and 10 nanometers. Between micrometers.

In some embodiments, the supporting substrate is prepared by using one or more stacked combinations of the following materials: silicon carbide, gallium nitride, aluminum nitride, silicon, gallium oxide, and sapphire; the thickness is between 20 ~ 700 microns.

According to another aspect of the present disclosure, a method for manufacturing a multilayer composite semiconductor substrate structure is provided, including:

Depositing a high thermal conductivity material layer on a sacrificial wafer, the high thermal conductivity material layer having a growth stop surface and a growth start surface opposite to the growth stop surface;

Forming a device functional layer on a support substrate, and growing a dielectric material layer on the device functional layer, the dielectric material layer having a growth stop surface;

Bonding the growth stop surface of the high thermal conductivity material layer with the growth stop surface of the dielectric material layer; and

Selective etching removes the sacrificial wafer, exposing the growth start surface of the high thermal conductivity material layer.

Attaching the growth stop surface of the high thermal conductivity material layer to a temporary support wafer, and selectively etching to remove the sacrificial wafer, exposing the growth start surface of the high thermal conductivity material layer;

Bonding the growth start surface of the high thermal conductivity material layer with the growth stop surface of the dielectric material layer;

The temporary support wafer is removed to expose a growth stop surface of the high thermal conductivity material layer.

In some embodiments, bonding is performed by a surface activation method or a plasma activation method to form a bonding interface layer between the high thermal conductivity material layer and the dielectric material layer.

In some embodiments, a device functional layer is formed on a support substrate by a growth or transfer method.

In some embodiments, the sacrificial wafer and the high thermal conductivity material layer have different etch rates.

In some embodiments, before bonding, the method further includes: grinding and polishing the surface to be bonded of the high thermal conductivity material layer.

In some embodiments, after depositing the high thermal conductivity material layer on the sacrificial wafer and before grinding and polishing, the method further includes: patterning the high thermal conductivity material layer.

In some embodiments, after the device functional layer or the dielectric material layer is formed and before the bonding, the method further includes: forming an electrode and performing metal wiring.

In some embodiments, after the bonding, the method further includes: thinning the supporting substrate.

(Three) beneficial effects

It can be seen from the above technical solution that the present disclosure can be used to fabricate a high exothermic multilayer composite semiconductor substrate structure for a high power device and a method for preparing the same having at least one of the following beneficial effects:

(1) The present disclosure can be used to fabricate a high-heat-dissipation multilayer composite semiconductor substrate structure for a high-power device, and a method for preparing the same. Avoiding direct high temperature growth damage to the device functional layer and stress problems caused by the device, but also can save material costs and grinding processing costs.

(2) The high-heat-dissipation multilayer composite semiconductor substrate structure and the preparation method thereof that can be used to make high-power devices provided by the present disclosure can be used for high-temperature growth of a high-conductivity material layer on a sacrifice wafer without severe restrictions. Through optimization of various growth conditions to obtain a high thermal conductivity material layer with higher thermal conductivity, a better device heat dissipation effect can be achieved.

(3) The high-heat-dissipation multilayer composite semiconductor substrate structure and the preparation method thereof which can be used for manufacturing high-power devices provided by the present disclosure can achieve high performance without the need for an expensive process of removing the initial substrate and grinding a self-supporting high-thermal-conductivity substrate. The integration of power devices with high thermal conductivity materials, without complicated additional processes, is more compatible with the current device manufacturing process.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. Those of ordinary skill in the art can obtain other drawings according to these drawings without paying creative labor.

FIG. 1 is a schematic structural diagram of a high-heat-dissipation multilayer composite semiconductor substrate structure that can be used to fabricate high-power devices according to an embodiment of the present disclosure.

FIG. 2 is another schematic structural diagram of a high-heat-dissipation multilayer composite semiconductor substrate structure that can be used to fabricate high-power devices according to an embodiment of the present disclosure.

FIG. 3 is a schematic diagram of a process of depositing a high thermal conductivity material layer on a sacrificial wafer according to an embodiment of the present disclosure.

4 is a schematic diagram of a process of forming a device functional layer and a dielectric material layer on a support substrate according to an embodiment of the present disclosure.

5 is a schematic diagram of a process of bonding a second surface of a high thermal conductivity material layer and a dielectric material layer at a low temperature according to an embodiment of the present disclosure.

FIG. 6 is a schematic diagram of a second preparation method according to an embodiment of the present disclosure.

FIG. 7 is a schematic diagram of four possible device structures according to an embodiment of the present disclosure.

＜ Symbol explanation ＞

100-sacrifice wafer;

101-high thermal conductivity material layer;

1011-first surface of the high thermal conductivity material layer;

1012-Second surface of the high thermal conductivity material layer;

102-Support substrate;

103-device functional layer;

104-dielectric material layer;

1041- growth stop surface of the dielectric material layer;

105-bonded interface layer;

106-Temporary support wafer (including temporary bonding glue);

107-source

108-drain;

109, 110, 111, 112-gate.

detailed description

In order to make the objectives, technical solutions, and advantages of the present disclosure more clear, the present disclosure is further described in detail below with reference to specific embodiments and with reference to the accompanying drawings.

The specific embodiments and drawings are only used to better understand the content of the present disclosure and not to limit the protection scope of the present disclosure. The components in the structure of the drawings of the embodiment are not scaled according to normal proportions, so they do not represent the actual relative sizes of the structures in the embodiment.

The present disclosure provides a high-heat-dissipation multilayer composite semiconductor substrate structure for manufacturing a high-power device and a preparation method thereof. Wherein, the multilayer composite semiconductor substrate structure includes a high thermal conductivity material layer, a bonding interface layer, a dielectric material layer, a device functional layer, and a supporting substrate; the high thermal conductivity material layer is bonded by bonding The interface layer and the dielectric material layer are bonded; the bonding interface layer is formed in a bonding process between the high thermal conductivity material layer and the dielectric material layer, and is located between the high thermal conductivity material layer and the dielectric material layer.

The manufacturing method of the high-heat-dissipation multilayer composite semiconductor substrate structure is a low-temperature process, which avoids the thermal damage and stress problems caused by the direct high-temperature deposition process of the high-thermal-conductivity material layer on the device functional layer, and can realize a high-quality high-thermal-conductivity material layer. Low-temperature integration with high-power devices can simultaneously achieve double-sided heat dissipation without the need for a support substrate removal process. It can significantly reduce costs while ensuring enhanced heat dissipation performance, and solves the problem of high cost and difficult to achieve heat dissipation solutions for high-power devices.

As shown in FIG. 1 to FIG. 5, the high-heat-dissipation multilayer composite semiconductor substrate structure provided by the present disclosure that can be used for manufacturing high-power devices includes a high thermal conductivity material layer 101, a bonding interface layer 105, a dielectric material layer 104, A device functional layer 103 and a support substrate 102. The high thermal conductivity material layer 101 has a first surface 1011 (growth start surface) and a second surface 1012 (growth stop surface) opposite to the first surface 1011. The high thermal conductivity The material layer 101 is bonded to the growth stop surface 1041 of the dielectric material layer 104 through the first surface 1011 or the second surface 1012 thereof, and a bonding interface layer 105 is formed between the two layers after bonding. The high thermal conductivity material layer 101 can achieve high heat dissipation for the device functional layer 103.

The high thermal conductivity material layer 101 is formed on the sacrificial wafer 100. The sacrificial wafer 100 and the high thermal conductivity material layer 101 have different etch rates. The high thermal conductivity material layer is exposed by selectively etching the sacrificial wafer 100. The surface 1011 facilitates subsequent front electrode formation and metal wiring. The high thermal conductivity material layer 101 is formed on the sacrificial wafer 100, which can avoid the thermal damage and stress problems caused by the high temperature growth of the dielectric material layer, and can be optimized to achieve a higher thermal conductivity high thermal conductivity material through various conditions. Layer 101.

The high thermal conductivity material layer 101 is made of a material having a thermal conductivity higher than that of silicon to ensure high heat dissipation characteristics, and the thickness is between 200 nanometers and 50 micrometers. The high thermal conductivity material layer 101 may use one or more of the following materials: diamond, silicon carbide, multi-layer graphene, carbon nanotubes, aluminum nitride, boron arsenide, and boron nitride; the crystal form is single crystal and Polycrystalline. The first surface 1011 and the second surface 1012 of the high thermal conductivity material layer 101 are its growth start surface and growth stop surface, respectively. The composite substrate composed of the high thermal conductivity material layer 101 / sacrifice wafer 100 has low warpage and high thermal conductivity. The second surface 1012 of the material layer has a small roughness and is easy to be polished and polished, which is beneficial to the subsequent bonding process. Compared with a self-supporting substrate, the material cost and processing cost can be significantly reduced.

The bonding interface layer 105 is prepared by combining one or more of the following materials: silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, silicon, silicon carbide, beryllium oxide, boron nitride, and titanium oxide , Nitrogen-carbon chemicals, modified diamond surface layer, modified dielectric material surface layer, hafnium oxide, hafnium oxide and zirconia; the crystal form is not limited, and can be amorphous, single crystal and polycrystalline. The thickness of the bonding interface layer ranges from 0.1 to 50 nanometers. The higher the thermal conductivity and the smaller the thickness of the material of the bonding interface layer, the more favorable it is to transfer heat to the high thermal conductivity material layer.

The device functional layer 103 is grown or transferred onto the supporting substrate 102 and is one or more combinations of the following materials: gallium nitride, aluminum gallium nitride, aluminum nitride, gallium oxide, silicon, silicon carbide, and diamond The thickness ranges from 10 nm to 10 microns. The device functional layer 103 is a main working part of the device and is a place where heat is mainly generated.

The supporting substrate 102 is prepared by using one or more stacked combinations of the following materials: silicon carbide, gallium nitride, aluminum nitride, silicon, gallium oxide, and sapphire. The thickness is between 50 microns and 700 microns. The supporting substrate 102 may also include a transition layer or a buffer layer required for the growth of the device functional layer 103, which is not shown in the figure.

A dielectric material layer 104 is deposited and grown on the device functional layer 103. The thickness of the dielectric material layer 104 ranges from 2 to 50 nanometers; on the premise that the device functional layer 103 is protected and can be used as an insulating layer or a passivation layer, the higher the thermal conductivity of the dielectric material layer 104, The smaller the thickness, the more beneficial the heat is to the high thermal conductivity material layer 101 and achieve the effect of high heat dissipation. The dielectric material layer 104 is prepared by combining one or more of the following materials: silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, amorphous silicon, amorphous silicon carbide, titanium oxide, nitrogen carbon Chemicals, hafnium oxide, hafnium oxide and zirconia.

In an embodiment of the present disclosure, after the high thermal conductivity material layer 101 is deposited on the sacrificial wafer 100 and before the grinding and polishing process, the deposited high thermal conductivity material layer 101 is patterned to meet the requirements of local heat dissipation. The structure after bonding and removing the sacrificial wafer 100 is shown in FIG. 2.

In another embodiment of the present disclosure, the high thermal conductivity material layer 101 is a diamond layer, and the dielectric material layer 104 is silicon nitride (SiN) or aluminum nitride (AlN) or aluminum oxide (Al ₂ O ₃ ). The device functional layer 103 is gallium nitride / aluminum nitride / gallium nitride (GaN / AlGaN / GaN), and the substrate material is aluminum nitride / silicon carbide (AlN / SiC) or aluminum nitride / silicon carbide / silicon / Silicon carbide (AlN / SiC / Si / SiC)); the thickness of each layer can be adjusted within the foregoing range according to actual needs, for example, the thickness of the high thermal conductivity diamond layer is 1 micron and 5 micron, respectively.

In yet another embodiment of the present disclosure, the high thermal conductivity material layer 101 is a diamond layer, the dielectric material layer 104 is silicon nitride (SiN) or aluminum oxide (Al ₂ O ₃ ), and the device functional layer 103 is gallium oxide ( Ga ₂ O ₃ ), the substrate material is alumina or silicon carbide; the thickness of each layer can be adjusted within the foregoing range according to actual needs, for example, the thickness of the high thermal conductivity diamond layer is 1 micrometer and 5 micrometers, respectively.

Based on the above-mentioned high-heat-dissipation multilayer composite semiconductor substrate structure that can be used to make high-power devices, the embodiments of the present disclosure also provide a method for preparing the high-heat-dissipation multilayer composite semiconductor substrate structure that can be used to make high-power devices. Two methods.

The first preparation method specifically includes the following steps:

Step 1: Grind and polish a layer of high thermal conductivity material on the sacrificial wafer:

The sacrificial wafer is used as a substrate for depositing the high thermal conductivity material layer, and supports the second surface of the high thermal conductivity material layer to complete the polishing process. The sacrificial wafer and the high thermal conductivity material layer have different etching rates. There are many ways to deposit a high thermal conductivity material layer on a sacrificial wafer. Microwave chemical vapor deposition can be used, as well as sputtering deposition or other deposition methods.

Step 2: Deposit a functional layer of the growing device on the supporting substrate, or transfer the functional layer of the device to the supporting substrate from elsewhere, and then form a dielectric material layer on the functional layer of the device:

Among them, there are many types of device functional layer deposition methods, such as molecular beam epitaxy, organic metal chemical vapor deposition, and the like.

The dielectric material layer may be formed in various forms, such as atomic layer deposition, physical vapor deposition, and organic metal chemical vapor deposition.

Step 3: Bond the second surface of the high thermal conductivity material layer with the growth stop surface of the dielectric material layer:

Among them, bonding refers to direct or indirect bonding at low temperature or even at room temperature, such as by surface activation method or plasma activation method; a bonding interface layer is formed after the bonding is completed.

Step 4: Selectively etching and removing the sacrificial wafer, exposing the first surface of the high thermal conductivity material layer, and obtaining the high heat dissipation multilayer composite semiconductor substrate structure.

The following describes the preparation process corresponding to the first preparation method in detail with reference to FIGS. 1-5.

A. Provide a sacrificial wafer 100, and the material of the sacrificial wafer is silicon. A high thermal conductivity material layer 101 is deposited on the front surface of the silicon wafer. As shown in FIG. 3, the material of the high thermal conductivity material layer 101 is diamond, and the deposition method is microwave chemical vapor deposition with a thickness of 2 μm.

B. A support substrate 102 containing a transition layer is also provided. The material is aluminum nitride / silicon carbide (AlN / SiC). The functional layer 103 of the device is grown on the transition layer (AlN) by an organometallic chemical vapor deposition method. Is a gallium nitride / aluminum gallium nitride / gallium nitride (GaN / AlGaN / GaN), and then a dielectric material layer 104 is deposited on the device functional layer 103 by a chemical vapor deposition method, and the material is silicon nitride (SiN). As shown in Figure 4.

C. Grind, polish and clean the second surface of the high thermal conductivity material layer so that its surface roughness is less than 1 nanometer, and then bond it with the dielectric material layer 104 to form a bonding interface layer 105, as shown in FIG. 5 As shown.

D. After the sacrificial wafer 100 is selectively etched and removed, a high-heat dissipation multilayer composite semiconductor substrate structure is obtained, as shown in FIG. 1.

In the embodiment of the present disclosure, the bonding method uses a surface-activated bonding method to perform direct bonding at room temperature in an ultra-high vacuum. In the direct bonding process, an accelerated atomic beam or ion beam such as argon (Ar) is used to bombard the second surface 1012 of the high thermal conductivity material layer 101 and the dielectric material layer 104 in an ultra-high vacuum ( ^10-6 Pa). The growth stop surface 1041 achieves the purpose of surface activation, and further obtains a uniform high-strength bond at room temperature. At this time, the bonding interface layer is a modified diamond layer and a modified silicon nitride layer caused by bombardment. It should be understood that the bonding method used in this bonding step is not limited to the surface activation bonding method, but may also be other bonding methods such as plasma-activated bonding, etc., or it may be deposited by an intermediate layer. To achieve indirect bonding.

In the embodiment of the present disclosure, after the high thermal conductivity material layer 101 is deposited on the sacrificial wafer 100 and before the grinding and polishing process, the deposited high thermal conductivity material layer 101 is patterned to meet the requirements of local heat dissipation. The structure after bonding and removing the sacrificial wafer 100 is shown in FIG. 2.

In the embodiment of the present disclosure, the wafer 100 may be a silicon wafer, the high thermal conductivity material layer 101 may be a diamond layer, and the dielectric material layer 104 may be silicon nitride (SiN) or aluminum nitride (AlN) or an oxide. Aluminum (Al ₂ O ₃ ), the device functional layer 103 is gallium oxide (Ga ₂ O ₃ ), and the substrate material is aluminum oxide (Al ₂ O ₃ ) or silicon carbide (SiC); the thickness of each layer can be adjusted according to actual requirements Adjust, for example, the thickness of the diamond layer with high thermal conductivity is 1 micron and 5 microns, respectively.

The second preparation method specifically includes the following steps:

Step 1: A layer of high thermal conductivity material on the sacrificial wafer is temporarily bonded to a temporary support wafer (including temporary bonding glue) through its second surface, and the sacrificial wafer is removed by etching or grinding to expose the high thermal conductivity First surface of the material layer:

The sacrificial wafer is used as a substrate for depositing the high thermal conductivity material layer, and the sacrificial wafer and the high thermal conductivity material layer have different etching rates. There are many ways to deposit a high thermal conductivity material layer on a sacrificial wafer. Microwave chemical vapor deposition can be used, as well as sputtering deposition or other deposition methods.

Step 3: Bond the first surface of the high thermal conductivity material layer to the growth stop surface of the dielectric material layer after being appropriately ground and polished:

Step 4: Remove the temporary support wafer, and expose the second surface of the high thermal conductivity material layer to obtain a high heat dissipation multilayer composite semiconductor substrate structure:

The following describes the preparation process corresponding to the first preparation method in detail with reference to FIGS. 1-6.

B. The high thermal conductivity material layer 101 / sacrificial wafer 100 composite semiconductor substrate is temporarily bonded to the temporary support wafer 106 (including the temporary bonding adhesive), as shown in FIG. 6 (a), the temporary support wafer 106 The substrate material may be glass, and the sacrificial wafer 100 is selectively etched and removed, as shown in FIG. 6 (b).

C. A supporting substrate 102 containing a transition layer is also provided. The material is aluminum nitride / silicon carbide (AlN / SiC). The functional layer 103 of the device is grown on the transition layer (AlN) by an organometallic chemical vapor deposition method. Is a gallium nitride / aluminum gallium nitride / gallium nitride (GaN / AlGaN / GaN), and then a dielectric material layer is deposited on the device functional layer 103 by a chemical vapor deposition method, and the material is silicon nitride (SiN), such as Shown in Figure 4.

D. The first surface of the thermal conductivity material layer is appropriately ground, polished, and cleaned so that its surface roughness is less than 1 nanometer, and then bonded to the dielectric material layer 104 to form a bonding interface layer 105, as shown in the figure. 6 (c).

E. After the temporary support wafer 100 (including the temporary bonding glue) is separated and removed by a known method, a high-heat-dissipation multilayer composite semiconductor substrate structure is obtained, as shown in FIG. 1 or 6 (d).

In the embodiment of the present disclosure, the growth process of the high thermal conductivity material layer on the sacrificial wafer is unlimited, and the thermal conductivity of the high thermal conductivity material layer can be improved as much as possible. However, the growth process of the high thermal conductivity material layer is a high temperature process containing various reducing gases. If it is grown directly on the dielectric material layer, it will cause damage to the functional layer of the device and it will be difficult to control.

After the high thermal conductivity material layer is deposited on the sacrificial wafer, the deposited high thermal conductivity material layer can be patterned to meet local heat dissipation requirements. After the device functional layer or the dielectric material layer is grown or before the bonding process, electrode formation and metal wiring processes can also be performed to simplify the device manufacturing process after bonding; after bonding, it can further The supporting substrate is further thinned.

In the embodiment of the present disclosure, the bonding method adopts a surface-active bonding method to perform direct or indirect bonding at room temperature in an ultra-high vacuum. During the direct bonding process, an accelerated atomic beam or an ion beam such as argon (Ar) is used to bombard the second surface 1012 of the high thermal conductivity material layer 101 and the growth of the dielectric material layer 104 in an ultra-high vacuum ( ^10-6 Pa). Stop surface 1041, remove surface contaminants and oxide layers to achieve surface activation, and then obtain uniform high-strength bonding at room temperature. At this time, the bonding interface layer is a modified diamond layer and a modified silicon nitride layer caused by bombardment. . During the indirect bonding process, an accelerated atomic beam or ion beam such as argon (Ar) is used to bombard the second surface 1012 of the high thermal conductivity material layer 101 and the growth of the dielectric material layer 104 in an ultra-high vacuum ( ^10-6 Pa). The stop surface 1041 is surface-activated, and an intermediate nano-layer of silicon or other materials is deposited by ion beam sputtering, and then bonded at room temperature. At this time, the bonding interface layer is a metamorphic diamond layer caused by bombardment, metamorphic nitridation. A silicon layer and a deposited nano-interlayer. It should be understood that the bonding method used in this bonding step is not limited to the surface activation bonding method, but may also be other bonding methods such as plasma-activated bonding.

In the embodiment of the present disclosure, after depositing the high-thermal-conductivity material layer 101 on the sacrificial wafer 100, the deposited high-thermal-conductivity material layer 101 can be patterned, which has met the requirements of local heat dissipation, and is removed after bonding. The structure after temporarily supporting the wafer 106 is shown in FIG. 2.

In addition, any high-power device that can be formed by such a high-heat-dissipation multilayer composite semiconductor substrate structure should be applicable to the embodiments of the present disclosure. Figure 7 shows four possible forms of high-power devices. The difference lies in the arrangement of the gate: (a) the bottom of the gate 109 is in contact with the surface of the device functional layer 103, and (b) the bottom of the gate 110 is at the bonding interface. Inside 105, (c) the bottom of the gate 111 is in the dielectric material layer 104, and (d) the bottom of the gate 112 is in the device functional layer 103.

So far, the embodiments of the present disclosure have been described in detail with reference to the drawings. Based on the above description, those skilled in the art should have a clear understanding of the present disclosure.

It should be noted that, the implementation manners not shown or described in the drawings or the text of the description are all forms known to those skilled in the art and have not been described in detail. In addition, the above definitions of the elements are not limited to the various specific structures and shapes mentioned in the embodiments, and those skilled in the art can simply change or replace them; this article can provide examples of parameters containing specific values. However, these parameters need not be exactly equal to the corresponding values, but can be approximated to the corresponding values within acceptable error tolerances or design constraints; the directional terms mentioned in the embodiments, such as "up", "down", "front" , "Back", "left", "right", etc., are merely directions for reference to the drawings, and are not intended to limit the scope of protection of the present disclosure; the above embodiments may be mixed with each other or used with Other embodiments are mixed and used, that is, the technical features in different embodiments can be freely combined to form more embodiments.

The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the present disclosure will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features disclosed herein.

It should be noted that, the implementation manners not shown or described in the drawings or the text of the description are all forms known to those skilled in the art and have not been described in detail. In addition, the above definitions of the elements and methods are not limited to the various specific structures, shapes, or manners mentioned in the embodiments, and those skilled in the art can simply modify or replace them.

The specific embodiments described above further describe the objectives, technical solutions, and beneficial effects of the present disclosure in detail. It should be understood that the above are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modification, equivalent replacement, or improvement made within the spirit and principle of this disclosure shall be included in the protection scope of this disclosure.

Claims

A multilayer composite semiconductor substrate structure includes: a high thermal conductivity material layer, a bonding interface layer, a dielectric material layer, a device functional layer, and a supporting substrate, wherein:

The bonding interface layer is formed between the high thermal conductivity material layer and the dielectric material layer, and the high thermal conductivity material layer is bonded to the dielectric material layer through the bonding interface layer;

The dielectric material layer is formed on the device functional layer supported by the supporting substrate.
The multilayer composite semiconductor substrate structure according to claim 1, wherein the thermal conductivity of the high thermal conductivity material layer is not lower than that of silicon, and the thickness is between 200 nanometers and 50 micrometers; the material is diamond, One or a combination of silicon carbide, multilayer graphene, carbon nanotubes, aluminum nitride, boron arsenide, and boron nitride.
The multilayer composite semiconductor substrate structure according to claim 1, wherein the thickness of the bonding interface layer is between 0.1 and 50 nanometers; and it is prepared by combining one or more of the following materials with one another: Silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, silicon, silicon carbide, beryllium oxide, boron nitride, titanium oxide, nitrogen-carbon chemicals, deteriorated diamond surface layer, deteriorated dielectric material surface layer, hafnium oxide, hafnium oxide, and Zirconia; crystal form is amorphous, single crystal or polycrystalline.
The multilayer composite semiconductor substrate structure according to claim 1, wherein the thickness of the dielectric material layer is between 2 and 50 nanometers, and is prepared by combining one or more of the following materials: oxidation Silicon, aluminum oxide, silicon nitride, aluminum nitride, amorphous silicon, amorphous silicon carbide, titanium oxide, nitrogen-carbon chemicals, hafnium oxide, hafnium oxide, and zirconia.
The multilayer composite semiconductor substrate structure according to claim 1, wherein the device functional layer is made of one of gallium nitride, aluminum gallium nitride, aluminum nitride, gallium oxide, silicon, silicon carbide, and diamond, or The combination; the thickness is between 10 nanometers and 10 micrometers.
The multilayer composite semiconductor substrate structure according to claim 1, wherein the supporting substrate is prepared by using one or more of a combination of the following materials: silicon carbide, gallium nitride, aluminum nitride, silicon , Gallium oxide and sapphire; thickness between 20-700 microns.
A method for preparing a multilayer composite semiconductor substrate structure includes:

Depositing a high thermal conductivity material layer on a sacrificial wafer, the high thermal conductivity material layer having a growth stop surface and a growth start surface opposite to the growth stop surface;

Forming a device functional layer on a support substrate, and growing a dielectric material layer on the device functional layer, the dielectric material layer having a growth stop surface;

Bonding the growth stop surface of the high thermal conductivity material layer with the growth stop surface of the dielectric material layer; and

Selective etching removes the sacrificial wafer, exposing the growth start surface of the high thermal conductivity material layer.
A method for preparing a multilayer composite semiconductor substrate structure includes:

Depositing a high thermal conductivity material layer on a sacrificial wafer, the high thermal conductivity material layer having a growth stop surface and a growth start surface opposite to the growth stop surface;

Attaching the growth stop surface of the high thermal conductivity material layer to a temporary support wafer, and selectively etching to remove the sacrificial wafer, exposing the growth start surface of the high thermal conductivity material layer;

Forming a device functional layer on a support substrate, and growing a dielectric material layer on the device functional layer, the dielectric material layer having a growth stop surface;

Bonding the growth start surface of the high thermal conductivity material layer with the growth stop surface of the dielectric material layer;

The temporary support wafer is removed to expose a growth stop surface of the high thermal conductivity material layer.
The manufacturing method according to claim 7 or 8, wherein bonding is performed by a surface activation method or a plasma activation method to form a bonding interface between the high thermal conductivity material layer and the dielectric material layer. Floor.
The manufacturing method according to claim 7 or 8, wherein a device functional layer is formed on the supporting substrate by a growth or transfer method.
The manufacturing method according to claim 7 or 8, wherein the sacrificial wafer and the high thermal conductivity material layer have different etch rates.
The method according to claim 7 or 8, further comprising: grinding and polishing the surface to be bonded of the high thermal conductivity material layer before bonding.
The method according to claim 12, further comprising: after the high thermal conductivity material layer is deposited on the sacrificial wafer and before the grinding and polishing process, the high thermal conductivity material layer is patterned.
The method according to claim 7 or 8, further comprising: after the device functional layer or the dielectric material layer is formed and before the bonding, forming electrodes and performing metal wiring.
The manufacturing method according to claim 7 or 8, further comprising: thinning the supporting substrate after bonding.