WO2020015755A1 - 一种功放供电装置和方法 - Google Patents

一种功放供电装置和方法 Download PDF

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Publication number
WO2020015755A1
WO2020015755A1 PCT/CN2019/096887 CN2019096887W WO2020015755A1 WO 2020015755 A1 WO2020015755 A1 WO 2020015755A1 CN 2019096887 W CN2019096887 W CN 2019096887W WO 2020015755 A1 WO2020015755 A1 WO 2020015755A1
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Prior art keywords
circuit
power
voltage
redundant
output
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PCT/CN2019/096887
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English (en)
French (fr)
Inventor
李祥峰
黎昌浪
曾吉祥
刘重
孙文昌
校焕庆
张金超
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中兴通讯股份有限公司
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Priority to BR112021000900-0A priority Critical patent/BR112021000900A2/pt
Priority to EP19837408.4A priority patent/EP3826173A4/en
Publication of WO2020015755A1 publication Critical patent/WO2020015755A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52—Circuit arrangements for protecting such amplifiers
    • H03F1/526—Circuit arrangements for protecting such amplifiers protecting by using redundant amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H03F1/0216—Continuous control
    • H03F1/0222—Continuous control by using a signal derived from the input signal
    • H03F1/0227—Continuous control by using a signal derived from the input signal using supply converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52—Circuit arrangements for protecting such amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/516—Some amplifier stages of an amplifier use supply voltages of different value
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H03F2203/7206—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias voltage in the amplifier

Definitions

  • This application relates to, but is not limited to, the field of base station communications, for example, to a power amplifier power supply device and method.
  • the communication technology of the base station is changing with each passing day, and the requirements for the RF power amplifier tube in the base station are getting higher and higher.
  • the gallium nitride (GaN) power amplifier tube has a broadband, high saturation electron mobility, higher breakdown voltage, and can withstand higher temperatures , Higher power capacity and other characteristics, has gradually become a key electronic component of radio frequency amplification of communication base stations.
  • the GaN power amplifier tube has strict power-on and power-off timing requirements.
  • the gate voltage required to supply power must be powered on earlier than the drain voltage and powered off later than the drain voltage. If the power supply of the GaN power amplifier tube does not meet the power-on and power-off timing requirements, and the power-on or power-off is in a short-circuit state, it is easy to burn the GaN power amplifier tube. Due to the high cost of the GaN power amplifier tube, such as a burned out GaN power amplifier tube, it will cause a lot of cost loss.
  • the embodiments of the present application provide a power amplifier power supply device and method, which at least realize the reliability of the power supply timing of the power amplifier in the base station.
  • a power supply device provided by an embodiment of the present application includes a gate voltage circuit, an enabling circuit, a redundant circuit, a power-down holding circuit, and a detection control circuit;
  • the redundant circuit is connected to the first power circuit, the second power circuit, the power-down holding circuit, and the gate voltage circuit, and is set to output the voltage between the first power circuit and the second power circuit. After the redundancy is performed, an input voltage is provided for the power-down holding circuit; after the output voltage of the first power circuit and the output voltage of the power-down hold circuit are redundant, an input voltage is provided for the gate voltage circuit;
  • the power-down holding circuit is connected to the gate voltage circuit and is configured to provide a hold of the power-down energy and a power-off delay to the gate voltage output by the gate voltage circuit;
  • the detection control circuit is connected to the power-down holding circuit, the gate voltage circuit, and the enable circuit, and is configured to detect the power-down hold circuit during power-on, and to detect the power-down circuit during normal work and power-down.
  • the voltage of the power-down holding circuit and the voltage of the gate voltage circuit are detected, and when the detection result meets the judgment condition, the gate voltage is earlier than the second power circuit through the enable control of the enable circuit.
  • the output drain voltage is powered on and the gate voltage is powered off after the drain voltage output by the second power supply circuit.
  • a second redundant backup voltage is generated to provide an input voltage for the gate voltage circuit
  • the voltage of the power-down holding circuit and the voltage of the gate voltage circuit are detected.
  • the gate voltage output by the gate voltage circuit is realized by enabling control.
  • the drain voltage output by the second power circuit is powered on and the gate voltage output by the gate voltage circuit is later than the drain voltage output by the second power circuit.
  • FIG. 1 is a structural diagram of an application scenario according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of components of a power amplifier power supply device according to an embodiment of the present application.
  • FIG. 3 is a flowchart of a power supply method for a power amplifier according to an embodiment of the present application
  • FIG. 5 is a flowchart of another power amplifier power supply method according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a power amplifier power supply device according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another power amplifier power supply device according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another power amplifier power supply device according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another power amplifier power supply device according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another power amplifier power supply device according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another power amplifier power supply device according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of another power amplifier power supply device according to an embodiment of the present application.
  • FIG. 13 is a power-on control flowchart of a power amplifier power supply method according to an embodiment of the present application.
  • FIG. 15 is a control flowchart of abnormality of a channel when a power supply device of a power amplifier works normally according to an embodiment of the present application;
  • 16 is a circuit diagram of a one-way power amplifier power supply device according to an embodiment of the present application.
  • FIG. 17 is a circuit diagram of a multi-channel power amplifier power supply device according to an embodiment of the present application.
  • the terms "including”, “comprising”, or any other variation are intended to cover non-exclusive inclusion, so that a method or device including a series of elements includes not only the explicitly stated elements, but also the absence of Other elements that are explicitly listed or include elements that are inherent to the implementation of the method or device.
  • the element limited by the sentence "including a " does not exclude that there are other related elements (such as steps in the method or units in the device) in the method or device including the element.
  • a unit may be part of a circuit, part of a processor, part of a program or software, etc.).
  • the power supply method provided by the embodiment of the present application includes a series of steps, but the power supply method provided by the embodiment of the present application is not limited to the described steps.
  • the power supply device provided by the embodiment of the present application includes a series of components
  • the power amplifier power supply device provided in the embodiment of the present application is not limited to including the explicitly recorded components.
  • first ⁇ second in the embodiments of the present application merely distinguishes similar objects, and does not represent a specific ordering of the objects. "First ⁇ second" can be interchanged in a specific order or order if allowed order. The objects of the "first ⁇ second" distinction can be interchanged where appropriate, so that the embodiments of the present application can be implemented in an order other than the order illustrated or described herein.
  • FIG. 1 An application scenario of the power supply method of the present application is shown in FIG. 1 and includes: a base station 101 and a base station 102. There are three terminals in a cell coverage area of the base station 101, which are a terminal 11, a terminal 12, and a terminal 13, respectively. There are five terminals in the coverage area, namely terminal 21, terminal 22, terminal 23, terminal 24, and terminal 25.
  • the terminal may be a mobile phone terminal as shown in FIG. 1, or may be one or more kinds of Internet of Things terminals.
  • Network element equipment (such as base stations) has strict power-on and power-off timing requirements for GaN power amplifiers; the gate voltage required to supply power must be powered on earlier than the drain voltage and powered off later than the drain.
  • the first is realized by an electronic switch circuit
  • the second is realized by a discharge circuit
  • the third is realized by a dedicated timing control chip or a microcontroller or a controller.
  • the first solution is realized by an electronic switch circuit. Before the drain voltage is supplied to the power amplifier, the electronic switch circuit is controlled by the gate voltage. Only when the gate voltage is established, the electronic switch is turned on. Once the gate voltage is lost, the electronic switch is turned off immediately. There are many problems with the reliability of the first solution, especially in the case of self-excitation of the power amplifier tube or abnormally large signals and high power, which causes the previous stage power supply to be turned off and then restarted.
  • the second solution is implemented by a discharge circuit. When the gate voltage is not powered off, the reliability of power supply is achieved by discharging the drain voltage, while the reference voltage comparison point of the discharge circuit is susceptible to interference, anomalies, and easy to cause high-voltage discharge, causing damage to the electronic switch of the discharge circuit , Reliability is average.
  • the third solution is implemented by a dedicated timing control chip or a single-chip microcomputer, which depends on the timing control chip or the controller in the single-chip microcomputer. Under abnormal conditions such as the controller, the timing cannot be controlled. Therefore, the reliability of power supply cannot be guaranteed, and there are limitations Sex.
  • the power supply device adopting the embodiment of the present application includes a gate voltage circuit, an enabling circuit, a redundant circuit, a power-down holding circuit, and a detection control circuit.
  • the redundant circuit, the redundant circuit, the first power circuit, and the second The power supply circuit, the power-down holding circuit, and the gate voltage circuit are connected and configured to provide an input voltage for the power-down holding circuit after redundantly outputting the output voltage of the first power circuit and the output voltage of the second power circuit; After the output voltage of the first power circuit is redundant with the output voltage of the power-down holding circuit, the input voltage is provided for the gate voltage circuit; the power-down holding circuit is connected to the gate voltage circuit and is set to the gate voltage The gate voltage output by the circuit provides the power-down energy holding and power-down delay; the detection control circuit is connected to the power-down holding circuit, the gate voltage circuit, and the enabling circuit, and is configured to power-down the power during the power-on process.
  • the holding circuit performs detection, and during the power-off process, the voltage of the power-down holding circuit and the voltage of the gate voltage circuit are detected, and the detection result meets the judgment condition Case, by enabling the enable control circuit, a gate voltage is achieved earlier than the drain voltage of the second power supply circuit and the gate voltage output from the electrical power drain voltage later than the second power supply circuit outputs. Because the redundant stored energy can be used to continuously supply power to the power-down holding circuit and the gate voltage circuit, the signal enable control can be performed through the detection results during power-up and power-down, which achieves The gate voltage is turned on earlier than the drain voltage output from the second power supply circuit and the gate voltage is turned off later than the drain voltage output from the second power supply circuit, which ensures the power-on hold and power-off delay. Therefore, the power amplifier is realized Reliability of power supply timing.
  • the power amplifier power supply device 310 includes a first power circuit 311, a second power circuit 312, a redundant circuit 313, a power-down holding circuit 314, and a gate voltage circuit. 315.
  • the redundancy circuit 313 is configured to provide a power-down holding circuit 314 after redundantly outputting the output voltage of the first power circuit (the first power circuit) 311 and the output voltage of the second power circuit (the P1 power circuit) 312. Input voltage; the first power circuit (first power circuit) 311 supplies power to the base station digital load.
  • the second power circuit (P1 power circuit) 312 supplies power to the drain of the power amplifier tube.
  • the redundancy circuit 313 is further configured to provide an input voltage to the gate voltage circuit 315 after redundantly outputting the output voltage of the first power circuit (first power circuit) 311 and the output voltage of the power-down holding circuit 314.
  • the power-down holding circuit 314 is configured to provide a hold of the power-down energy and a power-off delay to the gate voltage output by the gate voltage circuit.
  • the gate voltage circuit is configured to generate the gate voltage of the power amplifier and supply power to the gate of the power amplifier.
  • the detection control circuit 316 is configured to detect the power-off holding circuit during the power-up process, and to ensure the reliability of the power-down process at the beginning of the power-up process.
  • the detection control circuit 316 is configured to detect the voltage of the power-down holding circuit 314 and the voltage of the gate voltage circuit 315 during normal operation and power-down (can be real-time detection). When the detection result meets the judgment conditions, Through the enable control of the enable circuit 317, that is, after the logical judgment processing of the detection result and the judgment condition, a signal is output to the enable circuit to control the enable circuit to realize the drain of the gate voltage earlier than the output of the second power circuit The pole voltage is turned on and the gate voltage is turned off after the drain voltage output by the second power circuit. That is, during the power-off process, the energy redundancy conversion of one or more drain voltages of the power amplifier is fully utilized, and a sufficient delay is performed for the power-down holding circuit to ensure that the gate voltage is powered off after the drain voltage.
  • the first power circuit (such as the first power circuit) is powered on to supply power to the digital load of the base station, and the output voltage of the first power circuit (such as the first power circuit) and the second power circuit (such as the P1
  • the output voltage of the power supply circuit is redundant to supply power to the power-down holding circuit.
  • the output voltage of the power-down holding circuit and the output voltage of the first power circuit are redundant to the gate voltage circuit.
  • Power supply by detecting the output voltage of the power-down holding circuit and the output voltage of the first to n gate voltage circuits, after making a logical judgment, enabling control of the output voltage of the second power supply circuit (such as the P1 power supply circuit) to achieve the gate
  • the gate voltage output by the voltage circuit is powered on before the drain voltage output by the second power circuit (such as the P1 power circuit).
  • the gate voltage is enabled by the redundant circuit (in one embodiment, the redundant backup circuit) to enable the drain voltage of the power amplifier to be powered on, and the gate voltage is generated redundantly after the drain voltage is powered on.
  • the detection control circuit detects the power-off holding circuit during the power-on process, and ensures the reliability of the power-off process at the beginning of the power-on process. During the power-down process, the energy redundancy conversion of one or more drain voltages of the power amplifier is fully utilized, and a sufficient delay is performed for the power-down holding circuit to ensure that the gate voltage is powered off after the drain voltage.
  • the gate voltage is powered off after the drain voltage, thereby solving the problem of the reliability of the power supply timing of the power amplifier, regardless of any power channel failure, or any way before Or after powering on or off in other power channels, or when abnormal conditions occur during normal work, this application can reliably and effectively guarantee the power supply requirements of the GaN power amplifier tube.
  • the redundancy refers to: the realization of the "or" power supply of multiple voltages, that is, the power supply is selected, and the multiple voltages do not affect each other, and it is guaranteed that the system works normally as long as one of the voltages is normal.
  • the power amplifier power supply device in the embodiment of the present application is more compact and reliable, and can be widely used in the 4th generation mobile communication system (4G) and the fifth generation mobile communication system.
  • (4G) and the fifth generation mobile communication system 5th Generation, mobile communication system, 5G
  • Wireless communication base station equipment has high versatility and has wide application value.
  • the redundant circuit includes a first redundant circuit (redundant circuit 1) and a second redundant circuit (redundant circuit 2).
  • a first input terminal of the first redundant circuit (redundant circuit 1) is connected to an output terminal of the first power supply circuit (first power supply circuit).
  • the second input terminal of the first redundant circuit (redundant circuit 1) is connected to the output terminal of the second power supply circuit (P1th power supply circuit).
  • the output terminal of the first redundant circuit (redundant circuit 1) is connected to the input terminal of the power-down holding circuit, and is configured to provide an input voltage for the power-down holding circuit.
  • the first power circuit (first power circuit) supplies power to the digital load of the base station.
  • the second power circuit (the P1 power circuit) supplies power to the drain of the power amplifier.
  • the redundant circuit further includes a second redundant circuit (redundant circuit 2).
  • a first input terminal of the second redundant circuit (redundant circuit 2) is connected to an output terminal of the first power supply circuit (first power supply circuit).
  • the second input terminal of the second redundant circuit (redundant circuit 2) is connected to the output terminal of the power-down holding circuit.
  • An output terminal of the second redundant circuit (redundant circuit 2) is connected to the gate voltage circuit (first gate voltage circuit), and is configured to provide an input voltage to the gate voltage circuit.
  • the gate voltage circuit is configured to generate a gate voltage of the power amplifier and supply power to the gate of the power amplifier.
  • a first input terminal of the detection control circuit is connected to an output terminal of the power-down holding circuit; a second input terminal of the detection control circuit is connected to an output terminal of the gate voltage circuit; an output of the detection control circuit A terminal is connected to an input terminal of the enabling circuit.
  • an output end of the enabling circuit is connected to an enabling control circuit of the second power circuit (P1 power circuit), and is configured to perform startup control on the second power circuit (P1 power circuit).
  • the power supply device of the power amplifier may include a first power circuit, a P1 power circuit, a redundant circuit 1, a power-down holding circuit, a redundant circuit 2, a gate voltage circuit, a detection control circuit, and a power supply. Ergy circuit.
  • the first power supply circuit supplies power to the base station digital load; the P1 power supply circuit supplies power to the drain of the GaN power amplifier tube.
  • the power-down holding circuit is used to provide the power-down energy holding and power-down delay for the gate voltage output by the gate voltage circuit.
  • the input terminal of the power-down holding circuit is connected to the output terminal of the redundant circuit 1.
  • the output is connected to the input of the redundant circuit 2.
  • the redundant circuit 2 provides power-on energy retention and power-off delay for the gate voltage.
  • One input terminal of the redundant circuit 2 is connected to the output terminal of the first power circuit, and the other input of the redundant circuit 2 is provided. The terminal is connected to the output terminal of the power-down holding circuit, and the output terminal of the redundant circuit 2 is connected to the input terminal of the first gate voltage circuit.
  • the gate voltage circuit generates the gate voltage of the GaN power amplifier tube, and supplies power to the gate of the P1th GaN power amplifier tube.
  • One input terminal of the detection control circuit is connected to the output terminal of the power-down holding circuit; the other input terminal of the detection control circuit is connected to the output terminal of the gate voltage circuit; after the logic processing, the output signal of the detection control circuit controls the enable circuit.
  • the enabling circuit is configured to control the startup of the P1 power circuit, the input of the enabling circuit is connected to the output of the detection control circuit, and the output of the enabling circuit is connected to the enabling control circuit of the P1 power circuit.
  • the first power circuit (the first power circuit) is a single power source or multiple power sources.
  • the first power supply circuit supplies power to the digital partial load, and may not be limited to a single power supply, and may be a first to m-th power supply.
  • the second power circuit (the P1 power circuit) is a single power source or multiple power sources.
  • the P1th power supply circuit supplies power to the power amplifier, and is not limited to a single power supply. It can be the P1 to Pn power supplies.
  • the input source of the first power supply circuit (the first power supply circuit) is the same as that of the second power supply circuit (the P1 power supply circuit); or the first power supply circuit (the first power supply circuit) and the second power supply circuit
  • the input source of the power supply circuit (P1th power supply circuit) is different.
  • the input sources of the 1st to mth power sources and the P1 to Pn power sources may be the same or different input sources.
  • the first power circuit (the first power circuit) and the second power circuit (the P1 power circuit) connected to the first redundant circuit (the redundant circuit 1) are any combination of one or more power sources.
  • the first power circuit connected to the redundant circuit 1 may be one, several, or all of the 1 to m power sources, and one, several, or all of the P1 to Pn power sources; the implementation of the redundant circuit 1 It can be implemented for electronic switches, diodes, relays or switch circuits.
  • the first power circuit (first power circuit) connected to the second redundant circuit (redundant circuit 2) is any combination of one or more power sources.
  • the first power circuit connected to the redundant circuit 2 may be one, several, or all of the 1 to m power sources.
  • the redundant circuit 2 redundantly outputs the output voltage of the first power circuit and the output voltage of the power-down holding circuit. In addition, it provides energy to the gate voltage circuit.
  • the implementation forms of the power-down holding circuit include: a wide input range boost circuit, a wide input range step-down circuit, other conversion energy storage circuits or energy storage elements.
  • the implementation form of the gate voltage circuit includes one or more of the multiple power amplifier tubes.
  • any one or more of the first to n-way power amplifier tubes provide the gate voltage, and the implementation form of the gate voltage circuit can be flexibly configured according to the gate voltage load power.
  • a power supply method for a power amplifier is also provided. The method is implemented based on the power supply device for the power amplifier described above.
  • a power supply method for a power amplifier includes:
  • Step 410 After the output voltage of the first power circuit and the output voltage of the second power circuit are redundant, a first redundant backup voltage is generated to provide an input voltage for the power-down holding circuit.
  • a first redundant backup voltage is generated to provide an input voltage for the power-down holding circuit.
  • Step 420 After redundantly outputting the output voltage of the first power circuit and the output voltage of the power-down holding circuit, a second redundant backup voltage is generated to provide an input voltage for the gate voltage circuit.
  • a second redundant backup voltage is generated to provide an input voltage for the gate voltage circuit.
  • Step 430 Detect the power-off holding circuit during the power-on process.
  • Step 440 Detect the voltage of the power-down holding circuit and the voltage of the gate voltage circuit during normal operation and power-down.
  • the gate voltage is earlier than the drain by enabling control. Voltage power-up and gate voltage power-down later than drain voltage.
  • the gate voltage is output by the gate voltage circuit, and the drain voltage is output by the second power circuit.
  • the detection of the output voltage of the power-down holding circuit and the output voltage of the gate voltage circuit during normal operation and power-down may be real-time detection.
  • a power supply method for a power amplifier a first redundant backup voltage is stored in a first redundant circuit (redundant circuit 1), and a second redundant backup voltage is stored in a second redundant circuit (redundant circuit)
  • the method includes:
  • Step 510 After redundantly outputting the output voltage of the first power circuit and the output voltage of the second power circuit, a first redundant backup voltage is generated, and the first redundant circuit (redundant circuit 1) is used as a power-down holding circuit. Provide input voltage.
  • a first redundant backup voltage is generated to provide an input voltage for the power-down holding circuit.
  • Step 520 After redundantly outputting the output voltage of the first power supply circuit and the output voltage of the power-down holding circuit, a second redundant backup voltage is generated, and the second redundant circuit (redundant circuit 2) is used as the gate voltage circuit. Provide input voltage.
  • a second redundant backup voltage is generated to provide an input voltage for the gate voltage circuit.
  • Step 530 Detect the power-off holding circuit during the power-on process.
  • the enable circuit When it is detected that each of the output voltage of the power-down holding circuit and the output voltage of the gate voltage circuit is normal, the enable circuit is enabled, and the second power circuit (the P1 power circuit) is powered on.
  • Step 540 Power on the drain voltage of the power amplifier.
  • a power supply method for a power amplifier a first redundant backup voltage is stored in a first redundant circuit (redundant circuit 1), and a second redundant backup voltage is stored in a second redundant circuit (redundant circuit) In 2), as shown in FIG. 5, the method includes:
  • Step 610 After redundantly outputting the output voltage of the first power circuit and the output voltage of the second power circuit, a first redundant backup voltage is generated, and the first redundant circuit (redundant circuit 1) is used as a power-down holding circuit. Continue to supply power.
  • a first redundant backup voltage is generated to continue supplying power to the power-down holding circuit.
  • Step 620 After redundantly outputting the output voltage of the first power circuit and the output voltage of the power-down holding circuit, a second redundant backup voltage is generated, and the second redundant circuit (redundant circuit 2) is used as the gate voltage circuit. Power on and continue to power the gate of the amplifier.
  • a second redundant backup voltage is generated to continue supplying power to the gate voltage circuit.
  • Step 630 Detect the voltage of the power-down holding circuit and the voltage of the gate voltage circuit during the power-down process.
  • the gate voltage circuit is subsequently powered off.
  • Step 640 In response to the judgment result that the gate voltage is higher than the safe voltage of the power amplifier, the second redundant circuit (redundant circuit 2) is maintained for a specified time, and the output voltage of the gate voltage circuit is lower than the gate As a result of judging the undervoltage point of the voltage circuit, the gate voltage circuit is powered off.
  • the first power supply circuit is powered on to supply power to the digital load of the base station, and the output voltage of the first power supply circuit and the output voltage of the P1 power supply circuit are redundant to supply power to the power-down holding circuit, while maintaining power-down
  • the output voltage of the circuit is redundant with the output voltage of the first power supply circuit to supply power to the gate voltage circuit.
  • the energy stored in the drain voltage power circuit of the P1 power circuit is fully utilized, and the first redundant backup voltage is generated after the energy is redundantly provided to the power-down holding circuit, thereby providing a stable power-down holding circuit, and
  • the first power supply circuit and the power-down holding circuit redundantly generate the first redundant backup voltage and provide it to the gate voltage circuit, thereby providing a reliable gate voltage circuit to ensure the reliability of the power-off delay under any conditions.
  • the power-on process is not affected by the input voltage of the first power circuit and the input voltage of the P1 power circuit, and there is no mandatory power-on sequence for the first power circuit and the P1 power circuit.
  • the remaining circuit and detection control circuit ensure that the output voltage of the gate voltage circuit is enabled after the P1 power circuit is completed, and the normal power-on requirements of the GaN power amplifier tube are reliably realized; at the same time, the power-down holding circuit is detected during the power-on process. If an abnormality is found, the output of the P1 power supply circuit cannot be turned on, and the power-off holding circuit is checked to ensure that the power-on and power-off sequence is more reliable.
  • the P1-Pn power supply circuit When the input source of the P1-Pn power supply circuit is powered off, the P1-Pn power supply circuit is powered off, and the power-down holding circuit can be used to ensure that the drain voltage of the GaN power amplifier tube falls to a safe voltage range within the SOA curve, and then passes through lower The input 1 ⁇ n gate voltage circuit is fully delayed to ensure that the gate voltage is finally powered off.
  • the redundant circuits, power-down holding circuits, and gate voltage circuits will not be powered down to ensure power supply reliability; the P1 ⁇ Pn power supply circuits do not mutually supply power Impact, can be applied to multi-channel base station power amplifier, ensuring power supply reliability.
  • the power supply device may be implemented by software, and software (such as a computer program) may be stored in a memory.
  • the memory may be a volatile memory or a non-volatile memory, or may include a volatile memory. And non-volatile memory.
  • the non-volatile memory may be a read-only memory (Read Only Memory, ROM), a programmable read-only memory (Programmable Read-Only Memory, PROM), and an erasable programmable read-only memory (Erasable Programmable Read-Only Memory).
  • the volatile memory may be a Random Access Memory (RAM), and the volatile memory is used as an external cache.
  • RAM Random Access Memory
  • RAM random Access Memory
  • SRAM Static Random Access Memory
  • SSRAM Synchronous Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • Double Dynamic Data Random Access Random Memory DDRSDRAM
  • ESDRAM Enhanced Synchronous Random Access Memory
  • SLDRAM synchronous connection dynamic random access memory
  • DDRRAM Direct Rambus Random Access Memory
  • DRRAM Direct Rambus Random Access Memory
  • the memories described in the embodiments of the present application are intended to include, but not limited to, the memories already described in the present application and any other suitable types of memories.
  • a computer-readable storage medium configured to store the calculation program provided in the foregoing embodiment, so as to complete the steps described in the foregoing method.
  • the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface memory, optical disk, or CD-ROM; it may also be one or more including one or any combination of the above-mentioned memories device.
  • the enabling circuit in the embodiment of the present application may be the generating circuit of the xth power source, or any electronic switching circuit before and after the Px power source, and is not limited to the description of the enabling circuit in the following embodiments.
  • FIG. 6 is a schematic structural diagram of a power amplifier power supply device according to an embodiment of the present application.
  • the first power circuit supplies power to the base station digital load, and the first P1 power circuit supplies power to the power amplifier tube; the output voltage of the first power circuit and the output voltage of the P1 power circuit supply power to the power-down holding circuit through the redundant circuit 1, and the power-down holding circuit The output voltage and the output voltage of the first power supply circuit supply power to the gate voltage circuit through the redundant circuit 2.
  • the logical judgment is performed to satisfy the judgment condition. After that, the output voltage of the P1 power supply circuit is controlled to supply power to the power amplifier tube.
  • FIG. 7 is a schematic structural diagram of another power amplifier power supply device according to an embodiment of the present application.
  • an input voltage of the redundant circuit 1 may be selected, and may be an input voltage of a first power circuit or an output voltage of the first power circuit. The rest is the same as in FIG. 6.
  • the first power supply circuit supplies power to the base station digital load, and the P1 power supply circuit supplies power to the power amplifier tube; the input voltage of the first power supply circuit and the output voltage of the P1 power supply circuit supply power to the power-down holding circuit through the redundant circuit 1.
  • the output voltage of the first power supply circuit and the output voltage of the P1 power supply circuit supply power to the power-down holding circuit through the redundant circuit 1.
  • the output voltage of the power-down holding circuit and the output voltage of the first power supply circuit supply power to the gate voltage circuit through the redundant circuit 2.
  • a logical judgment is made. After the judgment condition is satisfied, the output voltage of the P1 power supply circuit is controlled to supply power to the power amplifier tube.
  • FIG. 8 is a schematic structural diagram of another power amplifier power supply device according to an embodiment of the present application.
  • an enabling circuit can enable an electronic switch in front of a P1 power circuit.
  • the first power supply circuit supplies power to the base station digital load
  • the P1 power supply circuit supplies power to the power amplifier tube; the output voltage of the first power supply circuit and the output voltage of the P1 power supply circuit supply power to the power-down holding circuit through the redundant circuit 1.
  • the output voltage of the power-down holding circuit and the output voltage of the first power supply circuit supply power to the gate voltage circuit through the redundant circuit 2.
  • the output voltage of the P1 power supply circuit is controlled to supply power to the power amplifier tube.
  • the enabling circuit is connected to the P1 power circuit through an electronic switch, and the input of the P1 power circuit is connected to the output of the electronic switch.
  • the enabling circuit can enable the electronic switch in front of the P1 power circuit.
  • FIG. 9 is a schematic structural diagram of another power amplifier power supply device according to an embodiment of the present application.
  • the enabling circuit can enable the electronic switch after the P1 power supply circuit.
  • the first power supply circuit supplies power to the base station digital load
  • the P1 power supply circuit supplies power to the power amplifier tube
  • the output voltage of the first power supply circuit and the output voltage of the P1 power supply circuit supply power to the power-down holding circuit through the redundant circuit 1.
  • the output voltage of the power-down holding circuit and the output voltage of the first power supply circuit supply power to the gate voltage circuit through the redundant circuit 2.
  • the output voltage of the P1 power supply circuit is controlled to supply power to the power amplifier tube.
  • the enabling circuit is connected to the P1 power circuit through an electronic switch.
  • the output of the P1 power circuit is connected to the input of the electronic switch.
  • the enabling circuit can enable the electronic switch behind the P1 power circuit.
  • FIG. 10 is a schematic structural diagram of another power amplifier power supply device according to an embodiment of the present application.
  • the input of the redundant circuit 1 in the schematic is the output voltage of the first, second, ..., mth power circuits and the The output voltage of the P1 power supply circuit;
  • the input of the redundant circuit 2 is the 1,2, ... m output voltage of the power supply circuit and the output voltage of the power-down holding circuit, and the output of the redundant circuit 2 generates the 1,2, ...
  • the input voltage of the n-gate voltage circuit is otherwise consistent with the content described in FIG. 7.
  • the 1,2, ... m power circuit supplies power to the base station digital load, and the P1 power circuit supplies power to the power amplifier; the output voltage of the 1,2, ...
  • FIG. 11 is a schematic structural diagram of another power amplifier power supply device according to an embodiment of the present application.
  • the input of the redundant circuit 1 is the output voltage of the 1,2, ... mth power supply circuit and the P1 , P2, ... Pn output voltage of the power supply circuit;
  • the input of the redundant circuit 2 is the first, the output voltage of the m power supply circuit and the output voltage of the power-down holding circuit, and the output of the redundant circuit 2 produces the first
  • the input voltage of 2, 2, ... n gate voltage circuit, and the rest are consistent with the content described in FIG. 7.
  • the 1,2, ... m power circuit supplies power to the base station digital load
  • the P1-Pn power circuit supplies power to the power amplifier; the output voltage of the 1,2, ...
  • the output voltage of the circuit supplies power to the power-down holding circuit through redundant circuit 1.
  • the output voltage of the power-down holding circuit and the output voltage of the 1,2, ... mth power circuit supply power to the gate voltage circuit through redundant circuit 2.
  • the output of the surplus circuit 2 generates the input voltage of the 1,2, ... nth gate voltage circuit.
  • FIG. 12 is a schematic structural diagram of another power amplifier power supply device according to an embodiment of the present application.
  • an output of the redundant circuit 2 generates a gate voltage through an n-th gate voltage circuit, and the rest are all It is the same as that described in FIG. 11.
  • the 1,2, ... m power circuit supplies power to the digital load of the base station, and the P1-Pn power circuit supplies power to the power amplifier; the output voltage of the 1,2, ... m power circuit and the P1-Pn power supply
  • the output voltage of the circuit supplies power to the power-down holding circuit through the redundant circuit 1.
  • the output voltage of the power-down holding circuit and the output of the 1,2, ... mth power circuit supply power to the gate voltage circuit through the redundant circuit 2.
  • the redundant circuit The output of 2 generates the input voltage of the n-th gate voltage circuit.
  • the control of the P1 power circuit can be controlled.
  • the output voltage powers the amplifier tube.
  • FIG. 13 is a power-on control flowchart of a power amplifier power supply device according to an embodiment of the present application, including:
  • Step 1010 The input source is powered on; the first power circuit is powered on.
  • Step 1020 Power on the power-off holding circuit through the redundant circuit 1.
  • Step 1030 Power on the gate voltage circuit through the redundant circuit 2.
  • Step 1040 The detection control circuit detects whether the output voltage of the power-down holding circuit and the output voltage of the gate voltage circuit are normal; in response to any one of the abnormal results of the output voltage of the power-down holding circuit and the output voltage of the gate voltage circuit, , Step 1070 is performed; and in response to the judgment result that the output voltage of the power-down holding circuit and the output voltage of the gate voltage circuit are normal, step 1050 is performed.
  • Step 1050 The enabling circuit is valid, and the P1 power circuit is enabled to be powered on.
  • Step 1060 The drain of the power amplifier is powered on.
  • Step 1070 Power off and perform maintenance inspection. Return to step 1010.
  • FIG. 14 is a power-down control flowchart of a power amplifier power supply device according to an embodiment of the present application, including:
  • Step 2020 Continue supplying power to the power-down holding circuit through the redundant circuit 1.
  • Step 2030 Continue supplying power to the gate voltage circuit through the redundant circuit 2 and continue to supply power to the gate of the power amplifier.
  • Step 2040 power off and hold, the detection control circuit detects whether the gate voltage is lower than the SOA safe voltage, and in response to the judgment result that the gate voltage is higher than the SOA safe voltage of the power amplifier, proceeds to step 2030; Judgment result of voltage; proceed to step 2050.
  • Step 2050 Power off the holding circuit.
  • step 2060 after the redundancy circuit 2 is maintained for a period of time, after the output voltage of the gate voltage circuit is lower than the undervoltage point of the gate voltage circuit, the gate voltage circuit is powered off.
  • Step 2070 Power off the gate voltage of the power amplifier.
  • FIG. 15 is a control flowchart of abnormal output of the Pn power supply circuit when the power supply device of the power amplifier works normally according to the embodiment of the present application, that is, if any one of the power amplifiers is abnormal, it does not affect the power supply of the other power amplifiers, decouples each other, and supplies power. reliable.
  • step 3010 during normal operation, the output voltage of the Pn power supply circuit is abnormal, and it is determined whether to repair the circuit. In response to the determination result of the maintenance, step 3040 is performed; in response to the determination result of no maintenance, step 3020 is performed.
  • Step 3020 Supply power to the power-off holding circuit through the redundant circuit 1 to keep the power-off holding circuit working normally.
  • Step 3030 Power the gate voltage circuit through the redundant circuit 2 to keep the gate voltage circuit working normally.
  • Step 3040 Power off and repair the Pn power supply circuit.
  • the power supply of this power amplifier is not affected by the input voltage of the 1st to mth power circuits and the P1 to Pn power circuits.
  • the redundant circuits and detection control circuits ensure that the gate voltage circuit can be enabled after the P1 to Pn problems.
  • the power supply circuit reliably realizes the normal power-on requirements of the GaN power amplifier tube.
  • the power-off holding circuit is tested during power-on. If an abnormality is found, the P1 power output cannot be turned on. The power-up and power-down sequences are more reliable.
  • the abnormality of any one of the 1st to nth gate voltage circuits in the power-on link does not affect the establishment of the gate voltage; the abnormality of any one of the P1 to Pn power supply circuits in the power-on link does not affect the drain voltage of other normal power amplifiers. Established; and found abnormal, can be powered off for maintenance at any time, power-on detection to ensure the reliability of the power-off sequence.
  • the power-off sequence is reliable.
  • the redundant circuit 1, redundant circuit 2, and power-off holding circuit ensure that the abnormality and normality of the drain voltage circuit of any one of the power amplifiers are not decoupled from each other.
  • the input In normal operation, if the input is abnormal, such as lightning surge or battery aging, the input voltage drops or jumps quickly; or the Pn power supply circuit or the nth power supply circuit is abnormally damaged, causing one or more gate voltages to drop. Redundant circuit 1, redundant circuit 2 and power-off keep the abnormality and normality that do not depend on any one power source.
  • the timing of the GaN power amplifier tube is decoupled from each other. It will not cause the other one or more channels to be paralyzed and must be repaired. It is stable and reliable.
  • the output undervoltage point of the gate voltage circuit may be a safety voltage of the GaN gate voltage SOA curve or a voltage value lower than the safety voltage.
  • FIG. 16 is a circuit diagram of a one-way power amplifier power supply device according to an embodiment of the present application; the first power source outputs 5.6V to the digital power through DC-DC conversion, and the P1 power source outputs 50V to power the drain of the power amplifier through DC-DC conversion; The first power supply and the P1 power supply supply power to the power-down holding circuit through a diode combination.
  • the power-down hold circuit and the first power supply pass through DC-DC to generate a gate voltage of -8V after being combined; when the power-down holding circuit has an output voltage greater than V2 Indicates that the power-off keeps the circuit normal; at the same time, the -8V voltage reaches the reference point of the comparison circuit, and the comparison circuit is turned on; the optocoupler D1 secondary enables the isolation module, and the P1 power supply is powered on.
  • the power-down holding circuit When powering off, the power-down holding circuit maintains energy so that the gate voltage drops to above the SOA safe voltage V1 of the power amplifier tube, and can still maintain the gate voltage of -8V. When the drain voltage drops below V1, it is still redundant through the first power supply. The power supply is delayed for -8V until the DC-DC conversion undervoltage caused by the gate voltage is turned off, and the gate voltage is powered off, which guarantees full power-down delay reliability.
  • FIG. 17 is a circuit diagram of a multi-channel power amplifier power supply device according to an embodiment of the present application; a first power source outputs 5.6V to a digital power supply through DC-DC conversion, and a second power source outputs 5.6V to a base station digital load through DC-DC conversion; ; The mth power supply outputs 5.6V or other voltage to the base station digital load through DC-DC conversion; the P1 power supply outputs 50V to power the drain of the power amplifier through DC-DC conversion; the P2 power supply outputs 50V to the power amplifier through DC-DC conversion The Pn power supply supplies 50V to the drain of the power amplifier through DC-DC conversion output; the first power supply, the second power supply, ...
  • the mth power supply and the P1 power supply, the P2 power supply, ... the Pn power supply passes The diode combination supplies power to the power-down holding circuit.
  • the power-down hold circuit and the first power supply, the second power supply, ... the m-th power supply passes through the DC-DC to generate a gate voltage of -8V1; -8V2, ...- 8Vn
  • the output voltage of the power-down holding circuit is greater than V2
  • the -8V voltage reaches the reference point of the comparison circuit, and the comparison circuit is turned on; the optocoupler D1 secondary enables the isolation module, P1, P2 ...
  • V1 is the safe operating voltage of the power amplifier tube or a voltage lower than the safe voltage
  • V2 is a lower holding voltage than V1, which may be the undervoltage point of the gate voltage or a voltage lower than the undervoltage point.
  • GaAS gallium arsenide

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Abstract

本文公开了一种功放供电装置和方法；功放供电装置包括：冗余电路，设置为在对第一电源电路的输出电压与第二电源电路的输出电压做冗余后，为下电保持电路提供输入电压；在对第一电源电路的输出电压与下电保持电路的输出电压做冗余后，为栅极电压电路提供输入电压；下电保持电路，设置为对栅极电压电路输出的栅极电压提供下电能量的保持和下电延时；检测控制电路，设置为在上电过程中，对下电保持电路做检测，在正常工作和下电过程中对下电保持电路的电压与栅极电压电路的电压做检测，在检测结果满足判断条件的情况下，通过使能电路的使能控制，实现栅极电压早于漏极电压上电和栅极电压晚于漏极电压下电。

Description

一种功放供电装置和方法
本申请要求在2018年07月19日提交中国专利局、申请号为201810797983.4的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及但不限于基站通信领域，例如涉及一种功放供电装置和方法。
背景技术
基站通信技术日新月异，基站中对射频功放管的要求也越来越高，氮化镓(GaN)功放管具有宽带、高饱和电子迁移率、更高的击穿电压、能够耐受更高的温度，更高的功率容量等特点，已逐渐成为通讯基站射频放大的关键电子元件。
而GaN功放管有严格的上电和下电时序要求，要求供电的栅极电压必须早于漏极电压上电，晚于漏极电压下电。如GaN功放管的供电不满足上电和下电时序要求，上电或下电处于短路状态，很容易烧毁GaN功放管，由于GaN功放管造价昂贵，如GaN功放管烧坏会造成大量的成本损耗。
如何保证基站中功放的供电时序的可靠性是要解决的问题，然而，相关技术中对此并未存在有效的解决方案。
发明内容
本申请实施例提供了一种功放供电装置和方法，至少实现了基站中功放的供电时序的可靠性。
本申请实施例提供的一种功放供电装置，包括：栅极电压电路、使能电路、冗余电路、下电保持电路和检测控制电路；其中，
所述冗余电路，冗余电路与第一电源电路、第二电源电路、下电保持电路和栅极电压电路连接，设置为在对第一电源电路的输出电压与第二电源电路的输出电压做冗余后，为所述下电保持电路提供输入电压；在对第一电源电路的输出电压与下电保持电路的输出电压做冗余后，为所述栅极电压电路提供输入电压；
所述下电保持电路，与栅极电压电路连接，设置为对栅极电压电路输出的栅极电压提供下电能量的保持和下电延时；
所述检测控制电路，与下电保持电路、栅极电压电路和使能电路连接，设置为在上电过程中对所述下电保持电路做检测，及在正常工作和下电过程中对所述下电保持电路的电压与所述栅极电压电路的电压做检测，在检测结果满足判断条件的情况下，通过所述使能电路的使能控制，实现栅极电压早于第二电源电路输出的漏极电压上电和栅极电压晚于第二电源电路输出的漏极电压下电。
本申请实施例提供的一种功放供电方法，包括：
在对第一电源电路的输出电压与第二电源电路的输出电压做冗余后，产生第一冗余备份电压为下电保持电路提供输入电压；
在对第一电源电路的输出电压与下电保持电路的输出电压做冗余后，产生第二冗余备份电压为栅极电压电路提供输入电压；
在上电过程中对所述下电保持电路做检测；
在正常工作和下电过程中对下电保持电路的电压与栅极电压电路的电压做检测，在检测结果满足判断条件的情况下，通过使能控制实现栅极电压电路输出的栅极电压早于第二电源电路输出的漏极电压上电和栅极电压电路输出的栅极电压晚于第二电源电路输出的漏极电压下电。
附图说明
图1为本申请实施例提供的一种应用场景的架构图；
图2为本申请实施例提供的一种功放供电装置的元器件组成示意图；
图3为本申请实施例提供的一种功放供电方法的流程图；
图4为本申请实施例提供的另一种功放供电方法的流程图；
图5为本申请实施例提供的另一种功放供电方法的流程图；
图6为本申请实施例提供的一种功放供电装置的结构示意图；
图7为本申请实施例提供的另一种功放供电装置的结构示意图；
图8为本申请实施例提供的另一种功放供电装置的结构示意图；
图9为本申请实施例提供的另一种功放供电装置的结构示意图；
图10为本申请实施例提供的另一种功放供电装置的结构示意图；
图11为本申请实施例提供的另一种功放供电装置的结构示意图；
图12为本申请实施例提供的另一种功放供电装置的结构示意图；
图13为本申请实施例提供的一种功放供电方法的上电控制流程图；
图14为本申请实施例提供的一种功放供电方法的下电控制流程图；
图15为本申请实施例提供的一种功放供电装置正常工作时某一通道异常的控制流程图；
图16为本申请实施例提供的一种一路功放供电装置的电路图；
图17为本申请实施例提供的一种多路功放供电装置的电路图。
具体实施方式
以下结合附图及实施例，对本申请进行说明。此处所提供的实施例仅用以解释本申请，并不用于限定本申请。另外，以下所提供的实施例是用于实施本申请的部分实施例，而非提供实施本申请的全部实施例，。
在本申请实施例中，术语“包括”、“包含”或者任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的方法或者装置不仅包括所明确记载的要素，而且还包括没有明确列出的其他要素，或者是还包括为实施方法或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的方法或者装置中还存在另外的相关要素(例如方法中的步骤或者装置中的单元，例如单元可以是部分电路、部分处理器、部分程序或软件等等)。
例如，本申请实施例提供的功放供电方法包含了一系列的步骤，但是本申请实施例提供的功放供电方法不限于所记载的步骤，本申请实施例提供的功放供电装置包括了一系列元器件，但是本申请实施例提供的功放供电装置不限于包括所明确记载的元器件。
本申请实施例所涉及的术语“第一\第二”仅仅是区别类似的对象，不代表针对对象的特定排序，“第一\第二”在允许的情况下可以互换特定的顺序或先后次序。“第一\第二”区分的对象在适当情况下可以互换，以使本申请的实施例能够以除本文中图示或描述的顺序以外的顺序实施。
本申请的功放供电方法的一个应用场景如图1所示，包括：基站101和基站102，基站101的小区覆盖范围内有三个终端，分别为终端11、终端12和终端13，基站102的小区覆盖范围内有五个终端，分别为终端21、终端22、终端23、终端24和终端25。终端可以如图1所示为手机终端，也可以为一种或多种物联网终端等。网元设备(如基站)中对GaN功放管有严格的上下电时序要求；要求供电的栅极电压必须早于漏极电压上电，晚于漏极下电。
相关技术中，基站供电可靠性实现方案主要有三种：第一种是通过电子开 关电路实现；第二种是通过放电电路实现；第三种是通过专用时序控制芯片或者单片机或者控制器等实现。其中，第一种方案是通过电子开关电路实现。在漏极电压供给功放前，通过栅极电压控制电子开关电路，只有栅极电压建立，电子开关才打开。栅极电压一但掉电，立刻关闭电子开关。第一种方案的可靠性存在较多问题，尤其是在功放管自激或者异常大信号，大功率的情况下，导致前级供电关断后再次启动，很容易出现超出电子开关的安全操作区域(Safe Operating Area，SOA)曲线，电子开关损坏的现象，可靠性一般。第二种方案是通过放电电路实现。在栅极电压未掉电时，通过对漏极电压放电实现供电的可靠性，而放电电路的基准电压比较点，容易受到干扰，出现异常，很容易引起高压放电，导致放电电路的电子开关损坏，可靠性一般。第三种方案是通过专用时序控制芯片或者单片机等实现，依赖时序控制芯片或者单片机中的控制器等，在控制器等异常条件下，无法控制时序，因此，无法保证供电的可靠性，存在局限性。
这三种方案存在各自的缺陷，且可靠性不高。如果不能保证功放管上下电时序的可靠性，容易使功放管上下电处于短路状态，很容易烧毁功放管。功放管造价昂贵，如烧坏会造成大量的成本损耗。采用本申请实施例的功放供电装置，包括栅极电压电路、使能电路、冗余电路、下电保持电路、检测控制电路；其中，冗余电路，冗余电路与第一电源电路、第二电源电路、下电保持电路和栅极电压电路连接，设置为在对第一电源电路的输出电压与第二电源电路的输出电压做冗余后，为所述下电保持电路提供输入电压；在对第一电源电路的输出电压与下电保持电路的输出电压做冗余后，为所述栅极电压电路提供输入电压；下电保持电路，与栅极电压电路连接，设置为对栅极电压电路输出的栅极电压提供下电能量的保持和下电延时；检测控制电路，与下电保持电路、栅极电压电路和使能电路连接，设置为在上电过程中对所述下电保持电路做检测，及在下电过程中对所述下电保持电路的电压与所述栅极电压电路的电压做检测，在检测结果满足判断条件的情况下，通过所述使能电路的使能控制，实现栅极电压早于第二电源电路输出的漏极电压上电和栅极电压晚于第二电源电路输出的漏极电压下电。由于能通过冗余存储的能量，采用冗余电路持续对下电保持电路和栅极电压电路供电，在上电过程中和下电过程中都可以通过检测结果进行信号的使能控制，实现了栅极电压早于第二电源电路输出的漏极电压上电和栅极电压晚于第二电源电路输出的漏极电压下电，确保了上电保持和下电延时，因此，实现了功放供电时序的可靠性。
本申请实施例的一种功放供电装置，如图2所示，功放供电装置310包括：第一电源电路311、第二电源电路312、冗余电路313、下电保持电路314、栅极电压电路315、检测控制电路316和使能电路317。冗余电路313，设置为在 对第一电源电路(第1电源电路)311的输出电压与第二电源电路(第P1电源电路)312的输出电压做冗余后，为下电保持电路314提供输入电压；第一电源电路(第1电源电路)311为基站数字负载供电。第二电源电路(第P1电源电路)312为功放管的漏极供电。冗余电路313，还设置为在对第一电源电路(第1电源电路)311的输出电压与下电保持电路314的输出电压做冗余后，为栅极电压电路315提供输入电压。下电保持电路314设置为对栅极电压电路输出的栅极电压提供下电能量的保持和下电延时。栅极电压电路，设置为产生功放的栅极电压，为功放的栅极供电。检测控制电路316设置为在上电过程中对下电保持电路做检测，在上电过程之初就保证下电过程的可靠性。及检测控制电路316设置为在正常工作和下电过程中对下电保持电路314的电压与栅极电压电路315的电压做检测(可以为实时检测)，在检测结果满足判断条件的情况下，通过使能电路317的使能控制，即：经过检测结果与判断条件的逻辑判断处理后，输出信号给使能电路，以控制使能电路，实现栅极电压早于第二电源电路输出的漏极电压上电和栅极电压晚于第二电源电路输出的漏极电压下电。即：在下电过程中充分利用功放的一个或多个漏极电压的能量冗余转换，为下电保持电路进行充分延时，保证了栅极电压晚于漏极电压下电。
一实际应用中，将第一电源电路(如第1电源电路)上电，给基站数字负载供电，将第一电源电路(如第1电源电路)的输出电压与第二电源电路(如第P1电源电路)的输出电压做冗余，给下电保持电路供电，同时将下电保持电路的输出电压与第一电源电路(如第1电源电路)的输出电压做冗余，给栅极电压电路供电，通过检测下电保持电路的输出电压与第1～n栅极电压电路的输出电压，做逻辑判断后，使能控制第二电源电路(如第P1电源电路)的输出电压，实现栅极电压电路输出的栅极电压早于第二电源电路(如第P1电源电路)输出的漏极电压上电。在上电过程中通过冗余电路(一实施例中，为冗余备份电路)产生栅极电压使能功放的漏极电压上电，漏极电压上电再次冗余产生栅极电压。检测控制电路在上电过程中对下电保持电路检测，在上电过程之初就保证下电过程的可靠性。在下电过程中充分利用功放的一个或多个漏极电压的能量冗余转换，为下电保持电路进行充分延时，保证了栅极电压晚于漏极电压下电。由于实现了下电能量的保持和下电延时，栅极电压晚于漏极电压下电，从而，解决了功放的供电时序的可靠性的问题，不论任意电源通道失效，或者任意一路先于或者后于其他电源通道上下电，或者在正常工作中出现异常情况，本申请均能可靠有效的保证GaN功放管的供电要求。
所述冗余是指：实现多路电压的“或”供电，即选择供电，多路电压之间互不影响，且保证只要其中一路电压正常，即可保证系统正常工作。
采用本申请实施例的功放供电装置，相比传统的实现方案，更加小型化和 可靠，可广泛应用于第四代移动通信系统(the 4th Generation mobile communication system，4G)、第五代移动通信系统(the 5th Generation mobile communication system，5G)无线通讯基站设备中，通用性高，具有广泛的应用价值。
一实施例中，冗余电路包括第一冗余电路(冗余电路1)和第二冗余电路(冗余电路2)。第一冗余电路(冗余电路1)的第一输入端连接第一电源电路(第1电源电路)的输出端。第一冗余电路(冗余电路1)的第二输入端连接第二电源电路(第P1电源电路)的输出端。第一冗余电路(冗余电路1)的输出端连接所述下电保持电路的输入端，设置为为下电保持电路提供输入电压。其中，第一电源电路(第1电源电路)为基站数字负载供电。第二电源电路(第P1电源电路)为功放的漏极供电。
一实施例中，冗余电路还包括第二冗余电路(冗余电路2)。第二冗余电路(冗余电路2)的第一输入端连接第一电源电路(第1电源电路)的输出端。第二冗余电路(冗余电路2)的第二输入端连接所述下电保持电路的输出端。第二冗余电路(冗余电路2)的输出端连接所述栅极电压电路(第1栅极电压电路)，设置为为栅极电压电路提供输入电压。
一实施例中，栅极电压电路，设置为产生功放的栅极电压，为功放的栅极供电。
一实施例中，检测控制电路的第一输入端连接所述下电保持电路的输出端；检测控制电路的第二输入端连接所述栅极电压电路的输出端；所述检测控制电路的输出端连接所述使能电路的输入端。
一实施例中，使能电路的输出端连接所述第二电源电路(第P1电源电路)的使能控制电路，设置为对所述第二电源电路(第P1电源电路)进行启动控制。
基于上述实施例，一实际应用中，功放供电装置可以包含第1电源电路、第P1电源电路、冗余电路1、下电保持电路、冗余电路2、栅极电压电路、检测控制电路、使能电路。第1电源电路为基站数字负载供电；第P1电源电路为GaN功放管的漏极供电。下电保持电路，用来为栅极电压电路输出的栅极电压提供下电能量的保持和下电延时，下电保持电路的输入端连接冗余电路1的输出端，下电保持电路的输出端连接冗余电路2的输入端。一实施例中，冗余电路2为栅极电压提供下电能量的保持和下电延时，冗余电路2的一输入端连接第1电源电路的输出端，冗余电路2的另一输入端连接下电保持电路的输出端，冗余电路2的输出端连接第1栅极电压电路的输入端。栅极电压电路产生GaN功放管的栅极电压，为第P1路GaN功放管的栅极供电。检测控制电路的一输入端连接下电保持电路的输出端；检测控制电路的另一输入端连接栅极电压电 路输出端；经过逻辑处理后，检测控制电路的输出信号控制使能电路。使能电路，设置为对第P1电源电路的启动进行控制，使能电路的输入端连接检测控制电路的输出端，使能电路的输出端连接第P1电源电路的使能控制电路。
一实施例中，第一电源电路(第1电源电路)为一路电源或多路电源。比如，第1电源电路为数字部分负载供电，可以不局限为一路电源，可以为第1～m电源。
一实施例中，第二电源电路(第P1电源电路)为一路电源或多路电源。比如，第P1电源电路为功放供电，也不局限为一路电源，可以为第P1～Pn电源。
一实施例中，第一电源电路(第1电源电路)与所述第二电源电路(第P1电源电路)的输入源相同；或者，第一电源电路(第1电源电路)与所述第二电源电路(第P1电源电路)的输入源不相同。比如，第1～m电源及第P1～Pn电源的输入源可以相同，也可以不同输入源。
一实施例中，第一冗余电路(冗余电路1)连接的第一电源电路(第1电源电路)及所述第二电源电路(第P1电源电路)为一路或多路电源的任意组合。比如，冗余电路1连接的第一电源电路可以为1～m电源中的一种、几种或者全部，以及第P1～Pn电源中的一种、几种或者全部；冗余电路1的实现可以为电子开关、二极管、继电器或者开关电路等实现。
一实施例中，第二冗余电路(冗余电路2)连接的第一电源电路(第1电源电路)为一路或多路电源的任意组合。比如，冗余电路2连接的第一电源电路可以为1～m电源中的一种、几种或者全部，冗余电路2将第一电源电路的输出电压与下电保持电路的输出电压做冗余，给栅极电压电路提供能量。
一实施例中，下电保持电路的实现形式包括：宽输入范围的升压电路、宽输入范围的降压电路、其他转换储能电路或者储能元件。
一实施例中，栅极电压电路的实现形式包括：多路功放管中的一路或者多路。比如，第1～n路功放管中的任意一路或者多路提供栅极电压，栅极电压电路的实现形式可以根据栅极电压负载功率灵活配置。
在本实施例中还提供了一种功放供电方法，该方法基于上述功放供电装置来实现，本申请中已经进行过说明的不再赘述。
本申请实施例中，一种功放供电方法，如图3所示，包括：
步骤410、在对第一电源电路的输出电压与第二电源电路的输出电压做冗余后，产生第一冗余备份电压为下电保持电路提供输入电压。
在对第1电源电路的输出电压与第P1电源电路的输出电压做冗余后，产生 第一冗余备份电压为下电保持电路提供输入电压。
步骤420、在对第一电源电路的输出电压与下电保持电路的输出电压做冗余后，产生第二冗余备份电压为栅极电压电路提供输入电压。
在对第1电源电路的输出电压与下电保持电路的输出电压做冗余后，产生第二冗余备份电压为栅极电压电路提供输入电压。
步骤430、在上电过程中对下电保持电路做检测。
步骤440、在正常工作和下电过程中对下电保持电路的电压与栅极电压电路的电压做检测，在检测结果满足判断条件的情况下，通过使能控制实现栅极电压早于漏极电压上电和栅极电压晚于漏极电压下电。
本实施例中，栅极电压由栅极电压电路输出，漏极电压由第二电源电路输出。
在正常工作和下电过程中对所述下电保持电路的输出电压与所述栅极电压电路的输出电压做检测，可以是实时检测。
本申请实施例中，一种功放供电方法，第一冗余备份电压存储于第一冗余电路(冗余电路1)中，第二冗余备份电压存储于第二冗余电路(冗余电路2)中，如图4所示，方法包括：
步骤510、在对第一电源电路的输出电压与第二电源电路的输出电压做冗余后，产生第一冗余备份电压，通过第一冗余电路(冗余电路1)为下电保持电路提供输入电压。
在对第1电源电路的输出电压与第P1电源电路的输出电压做冗余后，产生第一冗余备份电压为下电保持电路提供输入电压。
步骤520、在对第一电源电路的输出电压与下电保持电路的输出电压做冗余后，产生第二冗余备份电压，通过第二冗余电路(冗余电路2)为栅极电压电路提供输入电压。
在对第1电源电路的输出电压与下电保持电路的输出电压做冗余后，产生第二冗余备份电压为栅极电压电路提供输入电压。
步骤530、在上电过程中对下电保持电路做检测。
在检测出下电保持电路的输出电压和栅极电压电路的输出电压中的任意一路出现异常的情况下，输出异常信号。
在检测出下电保持电路的输出电压和栅极电压电路的输出电压中的任意一路出现异常的情况下，则下电并对所述异常进行检测。
在检测出下电保持电路的输出电压和栅极电压电路的输出电压中的每一路均正常的情况下，则使能电路有效，使能第二电源电路(第P1电源电路)上电。
步骤540、使能功放的漏极电压上电。
本申请实施例中，一种功放供电方法，第一冗余备份电压存储于第一冗余电路(冗余电路1)中，第二冗余备份电压存储于第二冗余电路(冗余电路2)中，如图5所示，方法包括：
步骤610、在对第一电源电路的输出电压与第二电源电路的输出电压做冗余后，产生第一冗余备份电压，通过第一冗余电路(冗余电路1)为下电保持电路继续供电。
在对第1电源电路的输出电压与第P1电源电路的输出电压做冗余后，产生第一冗余备份电压为下电保持电路继续供电。
步骤620、在对第一电源电路的输出电压与下电保持电路的输出电压做冗余后，产生第二冗余备份电压，通过第二冗余电路(冗余电路2)为栅极电压电路上电，为功放的栅极继续供电。
在对第1电源电路的输出电压与下电保持电路的输出电压做冗余后，产生第二冗余备份电压为栅极电压电路继续供电。
步骤630、在下电过程中对下电保持电路的电压与栅极电压电路的电压做检测。
判断检测栅极电压是否高于功放的安全电压，响应于检测出栅极电压高于功放的安全电压的判断结果，则后续将栅极电压电路下电。
步骤640、响应于检测出栅极电压高于功放的安全电压的判断结果，通过第二冗余电路(冗余电路2)继续保持指定时间，响应于栅极电压电路的输出电压低于栅极电压电路的欠压点的判断结果，将所述栅极电压电路下电。
一实际应用中，第1电源电路上电，给基站数字负载供电，将第1电源电路的输出电压与第P1电源电路的输出电压做冗余，给下电保持电路供电，同时将下电保持电路的输出电压与第1电源电路的输出电压做冗余，给栅极电压电路供电，通过检测下电保持电路的输出电压与第1～n栅极电压电路的输出电压，做逻辑判断后，使能控制第P1电源电路的输出电压，实现栅极电压电路输出的栅极电压早于第P1电源电路输出的漏极电压上电。即：充分利用第P1电源电路的漏极电压电源电路储存的能量，将此能量做冗余后产生第一冗余备份电压提供给下电保持电路，进而提供稳定的下电保持电路，并将第1电源电路与下电保持电路再次冗余产生第一冗余备份电压提供给栅极电压电路，进而提供可靠的栅极电压电路，保证任何条件下的下电延时的可靠性。
采用本申请的实施例，使得上电过程不受第1电源电路的输入电压和第P1电源电路的输入电压影响，对第1电源电路和第P1电源电路无强制的上电先后顺序，通过冗余电路及检测控制电路，保证了栅极电压电路的输出电压无问题后使能第P1电源电路，可靠的实现GaN功放管的正常上电要求；同时上电过程中对下电保持电路做检测，如发现异常，均无法开启第P1电源电路的输出，上电即对下电保持电路检验，保证了上电和下电时序更加可靠。当第P1～Pn电源电路的输入源下电时第P1～Pn电源电路下电，可以通过下电保持电路保证GaN功放管的漏极电压下降到SOA曲线安全的电压范围内，再通过更低输入的1～n栅极电压电路充分延时，保证栅极电压最后下电。在第P1～Pn电源电路的其中任意一路异常的情况下，由于冗余电路、下电保持电路和栅极电压电路不会掉电，保证了供电可靠性；第P1～Pn电源电路供电互不影响，可适用于多通道基站功放，保证了供电可靠性。
本申请实施例提供的一种功放供电装置，可以通过软件实现，可以将软件(如计算机程序)存储于存储器中，存储器可以是易失性存储器或非易失性存储器，也可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read Only Memory，ROM)、可编程只读存储器(Programmable Read-Only Memory，PROM)、可擦除可编程只读存储器(Erasable Programmable Read-Only Memory，EPROM)、电可擦除可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)、磁性随机存取存储器(Ferromagnetic Random Access Memory，FRAM)、快闪存储器(Flash Memory)、磁表面存储器、光盘、或只读光盘(Compact Disc Read-Only Memory，CD-ROM)；磁表面存储器可以是磁盘存储器或磁带存储器。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，易失性存储器用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static Random Access Memory，SRAM)、同步静态随机存取存储器(Synchronous Static Random Access Memory，SSRAM)、动态随机存取存储器(Dynamic Random Access Memory，DRAM)、同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate Synchronous Dynamic Random Access Memory，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced Synchronous Dynamic Random Access Memory，ESDRAM)、同步连接动态随机存取存储器(SyncLink Dynamic Random Access Memory，SLDRAM)、直接内存总线随机存取存储器(Direct Rambus Random Access Memory，DRRAM)。本申请实施例描述的存储器旨在包括但不限于本申请中已经描述的存储器和任意其它适合类型的存储器。
本申请实施例中，还提供了一种计算机可读存储介质，设置为存储上述实施例中提供的计算程序，以完成前述方法所述步骤。计算机可读存储介质可以是FRAM、ROM、PROM、EPROM、EEPROM、Flash Memory、磁表面存储器、光盘、或CD-ROM等存储器；也可以是包括上述存储器之一或任意组合的一种或多种设备。
下面结合附图对本申请可选实施例进行说明。
本申请实施例中的使能电路可以为第x电源的产生电路，也可以为Px电源前后的任何电子开关电路，不限于如下实施例中使能电路的描述。
可选实施例一：
图6为本申请实施例提供的一种功放供电装置的结构示意图，该示意图中只有一路功放及只有一路数字供电电源。第1电源电路给基站数字负载供电，第P1电源电路给功放管供电；第1电源电路的输出电压与P1电源电路的输出电压通过冗余电路1给下电保持电路供电，下电保持电路的输出电压与第1电源电路的输出电压通过冗余电路2给栅极电压电路供电，通过检测下电保持电路的电压与第1～n栅极电压电路的电压，经过逻辑判断，在满足判断条件后，使能控制第P1电源电路的输出电压给功放管供电。
可选实施例二：
图7为本申请实施例提供的另一种功放供电装置的结构示意图，该示意图中冗余电路1的输入电压可以选择，可以为第1电源电路的输入电压或者第1电源电路的输出电压，其余与图6相同。一实施例中，第1电源电路给基站数字负载供电，第P1电源电路给功放管供电；第1电源电路的输入电压与第P1电源电路的输出电压通过冗余电路1给下电保持电路供电，或者，第1电源电路的输出电压与第P1电源电路的输出电压通过冗余电路1给下电保持电路供电。下电保持电路的输出电压与第1电源电路的输出电压通过冗余电路2给栅极电压电路供电，通过检测下电保持电路的电压与第1～n栅极电压电路的电压，经过逻辑判断，在满足判断条件后，使能控制第P1电源电路的输出电压给功放管供电。
可选实施例三：
图8为本申请实施例提供的另一种功放供电装置的结构示意图，如图8所示，使能电路可以使能第P1电源电路前的电子开关，除此之外皆与图6所述的内容一致。一实施例中，第1电源电路给基站数字负载供电，第P1电源电路给功放管供电；第1电源电路的输出电压与第P1电源电路的输出电压通过冗余电路1给下电保持电路供电，下电保持电路的输出电压与第1电源电路的输出电 压通过冗余电路2给栅极电压电路供电，通过检测下电保持电路的输出电压与第1～n栅极电压电路的输出电压，经过逻辑判断，在满足判断条件后，使能控制第P1电源电路的输出电压给功放管供电。使能电路通过电子开关与第P1电源电路相连，第P1电源电路的输入端与电子开关的输出端相连，使能电路可以使能第P1电源电路前的电子开关。
可选实施例四：
图9为本申请实施例提供的另一种功放供电装置的结构示意图，如图9所示，使能电路可以使能第P1电源电路后的电子开关，除此之外皆与图6所述的内容一致。一实施例中，第1电源电路给基站数字负载供电，第P1电源电路给功放管供电；第1电源电路的输出电压与第P1电源电路的输出电压通过冗余电路1给下电保持电路供电，下电保持电路的输出电压与第1电源电路的输出电压通过冗余电路2给栅极电压电路供电，通过检测下电保持电路的电压与第1～n栅极电压电路的电压，经过逻辑判断，在满足判断条件后，使能控制第P1电源电路的输出电压给功放管供电。使能电路通过电子开关与第P1电源电路相连，第P1电源电路的输出端与电子开关的输入端相连，使能电路可以使能第P1电源电路后的电子开关。
可选实施例五：
图10为本申请实施例提供的另一种功放供电装置额结构示意图，如图10所示，该示意图中冗余电路1的输入为第1,2,……m电源电路的输出电压与第P1电源电路的输出电压；冗余电路2的输入为第1,2,……m电源电路的输出电压与下电保持电路的输出电压，冗余电路2的输出产生第1,2,……n栅极电压电路的输入电压，除此之外皆与图7所述的内容一致。一实施例中，第1,2,……m电源电路给基站数字负载供电，第P1电源电路给功放供电；第1,2,……m电源电路的输出电压与第P1电源电路的输出电压通过冗余电路1给下电保持电路供电，下电保持电路的输出与电压第1,2,……m电源电路的输出电压通过冗余电路2给栅极电压电路供电，冗余电路2的输出产生第1,2,……n栅极电压电路的输入电压，通过检测下电保持电路的电压与第1～n栅极电压电路的电压，经过逻辑判断，在满足判断条件后，使能控制第P1电源电路的输出电压给功放管供电。
可选实施例六：
图11为本申请实施例提供的另一种功放供电装置的结构示意图，如图11所示，该示意图冗余电路1的输入为第1,2,……m电源电路的输出电压与第P1，P2，……Pn电源电路的输出电压；冗余电路2的输入为第1,2,……m电源电路的输出电压与下电保持电路的输出电压，冗余电路2的输出产生第1,2,……n栅极电压电路的输入电压，除此之外其余皆与图7所述的内容一致。一实施例中， 第1,2,……m电源电路给基站数字负载供电，第P1～Pn电源电路给功放供电；第1,2,……m电源电路的输出电压与第P1～Pn电源电路的输出电压通过冗余电路1给下电保持电路供电，下电保持电路的输出电压与第1,2,……m电源电路的输出电压通过冗余电路2给栅极电压电路供电，冗余电路2的输出产生第1,2,……n栅极电压电路的输入电压，通过检测下电保持电路的电压与第1～n栅极电压电路的电压，经过逻辑判断，在满足判断条件后，使能控制第P1电源电路的输出电压给功放管供电。
可选实施例七：
图12为本申请实施例提供的另一种功放供电装置的结构示意图，如图12所示，冗余电路2的输出经第n栅极电压电路产生一路栅极电压，除此之外其余皆与图11所述的内容一致。一实施例中，第1,2,……m电源电路给基站数字负载供电，第P1～Pn电源电路给功放供电；第1,2,……m电源电路的输出电压与第P1～Pn电源电路输出电压通过冗余电路1给下电保持电路供电，下电保持电路的输出电压与第1,2,……m电源电路的输出通过冗余电路2给栅极电压电路供电，冗余电路2的输出产生第n栅极电压电路的输入电压，通过检测下电保持电路的电压与第n栅极电压电路的电压，经过逻辑判断，在满足判断条件后，使能控制第P1电源电路的输出电压给功放管供电。
可选实施例八：
图13是本申请实施例提供的一种功放供电装置的上电控制流程图，包括：
步骤1010、输入源上电；第1电源电路上电。
步骤1020、通过冗余电路1给下电保持电路上电。
步骤1030、通过冗余电路2给栅极电压电路上电。
步骤1040、检测控制电路检测下电保持电路的输出电压和栅极电压电路的输出电压是否正常；响应于下电保持电路的输出电压和栅极电压电路的输出电压中有任意一路异常的判断结果，执行步骤1070；响应于下电保持电路的输出电压和栅极电压电路的输出电压均正常的判断结果，执行步骤1050。
步骤1050、使能电路有效，使能第P1电源电路上电。
步骤1060、功放的漏极上电。
步骤1070、下电维修检查，返回执行步骤1010。
可选实施例九：
图14是本申请实施例提供的一种功放供电装置的下电控制流程图，包括：
步骤2010、输入源下电。
步骤2020、通过冗余电路1给下电保持电路继续供电。
步骤2030、通过冗余电路2给栅极电压电路继续供电，给功放的栅极继续供电。
步骤2040、下电保持，检测控制电路检测栅极电压是否低于SOA安全电压，响应于栅极电压高于功放SOA安全电压的判断结果，继续步骤2030；响应于栅极电压低于功放SOA安全电压的判断结果；进行步骤2050。
步骤2050、下电保持电路下电。
步骤2060、通过冗余电路2继续保持一段时间后，栅极电压电路的输出电压低于栅极电压电路的欠压点后，栅极电压电路下电。
步骤2070、功放的栅极电压下电。
可选实施例十：
图15是本申请实施例提供的一种功放供电装置正常工作时第Pn电源电路输出异常的控制流程图，即在任一一路功放异常的情况下不影响其他路功放供电，相互解耦，供电可靠。
步骤3010、正常工作时，第Pn电源电路的输出电压异常，判断是否对电路进行维修，响应于维修的判断结果，进行步骤3040；响应于不维修的判断结果，进行步骤3020。
步骤3020、通过冗余电路1给下电保持电路供电，保持下电保持电路正常工作。
步骤3030、通过冗余电路2给栅极电压电路供电，保持栅极电压电路正常工作。
步骤3040、下电维修第Pn电源电路。
本功放供电装置上电不受第1～m电源电路、第P1～Pn电源电路的输入电压影响，通过冗余电路及检测控制电路，保证了栅极电压电路无问题后使能第P1～Pn电源电路，可靠的实现GaN功放管的正常上电要求；同时上电过程中对下电保持电路做检测，如发现异常，均无法开启P1电源输出，上电即对下电保持电路检验，保证了上电和下电时序更加可靠。
上电环节中第1～n栅极电压电路中任意一路异常，均不影响栅极电压建立；上电环节中第P1～Pn电源电路中任意一路异常也不影响其他正常的功放的漏极电压建立；并发现异常，可随时下电维修，上电检测保证了下电时序的可靠性。
下电时序可靠，冗余电路1、冗余电路2及下电保持电路保证了不依赖任意一路功放漏极电压电路的异常与正常，时序相互解耦。
正常工作中，如输入异常，如雷击浪涌或者电池老化导致输入电压快速跌落或者跳变；或者第Pn电源电路或者第n电源电路异常损坏导致某一路或者多路栅极电压跌落，本申请的冗余电路1、冗余电路2及掉电保持保证了不依赖任意一路电源的异常与正常，GaN功放管的时序相互解耦，不会导致其他一路或多路路瘫痪必须维修，稳定可靠。
在一实施例中，栅极电压电路的输出欠压点可以为GaN栅极电压SOA曲线的安全电压或者比安全电压更低的电压值。
可选实施例十一：
图16是本申请实施例提供的一种一路功放供电装置的电路图；第1电源经过DC-DC变换输出5.6V给数字供电，第P1电源经过DC-DC变换输出50V给功放的漏极供电；第1电源与第P1电源经过二极管合路给下电保持电路供电，下电保持电路与第1电源经过合路后经过DC-DC产生栅极电压-8V；当下电保持电路的输出电压大于V2时，表示下电保持电路正常；同时-8V电压达到比较电路的基准点，比较电路导通；光耦D1次级使能隔离模块，第P1电源上电。
下电时，下电保持电路维持能量使得栅极电压掉到功放管SOA安全电压V1以上，仍能维持栅极电压-8V产生，当漏极电压掉到V1以下，仍通过第1电源冗余再延时供给-8V，直至栅极电压产生的DC-DC变换欠压，栅极电压掉电，保证了下电充分延时可靠性。
可选实施例十二：
图17是本申请实施例提供的一种多路功放供电装置的电路图；第1电源经过DC-DC变换输出5.6V给数字供电，第2电源经过DC-DC变换输出5.6V给基站数字负载供电；第m电源经过DC-DC变换输出5.6V或者其他电压给基站数字负载供电；第P1电源经过DC-DC变换输出50V给功放的漏极供电；第P2电源经过DC-DC变换输出50V给功放的漏极供电；第Pn电源经过DC-DC变换输出50V给功放的漏极供电；第1电源，第2电源，……第m电源与第P1电源，第P2电源，……第Pn电源经过二极管合路给下电保持电路供电，下电保持电路与第1电源，第2电源，……第m电源经过合路后经过DC-DC产生栅极电压-8V1；-8V2，……-8Vn,当下电保持电路的输出电压大于V2时，表示下电保持电路正常；同时-8V电压达到比较电路的基准点，比较电路导通；光耦D1次级使能隔离模块，第P1,P2……Pn电源上电；下电时，下电保持电路维持能量使得栅极电压掉到功放管SOA安全电压V1以上，仍能维持栅极电压-8V产生，当第P1电源，第P2电源，……第Pn电源的所有漏极电压均掉到V1以下，仍通过第1～m电源冗余再延时供给-8V，直至DC-DC欠压，栅极电压掉电，保证了下电充分延时可靠性。其中，V1为功放管的安全工作电压或者比安全电 压更低的电压值，V2为比V1更低的保持电压，可以为栅极电压的欠压点或者比该欠压点低的电压。
可选实施例十一和可选实施例十二仅是上述任意实施例的一种实现形式，本申请不局限于此实现。
在一实施例中，对于非GaN功放管，只要有本申请中供电时序要求的器件，如砷化镓(GaAS)等，本申请同样适用。

Claims (18)

  1. 一种功放供电装置，包括：第一电源电路、第二电源电路、栅极电压电路、使能电路、冗余电路、下电保持电路和检测控制电路；其中，
    所述冗余电路，与所述第一电源电路、所述第二电源电路、所述下电保持电路和所述栅极电压电路连接，设置为在对所述第一电源电路的输出电压与所述第二电源电路的输出电压做冗余后，为所述下电保持电路提供输入电压；在对所述第一电源电路的输出电压与所述下电保持电路的输出电压做冗余后，为所述栅极电压电路提供输入电压；
    所述下电保持电路，与所述栅极电压电路连接，设置为对所述栅极电压电路输出的栅极电压提供下电能量的保持和下电延时；
    所述检测控制电路，与所述下电保持电路、所述栅极电压电路和所述使能电路连接，设置为在上电过程中对所述下电保持电路做检测，及在正常工作和下电过程中对所述下电保持电路的电压与所述栅极电压电路的电压做检测，在检测结果满足判断条件的情况下，通过所述使能电路的使能控制，实现所述栅极电压早于所述第二电源电路输出的漏极电压上电和所述栅极电压晚于所述第二电源电路输出的漏极电压下电。
  2. 根据权利要求1所述的装置，其中，所述冗余电路包括第一冗余电路；
    所述第一冗余电路的第一输入端连接所述第一电源电路的输出端；
    所述第一冗余电路的第二输入端连接所述第二电源电路的输出端；
    所述第一冗余电路的输出端连接所述下电保持电路的输入端，设置为为所述下电保持电路提供输入电压；
    所述第一电源电路为基站数字负载供电；
    所述第二电源电路为功放的漏极供电。
  3. 根据权利要求2所述的装置，其中，所述冗余电路还包括第二冗余电路；
    所述第二冗余电路的第一输入端连接所述第一电源电路的输出端；
    所述第二冗余电路的第二输入端连接所述下电保持电路的输出端；
    所述第二冗余电路的输出端连接所述栅极电压电路，设置为为所述栅极电压电路提供输入电压。
  4. 根据权利要求1至3任一项所述的装置，其中，所述栅极电压电路，设置为产生功放的栅极电压，为所述功放的栅极供电。
  5. 根据权利要求1至4任一项所述的装置，其中，所述检测控制电路的第一检测输入端连接所述下电保持电路的输出端；
    所述检测控制电路的第二检测输入端连接所述栅极电压电路的输出端；
    所述检测控制电路的输出端连接所述使能电路的输入端。
  6. 根据权利要求1至5任一项所述的装置，其中，所述使能电路的输出端设置为连接所述第二电源电路的使能控制电路，对所述第二电源电路进行启动控制。
  7. 根据权利要求1至6任一项所述的装置，其中，所述第一电源电路为一路电源或多路电源。
  8. 根据权利要求1至6任一项所述的装置，其中，所述第二电源电路为一路电源或多路电源。
  9. 根据权利要求1至8任一项所述的装置，其中，所述第一电源电路与所述第二电源电路的输入源相同；或者，
    所述第一电源电路与所述第二电源电路的输入源不相同。
  10. 根据权利要求2或3所述的装置，其中，所述第一电源电路及所述第二电源电路均为一路或多路电源。
  11. 根据权利要求1至10任一项所述的装置，其中，所述下电保持电路的实现形式包括：宽输入范围的升压电路、宽输入范围的降压电路、其他转换储能电路或者储能元件。
  12. 根据权利要求1至11任一项所述的装置，其中，所述栅极电压电路设置为与多路功放管中的至少一路功放管连接，为所述至少一路功放管提供栅极电压。
  13. 一种功放供电方法，包括：
    冗余电路在对第一电源电路的输出电压与第二电源电路的输出电压做冗余后，产生第一冗余备份电压为下电保持电路提供输入电压；
    所述冗余电路在对所述第一电源电路的输出电压与所述下电保持电路的输出电压做冗余后，产生第二冗余备份电压为栅极电压电路提供输入电压；
    检测控制电路在上电过程中对所述下电保持电路做检测；在正常工作和下电过程中对所述下电保持电路的电压与所述栅极电压电路的电压做检测，在检测结果满足判断条件的情况下，通过使能电路的使能控制实现所述栅极电压电路输出的栅极电压早于所述第二电源电路输出的漏极电压上电和所述栅极电压电路输出的栅极电压晚于所述第二电源电路输出的漏极电压下电。
  14. 根据权利要求13所述的方法，其中，所述第一冗余备份电压存储于第一冗余电路中，所述第二冗余备份电压存储于第二冗余电路中；
    所述冗余电路在对第一电源电路的输出电压与第二电源电路的输出电压做冗余后，产生第一冗余备份电压为下电保持电路提供输入电压，包括：
    所述第一冗余电路对第一电源电路的输出电压与第二电源电路的输出电压做冗余后，产生所述第一冗余备份电压，将所述第一冗余电压提供给所述下电保持电路，使所述下电保持电路上电；
    所述冗余电路在对所述第一电源电路的输出电压与所述下电保持电路的输出电压做冗余后，产生第二冗余备份电压为栅极电压电路提供输入电压，包括：
    所述第二冗余电路对所述第一电源电路的输出电压与所述下电保持电路的输出电压做冗余后，产生第二冗余备份电压，将所述第二冗余电压提供给所述删除电压电路，使所述栅极电压电路上电。
  15. 根据权利要求13或14所述的方法，其中，所述在上电过程中对所述下电保持电路做检测，包括：
    所述检测控制电路在检测出所述下电保持电路的输出电压和所述栅极电压电路的输出电压中的任意一路出现异常的情况下，输出异常信号；
    所述检测控制电路在检测出所述下电保持电路的输出电压和所述栅极电压电路的输出电压中的每一路正常的情况下，则控制使能电路有效。
  16. 根据权利要求15所述的方法，其中，所述控制使能电路有效，包括：
    所述检测控制电路控制所述使能电路使能所述第二电源电路上电；
    所述检测控制电路控制所述使能电路使能功放的漏极电压上电。
  17. 根据权利要求14-16任一项所述的方法，还包括：
    所述第一冗余电路给所述下电保持电路继续供电；
    所述第二冗余电路给所述栅极电压电路继续供电，为功放的栅极继续供电。
  18. 根据权利要求17所述的方法，其中，所述在下电过程中对所述下电保持电路的输出电压与所述栅极电压电路的输出电压做检测，包括：
    所述检测控制电路在检测出栅极电压高于功放的安全电压的情况下，通过所述第一冗余电路继续供电，所述检测控制电路在所述栅极电压电路的输出电压低于所述栅极电压电路的欠压点的情况下，将所述栅极电压电路下电。
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