WO2020010892A1 - Drive unit and drive method therefor, gate drive circuit and display substrate - Google Patents

Drive unit and drive method therefor, gate drive circuit and display substrate Download PDF

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Publication number
WO2020010892A1
WO2020010892A1 PCT/CN2019/083448 CN2019083448W WO2020010892A1 WO 2020010892 A1 WO2020010892 A1 WO 2020010892A1 CN 2019083448 W CN2019083448 W CN 2019083448W WO 2020010892 A1 WO2020010892 A1 WO 2020010892A1
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Prior art keywords
transistor
node
pull
control
circuit
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PCT/CN2019/083448
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French (fr)
Chinese (zh)
Inventor
袁志东
袁粲
徐海侠
李蒙
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/613,643 priority Critical patent/US11257418B2/en
Publication of WO2020010892A1 publication Critical patent/WO2020010892A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a driving unit and a driving method thereof, a gate driving circuit, and a display substrate.
  • each driving transistor or OLED for example, a difference caused by a process or a difference caused by aging
  • the display brightness of the panel is uneven. Therefore, it is usually necessary to compensate the performance of the driving transistor or the OLED.
  • the present disclosure provides a driving unit including a shift register and a first output circuit.
  • the shift register includes a pull-up node, a pull-down node, and a driving signal output terminal.
  • the first output circuit is configured to Under the control of the voltage of the pull-up node, the voltage of the pull-down node, and the voltage provided by the driving signal output terminal, a double-pulse signal is output within a preset time period.
  • the first output circuit includes: a first control sub-circuit, a second control sub-circuit, and an output sub-circuit; the first control sub-circuit and the output sub-circuit are connected to a first node, The first control sub-circuit, the second control sub-circuit, and the output sub-circuit are connected to a second node;
  • the first control sub-circuit is connected to the pull-up node and the pull-down node, and is configured to be controlled by a voltage of the pull-up node, a voltage of the pull-down node, and a voltage of the second node, Controlling the voltage at the first node to be at an effective level within the preset time period, wherein the preset time period includes a first sub-time period, a second sub-time period, and a third time period which are continuously set; Sub-period
  • the second control sub-circuit is connected to the pull-down node and the drive signal output terminal, and is configured to control the second pull-down node under the control of the voltage of the pull-down node and the voltage provided by the drive signal output terminal.
  • the voltage at the node is at an inactive level during the first sub-period and the third sub-period, and at an active level during the second sub-period;
  • the output sub-circuit is connected to a first signal output terminal, and is configured to pass through the first signal output terminal when the voltage of the first node is at an active level and the voltage of the second node is at an inactive level.
  • a voltage at an active level is output, and when the voltage at the second node is at an active level, a voltage at an inactive level is output through the first signal output terminal.
  • the first control sub-circuit includes: a first transistor, a second transistor, and a third transistor;
  • a control pole of the first transistor is connected to the pull-up node, a first pole of the first transistor is connected to a first control signal input terminal, and a second pole of the first transistor is connected to the first node ;
  • a control pole of the second transistor is connected to the pull-down node, a first pole of the second transistor is connected to the first node, and a second pole of the second transistor is connected to a first working power terminal, where The first working power terminal is configured to provide a first working voltage at an inactive level;
  • a control electrode of the third transistor is connected to the second node, a first electrode of the third transistor is connected to the first node, and a second electrode of the third transistor is connected to the first working power terminal. connection.
  • the second control sub-circuit includes: a fourth transistor and a fifth transistor;
  • a control electrode of the fourth transistor is connected to the pull-down node, a first electrode of the fourth transistor is connected to a second working power terminal, and a second electrode of the fourth transistor is connected to the second node, wherein The second working power terminal is configured to provide a second working voltage at an effective level;
  • a control electrode of the fifth transistor is connected to the driving signal output terminal, a first electrode of the fifth transistor is connected to the second node, and a second electrode of the fifth transistor is connected to a second control signal input terminal. connection.
  • the output sub-circuit includes: a sixth transistor, a seventh transistor, an eighth crystal, and a first capacitor,
  • a control electrode of the sixth transistor is connected to the first control signal input terminal, a first electrode of the sixth transistor is connected to the second working power terminal, and a second electrode of the sixth transistor is connected to the first electrode.
  • the control electrode of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is connected to the second working power terminal, and the second electrode of the seventh transistor is connected to the first signal.
  • a control electrode of the eighth transistor is connected to the second node, a first electrode of the eighth transistor is connected to the first signal output terminal, and a second electrode of the eighth transistor is connected to the first operation. Power-side connection;
  • a first terminal of the first capacitor is connected to the first node, and a second terminal of the first capacitor is connected to the first signal output terminal.
  • the output sub-circuit includes: a sixth transistor, a seventh transistor, an eighth crystal, and a first capacitor;
  • a control electrode and a first electrode of the sixth transistor are respectively connected to a third control signal input terminal, and a second electrode of the sixth transistor is connected to the first node;
  • a control pole of the seventh transistor is connected to the first node, a first pole of the seventh transistor is connected to the third control signal input terminal, and a second pole of the seventh transistor is connected to the first node.
  • a control electrode of the eighth transistor is connected to the second node, a first electrode of the eighth transistor is connected to the first signal output terminal, and a second electrode of the eighth transistor is connected to the first operation. Power-side connection;
  • a first terminal of the first capacitor is connected to the first node, and a second terminal of the first capacitor is connected to the first signal output terminal.
  • the driving unit further includes: a second output circuit
  • the second output circuit is respectively connected to the pull-up node, the pull-down node, and the first signal output terminal, and is configured to be controlled by the voltage of the pull-up node and the voltage of the pull-down node, During the preset time period, a voltage at an effective level is output through the second signal output terminal.
  • the second output circuit includes: a ninth transistor and a tenth transistor;
  • a control pole of the ninth transistor is connected to the pull-up node, a first pole of the ninth transistor is connected to the first control signal input terminal, and a second pole of the ninth transistor is connected to the second The signal output is connected;
  • a control pole of the tenth transistor is connected to the pull-down node, a first pole of the tenth transistor is connected to the second signal output terminal, and a second pole of the tenth transistor is connected to the first working power source. ⁇ ⁇ End connection.
  • the driving unit further includes a second output circuit
  • the second output circuit includes: a ninth transistor and a tenth transistor;
  • a control pole of the ninth transistor is connected to the pull-up node, a first pole of the ninth transistor is connected to the first control signal input terminal, and a second pole of the ninth transistor is connected to the second The signal output is connected;
  • a control pole of the tenth transistor is connected to the pull-down node, a first pole of the tenth transistor is connected to the second signal output terminal, and a second pole of the tenth transistor is connected to the first working power source. ⁇ ⁇ End connection.
  • the pull-up node is configured to provide a voltage at an effective level within the preset period of time
  • the driving signal output terminal is configured to provide a voltage at an effective level within the preset period of time.
  • a flat voltage, the pull-down node is configured to provide a voltage at an inactive level within the preset time period.
  • the first control signal input terminal is configured to provide a first clock signal
  • the second control signal terminal is configured to provide a second clock signal
  • the first clock signal is at the preset time.
  • the second clock signal is at an active level during the first and third sub-periods, and is at an active level during the second sub-period. .
  • the shift register includes a precharge reset circuit, a pull-up circuit, a pull-down circuit, and a pull-down control circuit;
  • the precharge reset circuit is respectively connected to a precharge signal input terminal and a reset signal input terminal and is connected to the pull-up circuit to the pull-up node, and the pull-down circuit and the pull-down control circuit are connected to the pull-down node.
  • the pull-up circuit and the pull-down circuit are connected to the driving signal output terminal.
  • the precharge reset circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
  • the pull-down control circuit includes a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;
  • the pull-up circuit includes a seventeenth transistor and a second capacitor;
  • the pull-down circuit includes an eighteenth transistor;
  • the control pole of the eleventh transistor is connected to a fourth control signal input terminal, the first pole of the eleventh transistor is connected to the precharge signal input terminal, and the second pole of the eleventh transistor is connected to all Said pull-up node connection;
  • a control electrode of the twelfth transistor is connected to the fourth control signal input terminal, a first electrode of the twelfth transistor is connected to the pull-up node, and a second electrode of the twelfth transistor is connected to all The first pole connection of the thirteenth transistor;
  • a control electrode of the thirteenth transistor is connected to a reset signal input terminal, and a second electrode of the thirteenth transistor is connected to the first working power terminal;
  • a control electrode and a first electrode of the fourteenth transistor are respectively connected to the second working power terminal, and a second electrode of the fourteenth transistor is connected to the pull-down node;
  • a control pole of the fifteenth transistor is connected to the pull-down node, a first pole of the fifteenth transistor is connected to the pull-up node, and a second pole of the fifteenth transistor is connected to the first operation. Power end connection;
  • the control pole of the sixteenth transistor is connected to the pull-up node, the first pole of the sixteenth transistor is connected to the pull-down node, and the second pole of the sixteenth transistor is connected to the first operation. Power end connection;
  • a control pole of the seventeenth transistor is connected to the pull-up node, a first pole of the seventeenth transistor is connected to a fifth control signal input terminal, and a second pole of the seventeenth transistor is connected to the drive Signal output terminal connection;
  • a first terminal of the second capacitor is connected to the pull-up node, and a second terminal of the second capacitor is connected to the driving signal output terminal;
  • the control electrode of the eighteenth transistor is connected to the pull-down node, the first electrode of the eighteenth transistor is connected to the driving signal output terminal, and the second electrode of the eighteenth transistor is connected to the first The working power terminal is connected.
  • the precharge reset circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
  • the pull-down control circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and A nineteenth transistor;
  • the pull-up circuit includes a seventeenth transistor and a second capacitor;
  • the pull-down circuit includes an eighteenth transistor;
  • the control pole of the eleventh transistor is connected to a fourth control signal input terminal, the first pole of the eleventh transistor is connected to the precharge signal input terminal, and the second pole of the eleventh transistor is connected to all Said pull-up node connection;
  • a control electrode of the twelfth transistor is connected to the fourth control signal input terminal, a first electrode of the twelfth transistor is connected to the pull-up node, and a second electrode of the twelfth transistor is connected to all The first pole connection of the thirteenth transistor;
  • a control electrode of the thirteenth transistor is connected to the reset signal input terminal, and a second electrode of the thirteenth transistor is connected to the first working power terminal;
  • a control pole of the fourteenth transistor is connected to the fourth control signal input terminal, a first pole of the fourteenth transistor is connected to the second working power terminal, and a second pole of the fourteenth transistor Connected to the pull-down node;
  • a control pole of the fifteenth transistor is connected to the pull-down node, a first pole of the fifteenth transistor is connected to the pull-up node, and a second pole of the fifteenth transistor is connected to the first operation. Power end connection;
  • the control pole of the sixteenth transistor is connected to the pull-up node, the first pole of the sixteenth transistor is connected to the pull-down node, and the second pole of the sixteenth transistor is connected to the first operation. Power end connection;
  • a control pole of the seventeenth transistor is connected to the pull-up node, a first pole of the seventeenth transistor is connected to a fifth control signal input terminal, and a second pole of the seventeenth transistor is connected to the drive Signal output terminal connection;
  • a first end of the second capacitor is connected to the pull-up node, and a second end of the second capacitor is connected to the driving signal output terminal;
  • the control electrode of the eighteenth transistor is connected to the pull-down node, the first electrode of the eighteenth transistor is connected to the driving signal output terminal, and the second electrode of the eighteenth transistor is connected to the first Work power connection
  • the control pole of the nineteenth transistor is connected to the fifth control signal input terminal, the first pole of the nineteenth transistor is connected to the second working power terminal, and the second pole of the nineteenth transistor Connected to the pull-down node.
  • each transistor in the driving unit is a transistor of the same conductivity type.
  • the present disclosure provides a gate driving circuit including: a plurality of cascaded driving units, wherein the driving unit adopts a driving unit according to the present disclosure;
  • the driving signal output terminal of the shift register of each other driving unit is connected to the reset signal input terminal of the shift register of the previous-level driving unit;
  • the driving signal output terminal of the shift register of each other driving unit is connected to the precharge signal input terminal of the shift register of the next stage driving unit.
  • the present disclosure provides a display substrate including a gate driving circuit according to the present disclosure.
  • the present disclosure provides a driving method for driving a driving unit according to the present disclosure, the driving method including:
  • the voltage at the first node is controlled by the first control sub-circuit to be at an active level, and the voltage at the second node is controlled by the second control sub-circuit at an inactive level, so that the output sub- The circuit outputs a voltage at an effective level through the first signal output terminal;
  • the voltage at the first node is controlled by the first control sub-circuit to be at an effective level
  • the voltage at the second node is controlled by the second control sub-circuit at the effective level, so that the output sub-circuit Outputting a voltage at an inactive level through the first signal output terminal;
  • the voltage at the first node is controlled by the first control sub-circuit to be at an active level, and the voltage at the second node is controlled by the second control sub-circuit at an inactive level, so that the The output sub-circuit outputs a voltage at an effective level through the first signal output terminal.
  • the voltage at the pull-up node is at an active level
  • the voltage at the pull-down node is at an inactive level
  • the voltage at the output terminal of the driving signal is The voltage is at an active level
  • a working cycle of the shift register includes a precharge phase, an output phase, and a reset phase
  • the pull-up node is reset, the voltage of the pull-down node is controlled to be at an active level, and a voltage at an inactive level is output via the driving signal output terminal.
  • the preset time period is within the output stage.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel unit having an external compensation function
  • FIG. 2 is a working timing diagram of the pixel unit shown in FIG. 1;
  • 3a is a schematic circuit structure diagram of a shift register according to an embodiment of the present disclosure.
  • 3b is an operation timing diagram of a shift register according to an embodiment of the present disclosure.
  • 4a is a schematic circuit structure diagram of a shift register according to an embodiment of the present disclosure.
  • 4b is a schematic circuit structure diagram of a shift register according to another embodiment of the present disclosure.
  • FIG. 5 is a structural block diagram of a driving unit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic circuit structure diagram of a driving unit according to an embodiment of the present disclosure.
  • FIG. 7 is a working timing diagram of the driving unit shown in FIG. 6;
  • FIG. 8 is a schematic diagram of a circuit structure of a driving unit according to another embodiment of the present disclosure.
  • FIG. 9 is a schematic circuit configuration diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 10 is a flowchart of a driving method according to an embodiment of the present disclosure.
  • External compensation refers to reading the current at the driving transistor or OLED through an induction circuit, using the read electrical signal, and implementing a complex algorithm with the help of an external integrated circuit chip, which can non-uniformly drive the threshold voltage and mobility of the driving transistor. And the aging of the OLED.
  • a double pulse signal needs to be provided to the control electrode of the sensing transistor in the pixel unit.
  • the shift registers of various levels in a conventional gate driver circuit can only output single-pulse signals and cannot output double-pulse signals, the conventional GOA circuit cannot satisfy the sensing transistor.
  • Driving requirements during the sensing phase can be output through the gate driving chip to drive the sensing transistor.
  • due to the large size of the gate drive chip it is not conducive to the narrow frame design of the display substrate.
  • active level refers to a voltage that can control the corresponding transistor to be turned on
  • active level refers to a voltage that can control the corresponding transistor to be turned off.
  • the active level is high and the inactive level is low.
  • the transistor is a P-type transistor, the active level is low and the inactive level is high.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel unit having an external compensation function.
  • the pixel unit includes a switching transistor TFT, a driving transistor DTFT, a sensing transistor STFT, an organic light emitting diode OLED, and a capacitor.
  • the control electrode of the switching transistor TFT is connected to the first gate line G1, the first electrode is connected to the data line Data, and the second electrode is connected to the control electrode of the driving transistor DTFT.
  • the first electrode of the driving transistor DTFT is connected to the power input terminal VDD.
  • the second electrode is connected to the anode of the organic light emitting diode OLED;
  • the control electrode of the sensing transistor STFT is connected to the second gate line G2, the first electrode is connected to the signal reading line Sense, and the second electrode is connected to the anode of the organic light emitting diode OLED;
  • the capacitor One end is connected to the control electrode of the driving transistor DTFT, and the other end is connected to the second electrode of the driving transistor DTFT; the cathode of the organic light emitting diode OLED is grounded.
  • FIG. 2 is an operation timing diagram of the pixel unit shown in FIG. 1.
  • the working process of the pixel unit includes the following two phases: a display driving phase and a stable display phase, in which a period of time is taken as a sensing phase during the stable display phase, and the sensing is performed during the sensing phase.
  • the sensing phase may include the following phases: a reset phase s1, an accumulation phase s2, a signal reading phase s3, and a reset phase s4.
  • the first gate line G1 and the second gate line G2 provide an effective level
  • the sensing transistor STFT and the switching transistor TFT are turned on, and the reset signal is written by the signal reading line Sense and the sensing transistor STFT.
  • the test voltage Vsense is written into the control electrode of the driving transistor DTFT through the data line Data and the switching transistor TFT.
  • the second gate line G2 provides an inactive level
  • the sensing transistor STFT is turned off
  • the point P is charged by the current output from the driving transistor DTFT, so that the voltage at the point P rises until the voltage at the point P reaches Vsense -Vth, where Vth is the threshold voltage of the driving transistor DTFT.
  • Vth is the threshold voltage of the driving transistor DTFT.
  • the second gate line G2 provides an effective level
  • the sensing transistor STFT is turned on again, and the voltage at the point P measured by the signal reading line Sense is Vsense-Vth.
  • Vsense is known
  • the threshold voltage Vth of the driving transistor DTFT can be obtained by the voltage Vsense-Vth at the point P.
  • the second gate line G2 provides an active level, and the reset signal is written into the point P again through the signal read line Sense and the sensing transistor STFT.
  • the switching transistor TFT is in an on state, that is, during the entire sensing stage, the signal provided by the first gate line G1 connected to the control electrode of the switching transistor TFT is at an effective level.
  • the sensing transistor STFT is on during the reset phase s1, the signal read phase s3, and the reset phase s4, and is turned off during the accumulation phase s2, that is, during the reset phase s1, the signal read phase s3, and the reset phase s4.
  • the signal provided by the second gate line G2 connected to the control electrode of the sensing transistor STFT is at an active level, and the signal provided by the second gate line G2 is at an inactive level during the accumulation phase s2.
  • a double pulse signal needs to be provided for the second gate line G2 (or the control electrode of the sensing transistor STFT), where the first pulse corresponds to the reset phase s1 and the second The pulse corresponds to the signal reading phase s3 and the reset phase s4.
  • the shift registers of the various stages of the conventional GOA circuit can only output a single pulse signal, the driving requirements of the second gate line G2 in the sensing stage cannot be met.
  • the gate driving chip is used for driving, although the driving requirement of the second gate line G2 in the sensing stage can be satisfied, the size of the gate driving chip is not suitable for the narrow frame design of the display substrate.
  • the present disclosure provides a driving unit and a driving method thereof, a gate driving circuit, and a display substrate, which substantially avoid one or more of the problems due to the limitations and disadvantages of the prior art.
  • a signal at a pull-up node, a signal at a pull-down node, and a signal output from a driving signal output terminal in a shift register are used as control signals to output a double-pulse driving signal, so that it can be sensed
  • the second gate line G2 in the pixel unit is driven in a stage.
  • FIG. 5 is a schematic diagram of a circuit structure of a driving unit according to an embodiment of the present disclosure. As shown in FIG. 5, the driving unit includes a shift register SR and a first output circuit.
  • FIG. 3a is a structural block diagram of a shift register SR according to an embodiment of the present disclosure
  • FIG. 3b is an operation timing diagram of the shift register SR according to an embodiment of the present disclosure.
  • the shift register SR includes a precharge reset circuit, a pull-up circuit, a pull-down control circuit, and a pull-down circuit.
  • the precharge reset circuit is respectively connected to the precharge signal input terminal INPUT and the reset signal input terminal RESET and connected to the pull-up circuit to the pull-up node PU.
  • the pull-down control circuit and the pull-down circuit are connected to the pull-down node PD.
  • the pull-up circuit and the pull-down circuit are connected.
  • the working cycle of the shift register mainly includes the following three phases: a precharge phase, an output phase, and a reset phase.
  • the pull-up node PU is precharged by a precharge reset circuit to prepare for the subsequent output stage.
  • a voltage at an effective level is output to the driving signal output terminal Cout through the pull-up circuit, that is, a single pulse is output.
  • the pull-up node PU is reset by a precharge reset circuit, so that the pull-up circuit stops working.
  • the pull-down control circuit controls the voltage of the pull-down node PD to be at an active level.
  • the pull-down circuit outputs a non-active level voltage to the driving signal output terminal Cout, thereby achieving the purpose of resetting.
  • the shift register will be in a wait phase (until the pre-charge phase of the next cycle arrives).
  • the voltage of the pull-up node PU maintains an inactive level
  • the voltage of the pull-down node PD maintains an active level, so that the driving signal output terminal Cout keeps outputting a voltage of an inactive level.
  • FIG. 4a is a schematic diagram of a circuit structure of a shift register according to an embodiment of the present disclosure
  • FIG. 4b is a schematic diagram of a circuit structure of a shift register according to another embodiment of the present disclosure.
  • the shift register has a circuit structure of 8T1C (eight transistors M1 to M8 and one capacitor C1), where the precharge reset circuit corresponds to transistors M1 to M3, and the pull-up circuit corresponds to transistor M7 and capacitor C1.
  • the pull-down control circuit corresponds to the transistors M4 to M6, and the pull-down circuit corresponds to the transistor M8.
  • the precharge reset circuit includes an eleventh transistor M1, a twelfth transistor M2, and a thirteenth transistor M3; a pull-up circuit includes a seventeenth transistor M7 and a second capacitor C1; a pull-down control circuit includes a tenth The four crystal M4, the fifteenth transistor M5, and the sixteenth transistor M6; the pull-down circuit includes an eighteenth transistor M8.
  • the control pole of the eleventh crystal M1 is connected to the fourth control signal input terminal CLK4, the first pole is connected to the precharge signal input terminal INPUT, and the second pole is connected to the pull-up node PU.
  • the control electrode of the twelfth transistor M2 is connected to the fourth control signal input terminal CLK4, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the first electrode of the thirteenth transistor M3.
  • the control electrode of the thirteenth transistor M3 is connected to the reset signal input terminal RESET, and the second electrode is connected to the first working power terminal VGL, wherein the first working voltage at the inactive level is provided through the first working power terminal VGL.
  • the control electrode and the first electrode of the fourteenth transistor M4 are respectively connected to the second working power terminal VGH, and the second electrode is connected to the pull-down node PD, wherein the second working voltage at the effective level is provided through the second working power terminal VGH. .
  • the control electrode of the fifteenth transistor M5 is connected to the pull-down node PD, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the first working power terminal VGL.
  • the control electrode of the sixteenth transistor M6 is connected to the pull-up node PU, the first electrode is connected to the pull-down node PD, and the second electrode is connected to the first working power terminal VGL.
  • the control pole of the seventeenth transistor M7 is connected to the pull-up node PU, the first pole is connected to the fifth control signal input terminal CLK5, and the second pole is connected to the drive signal output terminal Cout.
  • One end of the second capacitor C1 is connected to the pull-up node PU, and the second end is connected to the driving signal output terminal Cout.
  • the control electrode of the eighteenth transistor M8 is connected to the pull-down node PD, the first electrode is connected to the driving signal output terminal Cout, and the second electrode is connected to the first working power terminal VGL.
  • the shift register shown in FIG. 4b has a circuit structure of 9T1C (9 transistors M1 to M9 and 1 capacitor C1), in which the precharge reset circuit corresponds to transistors M1 to M3, the pull-up circuit corresponds to transistor M7 and capacitor C1, and pull-down control The circuit corresponds to the transistors M4 to M6 and M9, and the pull-down circuit corresponds to the transistor M8.
  • the pull-down control circuit in the shift register shown in FIG. 4b further includes a nineteenth transistor M9.
  • the control pole of the nineteenth transistor M9 is connected to the fifth control signal input terminal CLK5, the first pole is connected to the second working power terminal VGH, and the second pole is connected to the pull-down node PD.
  • the control electrode of the fourteenth transistor M4 is connected to the fourth control signal input terminal CLK4.
  • the fourth control signal input terminal CLK4 and the fifth control signal input terminal CLK5 are respectively connected to corresponding clock signal lines, that is, the clock signal is used as a control signal.
  • the working process of the circuit shown in FIG. 4a and FIG. 4b is the same as that of FIG. 3, and will not be described in detail here.
  • the first output circuit includes: a first control sub-circuit 1, a second control sub-circuit 2 and an output sub-circuit 3; the first control sub-circuit 1 and the output sub-circuit 3 are connected to the first node Q1, and the first The control sub-circuit 1, the second control sub-circuit 2 and the output sub-circuit 3 are connected to the second node Q2.
  • the first control sub-circuit 1 is connected to the pull-up node PU of the shift register SR, the pull-down node PD of the shift register SR, and the second node Q2, and is used for the voltage of the pull-node PU, the voltage of the pull-down node PD, and the second node Under the control of the voltage of Q2, the voltage at the first node Q1 is controlled to be at an active level within a preset time period in the output stage of the shift register SR; wherein the preset time period includes: a first sub-time set continuously Period, second sub-period, and third sub-period.
  • the preset time period corresponds to the aforementioned sensing phase
  • the first sub time period corresponds to the reset phase s1 in FIG. 2
  • the second sub time period corresponds to the accumulation phase s2 in FIG. 2
  • the third sub time period corresponds to the signal reading phase s3 and the reset phase s4 in FIG. 2.
  • the specific duration can be set and adjusted according to actual needs.
  • the second control sub-circuit 2 is connected to the pull-down node PD of the shift register SR and the drive signal output terminal Cout of the shift register SR, and is used for controlling the voltage of the pull-down node PD and the voltage provided by the drive signal output terminal Cout.
  • the voltage at the second node Q2 is controlled to be at an inactive level during one sub-time period and the third sub-time period, and the voltage at the second node Q2 is controlled to be at an active level during the second sub-time period.
  • the output sub-circuit 3 is connected to the first node Q1, the second node Q2, and the first signal output terminal Gout1, and is used to control the voltage of the first node Q1 under the control of the voltage of the first node Q1 and the voltage of the second node Q2.
  • the voltage at the second node Q2 is at an inactive level
  • the voltage at the active level is output through the first signal output terminal Gout1
  • the voltage at the second node Q2 is at the active level through the first signal output terminal.
  • Gout1 outputs a voltage at an inactive level.
  • the working process of the driving unit according to the present disclosure in a preset time period includes three sub-time periods.
  • the voltage at the first node Q1 is at an active level, and the voltage at the second node Q2 is at an inactive level.
  • the output sub-circuit 3 outputs a voltage at an effective level through the first signal output terminal Gout1. That is, the first pulse is output; in the second sub-period, the voltage of the first node Q1 is at an effective level, and the voltage of the second node Q2 is at an effective level.
  • the output sub-circuit 3 outputs the signal at the first signal output terminal Gout1 at Voltage of non-active level; in the third sub-period, the voltage of the first node Q1 is at the active level, and the voltage of the second node Q2 is at the non-active level, the output sub-circuit 3 outputs through the first signal output terminal Gout1 At the active level, the second pulse is output.
  • the driving unit provided in the present disclosure can output a double pulse signal within a preset period of time, so that the second grid line in the pixel unit can be driven during the sensing stage, which is beneficial to the realization of a narrow frame.
  • FIG. 6 is a schematic diagram of a circuit structure of a driving unit according to an embodiment of the present disclosure, and illustrates an embodiment of the driving unit shown in FIG. 5.
  • the first control sub-circuit 1 is connected to the first clock signal line through the first control signal input terminal CLK1 (that is, the first clock signal provided through the first clock signal line is used as the control signal), and the first control The sub-circuit 1 also inputs a first working voltage through the first working power supply terminal VGL.
  • the first control sub-circuit 1 is used to write the first clock signal provided through the first clock signal line into the first clock signal under the control of the voltage of the pull-up node PU during the pre-charge phase and the output phase of the shift register SR.
  • the first clock signal is at an active level within a preset period of time; under the control of the voltage of the pull-down node PD, during the reset stage of the shift register SR, the first The working voltage is written into the first node Q1; and under the control of the voltage of the second node Q2, when the voltage of the second node Q2 is at an effective level, the first working voltage is written into the first node Q1.
  • the first working voltage terminal VGL provides a first working voltage at an inactive level.
  • the first control sub-circuit 1 includes a first transistor T1, a second transistor T2, and a third transistor T3.
  • the control pole of the first transistor T1 is connected to the pull-up node PU, the first pole of the first transistor T1 is connected to the first control signal input terminal CLK1, and the second pole of the first transistor T1 is connected to the first node Q1.
  • the control electrode of the second transistor T2 is connected to the pull-down node PD, the first electrode of the second transistor T2 is connected to the first node Q1, and the second electrode of the second transistor T2 is connected to the first working power terminal VGL.
  • the control electrode of the third transistor T3 is connected to the second node Q2, the first electrode of the third transistor T3 is connected to the first node Q1, and the second electrode of the third transistor T3 is connected to the first working power terminal VGL.
  • the second control sub-circuit 2 is connected to the second clock signal line through the second control signal input terminal CLK2 (that is, the second clock signal provided through the second clock signal line is used as the control signal), and the second control The sub-circuit 2 also inputs a second working voltage through the second working power terminal VGH.
  • the second control sub-circuit 2 is used to: under the control of the voltage of the pull-down node PD, write the second working voltage provided by the second working power terminal to the second node Q2 during the reset phase of the shift register SR; Under the control of the voltage provided by the driving signal output terminal Cout, during the output stage of the shift register SR, the second clock signal provided through the second control signal input terminal CLK2 is output to the second node Q2.
  • the first sub-time period and the third sub-time period are at an inactive level, and the second clock signal is at an active level during the second sub-time period.
  • the second working power terminal VGH provides a second working voltage at an active level.
  • the second control sub-circuit 2 includes a fourth transistor T4 and a fifth transistor T5.
  • the control electrode of the fourth transistor T4 is connected to the pull-down node PD, the first electrode of the fourth transistor T4 is connected to the second working power terminal VGH, and the second electrode of the fourth transistor T4 is connected to the second node Q2.
  • the control electrode of the fifth transistor T5 is connected to the driving signal output terminal Cout, the first electrode of the fifth transistor T5 is connected to the second node Q2, and the second electrode of the fifth transistor T5 is connected to the second control signal input terminal CLK2.
  • the output sub-circuit 3 further inputs a control signal through a third control signal input terminal, and is connected to the first working power terminal.
  • the output sub-circuit 3 is used to write the voltage at the effective level provided by the third control signal input terminal into the first sub-period under the control of the voltage of the first node Q1 in the first sub-time period and the third sub-time period.
  • the output sub-circuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a first capacitor C.
  • the control electrode of the sixth transistor T6 is connected to the first control signal input terminal CLK1, the first electrode of the sixth transistor T6 is connected to the second working power terminal VGH, and the second electrode of the sixth transistor T6 is connected to the first node Q1.
  • the control electrode of the seventh transistor T7 is connected to the first node Q1, the first electrode of the seventh transistor T7 is connected to the second working power terminal VGH, and the second electrode of the seventh transistor T7 is connected to the first signal output terminal Gout1.
  • the control electrode of the eighth transistor T8 is connected to the second node Q2, the first electrode of the eighth transistor T8 is connected to the first signal output terminal Gout1, and the second electrode of the eighth transistor T8 is connected to the first operating power terminal VGL.
  • the first terminal of the first capacitor C is connected to the first node Q1, and the second terminal of the first capacitor C is connected to the first signal output terminal Gout1.
  • the control signal provided through the first control signal input terminal CLK1 is at an active level within a preset time period. In the present disclosure, the capacitor C can ensure a stable output of the first signal output terminal Gout1.
  • FIG. 8 is a circuit diagram of a driving unit according to another embodiment of the present disclosure.
  • the difference between the driving unit shown in FIG. 8 and the driving unit shown in FIG. 6 is the connection manner of the sixth transistor T6 and the seventh transistor T7.
  • the control electrode and the first electrode of the sixth transistor T6 in this embodiment are respectively connected to the third control signal input terminal CLK3, and the second electrode of the sixth transistor is connected to the first node Q1.
  • the control signal input through the third control signal input terminal CLK3 can be the same as the control signal input through the first control signal input terminal CLK1. In this way, the sixth transistor T6 and the seventh transistor T7 in this embodiment can no longer be always affected by the positive voltage, thereby improving the reliability of the circuit.
  • the first control signal input terminal CLK1, the second control signal input terminal CLK2, the third control signal input terminal CLK3, the fourth control signal input terminal CLK4, and the fifth control signal input terminal CLK5 are respectively associated with corresponding clocks. Signal line connection.
  • the control signals input through the first control signal input terminal, the second control signal input terminal, the third control signal input terminal, the fourth control signal input terminal, and the fifth control signal input terminal are all clock signals.
  • the clock signal input through the third control signal input terminal is at an effective level within a preset time period.
  • FIG. 7 is a working timing diagram of the driving unit shown in FIG. 6. The working process of the driving unit shown in FIG. 6 will be described below with reference to FIG. 7. In the following description, it is assumed that each transistor is an N-type transistor, the first working power supply terminal VGL provides a low-level working voltage, and the second working power supply terminal VGH provides a high-level working voltage.
  • the working process of the driving unit corresponds to the working process of the shift register SR, and mainly includes a precharge stage, an output stage, and a reset stage.
  • the voltage at the pull-up node PU is at a high level
  • the voltage at the drive signal output terminal Cout is at a low level
  • the voltage at the pull-down node PD is at a low level
  • the first pass The first clock signal provided by the control signal input terminal CLK1 is at a low level
  • the second clock signal provided by the second control signal input terminal CLK2 is at a low level in some time periods and at a high level in some time periods.
  • the first transistor T1 is turned on, and the first clock signal is written into the first node Q1 through the first transistor T1. Since the first clock signal is at a low level, the voltage at the first node Q1 is at a low level, and the seventh transistor T7 is turned off. At the same time, under the control of the first clock signal at a low level, the sixth transistor T6 is also in an off state.
  • both the second transistor T2 and the fourth transistor T4 are turned off.
  • the fifth transistor T5 is turned off because the voltage at the drive signal output terminal Cout is at a low level.
  • the second node Q2 is in a floating state, and the second node Q2 maintains a high-level state at the end of the previous period.
  • the third transistor T3 and the eighth transistor T8 are both turned on.
  • the third transistor T3 writes a low-level operating voltage provided through the first operating voltage terminal VGL to the first node Q1, thereby maintaining the voltage of the first node Q1 to a low level.
  • the low-level operating voltage provided through the first operating voltage terminal VGL is written into the first signal output terminal Gout1 through the eighth transistor T8, and then the low-level voltage is output through the first signal output terminal Gout1.
  • the output stage includes at least a preset time period t0 (corresponding to a sensing stage for performing external compensation).
  • the preset time period t0 includes a first sub-time period t1, a second sub-time period t2, and a third sub-time period t3 which are continuously set.
  • the first clock signal is at a high level and the second clock signal is at a low level.
  • the first transistor T1 is continuously turned on, so that the first clock signal can be continuously written into the first node Q1. Since the first clock signal is at a high level and the voltage at the first node Q1 is at a high level, the sixth transistor T6 and the seventh transistor T7 are both turned on at this time, and the seventh transistor T7 constitutes a diode.
  • both the second transistor T2 and the fourth transistor T4 are maintained in an off state.
  • the fifth transistor T5 is turned on because the voltage at the driving signal output terminal Cout is at a high level.
  • the second clock signal can be written into the second node Q2 through the fifth transistor T5. Because the second clock signal is at a low level, the voltage at the second node Q2 is at a low level.
  • the third transistor T3 and the eighth transistor T8 are both turned off.
  • the eighth transistor T8 When the eighth transistor T8 is turned off, the high-level operating voltage provided through the second working power terminal VGH is written into the first signal output terminal Gout1 through the seventh transistor T7, and the first signal output terminal Gout1 outputs a high level Voltage.
  • the first clock signal is at a high level
  • the second clock signal is at a high level. Since the fifth transistor T5 is continuously turned on, the second clock signal at a high level is written into the second node Q2 through the fifth transistor T5. Since the voltage at the second node Q2 is at a high level, both the third transistor T3 and the eighth transistor T8 are turned on.
  • the eighth transistor T8 Since the eighth transistor T8 is turned on, the low-level operating voltage provided through the first working power supply terminal VGL is written into the first signal output terminal Gout1 through the eighth transistor T8, and the first signal output terminal Gout1 outputs a low-level voltage.
  • the first clock signal (through the first transistor T1), the high level The working voltage (through the sixth transistor T6) and the low-level working voltage (through the third transistor T3) charge the first node Q1 at the same time.
  • the magnitude of the voltage at the first node Q1 is related to the channel width-to-length ratio of the first transistor T1, the sixth transistor T6, and the third transistor T3.
  • the first signal output terminal Gout1 always outputs a low voltage.
  • the seventh transistor T7 When the voltage at the first node Q1 is at a high level, since the sixth transistor T6 is turned on, the seventh transistor T7 constitutes a diode. When the eighth transistor T8 is turned on, the seventh transistor T7 acts as a large resistor, and the first signal output terminal Gout1 outputs a low-level voltage. When the voltage at the first node Q1 is at a low level, the seventh transistor T7 is turned off, and the first signal output terminal Gout1 is charged by the eighth transistor T8 only through the low-level operating voltage provided by the first operating power terminal VGL. A signal output terminal Gout1 outputs a low-level voltage. The figure only illustrates the voltage at the first node Q1 at a high level during the second sub-period by way of example.
  • the first clock signal is at a high level and the second clock signal is at a low level.
  • the pull-up node PU maintains a high-level state
  • the first transistor T1 is continuously turned on, and the first clock signal is continuously written into the first node Q1.
  • the voltage at the first node Q1 is at a high level.
  • the sixth transistor T6 and the seventh transistor T7 are both turned on, and the seventh transistor T7 constitutes a diode. Because the voltage at the pull-down node PD is at a low level, both the second transistor T2 and the fourth transistor T4 are maintained in an off state.
  • the fifth transistor T5 is turned on because the voltage at the driving signal output terminal Cout is at a high level.
  • the second clock signal can be written into the second node Q2 through the fifth transistor T5.
  • the third transistor T3 and the eighth transistor T8 are both turned off at this time.
  • the eighth transistor T8 is turned off, the high-level operating voltage provided through the second working power terminal VGH is written into the first signal output terminal Gout1 through the seventh transistor T7, and the first signal output terminal Gout1 outputs a high level Voltage.
  • the first signal output terminal Gout1 of the driving unit provided by the present disclosure can output a double pulse signal at a preset time period t0, so that the second gate line in the pixel unit can be driven during the sensing stage. Since the technical solution of the present disclosure is based on the GOA circuit, it is beneficial to realize a narrow frame of the display substrate.
  • the duration of the preset time period t0 may be shorter than the duration of the output stage of the shift register SR (the start time of the preset time period t0 is later than the start time of the output stage, but the preset time period The end time of t0 is the same as the end time of the output phase).
  • the first clock signal is at a low level
  • the voltage at the first node Q1 At a low level the seventh transistor T7 is turned off.
  • the eighth transistor T8 is also turned off, and the first signal output terminal Gout1 is in a floating state.
  • the voltage at the first signal output terminal Gout1 maintains the voltage at the end of the precharge phase, that is, the low-level voltage.
  • the voltage at the pull-up node PU is at a low level
  • the voltage at the drive signal output terminal Cout is at a low level
  • the voltage at the pull-down node PD is at a high level.
  • the first clock signal provided through the first control signal input terminal CLK1 is at a low level
  • the second clock signal provided through the second control signal input terminal CLK2 is at a low level in some time periods and at a high level in some time periods. .
  • the first transistor T1 Since the voltage at the pull-up node PU is at a low level, the first transistor T1 is turned off. Because the voltage at the pull-down node PD is at a high level, the second transistor T2 and the fourth transistor T4 are turned on, and the low-level operating voltage provided through the first operating power terminal VGL is written into the first node Q1 through the second transistor T2. . The voltage at the first node Q1 is low, and the seventh transistor T7 is turned off. The high-level operating voltage provided by the second working power terminal VGH is written into the second node Q2 through the fourth transistor T4. The voltage at the second node Q2 is at a high level, and the third transistor T3 and the eighth transistor T8 are both turned on. through.
  • the low-level working voltage provided through the first working power supply terminal VGL is written into the first node Q1 through the third transistor T3, so as to maintain the voltage of the first node Q1 at a low level.
  • the low-level operating voltage provided through the first working power terminal VGL is written into the first signal output terminal Gout1 through the eighth transistor T8, and the first signal output terminal Gout1 outputs a low-level voltage.
  • the voltage at the pull-up node PU maintains a low state
  • the voltage at the drive signal output terminal Cout maintains a low state.
  • the voltage at the pull-down node PD maintains a high-level state, so the working process of the driving unit in the waiting phase is the same as the process in the reset phase. That is, the first signal output terminal Gout1 of the driving unit continuously outputs a low-level voltage during the waiting period.
  • the driving unit further includes a second output circuit 4 (not shown in FIG. 5).
  • the second output circuit 4 is respectively connected to the pull-up node PU, the pull-down node PD, and the second signal output terminal Gout2, and is used to control the voltage of the pull-up node PU and the voltage of the pull-down node PD under the control of During the preset time period t0, a voltage at an effective level is output through the second signal output terminal Gout2.
  • the second output circuit 4 is capable of outputting a single-pulse signal within a preset time period t0, so that the first gate line (the control electrode of the switching transistor TFT in FIG. 1) in the pixel unit can be detected during the sensing phase.
  • the connected gate line G1) is driven. That is, the driving unit provided by the present disclosure can not only provide a driving signal for a sensing transistor in a pixel unit during a sensing stage, but also provide a driving signal for a switching transistor in a pixel unit at the same time, thereby effectively reducing the need for a display substrate.
  • the number of gate driving circuits is more conducive to the realization of a narrow frame.
  • the second output circuit 4 is also connected to the first control signal input terminal CLK1 (ie, the first clock signal line) and the first working power terminal VGL, and the second output circuit 4 is configured to: Under the control of the voltage of the node PU, the first clock signal provided through the first control signal input terminal CLK1 is written into the second signal output terminal Gout2 during the precharge phase and the output phase of the shift register SR, and the first clock signal It is at an active level within a preset time period t0; under the control of the voltage of the pull-down node PD, during the reset phase of the shift register SR, the first working voltage provided by the first working power supply terminal VGL is written into the second Signal output terminal Gout2.
  • the second output circuit 4 includes a ninth transistor T9 and a tenth transistor T10.
  • the control pole of the ninth transistor T9 is connected to the pull-up node PU, the first pole of the ninth transistor T9 is connected to the first control signal input terminal CLK1, and the second pole of the ninth transistor T9 is connected to the second signal output terminal Gout2.
  • the control electrode of the tenth transistor T10 is connected to the pull-down node PD, the first electrode of the tenth transistor T10 is connected to the second signal output terminal Gout2, and the second electrode of the tenth transistor T10 is connected to the first working power terminal VGL.
  • the ninth transistor T9 is turned on and the tenth transistor T10 is turned off.
  • the first clock signal is written into the second signal output terminal Gout2 through the ninth transistor T9. Because the first clock signal is at a low level, the second signal output terminal Gout2 outputs a low-level voltage.
  • the ninth transistor T9 remains on and the tenth transistor T10 remains off State, the first clock signal is written into the second signal output terminal Gout2 through the ninth transistor T9.
  • the second signal output terminal Gout2 outputs a high-level voltage.
  • the second signal output terminal Gout2 of the driving unit provided in the present disclosure can output a single pulse signal within a preset time period t0, so that the first gate line in the pixel unit can be driven during the sensing phase. Conducive to the realization of narrow borders.
  • the ninth transistor T9 is turned off and the tenth transistor T10 is turned on.
  • the low-level operating voltage provided through the first working power supply terminal VGL is written into the second signal output terminal Gout2 through the tenth transistor T10, and the second signal output terminal Gout2 outputs a low-level voltage.
  • each transistor in the driving unit may be an N-type transistor, or each transistor in the driving unit may be a P-type transistor.
  • each transistor in the driving unit can be prepared at the same time through the same transistor manufacturing process, which can effectively shorten the production cycle.
  • FIG. 9 is a schematic circuit structure diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit includes a plurality of cascaded driving units GDX_1, GDX_2, ..., GDX_n, where the driving units GDX_1, GDX_2, ..., GDX_n can adopt the driving units provided in the above embodiments.
  • the specific structure and operation can be See the description in the previous embodiment.
  • the drive signal output terminal Cout of the shift register SR of each of the drive units GDX_2 ... GDX_n and the corresponding upper-stage drive units GDX_1, GDX_2 ... GDX_n The reset signal input terminal RESET of the shift register SR of -1 is connected. Except for the last stage drive unit GDX_n, the drive signal output terminal Cout of the shift register SR of each drive unit GDX_1, GDX_2 ... GDX_n-1 and the corresponding shift register SR of the next stage drive unit GDX_2 ... GDX_n Precharge signal input terminal INPUT connection.
  • the drive signal output terminal Cout of the shift register SR of each drive unit GDX_1, GDX_2 ... GDX_n can realize the cascade of the drive units, and the first signal output terminal Gout1 and the second of each drive unit The signal output terminal Gout2 realizes driving the first gate line G1 and the second gate line G2 in the pixel unit, respectively.
  • a display substrate includes a gate driving circuit, and the gate driving circuit may adopt a gate driving circuit according to an embodiment of the present disclosure.
  • the display substrate provided in the present disclosure is, for example, an OLED substrate.
  • FIG. 10 is a flowchart of a driving method according to an embodiment of the present disclosure, which is used to drive the driving unit described above. As shown in FIG. 10, the driving method may include the following steps S101 to S103.
  • step S101 during a first sub-period, the voltage at the first node is controlled by the first control sub-circuit at an active level, and the voltage at the second node is controlled by the second control sub-circuit at an inactive level.
  • the output sub-circuit is made to output a voltage at an effective level through the first signal output terminal.
  • step S102 during the second sub-period, the voltage at the first node is controlled by the first control sub-circuit to be at an effective level, and the voltage at the second node is controlled by the second control sub-circuit at the effective level, so that The output sub-circuit outputs a voltage at an inactive level through the first signal output terminal.
  • step S103 during the third sub-period, the voltage at the first node is controlled by the first control sub-circuit to be at an active level, and the voltage at the second node is controlled by the second control sub-circuit at an inactive level.
  • the output sub-circuit is made to output a voltage at an effective level through the first signal output terminal.
  • the voltage at the pull-up node is controlled by the pull-up circuit to be at an active level
  • the voltage at the pull-down node is controlled by the pull-down control circuit to be at an inactive level
  • the second output The second signal output terminal of the circuit outputs a voltage at an active level.
  • the preset time period includes a first sub-time period, a second sub-time period, and a third sub-time period that are continuously set.
  • the method further includes pre-charging the pull-up node through a pre-charging reset circuit before the first signal output terminal and the second signal output terminal respectively output a voltage at an effective level.
  • the method further includes, after the first signal output terminal and the second signal output terminal respectively output a voltage at an effective level, resetting the precharge reset circuit to stop the pull-up circuit, and the pull-up node The voltage is at an inactive level. At the same time, it is controlled by the pull-down control circuit so that the voltage at the pull-down node maintains an active level, so that the driving signal output terminal outputs a non-active level signal, and the first signal output terminal and the second signal output terminal are reset respectively.
  • the method further includes, after resetting the first signal output terminal and the second signal output terminal, controlling the voltage at the pull-up node to maintain an inactive level through a pull-up circuit, and controlling the pull-down node through a pull-down circuit.
  • the voltage at is maintained at an active level, so that the driving signal output terminal outputs a non-active level signal, and the first signal output terminal and the second signal output terminal respectively maintain an output reset level.
  • the duration of the preset time period is equal to the duration of the sensing time period, and the start time and end time of the preset time period are respectively aligned with the start time and end time of the sensing time period.
  • the duration of the preset time period is shorter than the duration of the stable display period of the light emitting diode.

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Abstract

Disclosed are a drive unit and a drive method therefor, a gate drive circuit and a display substrate. The drive unit comprises: a shift register (SR) and a first output circuit, wherein the first output circuit comprises: a first control sub-circuit (1), a second control sub-circuit (2), an output sub-circuit (3) and a first signal output end (Gout1); and the shift register (SR) comprises a pull-up node (PU), a pull-down node (PD) and a drive signal output end (Cout), the first control sub-circuit (1) and the output sub-circuit (3) being connected to a first node (Q1), and the first control sub-circuit (1), the second control sub-circuit (2) and the output sub-circuit (3) being connected to a second node (Q2).

Description

驱动单元及其驱动方法、栅极驱动电路和显示基板Driving unit and driving method thereof, gate driving circuit and display substrate
相关申请的交叉引用Cross-reference to related applications
本申请要求于2018年7月13日在中国知识产权局提交的申请号为201810770131.6的中国专利申请的优先权，该中国专利申请的全部公开内容通过引用合并于此。This application claims priority from Chinese Patent Application No. 201810770131.6 filed with the China Intellectual Property Office on July 13, 2018, the entire disclosure of which is incorporated herein by reference.
技术领域Technical field
本公开涉及显示技术领域，特别涉及一种驱动单元及其驱动方法、栅极驱动电路和显示基板。The present disclosure relates to the field of display technology, and in particular, to a driving unit and a driving method thereof, a gate driving circuit, and a display substrate.
背景技术Background technique
在对有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示面板中的OLED进行驱动时，由于各驱动晶体管或OLED的性能差异(例如，工艺导致的差异、老化导致的差异)，会导致显示面板的显示亮度不均一。因此，通常需要对驱动晶体管或OLED的性能进行补偿。When driving an OLED in an Organic Light-Emitting Diode (OLED) display panel, the performance of each driving transistor or OLED (for example, a difference caused by a process or a difference caused by aging) may cause a display. The display brightness of the panel is uneven. Therefore, it is usually necessary to compensate the performance of the driving transistor or the OLED.
发明内容Summary of the invention
一方面，本公开提供了一种驱动单元，包括：移位寄存器和第一输出电路，所述移位寄存器包括上拉节点、下拉节点和驱动信号输出端，所述第一输出电路构造为在所述上拉节点的电压、所述下拉节点的电压和所述驱动信号输出端提供的电压的控制下在预设时间段内输出双脉冲信号。In one aspect, the present disclosure provides a driving unit including a shift register and a first output circuit. The shift register includes a pull-up node, a pull-down node, and a driving signal output terminal. The first output circuit is configured to Under the control of the voltage of the pull-up node, the voltage of the pull-down node, and the voltage provided by the driving signal output terminal, a double-pulse signal is output within a preset time period.
根据本公开的实施例，所述第一输出电路包括：第一控制子电路、第二控制子电路和输出子电路；所述第一控制子电路和所述输出子电路连接于第一节点，所述第一控制子电路、所述第二控制子电路和所述输出子电路连接于第二节点；According to an embodiment of the present disclosure, the first output circuit includes: a first control sub-circuit, a second control sub-circuit, and an output sub-circuit; the first control sub-circuit and the output sub-circuit are connected to a first node, The first control sub-circuit, the second control sub-circuit, and the output sub-circuit are connected to a second node;
所述第一控制子电路与所述上拉节点和所述下拉节点连接，并且构造为在所述上拉节点的电压、所述下拉节点的电压、所述第二节 点的电压的控制下，在所述预设时间段内，控制所述第一节点处的电压处于有效电平，其中，所述预设时间段包括：连续设置的第一子时间段、第二子时间段和第三子时间段；The first control sub-circuit is connected to the pull-up node and the pull-down node, and is configured to be controlled by a voltage of the pull-up node, a voltage of the pull-down node, and a voltage of the second node, Controlling the voltage at the first node to be at an effective level within the preset time period, wherein the preset time period includes a first sub-time period, a second sub-time period, and a third time period which are continuously set; Sub-period
所述第二控制子电路与所述下拉节点和所述驱动信号输出端连接，并且构造为在所述下拉节点的电压、所述驱动信号输出端提供的电压的控制下，控制所述第二节点处的电压在所述第一子时间段和所述第三子时间段内处于非有效电平、在所述第二子时间段内处于有效电平；The second control sub-circuit is connected to the pull-down node and the drive signal output terminal, and is configured to control the second pull-down node under the control of the voltage of the pull-down node and the voltage provided by the drive signal output terminal. The voltage at the node is at an inactive level during the first sub-period and the third sub-period, and at an active level during the second sub-period;
所述输出子电路与第一信号输出端连接，并且构造为在所述第一节点的电压处于有效电平且所述第二节点的电压处于非有效电平时，通过所述第一信号输出端输出处于有效电平的电压，以及在所述第二节点的电压处于有效电平时，通过所述第一信号输出端输出处于非有效电平的电压。The output sub-circuit is connected to a first signal output terminal, and is configured to pass through the first signal output terminal when the voltage of the first node is at an active level and the voltage of the second node is at an inactive level. A voltage at an active level is output, and when the voltage at the second node is at an active level, a voltage at an inactive level is output through the first signal output terminal.
根据本公开的实施例，所述第一控制子电路包括：第一晶体管、第二晶体管和第三晶体管；According to an embodiment of the present disclosure, the first control sub-circuit includes: a first transistor, a second transistor, and a third transistor;
所述第一晶体管的控制极与所述上拉节点连接，所述第一晶体管的第一极与第一控制信号输入端连接，所述第一晶体管的第二极与所述第一节点连接；A control pole of the first transistor is connected to the pull-up node, a first pole of the first transistor is connected to a first control signal input terminal, and a second pole of the first transistor is connected to the first node ;
所述第二晶体管的控制极与所述下拉节点连接，所述第二晶体管的第一极与所述第一节点连接，所述第二晶体管的第二极与第一工作电源端连接，其中，所述第一工作电源端构造为提供处于非有效电平的第一工作电压；并且A control pole of the second transistor is connected to the pull-down node, a first pole of the second transistor is connected to the first node, and a second pole of the second transistor is connected to a first working power terminal, where The first working power terminal is configured to provide a first working voltage at an inactive level; and
所述第三晶体管的控制极与所述第二节点连接，所述第三晶体管的第一极与所述第一节点连接，所述第三晶体管的第二极与所述第一工作电源端连接。A control electrode of the third transistor is connected to the second node, a first electrode of the third transistor is connected to the first node, and a second electrode of the third transistor is connected to the first working power terminal. connection.
根据本公开的实施例，所述第二控制子电路包括：第四晶体管和第五晶体管；According to an embodiment of the present disclosure, the second control sub-circuit includes: a fourth transistor and a fifth transistor;
所述第四晶体管的控制极与所述下拉节点连接，所述第四晶体管的第一极与第二工作电源端连接，所述第四晶体管的第二极与所述第二节点连接，其中，所述第二工作电源端构造为提供处于有效电平 的第二工作电压；并且A control electrode of the fourth transistor is connected to the pull-down node, a first electrode of the fourth transistor is connected to a second working power terminal, and a second electrode of the fourth transistor is connected to the second node, wherein The second working power terminal is configured to provide a second working voltage at an effective level; and
所述第五晶体管的控制极与所述驱动信号输出端连接，所述第五晶体管的第一极与所述第二节点连接，所述第五晶体管的第二极与第二控制信号输入端连接。A control electrode of the fifth transistor is connected to the driving signal output terminal, a first electrode of the fifth transistor is connected to the second node, and a second electrode of the fifth transistor is connected to a second control signal input terminal. connection.
根据本公开的实施例，所述输出子电路包括：第六晶体管、第七晶体管、第八晶体和第一电容，According to an embodiment of the present disclosure, the output sub-circuit includes: a sixth transistor, a seventh transistor, an eighth crystal, and a first capacitor,
所述第六晶体管的控制极与所述第一控制信号输入端连接，所述第六晶体管的第一极与所述第二工作电源端连接，所述第六晶体管的第二极与所述第一节点连接；A control electrode of the sixth transistor is connected to the first control signal input terminal, a first electrode of the sixth transistor is connected to the second working power terminal, and a second electrode of the sixth transistor is connected to the first electrode. First node connected;
所述第七晶体管的控制极与所述第一节点连接，所述第七晶体管的第一极与所述第二工作电源端连接，所述第七晶体管的第二极与所述第一信号输出端连接；The control electrode of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is connected to the second working power terminal, and the second electrode of the seventh transistor is connected to the first signal. Output connection
所述第八晶体管的控制极与所述第二节点连接，所述第八晶体管的第一极与所述第一信号输出端连接，所述第八晶体管的第二极与所述第一工作电源端连接；并且A control electrode of the eighth transistor is connected to the second node, a first electrode of the eighth transistor is connected to the first signal output terminal, and a second electrode of the eighth transistor is connected to the first operation. Power-side connection; and
所述第一电容的第一端与所述第一节点连接，所述第一电容的第二端与所述第一信号输出端连接。A first terminal of the first capacitor is connected to the first node, and a second terminal of the first capacitor is connected to the first signal output terminal.
根据本公开的实施例，所述输出子电路包括：第六晶体管、第七晶体管、第八晶体和第一电容；According to an embodiment of the present disclosure, the output sub-circuit includes: a sixth transistor, a seventh transistor, an eighth crystal, and a first capacitor;
所述第六晶体管的控制极和第一极分别与第三控制信号输入端连接，所述第六晶体管的第二极与所述第一节点连接；A control electrode and a first electrode of the sixth transistor are respectively connected to a third control signal input terminal, and a second electrode of the sixth transistor is connected to the first node;
所述第七晶体管的控制极与所述第一节点连接，所述第七晶体管的第一极与所述第三控制信号输入端连接，所述第七晶体管的第二极与所述第一信号输出端连接；A control pole of the seventh transistor is connected to the first node, a first pole of the seventh transistor is connected to the third control signal input terminal, and a second pole of the seventh transistor is connected to the first node. Signal output terminal connection;
所述第八晶体管的控制极与所述第二节点连接，所述第八晶体管的第一极与所述第一信号输出端连接，所述第八晶体管的第二极与所述第一工作电源端连接；并且A control electrode of the eighth transistor is connected to the second node, a first electrode of the eighth transistor is connected to the first signal output terminal, and a second electrode of the eighth transistor is connected to the first operation. Power-side connection; and
所述第一电容的第一端与所述第一节点连接，所述第一电容的第二端与所述第一信号输出端连接。A first terminal of the first capacitor is connected to the first node, and a second terminal of the first capacitor is connected to the first signal output terminal.
根据本公开的实施例，驱动单元还包括：第二输出电路；According to an embodiment of the present disclosure, the driving unit further includes: a second output circuit;
所述第二输出电路分别与所述上拉节点、所述下拉节点和所述第一信号输出端连接，并且构造为在所述上拉节点的电压、所述下拉节点的电压的控制下，在所述预设时间段内，通过第二信号输出端输出处于有效电平的电压。The second output circuit is respectively connected to the pull-up node, the pull-down node, and the first signal output terminal, and is configured to be controlled by the voltage of the pull-up node and the voltage of the pull-down node, During the preset time period, a voltage at an effective level is output through the second signal output terminal.
根据本公开的实施例，所述第二输出电路包括：第九晶体管和第十晶体管；According to an embodiment of the present disclosure, the second output circuit includes: a ninth transistor and a tenth transistor;
所述第九晶体管的控制极与所述上拉节点连接，所述第九晶体管的第一极与所述第一控制信号输入端连接，所述第九晶体管的第二极与所述第二信号输出端连接；并且A control pole of the ninth transistor is connected to the pull-up node, a first pole of the ninth transistor is connected to the first control signal input terminal, and a second pole of the ninth transistor is connected to the second The signal output is connected; and
所述第十晶体管的控制极与所述下拉节点连接，所述第十晶体管的第一极与所述第二信号输出端连接，所述第十晶体管的第二极与所述第一工作电源端连接。A control pole of the tenth transistor is connected to the pull-down node, a first pole of the tenth transistor is connected to the second signal output terminal, and a second pole of the tenth transistor is connected to the first working power source.端 连接。 End connection.
根据本公开的实施例，驱动单元还包括第二输出电路；According to an embodiment of the present disclosure, the driving unit further includes a second output circuit;
其中，所述第二输出电路包括：第九晶体管和第十晶体管；The second output circuit includes: a ninth transistor and a tenth transistor;
所述第九晶体管的控制极与所述上拉节点连接，所述第九晶体管的第一极与所述第一控制信号输入端连接，所述第九晶体管的第二极与所述第二信号输出端连接；并且A control pole of the ninth transistor is connected to the pull-up node, a first pole of the ninth transistor is connected to the first control signal input terminal, and a second pole of the ninth transistor is connected to the second The signal output is connected; and
所述第十晶体管的控制极与所述下拉节点连接，所述第十晶体管的第一极与所述第二信号输出端连接，所述第十晶体管的第二极与所述第一工作电源端连接。A control pole of the tenth transistor is connected to the pull-down node, a first pole of the tenth transistor is connected to the second signal output terminal, and a second pole of the tenth transistor is connected to the first working power source.端 连接。 End connection.
根据本公开的实施例，所述上拉节点构造为在所述预设时间段内提供处于有效电平的电压，所述驱动信号输出端构造为在所述预设时间段内提供处于有效电平的电压，所述下拉节点构造为在所述预设时间段内提供处于非有效电平的电压。According to an embodiment of the present disclosure, the pull-up node is configured to provide a voltage at an effective level within the preset period of time, and the driving signal output terminal is configured to provide a voltage at an effective level within the preset period of time. A flat voltage, the pull-down node is configured to provide a voltage at an inactive level within the preset time period.
根据本公开的实施例，所述第一控制信号输入端构造为提供第一时钟信号，所述第二控制信号端构造为提供第二时钟信号，所述第一时钟信号在所述预设时间段内处于有效电平，所述第二时钟信号在所述第一子时间段和所述第三子时间段内处于非有效电平，并且在所述第二子时间段内处于有效电平。According to an embodiment of the present disclosure, the first control signal input terminal is configured to provide a first clock signal, the second control signal terminal is configured to provide a second clock signal, and the first clock signal is at the preset time. The second clock signal is at an active level during the first and third sub-periods, and is at an active level during the second sub-period. .
根据本公开的实施例，所述移位寄存器包括预充复位电路、上 拉电路、下拉电路和下拉控制电路；According to an embodiment of the present disclosure, the shift register includes a precharge reset circuit, a pull-up circuit, a pull-down circuit, and a pull-down control circuit;
所述预充复位电路分别与预充信号输入端和复位信号输入端连接并且与所述上拉电路连接于所述上拉节点，所述下拉电路与所述下拉控制电路连接于所述下拉节点，所述上拉电路和所述下拉电路连接于所述驱动信号输出端。The precharge reset circuit is respectively connected to a precharge signal input terminal and a reset signal input terminal and is connected to the pull-up circuit to the pull-up node, and the pull-down circuit and the pull-down control circuit are connected to the pull-down node. The pull-up circuit and the pull-down circuit are connected to the driving signal output terminal.
根据本公开的实施例，所述预充复位电路包括第十一晶体管、第十二晶体管和第十三晶体管；所述下拉控制电路包括第十四晶体管、第十五晶体管和第十六晶体管；所述上拉电路包括第十七晶体管和第二电容；所述下拉电路包括第十八晶体管；According to an embodiment of the present disclosure, the precharge reset circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; the pull-down control circuit includes a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor; The pull-up circuit includes a seventeenth transistor and a second capacitor; the pull-down circuit includes an eighteenth transistor;
所述第十一晶体管的控制极与第四控制信号输入端连接，所述第十一晶体管的第一极与所述预充信号输入端连接，所述第十一晶体管的第二极与所述上拉节点连接；The control pole of the eleventh transistor is connected to a fourth control signal input terminal, the first pole of the eleventh transistor is connected to the precharge signal input terminal, and the second pole of the eleventh transistor is connected to all Said pull-up node connection;
所述第十二晶体管的控制极与所述第四控制信号输入端连接，所述第十二晶体管的第一极与所述上拉节点连接，所述第十二晶体管的第二极与所述第十三晶体管的第一极连接；A control electrode of the twelfth transistor is connected to the fourth control signal input terminal, a first electrode of the twelfth transistor is connected to the pull-up node, and a second electrode of the twelfth transistor is connected to all The first pole connection of the thirteenth transistor;
所述第十三晶体管的控制极与复位信号输入端连接，所述第十三晶体管的第二极与所述第一工作电源端连接；A control electrode of the thirteenth transistor is connected to a reset signal input terminal, and a second electrode of the thirteenth transistor is connected to the first working power terminal;
所述第十四晶体管的控制极和第一极分别与所述第二工作电源端连接，所述第十四晶体管的第二极与所述下拉节点连接；A control electrode and a first electrode of the fourteenth transistor are respectively connected to the second working power terminal, and a second electrode of the fourteenth transistor is connected to the pull-down node;
所述第十五晶体管的控制极与所述下拉节点连接，所述第十五晶体管的第一极与所述上拉节点连接，所述第十五晶体管的第二极与所述第一工作电源端连接；A control pole of the fifteenth transistor is connected to the pull-down node, a first pole of the fifteenth transistor is connected to the pull-up node, and a second pole of the fifteenth transistor is connected to the first operation. Power end connection;
所述第十六晶体管的控制极与所述上拉节点连接，所述第十六晶体管的第一极与所述下拉节点连接，所述第十六晶体管的第二极与所述第一工作电源端连接；The control pole of the sixteenth transistor is connected to the pull-up node, the first pole of the sixteenth transistor is connected to the pull-down node, and the second pole of the sixteenth transistor is connected to the first operation. Power end connection;
所述第十七晶体管的控制极与所述上拉节点连接，所述第十七晶体管的第一极与第五控制信号输入端连接，所述第十七晶体管的第二极与所述驱动信号输出端连接；A control pole of the seventeenth transistor is connected to the pull-up node, a first pole of the seventeenth transistor is connected to a fifth control signal input terminal, and a second pole of the seventeenth transistor is connected to the drive Signal output terminal connection;
所述第二电容的第一端与所述上拉节点连接，所述第二电容的第二端与所述驱动信号输出端连接；并且A first terminal of the second capacitor is connected to the pull-up node, and a second terminal of the second capacitor is connected to the driving signal output terminal; and
所述第十八晶体管的控制极与所述下拉节点连接，所述第十八晶体管的第一极与所述驱动信号输出端连接，所述第十八晶体管的第二极与所述第一工作电源端连接。The control electrode of the eighteenth transistor is connected to the pull-down node, the first electrode of the eighteenth transistor is connected to the driving signal output terminal, and the second electrode of the eighteenth transistor is connected to the first The working power terminal is connected.
根据本公开的实施例，所述预充复位电路包括第十一晶体管、第十二晶体管和第十三晶体管；所述下拉控制电路包括第十四晶体管、第十五晶体管、第十六晶体管和第十九晶体管；所述上拉电路包括第十七晶体管和第二电容；所述下拉电路包括第十八晶体管；According to an embodiment of the present disclosure, the precharge reset circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; the pull-down control circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and A nineteenth transistor; the pull-up circuit includes a seventeenth transistor and a second capacitor; the pull-down circuit includes an eighteenth transistor;
所述第十一晶体管的控制极与第四控制信号输入端连接，所述第十一晶体管的第一极与所述预充信号输入端连接，所述第十一晶体管的第二极与所述上拉节点连接；The control pole of the eleventh transistor is connected to a fourth control signal input terminal, the first pole of the eleventh transistor is connected to the precharge signal input terminal, and the second pole of the eleventh transistor is connected to all Said pull-up node connection;
所述第十二晶体管的控制极与所述第四控制信号输入端连接，所述第十二晶体管的第一极与所述上拉节点连接，所述第十二晶体管的第二极与所述第十三晶体管的第一极连接；A control electrode of the twelfth transistor is connected to the fourth control signal input terminal, a first electrode of the twelfth transistor is connected to the pull-up node, and a second electrode of the twelfth transistor is connected to all The first pole connection of the thirteenth transistor;
所述第十三晶体管的控制极与所述复位信号输入端连接，所述第十三晶体管的第二极与所述第一工作电源端连接；A control electrode of the thirteenth transistor is connected to the reset signal input terminal, and a second electrode of the thirteenth transistor is connected to the first working power terminal;
所述第十四晶体管的控制极与所述第四控制信号输入端连接，所述第十四晶体管的第一极与所述第二工作电源端连接，所述第十四晶体管的第二极与所述下拉节点连接；A control pole of the fourteenth transistor is connected to the fourth control signal input terminal, a first pole of the fourteenth transistor is connected to the second working power terminal, and a second pole of the fourteenth transistor Connected to the pull-down node;
所述第十五晶体管的控制极与所述下拉节点连接，所述第十五晶体管的第一极与所述上拉节点连接，所述第十五晶体管的第二极与所述第一工作电源端连接；A control pole of the fifteenth transistor is connected to the pull-down node, a first pole of the fifteenth transistor is connected to the pull-up node, and a second pole of the fifteenth transistor is connected to the first operation. Power end connection;
所述第十六晶体管的控制极与所述上拉节点连接，所述第十六晶体管的第一极与所述下拉节点连接，所述第十六晶体管的第二极与所述第一工作电源端连接；The control pole of the sixteenth transistor is connected to the pull-up node, the first pole of the sixteenth transistor is connected to the pull-down node, and the second pole of the sixteenth transistor is connected to the first operation. Power end connection;
所述第十七晶体管的控制极与所述上拉节点连接，所述第十七晶体管的第一极与第五控制信号输入端连接，所述第十七晶体管的第二极与所述驱动信号输出端连接；A control pole of the seventeenth transistor is connected to the pull-up node, a first pole of the seventeenth transistor is connected to a fifth control signal input terminal, and a second pole of the seventeenth transistor is connected to the drive Signal output terminal connection;
所述第二电容的第一端与所述上拉节点连接，所述第二电容的第二端与所述驱动信号输出端连接；A first end of the second capacitor is connected to the pull-up node, and a second end of the second capacitor is connected to the driving signal output terminal;
所述第十八晶体管的控制极与所述下拉节点连接，所述第十八 晶体管的第一极与所述驱动信号输出端连接，所述第十八晶体管的第二极与所述第一工作电源端连接；The control electrode of the eighteenth transistor is connected to the pull-down node, the first electrode of the eighteenth transistor is connected to the driving signal output terminal, and the second electrode of the eighteenth transistor is connected to the first Work power connection
所述第十九晶体管的控制极与所述第五控制信号输入端连接，所述第十九晶体管的第一极与所述第二工作电源端连接，所述第十九晶体管的第二极与所述下拉节点连接。The control pole of the nineteenth transistor is connected to the fifth control signal input terminal, the first pole of the nineteenth transistor is connected to the second working power terminal, and the second pole of the nineteenth transistor Connected to the pull-down node.
根据本公开的实施例，所述驱动单元中的各晶体管为相同导电类型的晶体管。According to an embodiment of the present disclosure, each transistor in the driving unit is a transistor of the same conductivity type.
另一方面，本公开提供了一种栅极驱动电路，包括：级联的多个驱动单元，其中所述驱动单元采用根据本公开的驱动单元；In another aspect, the present disclosure provides a gate driving circuit including: a plurality of cascaded driving units, wherein the driving unit adopts a driving unit according to the present disclosure;
除第一级驱动单元外，其他各驱动单元的移位寄存器的驱动信号输出端与上一级驱动单元的移位寄存器的复位信号输入端连接；Except for the first-level driving unit, the driving signal output terminal of the shift register of each other driving unit is connected to the reset signal input terminal of the shift register of the previous-level driving unit;
除最后一级驱动单元外，其他各驱动单元的移位寄存器的驱动信号输出端与下一级驱动单元的移位寄存器的预充信号输入端连接。Except for the last stage driving unit, the driving signal output terminal of the shift register of each other driving unit is connected to the precharge signal input terminal of the shift register of the next stage driving unit.
另一方面，本公开提供了一种显示基板，包括：根据本公开的栅极驱动电路。In another aspect, the present disclosure provides a display substrate including a gate driving circuit according to the present disclosure.
另一方面，本公开提供了一种驱动方法，所述驱动方法用于驱动根据本公开的驱动单元，所述驱动方法包括：In another aspect, the present disclosure provides a driving method for driving a driving unit according to the present disclosure, the driving method including:
在所述第一子时间段内，通过第一控制子电路控制第一节点处的电压处于有效电平，通过第二控制子电路控制第二节点处的电压处于非有效电平，使得输出子电路通过第一信号输出端输出处于有效电平的电压；In the first sub-time period, the voltage at the first node is controlled by the first control sub-circuit to be at an active level, and the voltage at the second node is controlled by the second control sub-circuit at an inactive level, so that the output sub- The circuit outputs a voltage at an effective level through the first signal output terminal;
在所述第二子时间段内，通过第一控制子电路控制第一节点处的电压处于有效电平，通过第二控制子电路控制第二节点处的电压处于有效电平，使得输出子电路通过所述第一信号输出端输出处于非有效电平的电压；In the second sub-time period, the voltage at the first node is controlled by the first control sub-circuit to be at an effective level, and the voltage at the second node is controlled by the second control sub-circuit at the effective level, so that the output sub-circuit Outputting a voltage at an inactive level through the first signal output terminal;
在所述第三子时间段内，通过第一控制子电路控制第一节点处的电压处于有效电平，通过第二控制子电路控制第二节点处的电压处于非有效电平，使得所述输出子电路通过所述第一信号输出端输出处于有效电平的电压。In the third sub-time period, the voltage at the first node is controlled by the first control sub-circuit to be at an active level, and the voltage at the second node is controlled by the second control sub-circuit at an inactive level, so that the The output sub-circuit outputs a voltage at an effective level through the first signal output terminal.
根据本公开的实施例，在所述预设时间段内，所述上拉节点处 的电压处于有效电平，所述下拉节点处的电压处于非有效电平，所述驱动信号输出端处的电压处于有效电平。According to an embodiment of the present disclosure, during the preset time period, the voltage at the pull-up node is at an active level, the voltage at the pull-down node is at an inactive level, and the voltage at the output terminal of the driving signal is The voltage is at an active level.
根据本公开的实施例，所述移位寄存器的工作周期包括预充阶段、输出阶段和复位阶段，According to an embodiment of the present disclosure, a working cycle of the shift register includes a precharge phase, an output phase, and a reset phase,
在所述预充阶段，对所述上拉节点进行预充电；Pre-charging the pull-up node in the pre-charging stage;
在所述输出阶段，在上拉节点的电压的控制下，通过所述驱动信号输出端输出处于有效电平的电压；In the output stage, under the control of the voltage of the pull-up node, a voltage at an effective level is output through the driving signal output terminal;
在所述复位阶段，对上拉节点进行复位，控制下拉节点的电压处于有效电平，并经由所述驱动信号输出端输出处于非有效电平的电压In the reset stage, the pull-up node is reset, the voltage of the pull-down node is controlled to be at an active level, and a voltage at an inactive level is output via the driving signal output terminal.
其中，所述预设时间段在所述输出阶段内。The preset time period is within the output stage.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1为具有外部补偿功能的像素单元的电路结构示意图；FIG. 1 is a schematic diagram of a circuit structure of a pixel unit having an external compensation function; FIG.
图2为图1所示的像素单元的工作时序图；FIG. 2 is a working timing diagram of the pixel unit shown in FIG. 1;
图3a为根据本公开的实施例的移位寄存器的电路结构示意图；3a is a schematic circuit structure diagram of a shift register according to an embodiment of the present disclosure;
图3b为根据本公开的实施例的移位寄存器的工作时序图；3b is an operation timing diagram of a shift register according to an embodiment of the present disclosure;
图4a为根据本公开的实施例的移位寄存器的电路结构示意图；4a is a schematic circuit structure diagram of a shift register according to an embodiment of the present disclosure;
图4b为根据本公开的另一实施例的移位寄存器的电路结构示意图；4b is a schematic circuit structure diagram of a shift register according to another embodiment of the present disclosure;
图5为根据本公开的实施例的驱动单元的结构框图；5 is a structural block diagram of a driving unit according to an embodiment of the present disclosure;
图6为根据本公开的实施例的驱动单元的电路结构示意图；6 is a schematic circuit structure diagram of a driving unit according to an embodiment of the present disclosure;
图7为图6所示的驱动单元的工作时序图；7 is a working timing diagram of the driving unit shown in FIG. 6;
图8为根据本公开的另一实施例的驱动单元的电路结构示意图；8 is a schematic diagram of a circuit structure of a driving unit according to another embodiment of the present disclosure;
图9为根据本公开的实施例的栅极驱动电路的电路结构示意图；9 is a schematic circuit configuration diagram of a gate driving circuit according to an embodiment of the present disclosure;
图10为根据本公开的实施例的驱动方法的流程图。FIG. 10 is a flowchart of a driving method according to an embodiment of the present disclosure.
具体实施方式detailed description
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的驱动单元及其驱动方法、栅极驱动电路和显示 基板进行详细描述。In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the driving unit and the driving method thereof, the gate driving circuit, and the display substrate provided by the present disclosure are described in detail below with reference to the accompanying drawings.
在对OLED显示面板中的驱动晶体管或OLED的性能进行补偿时，通常采用为外部补偿的方式。外部补偿是指，通过感应电路将驱动晶体管或OLED处的电流读出来，利用读出的电信号，借助外部的集成电路芯片实施复杂的算法，可以对驱动晶体管的阈值电压和迁移率的非均匀性、以及OLED的老化等进行补偿。When compensating the performance of a driving transistor or an OLED in an OLED display panel, an external compensation method is usually adopted. External compensation refers to reading the current at the driving transistor or OLED through an induction circuit, using the read electrical signal, and implementing a complex algorithm with the help of an external integrated circuit chip, which can non-uniformly drive the threshold voltage and mobility of the driving transistor. And the aging of the OLED.
在感测驱动晶体管或OLED的属性的过程中(即，感测阶段)，需要向像素单元中的感测晶体管的控制极提供一个双脉冲信号。然而，由于常规的栅极驱动电路(Gate Driver on Array，简称GOA)中的各级移位寄存器通常只能输出单脉冲信号，而不能输出双脉冲信号，因此常规的GOA电路无法满足感测晶体管在感测阶段的驱动需求。此时，可以通过栅极驱动芯片输出双脉冲信号，以对感测晶体管进行驱动。但是，由于栅极驱动芯片尺寸较大，不利于显示基板的窄边框设计。During the process of sensing the attributes of the driving transistor or the OLED (ie, the sensing stage), a double pulse signal needs to be provided to the control electrode of the sensing transistor in the pixel unit. However, since the shift registers of various levels in a conventional gate driver circuit (GOA) can only output single-pulse signals and cannot output double-pulse signals, the conventional GOA circuit cannot satisfy the sensing transistor. Driving requirements during the sensing phase. At this time, a double-pulse signal can be output through the gate driving chip to drive the sensing transistor. However, due to the large size of the gate drive chip, it is not conducive to the narrow frame design of the display substrate.
在本公开中，“有效电平”是指能控制相应晶体管导通的电压，“非有效电平”是指能控制相应晶体管截止的电压。例如，当晶体管为N型晶体管时，有效电平为高电平，非有效电平为低电平。例如，当晶体管为P型晶体管时，有效电平为低电平，非有效电平为高电平。在下面描述中，以各晶体管为N型晶体管为例进行示例性描述。In the present disclosure, “active level” refers to a voltage that can control the corresponding transistor to be turned on, and “inactive level” refers to a voltage that can control the corresponding transistor to be turned off. For example, when the transistor is an N-type transistor, the active level is high and the inactive level is low. For example, when the transistor is a P-type transistor, the active level is low and the inactive level is high. In the following description, an example is described in which each transistor is an N-type transistor.
图1为具有外部补偿功能的像素单元的电路结构示意图。如图1所示，该像素单元包括开关晶体管TFT、驱动晶体管DTFT、感测晶体管STFT、有机发光二极管OLED和电容。开关晶体管TFT的控制极与第一栅线G1连接，第一极与数据线Data连接，第二极与驱动晶体管DTFT的控制极连接；驱动晶体管DTFT的第一极与电源输入端VDD连接，第二极与有机发光二极管OLED的阳极连接；感测晶体管STFT的控制极与第二栅线G2连接，第一极与信号读取线Sense连接，第二极与有机发光二极管OLED的阳极连接；电容的一端与驱动晶体管DTFT的控制极连接，另一端与驱动晶体管DTFT的第二极连接；有机发光二极管OLED的阴极接地。FIG. 1 is a schematic diagram of a circuit structure of a pixel unit having an external compensation function. As shown in FIG. 1, the pixel unit includes a switching transistor TFT, a driving transistor DTFT, a sensing transistor STFT, an organic light emitting diode OLED, and a capacitor. The control electrode of the switching transistor TFT is connected to the first gate line G1, the first electrode is connected to the data line Data, and the second electrode is connected to the control electrode of the driving transistor DTFT. The first electrode of the driving transistor DTFT is connected to the power input terminal VDD. The second electrode is connected to the anode of the organic light emitting diode OLED; the control electrode of the sensing transistor STFT is connected to the second gate line G2, the first electrode is connected to the signal reading line Sense, and the second electrode is connected to the anode of the organic light emitting diode OLED; the capacitor One end is connected to the control electrode of the driving transistor DTFT, and the other end is connected to the second electrode of the driving transistor DTFT; the cathode of the organic light emitting diode OLED is grounded.
图2为图1所示的像素单元的工作时序图。如图2所示，该像 素单元的工作过程包括以下两个阶段：显示驱动阶段和稳定显示阶段，其中，在稳定显示阶段内截取一段时间作为感测阶段，并在该感测阶段内感测驱动晶体管DTFT或OLED的属性。该感测阶段可以包括以下几个阶段：重置阶段s1、累积阶段s2、信号读取阶段s3和重置阶段s4。FIG. 2 is an operation timing diagram of the pixel unit shown in FIG. 1. As shown in FIG. 2, the working process of the pixel unit includes the following two phases: a display driving phase and a stable display phase, in which a period of time is taken as a sensing phase during the stable display phase, and the sensing is performed during the sensing phase. Properties of the driving transistor DTFT or OLED. The sensing phase may include the following phases: a reset phase s1, an accumulation phase s2, a signal reading phase s3, and a reset phase s4.
在重置阶段s1内，第一栅线G1和第二栅线G2提供有效电平，感测晶体管STFT和开关晶体管TFT导通，通过信号读取线Sense和感测晶体管STFT将重置信号写入点P，通过数据线Data和开关晶体管TFT将测试电压Vsense写入驱动晶体管DTFT的控制极。In the reset phase s1, the first gate line G1 and the second gate line G2 provide an effective level, the sensing transistor STFT and the switching transistor TFT are turned on, and the reset signal is written by the signal reading line Sense and the sensing transistor STFT. At point P, the test voltage Vsense is written into the control electrode of the driving transistor DTFT through the data line Data and the switching transistor TFT.
在累积阶段s2内，第二栅线G2提供非有效电平，感测晶体管STFT截止，通过驱动晶体管DTFT输出的电流对点P进行充电，使得点P的电压上升，直至点P的电压达到Vsense-Vth，其中Vth为驱动晶体管DTFT的阈值电压。当点P的电压达到Vsense-Vth时，驱动晶体管DTFT截止。In the accumulation phase s2, the second gate line G2 provides an inactive level, the sensing transistor STFT is turned off, and the point P is charged by the current output from the driving transistor DTFT, so that the voltage at the point P rises until the voltage at the point P reaches Vsense -Vth, where Vth is the threshold voltage of the driving transistor DTFT. When the voltage at the point P reaches Vsense-Vth, the driving transistor DTFT is turned off.
在信号读取阶段s3内，第二栅线G2提供有效电平，感测晶体管STFT再次导通，通过信号读取线Sense测得点P的电压为Vsense-Vth。在Vsense已知的情况下，通过点P的电压Vsense-Vth即可得到驱动晶体管DTFT的阈值电压Vth。In the signal reading phase s3, the second gate line G2 provides an effective level, the sensing transistor STFT is turned on again, and the voltage at the point P measured by the signal reading line Sense is Vsense-Vth. When Vsense is known, the threshold voltage Vth of the driving transistor DTFT can be obtained by the voltage Vsense-Vth at the point P.
在重置阶段s4内，第二栅线G2提供有效电平，通过信号读取线Sense和感测晶体管STFT再次将重置信号写入点P。In the reset phase s4, the second gate line G2 provides an active level, and the reset signal is written into the point P again through the signal read line Sense and the sensing transistor STFT.
在整个感测阶段内，开关晶体管TFT均处于开启状态，即在整个感测阶段内，与开关晶体管TFT的控制极所连接的第一栅线G1提供的信号处于有效电平。感测晶体管STFT在重置阶段s1、信号读取阶段s3和重置阶段s4内处于开启状态，在累积阶段s2处于截止状态，即在重置阶段s1、信号读取阶段s3和重置阶段s4内，与感测晶体管STFT的控制极所连接的第二栅线G2提供的信号处于有效电平，而在累积阶段s2内，第二栅线G2提供的信号处于非有效电平。由此可见，在整个感测阶段内，需要为第二栅线G2(或者，感测晶体管STFT的控制极)提供一个双脉冲信号，其中，第一个脉冲对应重置阶段s1，第二个脉冲对应信号读取阶段s3和重置阶段s4。During the entire sensing stage, the switching transistor TFT is in an on state, that is, during the entire sensing stage, the signal provided by the first gate line G1 connected to the control electrode of the switching transistor TFT is at an effective level. The sensing transistor STFT is on during the reset phase s1, the signal read phase s3, and the reset phase s4, and is turned off during the accumulation phase s2, that is, during the reset phase s1, the signal read phase s3, and the reset phase s4. The signal provided by the second gate line G2 connected to the control electrode of the sensing transistor STFT is at an active level, and the signal provided by the second gate line G2 is at an inactive level during the accumulation phase s2. It can be seen that during the entire sensing phase, a double pulse signal needs to be provided for the second gate line G2 (or the control electrode of the sensing transistor STFT), where the first pulse corresponds to the reset phase s1 and the second The pulse corresponds to the signal reading phase s3 and the reset phase s4.
如上所述，由于常规GOA电路的各级移位寄存器仅能输出单脉冲信号，因此无法满足第二栅线G2在感测阶段的驱动需求。在采用栅极驱动芯片进行驱动时，虽能满足第二栅线G2在感测阶段的驱动需求，但由于栅极驱动芯片的尺寸较大，不利于显示基板的窄边框设计。As described above, since the shift registers of the various stages of the conventional GOA circuit can only output a single pulse signal, the driving requirements of the second gate line G2 in the sensing stage cannot be met. When the gate driving chip is used for driving, although the driving requirement of the second gate line G2 in the sensing stage can be satisfied, the size of the gate driving chip is not suitable for the narrow frame design of the display substrate.
因此，本公开提供了一种驱动单元及其驱动方法、栅极驱动电路和显示基板，其基本避免了由于现有技术的局限和缺点而导致的问题中的一个或多个。Therefore, the present disclosure provides a driving unit and a driving method thereof, a gate driving circuit, and a display substrate, which substantially avoid one or more of the problems due to the limitations and disadvantages of the prior art.
在根据本公开的驱动单元中，将移位寄存器内的上拉节点处的信号、下拉节点处的信号、驱动信号输出端输出的信号作为控制信号，输出双脉冲驱动信号，从而能够在感测阶段内对像素单元中的第二栅线G2进行驱动。In the driving unit according to the present disclosure, a signal at a pull-up node, a signal at a pull-down node, and a signal output from a driving signal output terminal in a shift register are used as control signals to output a double-pulse driving signal, so that it can be sensed The second gate line G2 in the pixel unit is driven in a stage.
根据本公开的一个方面，提供了一种驱动单元。图5为根据本公开的实施例的驱动单元的电路结构示意图。如图5所示，该驱动单元包括移位寄存器SR和第一输出电路。According to an aspect of the present disclosure, a driving unit is provided. FIG. 5 is a schematic diagram of a circuit structure of a driving unit according to an embodiment of the present disclosure. As shown in FIG. 5, the driving unit includes a shift register SR and a first output circuit.
图3a为根据本公开的实施例的移位寄存器SR的结构框图，图3b为根据本公开的实施例的移位寄存器SR的工作时序图。如图3a所示，该移位寄存器SR包括预充复位电路、上拉电路、下拉控制电路、下拉电路。预充复位电路分别与预充信号输入端INPUT和复位信号输入端RESET连接并与上拉电路连接于上拉节点PU，下拉控制电路和下拉电路连接于下拉节点PD，上拉电路和下拉电路连接于驱动信号输出端Cout。FIG. 3a is a structural block diagram of a shift register SR according to an embodiment of the present disclosure, and FIG. 3b is an operation timing diagram of the shift register SR according to an embodiment of the present disclosure. As shown in FIG. 3a, the shift register SR includes a precharge reset circuit, a pull-up circuit, a pull-down control circuit, and a pull-down circuit. The precharge reset circuit is respectively connected to the precharge signal input terminal INPUT and the reset signal input terminal RESET and connected to the pull-up circuit to the pull-up node PU. The pull-down control circuit and the pull-down circuit are connected to the pull-down node PD. The pull-up circuit and the pull-down circuit are connected. At the driving signal output terminal Cout.
该移位寄存器的工作周期主要包括以下三个阶段：预充阶段、输出阶段和复位阶段。The working cycle of the shift register mainly includes the following three phases: a precharge phase, an output phase, and a reset phase.
在预充阶段内，在通过预充信号输入端INPUT所提供的写入信号的控制下，通过预充复位电路对上拉节点PU进行预充电，以为后续的输出阶段做准备。In the precharge stage, under the control of the write signal provided by the precharge signal input terminal INPUT, the pull-up node PU is precharged by a precharge reset circuit to prepare for the subsequent output stage.
在输出阶段内，在上拉节点PU的电压的控制下，通过上拉电路向驱动信号输出端Cout输出处于有效电平的电压，即输出一个单脉冲。In the output stage, under the control of the voltage of the pull-up node PU, a voltage at an effective level is output to the driving signal output terminal Cout through the pull-up circuit, that is, a single pulse is output.
在复位阶段内，在通过复位信号输入端RESET所提供的复位信号的控制下，通过预充复位电路对上拉节点PU进行复位处理，以使得上拉电路停止工作。同时，通过下拉控制电路控制下拉节点PD的电压处于有效电平，下拉电路在下拉节点PD的电压的控制下，向驱动信号输出端Cout输出非有效电平的电压，从而达到复位的目的。During the reset phase, under the control of the reset signal provided by the reset signal input terminal RESET, the pull-up node PU is reset by a precharge reset circuit, so that the pull-up circuit stops working. At the same time, the pull-down control circuit controls the voltage of the pull-down node PD to be at an active level. Under the control of the voltage of the pull-down node PD, the pull-down circuit outputs a non-active level voltage to the driving signal output terminal Cout, thereby achieving the purpose of resetting.
此外，在复位阶段结束后，移位寄存器会处于等待阶段(直至下一周期的预充阶段到来)。在等待阶段中，上拉节点PU的电压维持非有效电平，下拉节点PD的电压维持有效电平，以使得驱动信号输出端Cout保持输出非有效电平的电压。In addition, after the reset phase ends, the shift register will be in a wait phase (until the pre-charge phase of the next cycle arrives). In the waiting phase, the voltage of the pull-up node PU maintains an inactive level, and the voltage of the pull-down node PD maintains an active level, so that the driving signal output terminal Cout keeps outputting a voltage of an inactive level.
图4a为根据本公开的实施例的移位寄存器的电路结构示意图，图4b为根据本公开的另一实施例的移位寄存器的电路结构示意图。FIG. 4a is a schematic diagram of a circuit structure of a shift register according to an embodiment of the present disclosure, and FIG. 4b is a schematic diagram of a circuit structure of a shift register according to another embodiment of the present disclosure.
如图4a所示，该移位寄存器具有8T1C(8个晶体管M1～M8和1个电容C1)的电路结构，其中预充复位电路对应晶体管M1～M3，上拉电路对应晶体管M7和电容C1，下拉控制电路对应晶体管M4～M6，下拉电路对应晶体管M8。As shown in FIG. 4a, the shift register has a circuit structure of 8T1C (eight transistors M1 to M8 and one capacitor C1), where the precharge reset circuit corresponds to transistors M1 to M3, and the pull-up circuit corresponds to transistor M7 and capacitor C1. The pull-down control circuit corresponds to the transistors M4 to M6, and the pull-down circuit corresponds to the transistor M8.
如图4a所示，预充复位电路包括第十一晶体管M1、第十二晶体管M2和第十三晶体管M3；上拉电路包括第十七晶体管M7、第二电容C1；下拉控制电路包括第十四晶体M4、第十五晶体管M5和第十六晶体管M6；下拉电路包括第十八晶体管M8。第十一晶体M1的控制极与第四控制信号输入端CLK4连接，第一极与预充信号输入端INPUT连接，第二极与上拉节点PU连接。第十二晶体管M2的控制极与第四控制信号输入端CLK4连接，第一极与上拉节点PU连接，第二极与第十三晶体M3管的第一极连接。第十三晶体管M3的控制极与复位信号输入端RESET连接，第二极与第一工作电源端VGL连接，其中，通过第一工作电源端VGL提供处于非有效电平的第一工作电压。第十四晶体管M4的控制极和第一极分别与第二工作电源端VGH连接，第二极与下拉节点PD连接，其中，通过第二工作电源端VGH提供处于有效电平的第二工作电压。第十五晶体管M5的控制极与下拉节点PD连接，第一极与上拉节点PU连接，第二极与第一工作电源端VGL连接。第十六晶体管M6的控制极与上拉节点PU连接，第一极与下拉节点PD 连接，第二极与第一工作电源端VGL连接。第十七晶体管M7的控制极与上拉节点PU连接，第一极与第五控制信号输入端CLK5连接，第二极与驱动信号输出端Cout连接。第二电容C1的一端与上拉节点PU连接，第二端与驱动信号输出端Cout连接。第十八晶体管M8的控制极与下拉节点PD连接，第一极与驱动信号输出端Cout连接，第二极与第一工作电源端VGL连接。As shown in FIG. 4a, the precharge reset circuit includes an eleventh transistor M1, a twelfth transistor M2, and a thirteenth transistor M3; a pull-up circuit includes a seventeenth transistor M7 and a second capacitor C1; a pull-down control circuit includes a tenth The four crystal M4, the fifteenth transistor M5, and the sixteenth transistor M6; the pull-down circuit includes an eighteenth transistor M8. The control pole of the eleventh crystal M1 is connected to the fourth control signal input terminal CLK4, the first pole is connected to the precharge signal input terminal INPUT, and the second pole is connected to the pull-up node PU. The control electrode of the twelfth transistor M2 is connected to the fourth control signal input terminal CLK4, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the first electrode of the thirteenth transistor M3. The control electrode of the thirteenth transistor M3 is connected to the reset signal input terminal RESET, and the second electrode is connected to the first working power terminal VGL, wherein the first working voltage at the inactive level is provided through the first working power terminal VGL. The control electrode and the first electrode of the fourteenth transistor M4 are respectively connected to the second working power terminal VGH, and the second electrode is connected to the pull-down node PD, wherein the second working voltage at the effective level is provided through the second working power terminal VGH. . The control electrode of the fifteenth transistor M5 is connected to the pull-down node PD, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the first working power terminal VGL. The control electrode of the sixteenth transistor M6 is connected to the pull-up node PU, the first electrode is connected to the pull-down node PD, and the second electrode is connected to the first working power terminal VGL. The control pole of the seventeenth transistor M7 is connected to the pull-up node PU, the first pole is connected to the fifth control signal input terminal CLK5, and the second pole is connected to the drive signal output terminal Cout. One end of the second capacitor C1 is connected to the pull-up node PU, and the second end is connected to the driving signal output terminal Cout. The control electrode of the eighteenth transistor M8 is connected to the pull-down node PD, the first electrode is connected to the driving signal output terminal Cout, and the second electrode is connected to the first working power terminal VGL.
图4b所示的移位寄存器具有9T1C(9个晶体管M1～M9和1个电容C1)的电路结构，其中预充复位电路对应晶体管M1～M3，上拉电路对应晶体管M7和电容C1，下拉控制电路对应晶体管M4～M6、M9，下拉电路对应晶体管M8。与图4a所示的电路相比，图4b所示的移位寄存器中的下拉控制电路还包括第十九晶体管M9。第十九晶体管M9的控制极与第五控制信号输入端CLK5连接，第一极与第二工作电源端VGH连接，第二极与下拉节点PD连接。此外，如图4b所示，第十四晶体管M4的控制极与第四控制信号输入端CLK4连接。在一些实施例中，第四控制信号输入端CLK4和第五控制信号输入端CLK5分别与对应的时钟信号线连接，即将时钟信号作为控制信号。图4a和图4b所示的电路的工作过程与图3相同，此处不再进行详细描述。The shift register shown in FIG. 4b has a circuit structure of 9T1C (9 transistors M1 to M9 and 1 capacitor C1), in which the precharge reset circuit corresponds to transistors M1 to M3, the pull-up circuit corresponds to transistor M7 and capacitor C1, and pull-down control The circuit corresponds to the transistors M4 to M6 and M9, and the pull-down circuit corresponds to the transistor M8. Compared with the circuit shown in FIG. 4a, the pull-down control circuit in the shift register shown in FIG. 4b further includes a nineteenth transistor M9. The control pole of the nineteenth transistor M9 is connected to the fifth control signal input terminal CLK5, the first pole is connected to the second working power terminal VGH, and the second pole is connected to the pull-down node PD. In addition, as shown in FIG. 4b, the control electrode of the fourteenth transistor M4 is connected to the fourth control signal input terminal CLK4. In some embodiments, the fourth control signal input terminal CLK4 and the fifth control signal input terminal CLK5 are respectively connected to corresponding clock signal lines, that is, the clock signal is used as a control signal. The working process of the circuit shown in FIG. 4a and FIG. 4b is the same as that of FIG. 3, and will not be described in detail here.
需要说明的是，图4a和图4b所示的移位寄存器的电路结构仅起到示例性作用，其不会对本公开产生限制。本领域技术人员应该知晓的是，但凡是采用上述工作过程(预充阶段、输出阶段和复位阶段)的移位寄存器均属于本公开的保护范围，此处不再一一举例说明。It should be noted that the circuit structure of the shift register shown in FIG. 4a and FIG. 4b only serves as an example, which does not limit the present disclosure. Those skilled in the art should know that any shift register that adopts the above working process (pre-charge stage, output stage, and reset stage) belongs to the protection scope of the present disclosure, and no further examples are given here.
返回参考图5，第一输出电路包括：第一控制子电路1、第二控制子电路2和输出子电路3；第一控制子电路1和输出子电路3连接于第一节点Q1，第一控制子电路1、第二控制子电路2和输出子电路3连接于第二节点Q2。Referring back to FIG. 5, the first output circuit includes: a first control sub-circuit 1, a second control sub-circuit 2 and an output sub-circuit 3; the first control sub-circuit 1 and the output sub-circuit 3 are connected to the first node Q1, and the first The control sub-circuit 1, the second control sub-circuit 2 and the output sub-circuit 3 are connected to the second node Q2.
第一控制子电路1与移位寄存器SR的上拉节点PU、移位寄存器SR的下拉节点PD、第二节点Q2连接，用于在拉节点PU的电压、下拉节点PD的电压、第二节点Q2的电压的控制下，在移位寄存器SR的输出阶段内的预设时间段内控制第一节点Q1处的电压处于有效电平；其中，预设时间段包括：连续设置的第一子时间段、第二子时间 段和第三子时间段。需要说明的是，预设时间段对应于前述感测阶段，第一子时间段对应于图2中的重置阶段s1，第二子时间段对应于图2中的累积阶段s2，第三子时间段对应于图2中的信号读取阶段s3和重置阶段s4。具体时长可根据实际需要进行设定和调整。The first control sub-circuit 1 is connected to the pull-up node PU of the shift register SR, the pull-down node PD of the shift register SR, and the second node Q2, and is used for the voltage of the pull-node PU, the voltage of the pull-down node PD, and the second node Under the control of the voltage of Q2, the voltage at the first node Q1 is controlled to be at an active level within a preset time period in the output stage of the shift register SR; wherein the preset time period includes: a first sub-time set continuously Period, second sub-period, and third sub-period. It should be noted that the preset time period corresponds to the aforementioned sensing phase, the first sub time period corresponds to the reset phase s1 in FIG. 2, the second sub time period corresponds to the accumulation phase s2 in FIG. 2, and the third sub time period The time period corresponds to the signal reading phase s3 and the reset phase s4 in FIG. 2. The specific duration can be set and adjusted according to actual needs.
第二控制子电路2与移位寄存器SR的下拉节点PD、移位寄存器SR的驱动信号输出端Cout连接，用于在下拉节点PD的电压、驱动信号输出端Cout提供的电压的控制，在第一子时间段和第三子时间段内控制第二节点Q2处的电压处于非有效电平，以及在第二子时间段内控制第二节点Q2处的电压处于有效电平。The second control sub-circuit 2 is connected to the pull-down node PD of the shift register SR and the drive signal output terminal Cout of the shift register SR, and is used for controlling the voltage of the pull-down node PD and the voltage provided by the drive signal output terminal Cout. The voltage at the second node Q2 is controlled to be at an inactive level during one sub-time period and the third sub-time period, and the voltage at the second node Q2 is controlled to be at an active level during the second sub-time period.
输出子电路3与第一节点Q1、第二节点Q2、第一信号输出端Gout1连接，用于在第一节点Q1的电压和第二节点Q2的电压的控制下，在第一节点Q1的电压处于有效电平且第二节点Q2的电压处于非有效电平时，通过第一信号输出端Gout1输出处于有效电平的电压，以及在第二节点Q2的电压处于有效电平时通过第一信号输出端Gout1输出处于非有效电平的电压。The output sub-circuit 3 is connected to the first node Q1, the second node Q2, and the first signal output terminal Gout1, and is used to control the voltage of the first node Q1 under the control of the voltage of the first node Q1 and the voltage of the second node Q2. When the voltage at the second node Q2 is at an inactive level, the voltage at the active level is output through the first signal output terminal Gout1, and the voltage at the second node Q2 is at the active level through the first signal output terminal. Gout1 outputs a voltage at an inactive level.
根据本公开的驱动单元在预设时间段的工作过程包括三个子时间段。在第一子时间段内，第一节点Q1的电压处于有效电平，第二节点Q2的电压处于非有效电平，输出子电路3通过第一信号输出端Gout1输出处于有效电平的电压，即输出第一个脉冲；在第二子时间段内，第一节点Q1的电压处于有效电平，第二节点Q2的电压处于有效电平，输出子电路3通过第一信号输出端Gout1输出处于非有效电平的电压；在第三子时间段内，第一节点Q1的电压处于有效电平，第二节点Q2的电压处于非有效电平，输出子电路3通过第一信号输出端Gout1输出处于有效电平的电压，即输出第二个脉冲。由此可见，本公开提供的驱动单元可在预设时间段内输出一个双脉冲信号，从而能够在感测阶段对像素单元中的第二栅线进行驱动，有利于窄边框的实现。The working process of the driving unit according to the present disclosure in a preset time period includes three sub-time periods. During the first sub-period, the voltage at the first node Q1 is at an active level, and the voltage at the second node Q2 is at an inactive level. The output sub-circuit 3 outputs a voltage at an effective level through the first signal output terminal Gout1. That is, the first pulse is output; in the second sub-period, the voltage of the first node Q1 is at an effective level, and the voltage of the second node Q2 is at an effective level. The output sub-circuit 3 outputs the signal at the first signal output terminal Gout1 at Voltage of non-active level; in the third sub-period, the voltage of the first node Q1 is at the active level, and the voltage of the second node Q2 is at the non-active level, the output sub-circuit 3 outputs through the first signal output terminal Gout1 At the active level, the second pulse is output. It can be seen that the driving unit provided in the present disclosure can output a double pulse signal within a preset period of time, so that the second grid line in the pixel unit can be driven during the sensing stage, which is beneficial to the realization of a narrow frame.
图6为根据本公开的实施例的驱动单元的电路结构示意图，示出了图5所示驱动单元的一种实施方式。FIG. 6 is a schematic diagram of a circuit structure of a driving unit according to an embodiment of the present disclosure, and illustrates an embodiment of the driving unit shown in FIG. 5.
在一些实施例中，第一控制子电路1通过第一控制信号输入端 CLK1与第一时钟信号线连接(即将通过第一时钟信号线提供的第一时钟信号作为控制信号)，并且第一控制子电路1还通过第一工作电源端VGL输入第一工作电压。第一控制子电路1用于：在上拉节点PU的电压的控制下，在移位寄存器SR的预充阶段和输出阶段内，将通过第一时钟信号线提供的第一时钟信号写入第一节点Q1，第一时钟信号在预设时间段内处于有效电平；在下拉节点PD的电压的控制下，在移位寄存器SR的复位阶段内，将通过第一工作电源端提供的第一工作电压写入第一节点Q1；以及在第二节点Q2的电压的控制下，在第二节点Q2的电压处于有效电平时，将第一工作电压写入第一节点Q1。其中，通过第一工作电源端VGL提供处于非有效电平的第一工作电压。In some embodiments, the first control sub-circuit 1 is connected to the first clock signal line through the first control signal input terminal CLK1 (that is, the first clock signal provided through the first clock signal line is used as the control signal), and the first control The sub-circuit 1 also inputs a first working voltage through the first working power supply terminal VGL. The first control sub-circuit 1 is used to write the first clock signal provided through the first clock signal line into the first clock signal under the control of the voltage of the pull-up node PU during the pre-charge phase and the output phase of the shift register SR. At a node Q1, the first clock signal is at an active level within a preset period of time; under the control of the voltage of the pull-down node PD, during the reset stage of the shift register SR, the first The working voltage is written into the first node Q1; and under the control of the voltage of the second node Q2, when the voltage of the second node Q2 is at an effective level, the first working voltage is written into the first node Q1. The first working voltage terminal VGL provides a first working voltage at an inactive level.
在一些实施例中，如图6所示，第一控制子电路1包括第一晶体管T1、第二晶体管T2、第三晶体管T3。第一晶体管T1的控制极与上拉节点PU连接，第一晶体管T1的第一极与第一控制信号输入端CLK1连接，第一晶体管T1的第二极与第一节点Q1连接。第二晶体管T2的控制极与下拉节点PD连接，第二晶体管T2的第一极与第一节点Q1连接，第二晶体管T2的第二极与第一工作电源端VGL连接。第三晶体管T3的控制极与第二节点Q2连接，第三晶体管T3的第一极与第一节点Q1连接，第三晶体管T3的第二极与第一工作电源端VGL连接。In some embodiments, as shown in FIG. 6, the first control sub-circuit 1 includes a first transistor T1, a second transistor T2, and a third transistor T3. The control pole of the first transistor T1 is connected to the pull-up node PU, the first pole of the first transistor T1 is connected to the first control signal input terminal CLK1, and the second pole of the first transistor T1 is connected to the first node Q1. The control electrode of the second transistor T2 is connected to the pull-down node PD, the first electrode of the second transistor T2 is connected to the first node Q1, and the second electrode of the second transistor T2 is connected to the first working power terminal VGL. The control electrode of the third transistor T3 is connected to the second node Q2, the first electrode of the third transistor T3 is connected to the first node Q1, and the second electrode of the third transistor T3 is connected to the first working power terminal VGL.
在一些实施例中，第二控制子电路2通过第二控制信号输入端CLK2与第二时钟信号线连接(即将通过第二时钟信号线提供的第二时钟信号作为控制信号)，并且第二控制子电路2还通过第二工作电源端VGH输入第二工作电压。第二控制子电路2用于：在下拉节点PD的电压的控制下，在移位寄存器SR的复位阶段内，将通过第二工作电源端提供的第二工作电压写入第二节点Q2；在驱动信号输出端Cout所提供的电压的控制下，在移位寄存器SR的输出阶段内，将通过第二控制信号输入端CLK2提供的第二时钟信号输出至第二节点Q2，第二时钟信号在第一子时间段和第三子时间段内处于非有效电平，第二时钟信号在第二子时间段内处于有效电平。通过第二工作电源端 VGH提供处于有效电平的第二工作电压。In some embodiments, the second control sub-circuit 2 is connected to the second clock signal line through the second control signal input terminal CLK2 (that is, the second clock signal provided through the second clock signal line is used as the control signal), and the second control The sub-circuit 2 also inputs a second working voltage through the second working power terminal VGH. The second control sub-circuit 2 is used to: under the control of the voltage of the pull-down node PD, write the second working voltage provided by the second working power terminal to the second node Q2 during the reset phase of the shift register SR; Under the control of the voltage provided by the driving signal output terminal Cout, during the output stage of the shift register SR, the second clock signal provided through the second control signal input terminal CLK2 is output to the second node Q2. The first sub-time period and the third sub-time period are at an inactive level, and the second clock signal is at an active level during the second sub-time period. The second working power terminal VGH provides a second working voltage at an active level.
在一些实施例中，如图6所示，第二控制子电路2包括第四晶体管T4、第五晶体管T5。第四晶体管T4的控制极与下拉节点PD连接，第四晶体管T4的第一极与第二工作电源端VGH连接，第四晶体管T4的第二极与第二节点Q2连接。第五晶体管T5的控制极与驱动信号输出端Cout连接，第五晶体管T5的第一极与第二节点Q2连接，第五晶体管T5的第二极与第二控制信号输入端CLK2连接。In some embodiments, as shown in FIG. 6, the second control sub-circuit 2 includes a fourth transistor T4 and a fifth transistor T5. The control electrode of the fourth transistor T4 is connected to the pull-down node PD, the first electrode of the fourth transistor T4 is connected to the second working power terminal VGH, and the second electrode of the fourth transistor T4 is connected to the second node Q2. The control electrode of the fifth transistor T5 is connected to the driving signal output terminal Cout, the first electrode of the fifth transistor T5 is connected to the second node Q2, and the second electrode of the fifth transistor T5 is connected to the second control signal input terminal CLK2.
在一些实施例中，输出子电路3还通过第三控制信号输入端输入控制信号，并且与第一工作电源端连接。输出子电路3用于：在第一节点Q1的电压的控制下，在第一子时间段和第三子时间段内，将第三控制信号输入端提供的处于有效电平的电压写入第一信号输出端Gout1；在第二节点Q2的电压的控制下，在第二子时间段内，将通过第一工作电源端提供的第一工作电压写入第一信号输出端Gout1。In some embodiments, the output sub-circuit 3 further inputs a control signal through a third control signal input terminal, and is connected to the first working power terminal. The output sub-circuit 3 is used to write the voltage at the effective level provided by the third control signal input terminal into the first sub-period under the control of the voltage of the first node Q1 in the first sub-time period and the third sub-time period. A signal output terminal Gout1; under the control of the voltage of the second node Q2, in a second sub-period, write the first working voltage provided by the first working power terminal into the first signal output terminal Gout1.
在一些实施例中，如图6所示，输出子电路3包括第六晶体管T6、第七晶体管T7、第八晶体管T8和第一电容C。第六晶体管T6的控制极与第一控制信号输入端CLK1连接，第六晶体管T6的第一极与第二工作电源端VGH连接，第六晶体管T6的第二极与第一节点Q1连接。第七晶体管T7的控制极与第一节点Q1连接，第七晶体管T7的第一极与第二工作电源端VGH连接，第七晶体管T7的第二极与第一信号输出端Gout1连接。第八晶体管T8的控制极与第二节点Q2连接，第八晶体管T8的第一极与第一信号输出端Gout1连接，第八晶体管T8的第二极与第一工作电源端VGL连接。第一电容C的第一端与第一节点Q1连接，第一电容C的第二端与第一信号输出端Gout1连接。通过第一控制信号输入端CLK1提供的控制信号在预设时间段内处于有效电平。在本公开中，电容C可保证第一信号输出端Gout1的稳定输出。In some embodiments, as shown in FIG. 6, the output sub-circuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a first capacitor C. The control electrode of the sixth transistor T6 is connected to the first control signal input terminal CLK1, the first electrode of the sixth transistor T6 is connected to the second working power terminal VGH, and the second electrode of the sixth transistor T6 is connected to the first node Q1. The control electrode of the seventh transistor T7 is connected to the first node Q1, the first electrode of the seventh transistor T7 is connected to the second working power terminal VGH, and the second electrode of the seventh transistor T7 is connected to the first signal output terminal Gout1. The control electrode of the eighth transistor T8 is connected to the second node Q2, the first electrode of the eighth transistor T8 is connected to the first signal output terminal Gout1, and the second electrode of the eighth transistor T8 is connected to the first operating power terminal VGL. The first terminal of the first capacitor C is connected to the first node Q1, and the second terminal of the first capacitor C is connected to the first signal output terminal Gout1. The control signal provided through the first control signal input terminal CLK1 is at an active level within a preset time period. In the present disclosure, the capacitor C can ensure a stable output of the first signal output terminal Gout1.
图8为根据本公开的另一实施例的驱动单元的电路图。图8所示的驱动单元与图6所示的驱动单元的区别在于第六晶体管T6和第七晶体管T7的连接方式。本实施例中的第六晶体管T6的控制极和第 一极分别与第三控制信号输入端CLK3连接，第六晶体管的第二极与第一节点Q1连接。通过第三控制信号输入端CLK3输入的控制信号可以通过第一控制信号输入端CLK1输入的控制信号相同。这样就可以使得本实施例中的第六晶体管T6和第七晶体管T7不再一直受正压影响，从而能提高电路的信赖性。FIG. 8 is a circuit diagram of a driving unit according to another embodiment of the present disclosure. The difference between the driving unit shown in FIG. 8 and the driving unit shown in FIG. 6 is the connection manner of the sixth transistor T6 and the seventh transistor T7. The control electrode and the first electrode of the sixth transistor T6 in this embodiment are respectively connected to the third control signal input terminal CLK3, and the second electrode of the sixth transistor is connected to the first node Q1. The control signal input through the third control signal input terminal CLK3 can be the same as the control signal input through the first control signal input terminal CLK1. In this way, the sixth transistor T6 and the seventh transistor T7 in this embodiment can no longer be always affected by the positive voltage, thereby improving the reliability of the circuit.
在一些实施例中，第一控制信号输入端CLK1、第二控制信号输入端CLK2、第三控制信号输入端CLK3、第四控制信号输入端CLK4、第五控制信号输入端CLK5分别与对应的时钟信号线连接。在该情况下，通过第一控制信号输入端、第二控制信号输入端、第三控制信号输入端、第四控制信号输入端、第五控制信号输入端输入的控制信号均为时钟信号。通过第三控制信号输入端输入的时钟信号在预设时间段内处于有效电平。In some embodiments, the first control signal input terminal CLK1, the second control signal input terminal CLK2, the third control signal input terminal CLK3, the fourth control signal input terminal CLK4, and the fifth control signal input terminal CLK5 are respectively associated with corresponding clocks. Signal line connection. In this case, the control signals input through the first control signal input terminal, the second control signal input terminal, the third control signal input terminal, the fourth control signal input terminal, and the fifth control signal input terminal are all clock signals. The clock signal input through the third control signal input terminal is at an effective level within a preset time period.
图7为图6所示驱动单元的工作时序图，下面将结合附图7来对图6所示的驱动单元的工作过程进行描述。在以下描述中，假定各晶体管均为N型晶体管，第一工作电源端VGL提供低电平工作电压，第二工作电源端VGH提供高电平工作电压。FIG. 7 is a working timing diagram of the driving unit shown in FIG. 6. The working process of the driving unit shown in FIG. 6 will be described below with reference to FIG. 7. In the following description, it is assumed that each transistor is an N-type transistor, the first working power supply terminal VGL provides a low-level working voltage, and the second working power supply terminal VGH provides a high-level working voltage.
如图7所示，该驱动单元的工作过程对应于移位寄存器SR的工作过程，主要包括预充阶段、输出阶段、复位阶段。As shown in FIG. 7, the working process of the driving unit corresponds to the working process of the shift register SR, and mainly includes a precharge stage, an output stage, and a reset stage.
在移位寄存器SR的预充阶段，上拉节点PU处的电压处于高电平，驱动信号输出端Cout处的电压处于低电平，下拉节点PD处的电压处于低电平，则通过第一控制信号输入端CLK1提供的第一时钟信号处于低电平，通过第二控制信号输入端CLK2提供的第二时钟信号在部分时间段处于低电平而在部分时间段处于高电平。In the pre-charge stage of the shift register SR, the voltage at the pull-up node PU is at a high level, the voltage at the drive signal output terminal Cout is at a low level, and the voltage at the pull-down node PD is at a low level, then the first pass The first clock signal provided by the control signal input terminal CLK1 is at a low level, and the second clock signal provided by the second control signal input terminal CLK2 is at a low level in some time periods and at a high level in some time periods.
此时，由于上拉节点PU处的电压处于高电平，则第一晶体管T1导通，通过第一晶体管T1将第一时钟信号写入第一节点Q1。由于第一时钟信号处于低电平，因此第一节点Q1处的电压为低电平，第七晶体管T7截止。与此同时，在处于低电平的第一时钟信号的控制下，第六晶体管T6也处于截止状态。At this time, because the voltage at the pull-up node PU is at a high level, the first transistor T1 is turned on, and the first clock signal is written into the first node Q1 through the first transistor T1. Since the first clock signal is at a low level, the voltage at the first node Q1 is at a low level, and the seventh transistor T7 is turned off. At the same time, under the control of the first clock signal at a low level, the sixth transistor T6 is also in an off state.
由于下拉节点PD处的电压处于低电平，第二晶体管T2和第四晶体管T4均截止。与此同时，由于驱动信号输出端Cout处的电压处 于低电平，第五晶体管T5截止。第二节点Q2处于浮接(Floating)状态，第二节点Q2维持前一周期结束时的高电平状态，此时第三晶体管T3和第八晶体管T8均导通。通过第三晶体管T3将经由第一工作电压端VGL提供的低电平工作电压写入第一节点Q1，从而维持第一节点Q1的电压为低电平。将经由第一工作电压端VGL提供的低电平工作电压通过第八晶体管T8写入第一信号输出端Gout1，则通过第一信号输出端Gout1输出低电平电压。Since the voltage at the pull-down node PD is at a low level, both the second transistor T2 and the fourth transistor T4 are turned off. At the same time, the fifth transistor T5 is turned off because the voltage at the drive signal output terminal Cout is at a low level. The second node Q2 is in a floating state, and the second node Q2 maintains a high-level state at the end of the previous period. At this time, the third transistor T3 and the eighth transistor T8 are both turned on. The third transistor T3 writes a low-level operating voltage provided through the first operating voltage terminal VGL to the first node Q1, thereby maintaining the voltage of the first node Q1 to a low level. The low-level operating voltage provided through the first operating voltage terminal VGL is written into the first signal output terminal Gout1 through the eighth transistor T8, and then the low-level voltage is output through the first signal output terminal Gout1.
在移位寄存器SR的输出阶段，上拉节点PU处的电压处于高电平，驱动信号输出端Cout处的电压处于高电平，下拉节点PD处的电压处于低电平。输出阶段至少包括预设时间段t0(对应于进行外部补偿的感测阶段)。预设时间段t0包括：连续设置的第一子时间段t1、第二子时间段t2和第三子时间段t3。In the output stage of the shift register SR, the voltage at the pull-up node PU is at a high level, the voltage at the drive signal output terminal Cout is at a high level, and the voltage at the pull-down node PD is at a low level. The output stage includes at least a preset time period t0 (corresponding to a sensing stage for performing external compensation). The preset time period t0 includes a first sub-time period t1, a second sub-time period t2, and a third sub-time period t3 which are continuously set.
在第一子时间段t1内，第一时钟信号处于高电平，第二时钟信号处于低电平。此时，由于上拉节点PU处的电压维持高电平，第一晶体管T1持续导通，从而可以将第一时钟信号持续写入第一节点Q1。由于第一时钟信号处于高电平，第一节点Q1处的电压为高电平，此时第六晶体管T6和第七晶体管T7均导通，第七晶体管T7构成一个二极管。In the first sub-time period t1, the first clock signal is at a high level and the second clock signal is at a low level. At this time, since the voltage at the pull-up node PU remains high, the first transistor T1 is continuously turned on, so that the first clock signal can be continuously written into the first node Q1. Since the first clock signal is at a high level and the voltage at the first node Q1 is at a high level, the sixth transistor T6 and the seventh transistor T7 are both turned on at this time, and the seventh transistor T7 constitutes a diode.
由于下拉节点PD处的电压处于低电平，第二晶体管T2和第四晶体管T4均维持截止状态。与此同时，由于驱动信号输出端Cout处的电压处于高电平，第五晶体管T5导通。此时可将第二时钟信号通过第五晶体管T5写入第二节点Q2。又由于第二时钟信号处于低电平，因此第二节点Q2处的电压处于低电平，此时第三晶体管T3和第八晶体管T8均截止。Since the voltage at the pull-down node PD is at a low level, both the second transistor T2 and the fourth transistor T4 are maintained in an off state. At the same time, the fifth transistor T5 is turned on because the voltage at the driving signal output terminal Cout is at a high level. At this time, the second clock signal can be written into the second node Q2 through the fifth transistor T5. Because the second clock signal is at a low level, the voltage at the second node Q2 is at a low level. At this time, the third transistor T3 and the eighth transistor T8 are both turned off.
在第八晶体管T8截止的情况下，将经由第二工作电源端VGH提供的高电平工作电压通过第七晶体管T7写入第一信号输出端Gout1，则第一信号输出端Gout1输出高电平电压。When the eighth transistor T8 is turned off, the high-level operating voltage provided through the second working power terminal VGH is written into the first signal output terminal Gout1 through the seventh transistor T7, and the first signal output terminal Gout1 outputs a high level Voltage.
在第二子时间段t2内，第一时钟信号处于高电平，第二时钟信号处于高电平。由于第五晶体管T5持续导通，将处于高电平的第二时钟信号通过第五晶体管T5写入第二节点Q2。由于第二节点Q2处 的电压处于高电平，第三晶体管T3和第八晶体管T8均导通。In the second sub-time period t2, the first clock signal is at a high level, and the second clock signal is at a high level. Since the fifth transistor T5 is continuously turned on, the second clock signal at a high level is written into the second node Q2 through the fifth transistor T5. Since the voltage at the second node Q2 is at a high level, both the third transistor T3 and the eighth transistor T8 are turned on.
由于第八晶体管T8导通，将经由第一工作电源端VGL提供的低电平工作电压通过第八晶体管T8写入第一信号输出端Gout1，则第一信号输出端Gout1输出低电平电压。Since the eighth transistor T8 is turned on, the low-level operating voltage provided through the first working power supply terminal VGL is written into the first signal output terminal Gout1 through the eighth transistor T8, and the first signal output terminal Gout1 outputs a low-level voltage.
需要说明的是，在第二子时间段内，由于第一晶体管T1、第六晶体管T6和第三晶体管T3均处于导通状态，因此第一时钟信号(通过第一晶体管T1)、高电平工作电压(通过第六晶体管T6)和低电平工作电压(通过第三晶体管T3)同时对第一节点Q1进行充电。第一节点Q1处的电压大小与第一晶体管T1、第六晶体管T6和第三晶体管T3的沟道宽长比相关。然而，在第二节点Q2处的电压为高电平的情况下，无论第一节点Q1处的电压处于高电平还是处于低电平，第一信号输出端Gout1始终输出低电平电压。It should be noted that in the second sub-period, because the first transistor T1, the sixth transistor T6, and the third transistor T3 are all in an on state, the first clock signal (through the first transistor T1), the high level The working voltage (through the sixth transistor T6) and the low-level working voltage (through the third transistor T3) charge the first node Q1 at the same time. The magnitude of the voltage at the first node Q1 is related to the channel width-to-length ratio of the first transistor T1, the sixth transistor T6, and the third transistor T3. However, in the case where the voltage at the second node Q2 is high, regardless of whether the voltage at the first node Q1 is high or low, the first signal output terminal Gout1 always outputs a low voltage.
当第一节点Q1处的电压处于高电平时，由于第六晶体管T6导通，则第七晶体管T7构成一个二极管。在第八晶体管T8导通的情况下，第七晶体管T7作为一个大电阻，第一信号输出端Gout1输出低电平电压。当第一节点Q1处的电压处于低电平时，第七晶体管T7截止，仅经由第一工作电源端VGL提供的低电平工作电压通过第八晶体管T8对第一信号输出端Gout1进行充电，第一信号输出端Gout1输出低电平电压。附图中仅示例性给出了在第二子时间段内第一节点Q1处的电压为高电平的示意图。When the voltage at the first node Q1 is at a high level, since the sixth transistor T6 is turned on, the seventh transistor T7 constitutes a diode. When the eighth transistor T8 is turned on, the seventh transistor T7 acts as a large resistor, and the first signal output terminal Gout1 outputs a low-level voltage. When the voltage at the first node Q1 is at a low level, the seventh transistor T7 is turned off, and the first signal output terminal Gout1 is charged by the eighth transistor T8 only through the low-level operating voltage provided by the first operating power terminal VGL. A signal output terminal Gout1 outputs a low-level voltage. The figure only illustrates the voltage at the first node Q1 at a high level during the second sub-period by way of example.
在第三子时间段t3内，第一时钟信号处于高电平，第二时钟信号处于低电平。此时，由于上拉节点PU维持高电平状态，第一晶体管T1持续导通，将第一时钟信号持续写入第一节点Q1。第一节点Q1处的电压为高电平，此时第六晶体管T6和第七晶体管T7均导通，第七晶体管T7构成一个二极管。又由于下拉节点PD处的电压处于低电平，第二晶体管T2和第四晶体管T4均维持截止状态。与此同时，由于驱动信号输出端Cout处的电压处于高电平，第五晶体管T5导通。此时可将第二时钟信号通过第五晶体管T5写入第二节点Q2。又由于第二时钟信号处于低电平，第二节点Q2处的电压处于低电平，此时第三晶体管T3和第八晶体管T8均截止。在第八晶体管T8截止的情 况下，将经由第二工作电源端VGH提供的高电平工作电压通过第七晶体管T7写入第一信号输出端Gout1，则第一信号输出端Gout1输出高电平电压。In the third sub-period t3, the first clock signal is at a high level and the second clock signal is at a low level. At this time, because the pull-up node PU maintains a high-level state, the first transistor T1 is continuously turned on, and the first clock signal is continuously written into the first node Q1. The voltage at the first node Q1 is at a high level. At this time, the sixth transistor T6 and the seventh transistor T7 are both turned on, and the seventh transistor T7 constitutes a diode. Because the voltage at the pull-down node PD is at a low level, both the second transistor T2 and the fourth transistor T4 are maintained in an off state. At the same time, the fifth transistor T5 is turned on because the voltage at the driving signal output terminal Cout is at a high level. At this time, the second clock signal can be written into the second node Q2 through the fifth transistor T5. Because the second clock signal is at a low level and the voltage at the second node Q2 is at a low level, the third transistor T3 and the eighth transistor T8 are both turned off at this time. When the eighth transistor T8 is turned off, the high-level operating voltage provided through the second working power terminal VGH is written into the first signal output terminal Gout1 through the seventh transistor T7, and the first signal output terminal Gout1 outputs a high level Voltage.
由此可见，本公开提供的驱动单元的第一信号输出端Gout1可在预设时间段t0输出一个双脉冲信号，从而能够在感测阶段内对像素单元中的第二栅线进行驱动。由于本公开的技术方案是基于GOA电路，因而有利于实现显示基板的窄边框。It can be seen that the first signal output terminal Gout1 of the driving unit provided by the present disclosure can output a double pulse signal at a preset time period t0, so that the second gate line in the pixel unit can be driven during the sensing stage. Since the technical solution of the present disclosure is based on the GOA circuit, it is beneficial to realize a narrow frame of the display substrate.
需要说明的是，在实际应用中，预设时间段t0的时长可小于移位寄存器SR的输出阶段的时长(预设时间段t0的开始时刻晚于输出阶段的开始时刻，但预设时间段t0的结束时刻与输出阶段的结束时刻相同)。此时，在输出阶段内除预设时间段t0之外的其他时间(处于输出阶段内且位于预设时间段t0之前)，由于第一时钟信号处于低电平，第一节点Q1处的电压处于低电平，第七晶体管T7截止。此时，虽然第五晶体管T5导通，但是由于第二时钟信号处于低电平，因此第八晶体管T8也截止，第一信号输出端Gout1处于浮接状态。第一信号输出端Gout1处的电压维持预充阶段结束时的电压，即低电平电压。It should be noted that, in practical applications, the duration of the preset time period t0 may be shorter than the duration of the output stage of the shift register SR (the start time of the preset time period t0 is later than the start time of the output stage, but the preset time period The end time of t0 is the same as the end time of the output phase). At this time, during the output phase other than the preset time period t0 (in the output phase and before the preset time period t0), because the first clock signal is at a low level, the voltage at the first node Q1 At a low level, the seventh transistor T7 is turned off. At this time, although the fifth transistor T5 is turned on, because the second clock signal is at a low level, the eighth transistor T8 is also turned off, and the first signal output terminal Gout1 is in a floating state. The voltage at the first signal output terminal Gout1 maintains the voltage at the end of the precharge phase, that is, the low-level voltage.
在移位寄存器SR的复位阶段，上拉节点PU处的电压处于低电平，驱动信号输出端Cout处的电压处于低电平，下拉节点PD处的电压处于高电平。通过第一控制信号输入端CLK1提供的第一时钟信号处于低电平，通过第二控制信号输入端CLK2提供的第二时钟信号在部分时间段处于低电平而在部分时间段处于高电平。In the reset stage of the shift register SR, the voltage at the pull-up node PU is at a low level, the voltage at the drive signal output terminal Cout is at a low level, and the voltage at the pull-down node PD is at a high level. The first clock signal provided through the first control signal input terminal CLK1 is at a low level, and the second clock signal provided through the second control signal input terminal CLK2 is at a low level in some time periods and at a high level in some time periods. .
由于上拉节点PU处的电压处于低电平，第一晶体管T1截止。由于下拉节点PD处的电压处于高电平，第二晶体管T2和第四晶体管T4导通，将经由第一工作电源端VGL提供的低电平工作电压通过第二晶体管T2写入第一节点Q1。第一节点Q1处的电压为低电平，第七晶体管T7截止。将经由第二工作电源端VGH提供的高电平工作电压通过第四晶体管T4写入第二节点Q2，第二节点Q2处的电压处于高电平，第三晶体管T3和第八晶体管T8均导通。将经由第一工作电源端VGL提供的低电平工作电压通过第三晶体管T3写入第一节点Q1， 从而维持第一节点Q1的电压为低电平。将经由第一工作电源端VGL提供的低电平工作电压通过第八晶体管T8写入第一信号输出端Gout1，则第一信号输出端Gout1输出低电平电压。Since the voltage at the pull-up node PU is at a low level, the first transistor T1 is turned off. Because the voltage at the pull-down node PD is at a high level, the second transistor T2 and the fourth transistor T4 are turned on, and the low-level operating voltage provided through the first operating power terminal VGL is written into the first node Q1 through the second transistor T2. . The voltage at the first node Q1 is low, and the seventh transistor T7 is turned off. The high-level operating voltage provided by the second working power terminal VGH is written into the second node Q2 through the fourth transistor T4. The voltage at the second node Q2 is at a high level, and the third transistor T3 and the eighth transistor T8 are both turned on. through. The low-level working voltage provided through the first working power supply terminal VGL is written into the first node Q1 through the third transistor T3, so as to maintain the voltage of the first node Q1 at a low level. The low-level operating voltage provided through the first working power terminal VGL is written into the first signal output terminal Gout1 through the eighth transistor T8, and the first signal output terminal Gout1 outputs a low-level voltage.
需要说明的是，在移位寄存器SR的复位阶段结束至下一周期开始的等待阶段，由于上拉节点PU处的电压维持低电平状态，驱动信号输出端Cout处的电压维持低电平状态，下拉节点PD处的电压维持高电平状态，因此该驱动单元在等待阶段的工作过程与在复位阶段的过程相同。即，该驱动单元的第一信号输出端Gout1在等待阶段持续输出低电平电压。It should be noted that during the waiting period from the end of the reset phase of the shift register SR to the beginning of the next cycle, the voltage at the pull-up node PU maintains a low state, and the voltage at the drive signal output terminal Cout maintains a low state. The voltage at the pull-down node PD maintains a high-level state, so the working process of the driving unit in the waiting phase is the same as the process in the reset phase. That is, the first signal output terminal Gout1 of the driving unit continuously outputs a low-level voltage during the waiting period.
在一些实施例中，驱动单元还包括第二输出电路4(在图5中未示出)。如图6所示，第二输出电路4分别与上拉节点PU、下拉节点PD和第二信号输出端Gout2连接，用于在上拉节点PU的电压、下拉节点PD的电压的控制下，在预设时间段t0内，通过第二信号输出端Gout2输出处于有效电平的电压。In some embodiments, the driving unit further includes a second output circuit 4 (not shown in FIG. 5). As shown in FIG. 6, the second output circuit 4 is respectively connected to the pull-up node PU, the pull-down node PD, and the second signal output terminal Gout2, and is used to control the voltage of the pull-up node PU and the voltage of the pull-down node PD under the control of During the preset time period t0, a voltage at an effective level is output through the second signal output terminal Gout2.
在本公开中，第二输出电路4能够在预设时间段t0内输出单脉冲信号，从而能够在感测阶段内对像素单元中的第一栅线(图1中开关晶体管TFT的控制极所连接的栅线G1)进行驱动。即本公开提供的驱动单元，不仅能够在感测阶段内为像素单元中的感测晶体管提供驱动信号，还能同时为像素单元中的开关晶体管提供驱动信号，从而能有效减少显示基板中所需要的栅极驱动电路的数量，更有利于窄边框的实现。In the present disclosure, the second output circuit 4 is capable of outputting a single-pulse signal within a preset time period t0, so that the first gate line (the control electrode of the switching transistor TFT in FIG. 1) in the pixel unit can be detected during the sensing phase. The connected gate line G1) is driven. That is, the driving unit provided by the present disclosure can not only provide a driving signal for a sensing transistor in a pixel unit during a sensing stage, but also provide a driving signal for a switching transistor in a pixel unit at the same time, thereby effectively reducing the need for a display substrate. The number of gate driving circuits is more conducive to the realization of a narrow frame.
在一些实施例中，第二输出电路4还分别与第一控制信号输入端CLK1(即，第一时钟信号线)、第一工作电源端VGL连接，第二输出电路4用于：在上拉节点PU的电压的控制下，在移位寄存器SR的预充阶段和输出阶段内，将通过第一控制信号输入端CLK1提供的第一时钟信号写入第二信号输出端Gout2，第一时钟信号在预设时间段t0内处于有效电平；在下拉节点PD的电压的控制下，在移位寄存器SR的复位阶段内，将通过第一工作电源端VGL提供的第一工作电压写入第二信号输出端Gout2。In some embodiments, the second output circuit 4 is also connected to the first control signal input terminal CLK1 (ie, the first clock signal line) and the first working power terminal VGL, and the second output circuit 4 is configured to: Under the control of the voltage of the node PU, the first clock signal provided through the first control signal input terminal CLK1 is written into the second signal output terminal Gout2 during the precharge phase and the output phase of the shift register SR, and the first clock signal It is at an active level within a preset time period t0; under the control of the voltage of the pull-down node PD, during the reset phase of the shift register SR, the first working voltage provided by the first working power supply terminal VGL is written into the second Signal output terminal Gout2.
在一些实施例中，第二输出电路4包括第九晶体管T9和第十晶 体管T10。第九晶体管T9的控制极与上拉节点PU连接，第九晶体管T9的第一极与第一控制信号输入端CLK1连接，第九晶体管T9的第二极与第二信号输出端Gout2连接。第十晶体管T10的控制极与下拉节点PD连接，第十晶体管T10的第一极与第二信号输出端Gout2连接，第十晶体管T10的第二极与第一工作电源端VGL连接。In some embodiments, the second output circuit 4 includes a ninth transistor T9 and a tenth transistor T10. The control pole of the ninth transistor T9 is connected to the pull-up node PU, the first pole of the ninth transistor T9 is connected to the first control signal input terminal CLK1, and the second pole of the ninth transistor T9 is connected to the second signal output terminal Gout2. The control electrode of the tenth transistor T10 is connected to the pull-down node PD, the first electrode of the tenth transistor T10 is connected to the second signal output terminal Gout2, and the second electrode of the tenth transistor T10 is connected to the first working power terminal VGL.
为便于本领域技术人员理解，下面对第二输出电路4的工作过程进行描述。To facilitate understanding by those skilled in the art, the working process of the second output circuit 4 is described below.
在移位寄存器SR的预充阶段内，由于上拉节点PU处的电压为高电平，下拉节点PD处的电压为低电平，因此第九晶体管T9导通、第十晶体管T10截止，将第一时钟信号通过第九晶体管T9写入第二信号输出端Gout2。又由于第一时钟信号处于低电平，因此第二信号输出端Gout2输出低电平电压。During the pre-charge stage of the shift register SR, since the voltage at the pull-up node PU is high and the voltage at the pull-down node PD is low, the ninth transistor T9 is turned on and the tenth transistor T10 is turned off. The first clock signal is written into the second signal output terminal Gout2 through the ninth transistor T9. Because the first clock signal is at a low level, the second signal output terminal Gout2 outputs a low-level voltage.
在移位寄存器SR的输出阶段内，由于上拉节点PU处的电压为高电平，下拉节点PD处的电压为低电平，因此第九晶体管T9维持导通状态，第十晶体管T10维持截止状态，将第一时钟信号通过第九晶体管T9写入第二信号输出端Gout2。在输出阶段期间的预设时间段t0内，由于第一时钟信号处于高电平，因此第二信号输出端Gout2输出高电平电压。During the output stage of the shift register SR, because the voltage at the pull-up node PU is high and the voltage at the pull-down node PD is low, the ninth transistor T9 remains on and the tenth transistor T10 remains off State, the first clock signal is written into the second signal output terminal Gout2 through the ninth transistor T9. In the preset time period t0 during the output phase, since the first clock signal is at a high level, the second signal output terminal Gout2 outputs a high-level voltage.
由此可见，本公开提供的驱动单元的第二信号输出端Gout2可在预设时间段t0内输出一个单脉冲信号，从而能够在感测阶段内对像素单元中的第一栅线进行驱动，有利于窄边框的实现。It can be seen that the second signal output terminal Gout2 of the driving unit provided in the present disclosure can output a single pulse signal within a preset time period t0, so that the first gate line in the pixel unit can be driven during the sensing phase. Conducive to the realization of narrow borders.
在移位寄存器SR的复位阶段，由于上拉节点PU处的电压为低电平，下拉节点PD处的电压为高电平，因此第九晶体管T9截止，第十晶体管T10导通。将经由第一工作电源端VGL提供的低电平工作电压通过第十晶体管T10写入第二信号输出端Gout2，第二信号输出端Gout2输出低电平电压。In the reset stage of the shift register SR, since the voltage at the pull-up node PU is low and the voltage at the pull-down node PD is high, the ninth transistor T9 is turned off and the tenth transistor T10 is turned on. The low-level operating voltage provided through the first working power supply terminal VGL is written into the second signal output terminal Gout2 through the tenth transistor T10, and the second signal output terminal Gout2 outputs a low-level voltage.
在本公开的实施例中，驱动单元中的各晶体管可均为N型晶体管，或者驱动单元中的各晶体管也可均为P型晶体管。通过统一驱动单元中的晶体管的类型，可通过相同的晶体管制备工艺来同时制备出驱动单元中的各晶体管，进而能有效缩短生产周期。In the embodiment of the present disclosure, each transistor in the driving unit may be an N-type transistor, or each transistor in the driving unit may be a P-type transistor. By unifying the types of transistors in the driving unit, each transistor in the driving unit can be prepared at the same time through the same transistor manufacturing process, which can effectively shorten the production cycle.
根据本公开的另一个方面，提供了一种栅极驱动电路。图9为根据本公开的实施例的一种栅极驱动电路的电路结构示意图。如图9所示，该栅极驱动电路包括级联的若干个驱动单元GDX_1、GDX_2……GDX_n，其中驱动单元GDX_1、GDX_2……GDX_n可采用上述实施例提供的驱动单元，具体结构和操作可参见前述实施例中的描述。According to another aspect of the present disclosure, a gate driving circuit is provided. FIG. 9 is a schematic circuit structure diagram of a gate driving circuit according to an embodiment of the present disclosure. As shown in FIG. 9, the gate driving circuit includes a plurality of cascaded driving units GDX_1, GDX_2, ..., GDX_n, where the driving units GDX_1, GDX_2, ..., GDX_n can adopt the driving units provided in the above embodiments. The specific structure and operation can be See the description in the previous embodiment.
在该栅极驱动电路中，除第一级驱动单元GDX_1外，其他各驱动单元GDX_2……GDX_n的移位寄存器SR的驱动信号输出端Cout与相应的上一级驱动单元GDX_1、GDX_2……GDX_n-1的移位寄存器SR的复位信号输入端RESET连接。除最后一级驱动单元GDX_n外，其他各驱动单元GDX_1、GDX_2……GDX_n-1的移位寄存器SR的驱动信号输出端Cout与相应的下一级驱动单元GDX_2……GDX_n的移位寄存器SR的预充信号输入端INPUT连接。In this gate drive circuit, in addition to the first-stage drive unit GDX_1, the drive signal output terminal Cout of the shift register SR of each of the drive units GDX_2 ... GDX_n and the corresponding upper-stage drive units GDX_1, GDX_2 ... GDX_n The reset signal input terminal RESET of the shift register SR of -1 is connected. Except for the last stage drive unit GDX_n, the drive signal output terminal Cout of the shift register SR of each drive unit GDX_1, GDX_2 ... GDX_n-1 and the corresponding shift register SR of the next stage drive unit GDX_2 ... GDX_n Precharge signal input terminal INPUT connection.
在本实施例中，通过各驱动单元GDX_1、GDX_2……GDX_n的移位寄存器SR的驱动信号输出端Cout，可以实现驱动单元的级联，通过各驱动单元的第一信号输出端Gout1和第二信号输出端Gout2分别实现对像素单元内的第一栅线G1和第二栅线G2的驱动。In this embodiment, the drive signal output terminal Cout of the shift register SR of each drive unit GDX_1, GDX_2 ... GDX_n can realize the cascade of the drive units, and the first signal output terminal Gout1 and the second of each drive unit The signal output terminal Gout2 realizes driving the first gate line G1 and the second gate line G2 in the pixel unit, respectively.
根据本公开的又一个方面，提供了一种显示基板。该显示基板包括栅极驱动电路，该栅极驱动电路可采用根据本公开实施例的栅极驱动电路。本公开所提供的显示基板例如为OLED基板。According to still another aspect of the present disclosure, a display substrate is provided. The display substrate includes a gate driving circuit, and the gate driving circuit may adopt a gate driving circuit according to an embodiment of the present disclosure. The display substrate provided in the present disclosure is, for example, an OLED substrate.
根据本公开的又一个方面，提供了一种驱动方法。图10为根据本公开的实施例的一种驱动方法的流程图，该方法用于驱动上述的驱动单元。如图10所示，驱动方法可以包括以下的步骤S101至S103。According to yet another aspect of the present disclosure, a driving method is provided. FIG. 10 is a flowchart of a driving method according to an embodiment of the present disclosure, which is used to drive the driving unit described above. As shown in FIG. 10, the driving method may include the following steps S101 to S103.
在步骤S101中，在第一子时间段内，通过第一控制子电路控制第一节点处的电压处于有效电平，通过第二控制子电路控制第二节点处的电压处于非有效电平，使得输出子电路通过第一信号输出端输出处于有效电平的电压。In step S101, during a first sub-period, the voltage at the first node is controlled by the first control sub-circuit at an active level, and the voltage at the second node is controlled by the second control sub-circuit at an inactive level. The output sub-circuit is made to output a voltage at an effective level through the first signal output terminal.
在步骤S102中，在第二子时间段内，通过第一控制子电路控制第一节点处的电压处于有效电平，通过第二控制子电路控制第二节点处的电压处于有效电平，使得输出子电路通过第一信号输出端输出处于非有效电平的电压。In step S102, during the second sub-period, the voltage at the first node is controlled by the first control sub-circuit to be at an effective level, and the voltage at the second node is controlled by the second control sub-circuit at the effective level, so that The output sub-circuit outputs a voltage at an inactive level through the first signal output terminal.
在步骤S103中，在第三子时间段内，通过第一控制子电路控制第一节点处的电压处于有效电平，通过第二控制子电路控制第二节点处的电压处于非有效电平，使得输出子电路通过第一信号输出端输出处于有效电平的电压。In step S103, during the third sub-period, the voltage at the first node is controlled by the first control sub-circuit to be at an active level, and the voltage at the second node is controlled by the second control sub-circuit at an inactive level. The output sub-circuit is made to output a voltage at an effective level through the first signal output terminal.
对于上述步骤S101～步骤S103的具体操作可参见前述实施例中的相应内容，此处不再赘述。For specific operations of the foregoing steps S101 to S103, reference may be made to corresponding content in the foregoing embodiments, and details are not described herein again.
在一些实施例中，在预设时间段内，通过上拉电路控制上拉节点处的电压处于有效电平，通过下拉控制电路控制下拉节点处的电压处于非有效电平，则通过第二输出电路的第二信号输出端输出处于有效电平的电压。预设时间段包括连续设置的第一子时间段、第二子时间段和第三子时间段。In some embodiments, within a preset period of time, the voltage at the pull-up node is controlled by the pull-up circuit to be at an active level, and the voltage at the pull-down node is controlled by the pull-down control circuit to be at an inactive level, and then the second output The second signal output terminal of the circuit outputs a voltage at an active level. The preset time period includes a first sub-time period, a second sub-time period, and a third sub-time period that are continuously set.
在一些实施例中，该方法还包括在第一信号输出端和第二信号输出端分别输出处于有效电平的电压之前，通过预充复位电路对上拉节点进行预充电。In some embodiments, the method further includes pre-charging the pull-up node through a pre-charging reset circuit before the first signal output terminal and the second signal output terminal respectively output a voltage at an effective level.
在一些实施例中，该方法还包括在第一信号输出端和第二信号输出端分别输出处于有效电平的电压之后，通过复位预充复位电路以使上拉电路停止工作，上拉节点处的电压处于非有效电平。同时通过下拉控制电路控制，使得下拉节点处的电压维持有效电平，以使得驱动信号输出端输出非有效电平信号，并使得第一信号输出端和第二信号输出端分别复位。In some embodiments, the method further includes, after the first signal output terminal and the second signal output terminal respectively output a voltage at an effective level, resetting the precharge reset circuit to stop the pull-up circuit, and the pull-up node The voltage is at an inactive level. At the same time, it is controlled by the pull-down control circuit so that the voltage at the pull-down node maintains an active level, so that the driving signal output terminal outputs a non-active level signal, and the first signal output terminal and the second signal output terminal are reset respectively.
在一些实施例中，该方法还包括在对第一信号输出端和第二信号输出端进行复位之后，通过上拉电路控制上拉节点处的电压维持非有效电平，通过下拉电路控制下拉节点处的电压维持有效电平，以使得驱动信号输出端输出非有效电平信号，并使得第一信号输出端和第二信号输出端分别保持输出复位电平。In some embodiments, the method further includes, after resetting the first signal output terminal and the second signal output terminal, controlling the voltage at the pull-up node to maintain an inactive level through a pull-up circuit, and controlling the pull-down node through a pull-down circuit. The voltage at is maintained at an active level, so that the driving signal output terminal outputs a non-active level signal, and the first signal output terminal and the second signal output terminal respectively maintain an output reset level.
在一些实施例中，预设时间段的时长等于感测时间段的时长，并且预设时间段的开始时刻和结束时刻分别与感测时间段的开始时刻和结束时刻对齐。In some embodiments, the duration of the preset time period is equal to the duration of the sensing time period, and the start time and end time of the preset time period are respectively aligned with the start time and end time of the sensing time period.
在一些实施例中，预设时间段的时长小于发光二极管稳定显示阶段的时长。In some embodiments, the duration of the preset time period is shorter than the duration of the stable display period of the light emitting diode.
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。It can be understood that the above implementations are merely exemplary implementations adopted to explain the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various variations and improvements can be made without departing from the spirit and essence of the present disclosure, and these variations and improvements are also considered to be within the protection scope of the present disclosure.

Claims (20)

  1. 一种驱动单元，包括：移位寄存器和第一输出电路，所述移位寄存器包括上拉节点、下拉节点和驱动信号输出端，所述第一输出电路构造为在所述上拉节点的电压、所述下拉节点的电压和所述驱动信号输出端提供的电压的控制下在预设时间段内输出双脉冲信号。A driving unit includes a shift register and a first output circuit, the shift register includes a pull-up node, a pull-down node, and a driving signal output terminal, and the first output circuit is configured as a voltage at the pull-up node The double-pulse signal is output within a preset time period under the control of the voltage of the pull-down node and the voltage provided by the driving signal output terminal.
  2. 根据权利要求1所述的驱动单元，其中，所述第一输出电路包括：第一控制子电路、第二控制子电路和输出子电路；所述第一控制子电路和所述输出子电路连接于第一节点，所述第一控制子电路、所述第二控制子电路和所述输出子电路连接于第二节点；The driving unit according to claim 1, wherein the first output circuit comprises: a first control sub-circuit, a second control sub-circuit, and an output sub-circuit; and the first control sub-circuit is connected to the output sub-circuit At a first node, the first control sub-circuit, the second control sub-circuit, and the output sub-circuit are connected to a second node;
    所述第一控制子电路与所述上拉节点和所述下拉节点连接，并且构造为在所述上拉节点的电压、所述下拉节点的电压、所述第二节点的电压的控制下，在所述预设时间段内，控制所述第一节点处的电压处于有效电平，其中，所述预设时间段包括：连续设置的第一子时间段、第二子时间段和第三子时间段；The first control sub-circuit is connected to the pull-up node and the pull-down node, and is configured to be controlled by a voltage of the pull-up node, a voltage of the pull-down node, and a voltage of the second node, Controlling the voltage at the first node to be at an effective level within the preset time period, wherein the preset time period includes a first sub-time period, a second sub-time period, and a third time period which are continuously set; Sub-period
    所述第二控制子电路与所述下拉节点和所述驱动信号输出端连接，并且构造为在所述下拉节点的电压、所述驱动信号输出端提供的电压的控制下，控制所述第二节点处的电压在所述第一子时间段和所述第三子时间段内处于非有效电平、在所述第二子时间段内处于有效电平；The second control sub-circuit is connected to the pull-down node and the drive signal output terminal, and is configured to control the second pull-down node under the control of the voltage of the pull-down node and the voltage provided by the drive signal output terminal. The voltage at the node is at an inactive level during the first sub-period and the third sub-period, and at an active level during the second sub-period;
    所述输出子电路与第一信号输出端连接，并且构造为在所述第一节点的电压处于有效电平且所述第二节点的电压处于非有效电平时，通过所述第一信号输出端输出处于有效电平的电压，以及在所述第二节点的电压处于有效电平时，通过所述第一信号输出端输出处于非有效电平的电压。The output sub-circuit is connected to a first signal output terminal, and is configured to pass through the first signal output terminal when the voltage of the first node is at an active level and the voltage of the second node is at an inactive level. A voltage at an active level is output, and when the voltage at the second node is at an active level, a voltage at an inactive level is output through the first signal output terminal.
  3. 根据权利要求2所述的驱动单元，其中，所述第一控制子电路包括：第一晶体管、第二晶体管和第三晶体管；The driving unit according to claim 2, wherein the first control sub-circuit comprises: a first transistor, a second transistor, and a third transistor;
    所述第一晶体管的控制极与所述上拉节点连接，所述第一晶体 管的第一极与第一控制信号输入端连接，所述第一晶体管的第二极与所述第一节点连接；A control pole of the first transistor is connected to the pull-up node, a first pole of the first transistor is connected to a first control signal input terminal, and a second pole of the first transistor is connected to the first node ;
    所述第二晶体管的控制极与所述下拉节点连接，所述第二晶体管的第一极与所述第一节点连接，所述第二晶体管的第二极与第一工作电源端连接，其中，所述第一工作电源端构造为提供处于非有效电平的第一工作电压；并且A control pole of the second transistor is connected to the pull-down node, a first pole of the second transistor is connected to the first node, and a second pole of the second transistor is connected to a first working power terminal, where The first working power terminal is configured to provide a first working voltage at an inactive level; and
    所述第三晶体管的控制极与所述第二节点连接，所述第三晶体管的第一极与所述第一节点连接，所述第三晶体管的第二极与所述第一工作电源端连接。A control electrode of the third transistor is connected to the second node, a first electrode of the third transistor is connected to the first node, and a second electrode of the third transistor is connected to the first working power terminal. connection.
  4. 根据权利要求3所述的驱动单元，其中，所述第二控制子电路包括：第四晶体管和第五晶体管；The driving unit according to claim 3, wherein the second control sub-circuit comprises: a fourth transistor and a fifth transistor;
    所述第四晶体管的控制极与所述下拉节点连接，所述第四晶体管的第一极与第二工作电源端连接，所述第四晶体管的第二极与所述第二节点连接，其中，所述第二工作电源端构造为提供处于有效电平的第二工作电压；并且A control electrode of the fourth transistor is connected to the pull-down node, a first electrode of the fourth transistor is connected to a second working power terminal, and a second electrode of the fourth transistor is connected to the second node, wherein The second working power terminal is configured to provide a second working voltage at an effective level; and
    所述第五晶体管的控制极与所述驱动信号输出端连接，所述第五晶体管的第一极与所述第二节点连接，所述第五晶体管的第二极与第二控制信号输入端连接。A control electrode of the fifth transistor is connected to the driving signal output terminal, a first electrode of the fifth transistor is connected to the second node, and a second electrode of the fifth transistor is connected to a second control signal input terminal. connection.
  5. 根据权利要求4所述的驱动单元，其中，所述输出子电路包括：第六晶体管、第七晶体管、第八晶体和第一电容，The driving unit according to claim 4, wherein the output sub-circuit comprises: a sixth transistor, a seventh transistor, an eighth crystal, and a first capacitor,
    所述第六晶体管的控制极与所述第一控制信号输入端连接，所述第六晶体管的第一极与所述第二工作电源端连接，所述第六晶体管的第二极与所述第一节点连接；A control electrode of the sixth transistor is connected to the first control signal input terminal, a first electrode of the sixth transistor is connected to the second working power terminal, and a second electrode of the sixth transistor is connected to the first electrode. First node connected;
    所述第七晶体管的控制极与所述第一节点连接，所述第七晶体管的第一极与所述第二工作电源端连接，所述第七晶体管的第二极与所述第一信号输出端连接；The control electrode of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is connected to the second working power terminal, and the second electrode of the seventh transistor is connected to the first signal. Output connection
    所述第八晶体管的控制极与所述第二节点连接，所述第八晶体管的第一极与所述第一信号输出端连接，所述第八晶体管的第二极与 所述第一工作电源端连接；并且A control electrode of the eighth transistor is connected to the second node, a first electrode of the eighth transistor is connected to the first signal output terminal, and a second electrode of the eighth transistor is connected to the first operation. Power-side connection; and
    所述第一电容的第一端与所述第一节点连接，所述第一电容的第二端与所述第一信号输出端连接。A first terminal of the first capacitor is connected to the first node, and a second terminal of the first capacitor is connected to the first signal output terminal.
  6. 根据权利要求4所述的驱动单元，其中，所述输出子电路包括：第六晶体管、第七晶体管、第八晶体和第一电容；The driving unit according to claim 4, wherein the output sub-circuit comprises: a sixth transistor, a seventh transistor, an eighth crystal, and a first capacitor;
    所述第六晶体管的控制极和第一极分别与第三控制信号输入端连接，所述第六晶体管的第二极与所述第一节点连接；A control electrode and a first electrode of the sixth transistor are respectively connected to a third control signal input terminal, and a second electrode of the sixth transistor is connected to the first node;
    所述第七晶体管的控制极与所述第一节点连接，所述第七晶体管的第一极与所述第三控制信号输入端连接，所述第七晶体管的第二极与所述第一信号输出端连接；A control pole of the seventh transistor is connected to the first node, a first pole of the seventh transistor is connected to the third control signal input terminal, and a second pole of the seventh transistor is connected to the first node. Signal output terminal connection;
    所述第八晶体管的控制极与所述第二节点连接，所述第八晶体管的第一极与所述第一信号输出端连接，所述第八晶体管的第二极与所述第一工作电源端连接；并且A control electrode of the eighth transistor is connected to the second node, a first electrode of the eighth transistor is connected to the first signal output terminal, and a second electrode of the eighth transistor is connected to the first operation. Power-side connection; and
    所述第一电容的第一端与所述第一节点连接，所述第一电容的第二端与所述第一信号输出端连接。A first terminal of the first capacitor is connected to the first node, and a second terminal of the first capacitor is connected to the first signal output terminal.
  7. 根据权利要求5所述的驱动单元，还包括：第二输出电路；The driving unit according to claim 5, further comprising: a second output circuit;
    所述第二输出电路分别与所述上拉节点、所述下拉节点和所述第一信号输出端连接，并且构造为在所述上拉节点的电压、所述下拉节点的电压的控制下，在所述预设时间段内，通过第二信号输出端输出处于有效电平的电压。The second output circuit is respectively connected to the pull-up node, the pull-down node, and the first signal output terminal, and is configured to be controlled by the voltage of the pull-up node and the voltage of the pull-down node, During the preset time period, a voltage at an effective level is output through the second signal output terminal.
  8. 根据权利要求7所述的驱动单元，其中，所述第二输出电路包括：第九晶体管和第十晶体管；The driving unit according to claim 7, wherein the second output circuit comprises: a ninth transistor and a tenth transistor;
    所述第九晶体管的控制极与所述上拉节点连接，所述第九晶体管的第一极与所述第一控制信号输入端连接，所述第九晶体管的第二极与所述第二信号输出端连接；并且A control pole of the ninth transistor is connected to the pull-up node, a first pole of the ninth transistor is connected to the first control signal input terminal, and a second pole of the ninth transistor is connected to the second The signal output is connected; and
    所述第十晶体管的控制极与所述下拉节点连接，所述第十晶体管的第一极与所述第二信号输出端连接，所述第十晶体管的第二极与 所述第一工作电源端连接。A control pole of the tenth transistor is connected to the pull-down node, a first pole of the tenth transistor is connected to the second signal output terminal, and a second pole of the tenth transistor is connected to the first working power source.端 连接。 End connection.
  9. 根据权利要求6所述的驱动单元，还包括第二输出电路；The driving unit according to claim 6, further comprising a second output circuit;
    其中，所述第二输出电路包括：第九晶体管和第十晶体管；The second output circuit includes: a ninth transistor and a tenth transistor;
    所述第九晶体管的控制极与所述上拉节点连接，所述第九晶体管的第一极与所述第一控制信号输入端连接，所述第九晶体管的第二极与所述第二信号输出端连接；并且A control pole of the ninth transistor is connected to the pull-up node, a first pole of the ninth transistor is connected to the first control signal input terminal, and a second pole of the ninth transistor is connected to the second The signal output is connected; and
    所述第十晶体管的控制极与所述下拉节点连接，所述第十晶体管的第一极与所述第二信号输出端连接，所述第十晶体管的第二极与所述第一工作电源端连接。A control pole of the tenth transistor is connected to the pull-down node, a first pole of the tenth transistor is connected to the second signal output terminal, and a second pole of the tenth transistor is connected to the first working power source.端 连接。 End connection.
  10. 根据权利要求1所述的驱动单元，其中，所述上拉节点构造为在所述预设时间段内提供处于有效电平的电压，所述驱动信号输出端构造为在所述预设时间段内提供处于有效电平的电压，所述下拉节点构造为在所述预设时间段内提供处于非有效电平的电压。The driving unit according to claim 1, wherein the pull-up node is configured to provide a voltage at an effective level within the preset time period, and the driving signal output end is configured to be within the preset time period A voltage at an active level is provided within, and the pull-down node is configured to provide a voltage at an inactive level within the preset time period.
  11. 根据权利要求4所述的驱动单元，其中，所述第一控制信号输入端构造为提供第一时钟信号，所述第二控制信号端构造为提供第二时钟信号，所述第一时钟信号在所述预设时间段内处于有效电平，所述第二时钟信号在所述第一子时间段和所述第三子时间段内处于非有效电平，并且在所述第二子时间段内处于有效电平。The driving unit according to claim 4, wherein the first control signal input terminal is configured to provide a first clock signal, the second control signal terminal is configured to provide a second clock signal, and the first clock signal is at The preset time period is at an active level, the second clock signal is at an inactive level during the first sub-time period and the third sub-time period, and during the second sub-time period Is at a valid level.
  12. 根据权利要求5所述的驱动单元，其中，所述移位寄存器包括预充复位电路、上拉电路、下拉电路和下拉控制电路；The driving unit according to claim 5, wherein the shift register comprises a precharge reset circuit, a pull-up circuit, a pull-down circuit, and a pull-down control circuit;
    所述预充复位电路分别与预充信号输入端和复位信号输入端连接并且与所述上拉电路连接于所述上拉节点，所述下拉电路与所述下拉控制电路连接于所述下拉节点，所述上拉电路和所述下拉电路连接于所述驱动信号输出端。The precharge reset circuit is respectively connected to a precharge signal input terminal and a reset signal input terminal and is connected to the pull-up circuit to the pull-up node, and the pull-down circuit and the pull-down control circuit are connected to the pull-down node. The pull-up circuit and the pull-down circuit are connected to the driving signal output terminal.
  13. 根据权利要求12所述的驱动单元，其中，所述预充复位电 路包括第十一晶体管、第十二晶体管和第十三晶体管；所述下拉控制电路包括第十四晶体管、第十五晶体管和第十六晶体管；所述上拉电路包括第十七晶体管和第二电容；所述下拉电路包括第十八晶体管；The driving unit according to claim 12, wherein the precharge reset circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; and the pull-down control circuit includes a fourteenth transistor, a fifteenth transistor, and A sixteenth transistor; the pull-up circuit includes a seventeenth transistor and a second capacitor; the pull-down circuit includes an eighteenth transistor;
    所述第十一晶体管的控制极与第四控制信号输入端连接，所述第十一晶体管的第一极与所述预充信号输入端连接，所述第十一晶体管的第二极与所述上拉节点连接；The control pole of the eleventh transistor is connected to a fourth control signal input terminal, the first pole of the eleventh transistor is connected to the precharge signal input terminal, and the second pole of the eleventh transistor is connected to all Said pull-up node connection;
    所述第十二晶体管的控制极与所述第四控制信号输入端连接，所述第十二晶体管的第一极与所述上拉节点连接，所述第十二晶体管的第二极与所述第十三晶体管的第一极连接；A control electrode of the twelfth transistor is connected to the fourth control signal input terminal, a first electrode of the twelfth transistor is connected to the pull-up node, and a second electrode of the twelfth transistor is connected to all The first pole connection of the thirteenth transistor;
    所述第十三晶体管的控制极与复位信号输入端连接，所述第十三晶体管的第二极与所述第一工作电源端连接；A control electrode of the thirteenth transistor is connected to a reset signal input terminal, and a second electrode of the thirteenth transistor is connected to the first working power terminal;
    所述第十四晶体管的控制极和第一极分别与所述第二工作电源端连接，所述第十四晶体管的第二极与所述下拉节点连接；A control electrode and a first electrode of the fourteenth transistor are respectively connected to the second working power terminal, and a second electrode of the fourteenth transistor is connected to the pull-down node;
    所述第十五晶体管的控制极与所述下拉节点连接，所述第十五晶体管的第一极与所述上拉节点连接，所述第十五晶体管的第二极与所述第一工作电源端连接；A control pole of the fifteenth transistor is connected to the pull-down node, a first pole of the fifteenth transistor is connected to the pull-up node, and a second pole of the fifteenth transistor is connected to the first operation. Power end connection;
    所述第十六晶体管的控制极与所述上拉节点连接，所述第十六晶体管的第一极与所述下拉节点连接，所述第十六晶体管的第二极与所述第一工作电源端连接；The control pole of the sixteenth transistor is connected to the pull-up node, the first pole of the sixteenth transistor is connected to the pull-down node, and the second pole of the sixteenth transistor is connected to the first operation. Power end connection;
    所述第十七晶体管的控制极与所述上拉节点连接，所述第十七晶体管的第一极与第五控制信号输入端连接，所述第十七晶体管的第二极与所述驱动信号输出端连接；A control pole of the seventeenth transistor is connected to the pull-up node, a first pole of the seventeenth transistor is connected to a fifth control signal input terminal, and a second pole of the seventeenth transistor is connected to the drive Signal output terminal connection;
    所述第二电容的第一端与所述上拉节点连接，所述第二电容的第二端与所述驱动信号输出端连接；并且A first terminal of the second capacitor is connected to the pull-up node, and a second terminal of the second capacitor is connected to the driving signal output terminal; and
    所述第十八晶体管的控制极与所述下拉节点连接，所述第十八晶体管的第一极与所述驱动信号输出端连接，所述第十八晶体管的第二极与所述第一工作电源端连接。The control electrode of the eighteenth transistor is connected to the pull-down node, the first electrode of the eighteenth transistor is connected to the driving signal output terminal, and the second electrode of the eighteenth transistor is connected to the first The working power terminal is connected.
  14. 根据权利要求12所述的驱动单元，其中，所述预充复位电路包括第十一晶体管、第十二晶体管和第十三晶体管；所述下拉控制 电路包括第十四晶体管、第十五晶体管、第十六晶体管和第十九晶体管；所述上拉电路包括第十七晶体管和第二电容；所述下拉电路包括第十八晶体管；The driving unit according to claim 12, wherein the precharge reset circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; and the pull-down control circuit includes a fourteenth transistor, a fifteenth transistor, A sixteenth transistor and a nineteenth transistor; the pull-up circuit includes a seventeenth transistor and a second capacitor; the pull-down circuit includes an eighteenth transistor;
    所述第十一晶体管的控制极与第四控制信号输入端连接，所述第十一晶体管的第一极与所述预充信号输入端连接，所述第十一晶体管的第二极与所述上拉节点连接；The control pole of the eleventh transistor is connected to a fourth control signal input terminal, the first pole of the eleventh transistor is connected to the precharge signal input terminal, and the second pole of the eleventh transistor is connected to all Said pull-up node connection;
    所述第十二晶体管的控制极与所述第四控制信号输入端连接，所述第十二晶体管的第一极与所述上拉节点连接，所述第十二晶体管的第二极与所述第十三晶体管的第一极连接；A control electrode of the twelfth transistor is connected to the fourth control signal input terminal, a first electrode of the twelfth transistor is connected to the pull-up node, and a second electrode of the twelfth transistor is connected to all The first pole connection of the thirteenth transistor;
    所述第十三晶体管的控制极与所述复位信号输入端连接，所述第十三晶体管的第二极与所述第一工作电源端连接；A control electrode of the thirteenth transistor is connected to the reset signal input terminal, and a second electrode of the thirteenth transistor is connected to the first working power terminal;
    所述第十四晶体管的控制极与所述第四控制信号输入端连接，所述第十四晶体管的第一极与所述第二工作电源端连接，所述第十四晶体管的第二极与所述下拉节点连接；A control pole of the fourteenth transistor is connected to the fourth control signal input terminal, a first pole of the fourteenth transistor is connected to the second working power terminal, and a second pole of the fourteenth transistor Connected to the pull-down node;
    所述第十五晶体管的控制极与所述下拉节点连接，所述第十五晶体管的第一极与所述上拉节点连接，所述第十五晶体管的第二极与所述第一工作电源端连接；A control pole of the fifteenth transistor is connected to the pull-down node, a first pole of the fifteenth transistor is connected to the pull-up node, and a second pole of the fifteenth transistor is connected to the first operation. Power end connection;
    所述第十六晶体管的控制极与所述上拉节点连接，所述第十六晶体管的第一极与所述下拉节点连接，所述第十六晶体管的第二极与所述第一工作电源端连接；The control pole of the sixteenth transistor is connected to the pull-up node, the first pole of the sixteenth transistor is connected to the pull-down node, and the second pole of the sixteenth transistor is connected to the first operation. Power end connection;
    所述第十七晶体管的控制极与所述上拉节点连接，所述第十七晶体管的第一极与第五控制信号输入端连接，所述第十七晶体管的第二极与所述驱动信号输出端连接；A control pole of the seventeenth transistor is connected to the pull-up node, a first pole of the seventeenth transistor is connected to a fifth control signal input terminal, and a second pole of the seventeenth transistor is connected to the drive Signal output terminal connection;
    所述第二电容的第一端与所述上拉节点连接，所述第二电容的第二端与所述驱动信号输出端连接；A first end of the second capacitor is connected to the pull-up node, and a second end of the second capacitor is connected to the driving signal output terminal;
    所述第十八晶体管的控制极与所述下拉节点连接，所述第十八晶体管的第一极与所述驱动信号输出端连接，所述第十八晶体管的第二极与所述第一工作电源端连接；The control electrode of the eighteenth transistor is connected to the pull-down node, the first electrode of the eighteenth transistor is connected to the driving signal output terminal, and the second electrode of the eighteenth transistor is connected to the first Work power connection
    所述第十九晶体管的控制极与所述第五控制信号输入端连接，所述第十九晶体管的第一极与所述第二工作电源端连接，所述第十九 晶体管的第二极与所述下拉节点连接。The control pole of the nineteenth transistor is connected to the fifth control signal input terminal, the first pole of the nineteenth transistor is connected to the second working power terminal, and the second pole of the nineteenth transistor Connected to the pull-down node.
  15. 根据权利要求13所述的驱动单元，其中，所述驱动单元中的各晶体管为相同导电类型的晶体管。The driving unit according to claim 13, wherein each transistor in the driving unit is a transistor of the same conductivity type.
  16. 一种栅极驱动电路，包括：级联的多个驱动单元，其中所述驱动单元采用上述权利要求1所述的驱动单元；A gate driving circuit includes: a plurality of cascaded driving units, wherein the driving unit adopts the driving unit according to claim 1;
    除第一级驱动单元外，其他各驱动单元的移位寄存器的驱动信号输出端与上一级驱动单元的移位寄存器的复位信号输入端连接；Except for the first-level driving unit, the driving signal output terminal of the shift register of each other driving unit is connected to the reset signal input terminal of the shift register of the previous-level driving unit;
    除最后一级驱动单元外，其他各驱动单元的移位寄存器的驱动信号输出端与下一级驱动单元的移位寄存器的预充信号输入端连接。Except for the last stage driving unit, the driving signal output terminal of the shift register of each other driving unit is connected to the precharge signal input terminal of the shift register of the next stage driving unit.
  17. 一种显示基板，包括：如权利要求16所述的栅极驱动电路。A display substrate comprising: the gate driving circuit according to claim 16.
  18. 一种驱动方法，所述驱动方法用于驱动权利要求2所述的驱动单元，所述驱动方法包括：A driving method for driving the driving unit according to claim 2, the driving method comprising:
    在所述第一子时间段内，通过第一控制子电路控制第一节点处的电压处于有效电平，通过第二控制子电路控制第二节点处的电压处于非有效电平，使得输出子电路通过第一信号输出端输出处于有效电平的电压；In the first sub-time period, the voltage at the first node is controlled by the first control sub-circuit to be at an active level, and the voltage at the second node is controlled by the second control sub-circuit at an inactive level, so that the output sub- The circuit outputs a voltage at an effective level through the first signal output terminal;
    在所述第二子时间段内，通过第一控制子电路控制第一节点处的电压处于有效电平，通过第二控制子电路控制第二节点处的电压处于有效电平，使得输出子电路通过所述第一信号输出端输出处于非有效电平的电压；In the second sub-time period, the voltage at the first node is controlled by the first control sub-circuit to be at an effective level, and the voltage at the second node is controlled by the second control sub-circuit at the effective level, so that the output sub-circuit Outputting a voltage at an inactive level through the first signal output terminal;
    在所述第三子时间段内，通过第一控制子电路控制第一节点处的电压处于有效电平，通过第二控制子电路控制第二节点处的电压处于非有效电平，使得所述输出子电路通过所述第一信号输出端输出处于有效电平的电压。In the third sub-time period, the voltage at the first node is controlled by the first control sub-circuit to be at an active level, and the voltage at the second node is controlled by the second control sub-circuit at an inactive level, so that the The output sub-circuit outputs a voltage at an effective level through the first signal output terminal.
  19. 根据权利要求18所述的驱动方法，其中，The driving method according to claim 18, wherein:
    在所述预设时间段内，所述上拉节点处的电压处于有效电平，所述下拉节点处的电压处于非有效电平，所述驱动信号输出端处的电压处于有效电平。During the preset time period, the voltage at the pull-up node is at an active level, the voltage at the pull-down node is at an inactive level, and the voltage at the output terminal of the drive signal is at an active level.
  20. 根据权利要求19所述的驱动方法，其中，The driving method according to claim 19, wherein:
    所述移位寄存器的工作周期包括预充阶段、输出阶段和复位阶段，The working cycle of the shift register includes a precharge stage, an output stage, and a reset stage,
    在所述预充阶段，对所述上拉节点进行预充电；Pre-charging the pull-up node in the pre-charging stage;
    在所述输出阶段，在上拉节点的电压的控制下，通过所述驱动信号输出端输出处于有效电平的电压；In the output stage, under the control of the voltage of the pull-up node, a voltage at an effective level is output through the driving signal output terminal;
    在所述复位阶段，对上拉节点进行复位，控制下拉节点的电压处于有效电平，并经由所述驱动信号输出端输出处于非有效电平的电压In the reset stage, the pull-up node is reset, the voltage of the pull-down node is controlled to be at an active level, and a voltage at an inactive level is output via the driving signal output terminal.
    其中，所述预设时间段在所述输出阶段内。The preset time period is within the output stage.
PCT/CN2019/083448 2018-07-13 2019-04-19 Drive unit and drive method therefor, gate drive circuit and display substrate WO2020010892A1 (en)

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US11257418B2 (en) 2022-02-22

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