WO2020004015A1 - Dynamic variable capacity memory device and storage capacity dynamic variable method - Google Patents

Dynamic variable capacity memory device and storage capacity dynamic variable method Download PDF

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Publication number
WO2020004015A1
WO2020004015A1 PCT/JP2019/023123 JP2019023123W WO2020004015A1 WO 2020004015 A1 WO2020004015 A1 WO 2020004015A1 JP 2019023123 W JP2019023123 W JP 2019023123W WO 2020004015 A1 WO2020004015 A1 WO 2020004015A1
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Prior art keywords
storage
unit
capacity
path
data
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PCT/JP2019/023123
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French (fr)
Japanese (ja)
Inventor
徹 保米本
佳奈 益本
松田　俊哉
松村　和之
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日本電信電話株式会社
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Publication of WO2020004015A1 publication Critical patent/WO2020004015A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L13/00—Details of the apparatus or circuits covered by groups H04L15/00 or H04L17/00
    • H04L13/02—Details not particular to receiver or transmitter
    • H04L13/08—Intermediate storage means

Definitions

  • the present invention relates to a dynamic variable-capacity memory device capable of changing a storage capacity of a memory device mounted on a communication device in a communication network, and a dynamic storage-capacity variable method.
  • a plurality of communication devices that communicate with each other in a communication network each have a memory device, and perform a process of reading and writing data for communication in the memory device.
  • a packet buffer device described in Patent Document 1 as a memory device includes a memory unit, a write block buffer, and a read block buffer.
  • An SDRAM (Synchronous Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) is applied to the memory unit.
  • input packet data is sequentially stored in the write block buffer, and when a predetermined amount of data is stored in the write block buffer, the data is written to the memory unit. Further, in response to an output instruction, data is read from the memory unit, stored in the read block buffer, and each packet data included in the stored data is read and output.
  • the memory unit for storing communication data has a fixed storage capacity because it is composed of an SDRAM or an SRAM. For this reason, if the storage capacity of the memory unit is insufficient due to an increase in the amount of communication data, communication data cannot be held and data is lost.
  • the operation of the communication device itself including the packet buffer device is temporarily stopped. After that, it is necessary to perform additional processing such as adding an SDRAM or an SRAM and replacing the SDRAM or the SRAM with a larger capacity than the current one. Therefore, there is a problem that the communication device must be temporarily stopped in order to increase the storage capacity of the memory unit. Stopping the communication device causes a problem that hinders the communication operation.
  • the present invention has been made in view of the above circumstances, and is provided in a communication device.
  • a dynamic variable device capable of increasing or decreasing a storage area by changing a data storage capacity without stopping the communication device. It is an object to provide a capacity memory device and a method of dynamically changing a storage capacity.
  • the invention according to claim 1 is provided by an electronic circuit mounted on a plurality of communication devices that communicate with each other via a bidirectional path and capable of changing a circuit configuration capable of storing data.
  • a storage unit using a storage circuit by the electronic circuit an allocation amount corresponding to a data capacity capable of transmitting a path between the communication devices is determined, and the allocation amount is determined.
  • a dynamic variable-capacity memory device comprising: a control unit for performing variable-capacity control in which a storage area having a corresponding storage capacity is formed in the storage unit by a storage circuit.
  • a dynamic variable capacity memory device which is mounted on a plurality of communication devices that communicate with each other via a bidirectional path and is configured by an electronic circuit capable of changing a circuit configuration capable of storing data.
  • a method of dynamically changing a storage capacity wherein the dynamic variable capacity memory device includes a storage circuit including the electronic circuit, and includes a storage unit capable of changing a configuration of the storage circuit, and transmits a path between the communication devices. Determining an allocation amount corresponding to the data amount to be performed, and performing a variable capacity control of forming a storage area of the storage capacity according to the allocation amount in the storage unit by a storage circuit. This is a dynamic capacity variable method.
  • the dynamic variable-capacity memory device includes a storage unit that can change the configuration of a storage circuit that stores data. Then, the control unit obtains an assigned amount corresponding to a data capacity capable of transmitting a path between the communication devices. Further, the control unit can form a storage area for storing the data of the path in the storage unit by the storage circuit by the capacity variable control according to the assigned amount. Therefore, without stopping the communication device, it is possible to increase or decrease the storage area by changing the data storage capacity of the dynamic variable capacity memory device.
  • the storage circuit is configured by using a plurality of unit memories in which a plurality of electronic storage elements are integrated, and is connected to a number of unit memories corresponding to a storage capacity according to the allocated amount, and is connected to a storage area.
  • a storage area capable of accommodating the data capacity of the corresponding path can be easily formed in the storage unit according to the assigned amount corresponding to the data capacity capable of transmitting the path between the communication devices.
  • a specific packet with a unique number is generated and transmitted to the bidirectional path, and the packet is transmitted from the bidirectional path.
  • a receiving unit that notifies the control unit of the reception time of each bidirectional path when receiving the specific packet with the unique number, and a deleting unit that deletes the specific packet after the notification. 3.
  • the reception time difference is obtained from the reception time of each path, the data capacity of the path according to the reception time difference is obtained, and the quota corresponding to the data capacity is obtained. It is a dynamic variable capacity memory device.
  • the quota corresponding to the data capacity of this path can be obtained.
  • the storage capacity of the storage unit can be changed according to the data capacity of the actual path, so that the storage size of the storage unit can be minimized.
  • the dynamic variable capacity memory device according to any one of claims 1 to 3, wherein a storage area having a capacity is formed.
  • a storage area having a storage capacity corresponding to the path amount can be allocated to another unused storage unit other than the storage unit in the dynamic variable capacity memory device, so that the storage capacity is easily increased. be able to.
  • a dynamic variable-capacity memory device and a storage-capacity dynamic variable method which are mounted on a communication device and vary the storage capacity of data to increase or decrease the storage area without stopping the communication device. Can be provided.
  • FIG. 1 is a block diagram illustrating a configuration of a communication network having a communication device equipped with a dynamic variable capacity memory device according to an embodiment of the present invention.
  • FIG. 3 is a block diagram illustrating a configuration of a dynamic variable capacity memory device.
  • FIG. 3 is a block diagram illustrating a configuration of a non-instantaneous interruption transmission / reception unit of a communication device connected by a clockwise route and a counterclockwise route.
  • FIG. 3 is a block diagram illustrating a configuration of a hitless transmission / reception unit during normal operation.
  • FIG. 3 is a block diagram illustrating a configuration of a hitless transmission / reception unit during variable capacity control.
  • FIG. 3 is a diagram showing a block SRAM and a unit SRAM.
  • FIG. 3 is a block diagram illustrating a configuration of a variable capacity storage unit.
  • FIG. 3 is a block diagram illustrating a configuration in which unit SRAMs of a variable capacity storage unit are connected to form a storage area.
  • FIG. 4A shows a storage area by a unit SRAM during an exit from an input port to an output port
  • FIG. 4A shows two unit SRAMs between an input port i1 and an output port o1
  • FIG. 4B shows a storage area between an input port i2 and an output port o2.
  • (C) is a diagram showing one unit SRAM between the input port i3 and the output port o3
  • (d) is a diagram showing one unit SRAM between the input port i4 and the output port o4.
  • It is. 5 is a flowchart for explaining an operation of dynamically changing the memory capacity by the dynamic variable capacity memory device.
  • FIG. 9 is a block diagram illustrating a configuration when another GA circuit storage unit is additionally used in the dynamic variable capacity memory
  • FIG. 1 is a block diagram showing a configuration of a communication NW (network) having a communication device equipped with a dynamic variable capacity memory device according to an embodiment of the present invention.
  • the communication NW 10 shown in FIG. 1 has a plurality (four) of communication devices 20a, 20b, 20c, and 20d connected in a ring by two-way transmission lines.
  • the transmission line is divided into a left-handed route and a right-handed route, and is configured using an optical cable using an optical fiber or an electric cable using a conductive wire or the like.
  • the communication devices 20a to 20d perform communication between the communication devices 20a to 20d and communication processing with a communication terminal such as a personal computer (not shown).
  • a communication terminal such as a personal computer (not shown).
  • Each of the communication devices 20a to 20d includes a communication control unit 30 using a computer, and a dynamic variable capacity memory device 40 which is a characteristic element of the present embodiment.
  • the dynamic variable-capacity memory device (also referred to as a memory device) 40 is configured using an FPGA (Field-Programmable Gate ⁇ ⁇ ⁇ Array) using a gate array in which the configuration of a storage circuit using an electronic circuit is variable.
  • FPGA Field-Programmable Gate ⁇ ⁇ ⁇ Array
  • a storage area of a predetermined storage capacity can be allocated to the FPGA. This storage area is generally used when configuring (setting) the FPGA of the memory device 40, and cannot be changed during the operation of the communication devices 20a to 20d. However, in the present embodiment, it can be changed during the operation as described later.
  • the memory device 40 includes a variable capacity storage section 41, a variable capacity control section 42, a label switch 43, instantaneous interruption transmission / reception sections 44a, 44b, 44c, and an Ethernet (registered trademark) switch 45. It is comprised including.
  • the label switch 43 is input from the uninterrupted transmission / reception units 44a to 44c to a destination indicated by a label of a fixed length identification based on a packet transport technology called MPLS-TP (Multi-Protocol Label Switching Switching Transport Profile). A switching operation is performed to transfer the data to the left and right paths.
  • the label switch 43 writes data received from the left and right paths into the variable capacity storage unit (also referred to as a storage unit) 41, reads out the written data, and outputs the read data to the hitless transmission / reception units 44a to 44c.
  • the Ethernet switch 45 attaches a unique MAC (Media Access Control) address to the head of the data received by the communication control unit 30 from a communication terminal (not shown), and adds an Ethernet frame signal (also referred to as a frame signal). Convert to Further, the Ethernet switch 45 performs a switching operation of transferring the frame signal to the destination indicated by the MAC address of the converted frame signal.
  • MAC Media Access Control
  • Each of the uninterrupted transmission / reception units 44a to 44c has the same configuration, receives a signal from a communication device on the communication partner side without any interruption based on the packet transport technology of the MPLS-TP, and communicates with the communication unit on the other end. An operation of transmitting a signal to the device without interruption is performed.
  • the hitless transmission / reception units 44a to 44c detect the state (path state) of data transmitted to two transmission lines (paths) connecting the communication devices 20a to 20d, and change the capacity of the capacity control unit (control unit). ). Note that the path status is a data reception time or the like.
  • the hitless transmission / reception units 44a to 44c include a sequence number insertion unit 51, a two-lane data duplication unit 52, a specific packet insertion unit 53a, 53b, specific packet deletion units 54a and 54b, hitless switching unit 55, and sequence number deletion unit 56.
  • the specific packet insertion units 53a and 53b constitute an insertion unit described in the claims.
  • the specific packet deletion units 54a and 54b constitute a deletion unit described in the claims.
  • FIG. 3 shows a state in which the hitless transmission / reception unit 44a1 of the communication device 20a and the hitless transmission / reception unit 44a2 of the communication device 20b are connected by the right and left paths of the path number P4 (see FIG. 2). Show. Note that the path number P4 is also referred to as a path P4.
  • the hitless transmission / reception units 44a1 and 44a2 when a normal operation is performed in the memory device 40.
  • the normal operation is an operation that does not include an operation of changing a storage capacity described later.
  • the sequence number insertion unit 51 attaches a sequence number (sequence number) to the head of the frame signal from the Ethernet switch 45 (FIG. 2) and outputs the frame signal to the duplication unit 52.
  • the sequence number is incremented by one each time a new Ethernet frame is added. Note that the sequence number is also simply referred to as a number.
  • the two-lane data copying unit (also referred to as a copying unit) 52 copies the numbered frame signal into two (see arrows Y1a and Y1b in FIG. 4), and connects to the counterclockwise path via the specific packet insertion units 53a and 53b. Send to the clockwise route. Note that the specific packet insertion units 53a and 53b perform only an operation of passing a signal during normal operation.
  • the specific packet deletion units 54a and 54b pass the numbered frame signals transmitted from the left and right paths and output the frame signals to the hitless switching unit 55 during normal operation. Perform the operation.
  • the hitless switching unit (also referred to as a switching unit) 55 outputs frame signals received from the left and right paths to the sequence number deletion unit 56 in numerical order during normal operation, as indicated by arrows Y2 and Y3 in FIG. .
  • the switching unit 55 Delete (discard) the signal.
  • the switching unit 55 deletes the frame signals having the overlapping numbers as described above, and outputs the frame signals to the next sequence number deleting unit 56 in the order of one number.
  • the deletion unit 56 deletes the frame signal number and outputs the frame signal number to the Ethernet switch 45 (FIG. 2).
  • the switching unit 55 illustrated in FIG. Wait for the output of "7” because there is a possibility that "has jumped.
  • the number “6” is input from the counterclockwise route (arrow Y3 in FIG. 4) during this waiting, the number “6” is output.
  • the clockwise route since “7” comes after the number “5”, it indicates that some trouble has occurred in the clockwise route.
  • the switching unit 55 has a function of not outputting the same number received from the left and right paths or a number smaller than the already received number, and if one of the paths is normal, it can continue to output packets in numerical order. Has a possible function.
  • variable capacity control unit 42 can perform variable capacity control when an instruction signal for changing the storage capacity is input from outside.
  • the control unit 42 performs control of allocating a required storage capacity for each path in an initial state in which the storage capacity is not allocated to the memory device 40, and if the storage capacity is allocated, the control unit 42 obtains the required capacity. Then, the capacity variable control for increasing or decreasing the storage capacity is performed.
  • the uninterrupted transmission / reception unit 44a sets the switching unit 55 and the duplication unit 52 in a state corresponding to the variable capacity control as described later in cooperation with the control unit 42. Switching is performed, and the deletion processing of the specific packet deletion units 54a and 54b and the insertion processing of the specific packet insertion units 53a and 53b are validated.
  • the switching unit 55 and the copying unit 52 return to the normal operation state when the end of the variable capacity control is notified (control state notification).
  • the switching unit 55 makes the selection of one route (for example, the clockwise route) valid as indicated by the arrow Y2, and the selection of the other route (the counterclockwise route).
  • a process is performed to invalidate the selection as indicated by an X mark at the end of the arrow Y3.
  • the duplication unit 52 performs a process of invalidating the output of the frame signal to which the sequence number is assigned, as indicated by the X mark at the end of the arrow Y1.
  • the specific packet insertion units 53a and 53b After such setting, the specific packet insertion units 53a and 53b generate specific packets with a sequence number (for example, No. 5) in the hitless transmission / reception unit 44a2 shown in FIG. To the route. This transmission is performed periodically.
  • the specific packet is, for example, an OAM (Operations Administration Maintenance) packet for performing operation, management, and maintenance of the network.
  • OAM Operations Administration Maintenance
  • the specific packet deletion units 54a and 54b receive the OAM packet with the sequence number transmitted from both the clockwise route and the counterclockwise route.
  • the time is output to the variable capacity control unit 42, and after this output, the OAM packet is deleted. Note that the reception time is notified to the control unit 42 as a path state.
  • the control unit 42 calculates a reception time difference from the reception times of both OAM packets. For example, if a counterclockwise fifth OAM packet is received 10 seconds after the reception time of the clockwise fifth OAM packet, the reception time difference is determined to be 10 seconds.
  • the control unit 42 obtains a bit (bit) indicating the data capacity (path amount) of this path according to the reception time difference. For this, first, the reception time difference is converted into a distance difference (for example, 1 km). Next, the maximum value of the path speed (for example, 1 Gbps) is multiplied by the delay value (for example, 5 ns / m) of the optical fiber that is the path, and the multiplication result is multiplied by the distance difference (1 km) to reduce the data capacity.
  • a data capacity (path amount) of 1 Gbit ⁇ 5 ns / m ⁇ 1 km 5 kbit is obtained.
  • the 5 kbit data capacity corresponds to the distance difference between the clockwise route and the counterclockwise route that is 1 km longer than this. Therefore, the control unit 42 stores a storage area (for example, the storage area 41a in FIG. 2) having the same storage capacity in the variable capacity storage unit ( Assign it for In the allocated storage area 41a, the fifth data received from the clockwise path of the path P4 by the label switch 43 (FIG. 2) is temporarily stored. After this holding, if the user waits until the same fifth data from the counterclockwise route is received, the distance difference between the left and right routes of the path P4 can be absorbed.
  • a storage area for example, the storage area 41a in FIG. 2
  • Assign it for In the allocated storage area 41a the fifth data received from the clockwise path of the path P4 by the label switch 43 (FIG. 2) is temporarily stored. After this holding, if the user waits until the same fifth data from the counterclockwise route is received, the distance difference between the left and right routes of the path P4 can be absorbed.
  • the control unit 42 increases the storage capacity of the larger amount. Find the quota to be assigned.
  • the storage area 41a of the path P4 having the path amount indicated by the assigned amount is newly assigned to the storage unit 41.
  • the allocation amount indicates a data capacity required to allocate a unit SRAM (described later) corresponding to the path amount.
  • the dynamic allocation of the storage capacity to the storage unit 41 based on this allocation amount will be described.
  • the memory device 40 is configured using an FPGA (see FIG. 2).
  • the variable capacity storage unit 41 includes a large number of block SRAMs 61 each of which is defined as a minimum storage unit such as 8 bits in the FPGA.
  • the FPGA constitutes a storage circuit described in the claims.
  • the block SRAM 61 constitutes an electronic storage element described in the claims.
  • a predetermined number (for example, eight) of block SRAMs 61 are grouped together to constitute a unit SRAM 62 as a unit memory.
  • the unit SRAM 62 has a port for inputting and outputting 64-bit data, for example. It is assumed that the storage capacity of the unit SRAM 62 is, for example, 64 bits ⁇ 512 records.
  • variable capacity storage unit 41 a storage area having an arbitrary storage capacity from a small capacity to a large capacity can be configured by combining a plurality of unit SRAMs 62 according to a predetermined logic.
  • the storage unit 41 includes a plurality of unit SRAMs 62a, 62b, 62c, 62d, and 62e, a 1 ⁇ 2 selector 63 for connecting the unit SRAMs 62a to 62e, a 2 ⁇ 1 selector 64, A crossbar SW (switch) 65 for the input ports i1 to i4 and a crossbar SW66 for the output ports o1 to o4 are provided.
  • the 1 ⁇ 2 selector 63 determines whether one movable portion 63a on the data input side is connected to one of the first fixed portion 63b and the second fixed portion 63c and outputs data from the first fixed portion 63b. It is configured to be able to select whether to output from the second fixed unit 63c.
  • Reference numerals 63a to 63c of the movable portion 63a, the first fixed portion 63b, and the second fixed portion 63c are representatively shown as the 1 ⁇ 2 selector 63 on the leftmost side of the drawing.
  • the 2 ⁇ 1 selector 64 connects one of the movable portions 64c on the data output side to one of the first fixed portion 64a and the second fixed portion 64b on the data input side, and is input from the first fixed portion 64a.
  • the configuration is such that it is possible to select whether to output data from the movable section 64c or to output data input from the second fixed section 64b from the movable section 64c.
  • Reference numerals 64a to 64c of the first fixed portion 64a, the second fixed portion 64b, and the movable portion 64c are representatively shown as the 2 ⁇ 1 selector 64 on the leftmost side of the drawing.
  • the crossbar SW65 has a configuration in which four input bars connected to input ports i1 to i4 to which data of four paths P1 to P4 are input and five output bars for outputting data are spaced apart from each other. Is provided.
  • the four input bars are referred to as a first input bar, a second input bar, a third input bar, and a fourth input bar in order from the top of the drawing.
  • the five output bars are referred to as a first output bar, a second output bar, a third output bar, a fourth output bar, and a fifth output bar in order from the left side of the drawing.
  • the crossbar SW65 When the quota related to the variable capacity control is input, the crossbar SW65 is connected to bars that intersect according to the quota, and by this connection, the data input from any of the input ports i1 to i4 is It is configured to output from any output bar.
  • the crossbar SW 66 has a configuration in which four output bars connected to output ports o1 to o4 to which data of four paths P1 to P4 are output and five input bars for inputting data are spaced apart from each other. Is provided.
  • the four output bars are referred to as a first output bar, a second output bar, a third output bar, and a fourth output bar in order from the top of the drawing.
  • the five input bars are referred to as a first input bar, a second input bar, a third input bar, a fourth input bar, and a fifth input bar in order from the left side of the drawing.
  • the crossbar SW 66 is configured to output data input from any of the input bars to the output ports o1 to o4 via any of the output bars by connecting the crossing bars according to the assigned amount. It has become.
  • each of the unit SRAMs 62a to 62e two adjacent unit SRAMs 62 are connected via a set of 1 ⁇ 2 selector 63 and 2 ⁇ 1 selector 64.
  • the first fixed portions 63b of all the 1 ⁇ 2 selectors 63 and the first fixed portions 64a of the 2 ⁇ 1 selector 64 are conductively connected.
  • the data input end of the unit SRAM 62a is connected to the first output bar of the crossbar SW65.
  • the data output end of the unit SRAM 62e is connected to the fifth input bar of the crossbar SW66.
  • the second fixed portion 63c of the 1 ⁇ 2 selector 63 between the unit SRAMs 62a and 62b is connected to the first input bar of the crossbar SW 66, and the second fixed portion 64b of the 2 ⁇ 1 selector 64 is connected to the second input bar of the crossbar SW65. Connected to output bar.
  • the second fixed portion 63c of the 1 ⁇ 2 selector 63 between the unit SRAMs 62b and 62c is connected to the second input bar of the crossbar SW 66, and the second fixed portion 64b of the 2 ⁇ 1 selector 64 is connected to the third Connected to output bar.
  • the second fixed part 63c of the 1 ⁇ 2 selector 63 between the unit SRAMs 62c and 62d is connected to the third input bar of the crossbar SW 66, and the second fixed part 64b of the 2 ⁇ 1 selector 64 is connected to the fourth input bar of the crossbar SW65. Connected to output bar.
  • the second fixed portion 63c of the 1 ⁇ 2 selector 63 between the unit SRAMs 62d and 62e is connected to the fourth input bar of the crossbar SW 66, and the second fixed portion 64b of the 2 ⁇ 1 selector 64 is connected to the fifth input bar of the crossbar SW65. Connected to output bar.
  • the variable capacity storage unit 41 switches and sets the state shown in FIG. 7 to the state shown in FIG. 8 as follows. That is, the movable portion 63a of the 1 ⁇ 2 selector 63 between the unit SRAMs 62b and 62c is connected to the second fixed portion 63c.
  • the crossbar SW65 is indicated by ⁇ k1
  • the first input bar connected to the input port i1 is connected to the first output bar (connection point k1)
  • the crossbar SW66 is indicated by ⁇ k5.
  • the second input bar connected to the second fixing portion 63c is connected to the first output bar connected to the output port o1 (connection point k5).
  • the data transmission path of the path P1 passes from the input port i1 through the connection point k1 of the crossbar SW65, passes through the two unit SRAMs 62a and 62b, and connects the connection point k5 of the 1 ⁇ 2 selector 63 to the crossbar SW66. It is formed so as to pass through to the output port o1. That is, as shown in FIG. 9A, a storage area is formed in the variable capacity storage unit 41 by the two unit SRAMs 62a and 62b during the passage from the input port i1 to the output port o1. This formation is performed dynamically without stopping the communicating communication devices 20a and 20b. The subsequent formation of the storage area is also performed dynamically.
  • the storage unit 41 replaces the movable unit 63a of the 2 ⁇ 1 selector 64 on the input side of the unit SRAM 62c with the second fixed unit. 63c, and the movable portion 63a of the 1 ⁇ 2 selector 63 on the output side of the unit SRAM 62c is connected to the second fixed portion 63c.
  • the crossbar SW65 is indicated by ⁇ k2
  • the second input bar connected to the input port i2 is connected to the third output bar (connection point k2)
  • the crossbar SW66 is indicated by ⁇ k6.
  • the third input bar connected to the second fixing portion 63c is connected to the second output bar connected to the output port o2 (connection point k6).
  • the data transmission path of the path P2 passes from the input port i2 through the connection point k2 of the crossbar SW 65 to one unit SRAM 62c, and from the 1 ⁇ 2 selector 63 on the output side of the unit SRAM 62c to the crossbar SW 66 Through the connection point k6 to the output port o2. That is, as shown in FIG. 9B, a storage area of one unit SRAM 62c is dynamically formed in the storage unit 41 during the passage from the input port i2 to the output port o2.
  • the storage unit 41 stores the input side of the unit SRAM 62d at the connection point k3 of the crossbar SW 65 via the 2 ⁇ 1 selector 64.
  • the output side of the unit SRAM 62 d is connected to the connection point k 7 of the crossbar SW 66 via the 1 ⁇ 2 selector 63.
  • the data transmission path of the path P3 passes from the input port i3 through the connection point k3, through one unit SRAM 62d, and from the 1 ⁇ 2 selector 63 on the output side to the output port o2 through the connection point k7. It is formed as follows. That is, as shown in FIG. 9C, a storage area by one unit SRAM 62d is dynamically formed in the storage unit 41 during the passage from the input port i3 to the output port o3.
  • the storage unit 41 connects the input side of the unit SRAM 62e to the connection point k4 of the crossbar SW 65 via the 2 ⁇ 1 selector 64. Then, the output side of the unit SRAM 62e is connected to the connection point k8 of the crossbar SW66.
  • the data transmission path of the path P4 is formed so as to pass from the input port i4 through the connection point k4, through one unit SRAM 62e, through the connection point k8 to the output port o4. That is, as shown in FIG. 9D, a storage area of one unit SRAM 62e is dynamically formed in the storage unit 41 during the passage from the input port i4 to the output port o4.
  • variable capacity control unit 42 responds to the path amount in the path P4 state from the uninterrupted transmission / reception unit 44a related to the path number P4.
  • the storage area 41 a of the path P ⁇ b> 4 can be allocated to the variable-capacity storage unit 41 by increasing or decreasing.
  • control unit 42 can allocate the storage area 41b of the path P3 to the storage unit 41 with the allocation amount according to the path amount in the path P3 state from the hitless transmission / reception unit 44b related to the path number P3. Moreover, the control unit 42 can allocate the storage area 41c of the path P1 to the storage unit 41 with the allocation amount according to the path amount in the path P1 state from the hitless transmission / reception unit 44c related to the path number P1. Become.
  • the storage capacity can be varied by changing the number of unit SRAMs 62, the storage capacity can be freely increased or decreased within the maximum storage capacity of the storage unit 41.
  • a unit SDRAM may be used instead of the unit SRAM 62.
  • step S1 an instruction signal for externally changing the storage capacity is input to the variable capacity control unit 42 of each of the communication devices 20a and 20b. Thereby, the control unit 42 can perform the variable capacity control.
  • step S2 the control unit 42 notifies the capacity variable control to the hitless transmission / reception unit 44a, and the hitless transmission / reception unit 44a sets the switching unit 55 and the copy unit 52 to the capacity variable control compatible state (see FIG. 5). Switch to
  • step S3 the hitless transmission / reception unit 44a validates the deletion processing of the specific packet deletion units 54a and 54b and the insertion processing of the specific packet insertion units 53a and 53b.
  • step S4 for example, the specific packet insertion units 53a and 53b of the hitless transmission / reception unit 44a2 (FIG. 3) in the communication device 20b generate a specific packet with a sequence number (for example, No. 5), and The packet is transmitted to the right and left routes at the same time.
  • a sequence number for example, No. 5
  • step S5 the specific packet deletion units 54a and 54b of the hitless transmission / reception unit 44a1 (FIG. 3) in the communication device 20a receive the numbered specific packets transmitted from the left and right paths. Is notified to the variable capacity control unit 42. After this output, the specific packet is deleted.
  • step S6 the control unit 42 obtains a reception time difference from both the right and left specific packet reception times, obtains a path amount (data capacity) according to the reception time difference, and obtains an allocation amount corresponding to the path amount. It is assumed that this allocation amount is the path amount of the two unit SRAMs 62a and 62b of the path P1 (see FIG. 9A).
  • step S7 the control unit 42 performs variable capacity control on the variable capacity storage unit 41 of the memory device 40 using the allocated amount.
  • step S8 the variable capacity storage unit 41 expands the storage area 41c (FIG. 2) of the path P1 according to the variable capacity control as follows. That is, the variable capacity storage unit 41 shown in FIG. 8 connects the movable unit 63a of the 1 ⁇ 2 selector 63 between the unit SRAMs 62b and 62c to the second fixed unit 63c according to the variable capacity control. Furthermore, a connection point k1 is formed by connecting the intersections of the crossbar SW65, and a connection point k5 is formed by connecting the intersections of the crossbar SW66.
  • the data transmission path of the path P4 passes from the input port i1 to the output port o1 via the connection point k1 and the two unit SRAMs 62a and 62b, and from the 1 ⁇ 2 selector 63 to the output port o1 via the connection point k5. Formed. That is, the storage area 41c of the path P1 by the two unit SRAMs 62a and 62b during the passage from the input port i1 to the output port o1 is formed in the variable capacity storage unit 41.
  • step S9 the control unit 42 notifies the non-instantaneous interruption transmission / reception unit 44a of the end of the variable capacity control.
  • step S10 based on the above notification, the hitless transmission / reception unit 44a returns the switching unit 55 and the duplication unit 52 to the normal operation state, stops the specific packet insertion processing of the specific packet insertion units 53a and 53b, and deletes the specific packet. The processing of deleting the specific packet by the units 54a and 54b is stopped.
  • the dynamic variable capacity memory device 40 is mounted on a plurality of communication devices 20a to 20d that communicate with each other via a bidirectional path, and is configured by an electronic circuit that is a gate array capable of changing a circuit configuration capable of storing data. ing.
  • This memory device 40 was configured as follows.
  • the dynamic variable-capacity memory device 40 includes a storage unit 41 using a storage circuit (FPGA) using an electronic circuit, which is a gate array capable of storing data.
  • a capacity variable control for forming a storage area of a storage capacity according to the allocated amount in the storage unit 41 by a storage circuit is performed by obtaining an allocated amount corresponding to a data capacity capable of transmitting a path between the communication devices 20a to 20d.
  • a control unit 42 for performing the control.
  • the memory device 40 includes the storage unit 41 that can change the configuration of the storage circuit that stores data. Then, the control unit 42 calculates an assigned amount corresponding to the data capacity that can be transmitted through the path between the communication devices 20a to 20d. Further, the control unit 42 can form a storage area for storing the data of the path in the storage unit 41 by the storage circuit by the capacity variable control according to the allocated amount. Therefore, it is possible to increase or decrease the storage area by changing the data storage capacity without stopping the communication devices 20a to 20d.
  • the storage circuit is configured using a plurality of unit memories such as a unit SRAM 62 in which a plurality of electronic storage elements such as a block SRAM are integrated.
  • a configuration is employed in which a storage area is formed by connecting a number of unit memories corresponding to a storage capacity corresponding to the allocated amount.
  • a storage area capable of accommodating the data capacity of the corresponding path can be easily formed in the storage unit 41 in accordance with the assigned amount corresponding to the data capacity that can be transmitted through the path between the communication devices 20a to 20d.
  • the dynamic variable capacity memory device 40 includes an insertion unit (specific packet insertion units 53a and 53b) and a deletion unit (specific packet deletion units 54a and 54b).
  • the inserter generates a specific packet with a unique number (sequence number) and transmits the specific packet to a bidirectional path when the variable capacity control is possible.
  • the deletion unit notifies the control unit 42 of the reception time of each bidirectional path when receiving the specific packet with the unique number transmitted from the bidirectional path when the variable capacity control is possible. Delete the specific packet after notification.
  • the control unit 42 is configured to calculate the reception time difference from the reception time for each bidirectional path, obtain the data capacity of the path according to the reception time difference, and obtain the assigned amount corresponding to the data capacity.
  • variable capacity control unit 42 uses the other GA circuit storage unit 47 of the FPGA other than the variable capacity storage unit 41 in the dynamic variable capacity memory device 40 as a storage unit for data storage. May be used. That is, the other GA circuit storage unit 47 uses an unused FPGA in the dynamic variable capacity memory device 40 as a storage unit.
  • the other GA circuit storage unit 47 constitutes another storage unit described in the claims.
  • Operation control in the case where a storage area having a storage capacity corresponding to the pass amount is assigned to the other GA circuit storage unit 47 is the same as the control in the storage unit 41 described above. According to this configuration, the storage area can be allocated to the other GA circuit storage unit 47 when the entire storage area of the storage unit 41 is used. Therefore, the storage capacity of the memory device 40 can be easily increased dynamically.

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Abstract

[Problem] To make a data storage capacity variable and to increase or reduce the storage area in a device mounted in a communication device, without stopping the communication device. [Solution] A dynamic variable capacity memory device 40 is mounted in a plurality of communication devices 20a-20d that communicate with each other via a bidirectional path, and is configured from an electronic circuit that is a gate array, which has a variable circuit configuration is capable of storing data. The dynamic variable capacity memory device 40 comprises a storage unit in which there is used a storage circuit (FPGA) based on an electronic circuit that is a gate array capable of storing data. The dynamic variable capacity memory device 40 is also configured to comprise a control unit that: establishes an allotment that corresponds to a data capacity transmittable through a path between the communication devices 20a-20d; and performs a capacity variable control for forming, with a storage circuit, a storage area of storage capacity for storing data of the corresponding path in the storage unit, in accordance with the allotment.

Description

動的可変容量メモリ装置及び記憶容量動的可変方法Dynamic variable capacity memory device and storage capacity dynamic variable method
　本発明は、通信ネットワークにおいて通信装置に搭載されるメモリ装置の記憶容量を変えることが可能な動的可変容量メモリ装置及び記憶容量動的可変方法に関する。 The present invention relates to a dynamic variable-capacity memory device capable of changing a storage capacity of a memory device mounted on a communication device in a communication network, and a dynamic storage-capacity variable method.
　従来、通信ネットワークにおいて互いに通信を行う複数の通信装置は個々にメモリ装置を備え、メモリ装置に通信用のデータを読み書きする処理を行っている。
　例えば、メモリ装置としての特許文献１に記載のパケットバッファ装置は、メモリ部、書込ブロックバッファ及び読出ブロックバッファを備える。メモリ部には、ＳＤＲＡＭ（Synchronous Dynamic Random Access Memory）や、ＳＲＡＭ（Static Random Access Memory）が適用されている。 2. Description of the Related Art Conventionally, a plurality of communication devices that communicate with each other in a communication network each have a memory device, and perform a process of reading and writing data for communication in the memory device.
For example, a packet buffer device described in Patent Document 1 as a memory device includes a memory unit, a write block buffer, and a read block buffer. An SDRAM (Synchronous Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) is applied to the memory unit.
　このようなパケットバッファ装置において、入力パケットデータを書込ブロックバッファへ順次格納し、書込ブロックバッファに所定量のデータが格納された時点で、当該データをメモリ部へ書き込む。また、出力指示に応じて、メモリ部からデータを読み出して読出ブロックバッファへ格納し、この格納データに含まれる各パケットデータを読み出して出力する動作が行われている。 In such a packet buffer device, input packet data is sequentially stored in the write block buffer, and when a predetermined amount of data is stored in the write block buffer, the data is written to the memory unit. Further, in response to an output instruction, data is read from the memory unit, stored in the read block buffer, and each packet data included in the stored data is read and output.
特開２０１３－１３５３８３号公報JP 2013-135383 A
　しかし、上記特許文献１のパケットバッファ装置において通信用のデータを記憶するメモリ部は、ＳＤＲＡＭやＳＲＡＭで構成されているため記憶容量が固定となっている。このため、通信のデータ量の増加に伴いメモリ部の記憶容量が不足すると通信データを保持できなくなってデータを失うことになる。 However, in the packet buffer device disclosed in Patent Document 1, the memory unit for storing communication data has a fixed storage capacity because it is composed of an SDRAM or an SRAM. For this reason, if the storage capacity of the memory unit is insufficient due to an increase in the amount of communication data, communication data cannot be held and data is lost.
　そこで、メモリ部の記憶容量の増設が必要な場合、パケットバッファ装置を含む通信装置自体の動作を一旦停止する。この後、ＳＤＲＡＭやＳＲＡＭを追加して増設したり、現在よりも大容量のＳＤＲＡＭやＳＲＡＭに交換したりする等の増設処理を行う必要がある。従って、メモリ部の記憶容量増設のために通信装置を一旦停止しなければならない問題がある。通信装置を停止すると通信動作に支障を来す不具合が生じる。 Therefore, when the storage capacity of the memory unit needs to be increased, the operation of the communication device itself including the packet buffer device is temporarily stopped. After that, it is necessary to perform additional processing such as adding an SDRAM or an SRAM and replacing the SDRAM or the SRAM with a larger capacity than the current one. Therefore, there is a problem that the communication device must be temporarily stopped in order to increase the storage capacity of the memory unit. Stopping the communication device causes a problem that hinders the communication operation.
　本発明は、このような事情に鑑みてなされたものであり、通信装置に搭載され、この通信装置を停止すること無くデータの記憶容量を可変して記憶領域を増設又は減設できる動的可変容量メモリ装置及び記憶容量動的可変方法を提供することを課題とする。 SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is provided in a communication device. A dynamic variable device capable of increasing or decreasing a storage area by changing a data storage capacity without stopping the communication device. It is an object to provide a capacity memory device and a method of dynamically changing a storage capacity.
　上記課題を解決するための手段として、請求項１に係る発明は、双方向のパスを介して互いに通信を行う複数の通信装置に搭載され、データを記憶可能な回路構成を可変できる電子回路により構成された動的可変容量メモリ装置であって、前記電子回路による記憶回路を用いた記憶部と、前記通信装置間のパスを伝送可能なデータ容量に対応する割当量を求め、当該割当量に応じた記憶容量の記憶領域を前記記憶部に記憶回路で形成する容量可変制御を行う制御部とを備えることを特徴とする動的可変容量メモリ装置である。 As a means for solving the above problems, the invention according to claim 1 is provided by an electronic circuit mounted on a plurality of communication devices that communicate with each other via a bidirectional path and capable of changing a circuit configuration capable of storing data. In the configured dynamic variable capacity memory device, a storage unit using a storage circuit by the electronic circuit, an allocation amount corresponding to a data capacity capable of transmitting a path between the communication devices is determined, and the allocation amount is determined. A dynamic variable-capacity memory device, comprising: a control unit for performing variable-capacity control in which a storage area having a corresponding storage capacity is formed in the storage unit by a storage circuit.
　請求項５に係る発明は、双方向のパスを介して互いに通信を行う複数の通信装置に搭載され、データを記憶可能な回路構成を可変できる電子回路により構成された動的可変容量メモリ装置による記憶容量動的可変方法であって、前記動的可変容量メモリ装置は、前記電子回路による記憶回路を搭載し、当該記憶回路の構成が可変できる記憶部を備え、前記通信装置間のパスを伝送するデータ容量に対応する割当量を求めるステップと、前記割当量に応じた記憶容量の記憶領域を前記記憶部に記憶回路で形成する容量可変制御を行うステップとを実行することを特徴とする記憶容量動的可変方法である。 According to a fifth aspect of the present invention, there is provided a dynamic variable capacity memory device which is mounted on a plurality of communication devices that communicate with each other via a bidirectional path and is configured by an electronic circuit capable of changing a circuit configuration capable of storing data. A method of dynamically changing a storage capacity, wherein the dynamic variable capacity memory device includes a storage circuit including the electronic circuit, and includes a storage unit capable of changing a configuration of the storage circuit, and transmits a path between the communication devices. Determining an allocation amount corresponding to the data amount to be performed, and performing a variable capacity control of forming a storage area of the storage capacity according to the allocation amount in the storage unit by a storage circuit. This is a dynamic capacity variable method.
　請求項１の構成及び請求項５の方法によれば、動的可変容量メモリ装置は、データを記憶する記憶回路の構成が可変できる記憶部を備える。そして、制御部で、通信装置間のパスを伝送可能なデータ容量に対応する割当量を求める。更に、制御部で、その割当量に応じた容量可変制御によって、記憶部に当該パスのデータを記憶する記憶領域を記憶回路で形成することが可能となる。このため、通信装置を停止すること無く、動的可変容量メモリ装置のデータの記憶容量を可変して記憶領域を増設又は減設することができる。 According to the configuration of claim 1 and the method of claim 5, the dynamic variable-capacity memory device includes a storage unit that can change the configuration of a storage circuit that stores data. Then, the control unit obtains an assigned amount corresponding to a data capacity capable of transmitting a path between the communication devices. Further, the control unit can form a storage area for storing the data of the path in the storage unit by the storage circuit by the capacity variable control according to the assigned amount. Therefore, without stopping the communication device, it is possible to increase or decrease the storage area by changing the data storage capacity of the dynamic variable capacity memory device.
　請求項２に係る発明は、前記記憶回路は、電子記憶素子を複数纏めた単位メモリを複数用いて構成され、前記割当量に応じた記憶容量に対応する数の単位メモリが接続されて記憶領域が形成されることを特徴とする請求項１に記載の動的可変容量メモリ装置である。 The invention according to claim 2, wherein the storage circuit is configured by using a plurality of unit memories in which a plurality of electronic storage elements are integrated, and is connected to a number of unit memories corresponding to a storage capacity according to the allocated amount, and is connected to a storage area. 2. The dynamic variable capacity memory device according to claim 1, wherein
　この構成によれば、通信装置間のパスを伝送可能なデータ容量に対応する割当量に応じて、記憶部に該当パスのデータ容量を収容可能な記憶領域を容易に形成できる。 According to this configuration, a storage area capable of accommodating the data capacity of the corresponding path can be easily formed in the storage unit according to the assigned amount corresponding to the data capacity capable of transmitting the path between the communication devices.
　請求項３に係る発明は、前記容量可変制御が可能な場合において、固有番号を付けた特定パケットを生成して前記双方向のパスへ送信する挿入部と、前記双方向のパスから送信されてきた固有番号付きの特定パケットを受信時に、当該双方向のパス毎の受信時刻を前記制御部へ通知し、この通知後に特定パケットを削除する削除部とを備え、前記制御部は、前記双方向のパス毎の受信時刻から受信時刻差を求め、この受信時刻差に応じたパスのデータ容量を求め、このデータ容量に対応する割当量を求めることを特徴とする請求項１又は２に記載の動的可変容量メモリ装置である。 According to a third aspect of the present invention, when the variable capacity control is possible, a specific packet with a unique number is generated and transmitted to the bidirectional path, and the packet is transmitted from the bidirectional path. A receiving unit that notifies the control unit of the reception time of each bidirectional path when receiving the specific packet with the unique number, and a deleting unit that deletes the specific packet after the notification. 3. The reception time difference is obtained from the reception time of each path, the data capacity of the path according to the reception time difference is obtained, and the quota corresponding to the data capacity is obtained. It is a dynamic variable capacity memory device.
　この構成によれば、通信装置間のパスをデータが伝送中に、このパスのデータ容量に対応する割当量を求めることができる。このため、実際のパスのデータ容量に応じて記憶部の記憶容量を可変できるので、記憶部の記憶サイズを最小限で構成できる。 According to this configuration, while data is being transmitted on the path between the communication devices, the quota corresponding to the data capacity of this path can be obtained. For this reason, the storage capacity of the storage unit can be changed according to the data capacity of the actual path, so that the storage size of the storage unit can be minimized.
　請求項４に係る発明は、前記記憶部以外の未使用の電子回路を他記憶部として用い、前記制御部は、前記割当量に応じて、前記他記憶部に前記パスのデータを記憶する記憶容量の記憶領域を形成することを特徴とする請求項１～３の何れか１項に記載の動的可変容量メモリ装置である。 The invention according to claim 4, wherein an unused electronic circuit other than the storage unit is used as another storage unit, and the control unit stores the data of the path in the other storage unit according to the allocation amount. The dynamic variable capacity memory device according to any one of claims 1 to 3, wherein a storage area having a capacity is formed.
　この構成によれば、動的可変容量メモリ装置内の記憶部以外の未使用の他記憶部に、パス量に応じた記憶容量の記憶領域を割り当てることができるので、記憶容量を容易に増加することができる。 According to this configuration, a storage area having a storage capacity corresponding to the path amount can be allocated to another unused storage unit other than the storage unit in the dynamic variable capacity memory device, so that the storage capacity is easily increased. be able to.
　本発明によれば、通信装置に搭載され、この通信装置を停止すること無くデータの記憶容量を可変して記憶領域を増設又は減設する動的可変容量メモリ装置及び記憶容量動的可変方法を提供することができる。 According to the present invention, there is provided a dynamic variable-capacity memory device and a storage-capacity dynamic variable method, which are mounted on a communication device and vary the storage capacity of data to increase or decrease the storage area without stopping the communication device. Can be provided.
本発明の実施形態に係る動的可変容量メモリ装置を搭載した通信装置を有する通信ＮＷの構成を示すブロック図である。1 is a block diagram illustrating a configuration of a communication network having a communication device equipped with a dynamic variable capacity memory device according to an embodiment of the present invention. 動的可変容量メモリ装置の構成を示すブロック図である。FIG. 3 is a block diagram illustrating a configuration of a dynamic variable capacity memory device. 右回り経路及び左回り経路で接続された通信装置の無瞬断送受信部の構成を示すブロック図である。FIG. 3 is a block diagram illustrating a configuration of a non-instantaneous interruption transmission / reception unit of a communication device connected by a clockwise route and a counterclockwise route. 通常動作時の無瞬断送受信部の構成を示すブロック図である。FIG. 3 is a block diagram illustrating a configuration of a hitless transmission / reception unit during normal operation. 容量可変制御時の無瞬断送受信部の構成を示すブロック図である。FIG. 3 is a block diagram illustrating a configuration of a hitless transmission / reception unit during variable capacity control. ブロックＳＲＡＭ及び単位ＳＲＡＭを示す図である。FIG. 3 is a diagram showing a block SRAM and a unit SRAM. 可変容量記憶部の構成を示すブロック図である。FIG. 3 is a block diagram illustrating a configuration of a variable capacity storage unit. 可変容量記憶部の単位ＳＲＡＭを接続して記憶領域を形成する構成を示すブロック図である。FIG. 3 is a block diagram illustrating a configuration in which unit SRAMs of a variable capacity storage unit are connected to form a storage area. 入力ポートから出力ポートへ抜ける間の単位ＳＲＡＭによる記憶領域を示し、（ａ）は入力ポートｉ１から出力ポートｏ１間の２つの単位ＳＲＡＭを示す図、（ｂ）は入力ポートｉ２から出力ポートｏ２間の１つの単位ＳＲＡＭを示す図、（ｃ）は入力ポートｉ３から出力ポートｏ３間の１つの単位ＳＲＡＭを示す図、（ｄ）は入力ポートｉ４から出力ポートｏ４間の１つの単位ＳＲＡＭを示す図である。FIG. 4A shows a storage area by a unit SRAM during an exit from an input port to an output port, FIG. 4A shows two unit SRAMs between an input port i1 and an output port o1, and FIG. 4B shows a storage area between an input port i2 and an output port o2. (C) is a diagram showing one unit SRAM between the input port i3 and the output port o3, and (d) is a diagram showing one unit SRAM between the input port i4 and the output port o4. It is. 動的可変容量メモリ装置によるメモリ容量動的可変の動作を説明するためのフローチャートである。5 is a flowchart for explaining an operation of dynamically changing the memory capacity by the dynamic variable capacity memory device. 動的可変容量メモリ装置に他ＧＡ回路記憶部を追加使用する際の構成を示すブロック図である。FIG. 9 is a block diagram illustrating a configuration when another GA circuit storage unit is additionally used in the dynamic variable capacity memory device.
　以下、本発明の実施形態を、図面を参照して説明する。但し、本明細書の全図において対応する構成部分には同一符号を付し、その説明を適宜省略する。
＜実施形態の構成＞
　図１は、本発明の実施形態に係る動的可変容量メモリ装置を搭載した通信装置を有する通信ＮＷ（ネットワーク）の構成を示すブロック図である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings in this specification, corresponding components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
<Configuration of the embodiment>
FIG. 1 is a block diagram showing a configuration of a communication NW (network) having a communication device equipped with a dynamic variable capacity memory device according to an embodiment of the present invention.
　図１に示す通信ＮＷ１０は、複数（４つ）の通信装置２０ａ，２０ｂ，２０ｃ，２０ｄが双方向２系統の伝送路によりリング状に接続されている。伝送路は、左回り経路と右回り経路とに分かれており、光ファイバを用いた光ケーブルや導電線等を用いた電気ケーブルを用いて構成されている。 The communication NW 10 shown in FIG. 1 has a plurality (four) of communication devices 20a, 20b, 20c, and 20d connected in a ring by two-way transmission lines. The transmission line is divided into a left-handed route and a right-handed route, and is configured using an optical cable using an optical fiber or an electric cable using a conductive wire or the like.
　通信装置２０ａ～２０ｄは、通信装置２０ａ～２０ｄ同士の通信並びに図示せぬパーソナルコンピュータ等の通信端末機との通信処理を行う。この通信装置２０ａ～２０ｄは、コンピュータを用いた通信制御部３０と、本実施形態の特徴要素である動的可変容量メモリ装置４０とを備える。 The communication devices 20a to 20d perform communication between the communication devices 20a to 20d and communication processing with a communication terminal such as a personal computer (not shown). Each of the communication devices 20a to 20d includes a communication control unit 30 using a computer, and a dynamic variable capacity memory device 40 which is a characteristic element of the present embodiment.
　動的可変容量メモリ装置（メモリ装置ともいう）４０は、電子回路による記憶回路の構成が可変できるゲートアレイによるＦＰＧＡ（Field-Programmable Gate Array）を用いて構成されている。ＦＰＧＡには所定記憶容量の記憶領域を割り当てることができる。この記憶領域は、一般的に、メモリ装置４０のＦＰＧＡをコンフィグレーション（設定）する際に行われ、通信装置２０ａ～２０ｄの動作中に変更することはできない。しかし、本実施形態では、後述のようにその動作中に変更可能とした。 The dynamic variable-capacity memory device (also referred to as a memory device) 40 is configured using an FPGA (Field-Programmable Gate に よ る Array) using a gate array in which the configuration of a storage circuit using an electronic circuit is variable. A storage area of a predetermined storage capacity can be allocated to the FPGA. This storage area is generally used when configuring (setting) the FPGA of the memory device 40, and cannot be changed during the operation of the communication devices 20a to 20d. However, in the present embodiment, it can be changed during the operation as described later.
　メモリ装置４０は、図２に示すように、可変容量記憶部４１と、容量可変制御部４２と、ラベルスイッチ４３と、無瞬断送受信部４４ａ，４４ｂ，４４ｃと、イーサネット（登録商標）スイッチ４５とを備えて構成されている。 As shown in FIG. 2, the memory device 40 includes a variable capacity storage section 41, a variable capacity control section 42, a label switch 43, instantaneous interruption transmission / reception sections 44a, 44b, 44c, and an Ethernet (registered trademark) switch 45. It is comprised including.
　ラベルスイッチ４３は、ＭＰＬＳ－ＴＰ（Multi-Protocol Label Switching-Transport Profile）と呼ばれるパケットトランスポート技術に基づき、固定長識別識のラベルで示される宛先に、無瞬断送受信部４４ａ～４４ｃから入力されるデータを左右の経路へ転送するスイッチング動作を行う。また、ラベルスイッチ４３は、左右の経路から受信されたデータを可変容量記憶部（記憶部ともいう）４１へ書き込み、この書き込まれたデータを読み出して無瞬断送受信部４４ａ～４４ｃへ出力する。 The label switch 43 is input from the uninterrupted transmission / reception units 44a to 44c to a destination indicated by a label of a fixed length identification based on a packet transport technology called MPLS-TP (Multi-Protocol Label Switching Switching Transport Profile). A switching operation is performed to transfer the data to the left and right paths. The label switch 43 writes data received from the left and right paths into the variable capacity storage unit (also referred to as a storage unit) 41, reads out the written data, and outputs the read data to the hitless transmission / reception units 44a to 44c.
　イーサネットスイッチ４５は、通信制御部３０が通信端末機（図示せず）から受信したデータを、このデータの先頭に固有のＭＡＣ（Media Access Control）アドレスを付けてイーサネットフレーム信号（フレーム信号ともいう）に変換する。更に、イーサネットスイッチ４５は、その変換されたフレーム信号のＭＡＣアドレスが示す宛先へ、フレーム信号を転送するスイッチング動作を行う。 The Ethernet switch 45 attaches a unique MAC (Media Access Control) address to the head of the data received by the communication control unit 30 from a communication terminal (not shown), and adds an Ethernet frame signal (also referred to as a frame signal). Convert to Further, the Ethernet switch 45 performs a switching operation of transferring the frame signal to the destination indicated by the MAC address of the converted frame signal.
　無瞬断送受信部４４ａ～４４ｃは、何れも同構成であり、ＭＰＬＳ－ＴＰのパケットトランスポート技術に基づき、通信相手側の通信装置からの信号を無瞬断で受信し、また相手側の通信装置へ信号を無瞬断で送信する動作を行う。この無瞬断送受信部４４ａ～４４ｃは、通信装置２０ａ～２０ｄ間を接続する２系統の伝送路（パス）に伝送されるデータの状態（パス状態）を検出して容量可変制御部（制御部ともいう）４２へ通知する。なお、パス状態とは、データ受信時刻等である。 Each of the uninterrupted transmission / reception units 44a to 44c has the same configuration, receives a signal from a communication device on the communication partner side without any interruption based on the packet transport technology of the MPLS-TP, and communicates with the communication unit on the other end. An operation of transmitting a signal to the device without interruption is performed. The hitless transmission / reception units 44a to 44c detect the state (path state) of data transmitted to two transmission lines (paths) connecting the communication devices 20a to 20d, and change the capacity of the capacity control unit (control unit). ). Note that the path status is a data reception time or the like.
　また、無瞬断送受信部４４ａ～４４ｃは、図３に無瞬断送受信部４４ａを代表して示すように、シーケンスナンバ挿入部５１と、２レーンデータ複製部５２と、特定パケット挿入部５３ａ，５３ｂと、特定パケット削除部５４ａ，５４ｂと、ヒットレス切替部５５と、シーケンスナンバ削除部５６とを備えて構成されている。なお、特定パケット挿入部５３ａ，５３ｂは、請求項記載の挿入部を構成する。特定パケット削除部５４ａ，５４ｂは、請求項記載の削除部を構成する。 The hitless transmission / reception units 44a to 44c include a sequence number insertion unit 51, a two-lane data duplication unit 52, a specific packet insertion unit 53a, 53b, specific packet deletion units 54a and 54b, hitless switching unit 55, and sequence number deletion unit 56. The specific packet insertion units 53a and 53b constitute an insertion unit described in the claims. The specific packet deletion units 54a and 54b constitute a deletion unit described in the claims.
　但し、図３には、通信装置２０ａの無瞬断送受信部４４ａ１と、通信装置２０ｂの無瞬断送受信部４４ａ２とが、パス番号Ｐ４（図２参照）の左右の経路で接続された状態を示す。なお、パス番号Ｐ４はパスＰ４とも称す。 However, FIG. 3 shows a state in which the hitless transmission / reception unit 44a1 of the communication device 20a and the hitless transmission / reception unit 44a2 of the communication device 20b are connected by the right and left paths of the path number P4 (see FIG. 2). Show. Note that the path number P4 is also referred to as a path P4.
　最初に、メモリ装置４０で通常動作が行われる場合に、無瞬断送受信部４４ａ１，４４ａ２が行う処理動作について説明する。なお、通常動作とは、後述の記憶容量を可変する動作を含まない動作である。 First, a description will be given of a processing operation performed by the hitless transmission / reception units 44a1 and 44a2 when a normal operation is performed in the memory device 40. Note that the normal operation is an operation that does not include an operation of changing a storage capacity described later.
　無瞬断送受信部４４ａ２において、シーケンスナンバ挿入部５１は、イーサネットスイッチ４５（図２）からのフレーム信号の先頭にシーケンス番号（シーケンスナンバ）を付けて、複製部５２へ出力する。そのシーケンス番号は、新たなイーサネットフレームに付けられる都度、１つずつ番号が上がるようになっている。なお、シーケンス番号を、単に番号とも称す。 In the uninterrupted transmission / reception unit 44a2, the sequence number insertion unit 51 attaches a sequence number (sequence number) to the head of the frame signal from the Ethernet switch 45 (FIG. 2) and outputs the frame signal to the duplication unit 52. The sequence number is incremented by one each time a new Ethernet frame is added. Note that the sequence number is also simply referred to as a number.
　２レーンデータ複製部（複製部ともいう）５２は、番号付のフレーム信号を２つに複製（図４の矢印Ｙ１ａ，Ｙ１ｂ参照）し、特定パケット挿入部５３ａ，５３ｂを介して左回り経路と右回り経路とに送信する。なお、特定パケット挿入部５３ａ，５３ｂは、通常動作時に信号を通過させる動作のみを行う。 The two-lane data copying unit (also referred to as a copying unit) 52 copies the numbered frame signal into two (see arrows Y1a and Y1b in FIG. 4), and connects to the counterclockwise path via the specific packet insertion units 53a and 53b. Send to the clockwise route. Note that the specific packet insertion units 53a and 53b perform only an operation of passing a signal during normal operation.
　次に、無瞬断送受信部４４ａ１において、特定パケット削除部５４ａ，５４ｂは、通常動作時において、左右の経路から送信されてきた番号付のフレーム信号を通過させてヒットレス切替部５５へ出力する動作を行う。 Next, in the uninterrupted transmission / reception unit 44a1, the specific packet deletion units 54a and 54b pass the numbered frame signals transmitted from the left and right paths and output the frame signals to the hitless switching unit 55 during normal operation. Perform the operation.
　ヒットレス切替部（切替部ともいう）５５は、通常動作時において、図４に矢印Ｙ２，Ｙ３で示すように左右の経路から受信されるフレーム信号を、番号順にシーケンスナンバ削除部５６へ出力する。この際、切替部５５は、左右何れかの経路から受信（例えば矢印Ｙ２）したフレーム信号の番号が、先に受信（例えば矢印Ｙ３）したフレーム信号の番号と同じか、又は小さい場合、このフレーム信号を削除（破棄）する。切替部５５は、このように番号が重複するフレーム信号の削除を行って、１つの番号順にフレーム信号を次のシーケンスナンバ削除部５６へ出力する。この削除部５６は、フレーム信号の番号を削除してイーサネットスイッチ４５（図２）へ出力する。 The hitless switching unit (also referred to as a switching unit) 55 outputs frame signals received from the left and right paths to the sequence number deletion unit 56 in numerical order during normal operation, as indicated by arrows Y2 and Y3 in FIG. . At this time, if the number of the frame signal received (for example, arrow Y2) from one of the left and right paths is the same as or smaller than the number of the frame signal previously received (for example, arrow Y3), the switching unit 55 Delete (discard) the signal. The switching unit 55 deletes the frame signals having the overlapping numbers as described above, and outputs the frame signals to the next sequence number deleting unit 56 in the order of one number. The deletion unit 56 deletes the frame signal number and outputs the frame signal number to the Ethernet switch 45 (FIG. 2).
　また、図３に示す切替部５５は、例えば、右回り経路（図４の矢印Ｙ２）から番号「５」が入力された後に、１つ飛んだ番号「７」が入力された場合、「６」が飛んだ可能性があるので「７」の出力を待つ。この待ち時に左回り経路（図４の矢印Ｙ３）から番号「６」が入力されると、この「６」を出力する。この際、右回り経路では、番号「５」の次に「７」が来たので、右回り経路で何らかの不具合が発生したことを示唆する。 In addition, for example, when the number “5” is input from the clockwise route (arrow Y2 in FIG. 4) and then the next skipped number “7” is input, the switching unit 55 illustrated in FIG. Wait for the output of "7" because there is a possibility that "has jumped. When the number “6” is input from the counterclockwise route (arrow Y3 in FIG. 4) during this waiting, the number “6” is output. At this time, on the clockwise route, since “7” comes after the number “5”, it indicates that some trouble has occurred in the clockwise route.
　このように切替部５５は、左右の経路から受信された同じ番号又は既に受信した番号よりも小さい番号を出力しない機能と、一方の経路が正常であれば、番号順にパケットを出力し続けることが可能な機能を有する。 As described above, the switching unit 55 has a function of not outputting the same number received from the left and right paths or a number smaller than the already received number, and if one of the paths is normal, it can continue to output packets in numerical order. Has a possible function.
　次に、容量可変制御部４２の容量可変制御によって、メモリ装置４０において記憶容量可変動作が行われる場合において、無瞬断送受信部４４ａ１，４４ａ２が行う処理動作について説明する。 Next, a description will be given of processing operations performed by the hitless transmission / reception units 44a1 and 44a2 when the storage capacity variable operation is performed in the memory device 40 by the capacity variable control of the capacity variable control unit 42.
　但し、容量可変制御部４２は、外部から記憶容量の可変を行う指示信号が入力された場合に、容量可変制御が可能となる。制御部４２は、メモリ装置４０に記憶容量が割り当てられていない初期状態であれば、パス毎に必要な記憶容量を割り当てる制御を行い、記憶容量が割り当てられていれば、必要な容量となるように、記憶容量を増設又は減設する容量可変制御を行うことになる。 However, the variable capacity control unit 42 can perform variable capacity control when an instruction signal for changing the storage capacity is input from outside. The control unit 42 performs control of allocating a required storage capacity for each path in an initial state in which the storage capacity is not allocated to the memory device 40, and if the storage capacity is allocated, the control unit 42 obtains the required capacity. Then, the capacity variable control for increasing or decreasing the storage capacity is performed.
　また、上記記憶容量可変動作が可能となった場合、無瞬断送受信部４４ａは、制御部４２との連携によって切替部５５及び複製部５２を、後述のように容量可変制御に対応した状態に切り替え、特定パケット削除部５４ａ，５４ｂの削除処理及び特定パケット挿入部５３ａ，５３ｂの挿入処理を有効とする。また、切替部５５及び複製部５２は、容量可変制御の終了が通知（制御状態通知）された際に通常動作の状態に戻る。 When the above-mentioned variable storage capacity operation is enabled, the uninterrupted transmission / reception unit 44a sets the switching unit 55 and the duplication unit 52 in a state corresponding to the variable capacity control as described later in cooperation with the control unit 42. Switching is performed, and the deletion processing of the specific packet deletion units 54a and 54b and the insertion processing of the specific packet insertion units 53a and 53b are validated. The switching unit 55 and the copying unit 52 return to the normal operation state when the end of the variable capacity control is notified (control state notification).
　図５に示すように、無瞬断送受信部４４ａにおいて、切替部５５は、一方の経路（例えば右回り経路）の選択を矢印Ｙ２で示すように有効とし、他方の経路（左回り経路）の選択を矢印Ｙ３の先に×印を付けて示すように無効とする処理を行う。また、複製部５２は、シーケンス番号が付されたフレーム信号を矢印Ｙ１の先に×印を付けて示すように、そのフレーム信号の出力を無効とする処理を行う。 As shown in FIG. 5, in the hitless transmission / reception unit 44a, the switching unit 55 makes the selection of one route (for example, the clockwise route) valid as indicated by the arrow Y2, and the selection of the other route (the counterclockwise route). A process is performed to invalidate the selection as indicated by an X mark at the end of the arrow Y3. In addition, the duplication unit 52 performs a process of invalidating the output of the frame signal to which the sequence number is assigned, as indicated by the X mark at the end of the arrow Y1.
　このような設定後、例えば図３に示す無瞬断送受信部４４ａ２において、特定パケット挿入部５３ａ，５３ｂは、シーケンス番号（例えば５番）を付けた特定パケットを生成し、この特定パケットを同時に左右の経路へ送信する。この送信は定期的に行われる。但し、特定パケットは、例えば、ネットワークの運用、管理、保守を行うためのＯＡＭ（Operations Administration Maintenance）パケットであるとする。 After such setting, the specific packet insertion units 53a and 53b generate specific packets with a sequence number (for example, No. 5) in the hitless transmission / reception unit 44a2 shown in FIG. To the route. This transmission is performed periodically. However, the specific packet is, for example, an OAM (Operations Administration Maintenance) packet for performing operation, management, and maintenance of the network.
　次に、無瞬断送受信部４４ａ１において、特定パケット削除部５４ａ，５４ｂは、右回り経路と左回り経路との双方から送信されてきたシーケンス番号付きのＯＡＭパケットを受信した際に、双方の受信時刻を容量可変制御部４２へ出力し、この出力後にＯＡＭパケットを削除する。なお、受信時刻は、パス状態として制御部４２へ通知される。 Next, in the uninterrupted transmission / reception unit 44a1, the specific packet deletion units 54a and 54b receive the OAM packet with the sequence number transmitted from both the clockwise route and the counterclockwise route. The time is output to the variable capacity control unit 42, and after this output, the OAM packet is deleted. Note that the reception time is notified to the control unit 42 as a path state.
　制御部４２は、双方のＯＡＭパケットの受信時刻から受信時刻差を求める。例えば、右回りの５番ＯＡＭパケットの受信時刻から１０秒後に左回りの５番ＯＡＭパケットが受信されたとすると、受信時刻差が１０秒と求められる。 The control unit 42 calculates a reception time difference from the reception times of both OAM packets. For example, if a counterclockwise fifth OAM packet is received 10 seconds after the reception time of the clockwise fifth OAM packet, the reception time difference is determined to be 10 seconds.
　制御部４２は、その受信時刻差に応じて、このパスのデータ容量（パス量）を示すｂｉｔ（ビット）を求める。これは、まず受信時刻差を距離差（例えば１ｋｍ）に換算する。次に、パスの速度の最大値（例えば１Ｇｂｐｓ）と、経路である光ファイバの遅延値（例えば５ｎｓ／ｍ）を乗算し、この乗算結果に上記距離差（１ｋｍ）を乗算してデータ容量を求める。即ち、１Ｇｂｉｔ×５ｎｓ／ｍ×１ｋｍ＝５ｋｂｉｔとデータ容量（パス量）が求められる。 The control unit 42 obtains a bit (bit) indicating the data capacity (path amount) of this path according to the reception time difference. For this, first, the reception time difference is converted into a distance difference (for example, 1 km). Next, the maximum value of the path speed (for example, 1 Gbps) is multiplied by the delay value (for example, 5 ns / m) of the optical fiber that is the path, and the multiplication result is multiplied by the distance difference (1 km) to reduce the data capacity. Ask. That is, a data capacity (path amount) of 1 Gbit × 5 ns / m × 1 km = 5 kbit is obtained.
　この５ｋｂｉｔのデータ容量は、右回り経路と、これよりも１ｋｍ距離が長い左回り経路との距離差に対応している。そこで、制御部４２は、可変容量記憶部（記憶部ともいう）４１に、そのデータ容量と同じ記憶容量の記憶領域（例えば図２の記憶領域４１ａ）を、パス４の右回り経路のデータ記憶用のものとして割り当てる。この割り当てられた記憶領域４１ａには、ラベルスイッチ４３（図２）でパスＰ４の右回り経路から受信した５番のデータが一旦保持される。この保持後、左回り経路からの同じ５番のデータが受信されるまで待てば、パスＰ４の左右経路の距離差を吸収可能となる。 The 5 kbit data capacity corresponds to the distance difference between the clockwise route and the counterclockwise route that is 1 km longer than this. Therefore, the control unit 42 stores a storage area (for example, the storage area 41a in FIG. 2) having the same storage capacity in the variable capacity storage unit ( Assign it for In the allocated storage area 41a, the fifth data received from the clockwise path of the path P4 by the label switch 43 (FIG. 2) is temporarily stored. After this holding, if the user waits until the same fifth data from the counterclockwise route is received, the distance difference between the left and right routes of the path P4 can be absorbed.
　制御部４２は、上記のように求められるパス（例えばパスＰ４）のパス量が、記憶部４１に割当済みの同パスＰ４の記憶領域４１ａの記憶容量よりも多い場合、多い分の記憶容量を割り当てる割当量を求める。また、パスＰ４のパス量を新規に割り当てる必要がある場合、割当量で示されるパス量のパスＰ４の記憶領域４１ａを、記憶部４１に新規に割り当てることになる。 When the path amount of the path (for example, path P4) obtained as described above is larger than the storage capacity of the storage area 41a of the same path P4 allocated to the storage unit 41, the control unit 42 increases the storage capacity of the larger amount. Find the quota to be assigned. When it is necessary to newly assign the path amount of the path P4, the storage area 41a of the path P4 having the path amount indicated by the assigned amount is newly assigned to the storage unit 41.
　割当量は、言い換えれば、パス量に対応する単位ＳＲＡＭ（後述）を割り当てるために必要なデータ容量を示す。この割当量による記憶部４１への記憶容量の動的割当について説明する。 In other words, the allocation amount indicates a data capacity required to allocate a unit SRAM (described later) corresponding to the path amount. The dynamic allocation of the storage capacity to the storage unit 41 based on this allocation amount will be described.
　前述したように、メモリ装置４０はＦＰＧＡ（図２参照）を用いて構成されている。可変容量記憶部４１は、図６に示すように、ＦＰＧＡにおいて８ｂｉｔ等の最小記憶単位と定めるブロックＳＲＡＭ６１を多数備える。なお、ＦＰＧＡは、請求項記載の記憶回路を構成する。また、ブロックＳＲＡＭ６１は、請求項記載の電子記憶素子を構成する。 As described above, the memory device 40 is configured using an FPGA (see FIG. 2). As shown in FIG. 6, the variable capacity storage unit 41 includes a large number of block SRAMs 61 each of which is defined as a minimum storage unit such as 8 bits in the FPGA. The FPGA constitutes a storage circuit described in the claims. Further, the block SRAM 61 constitutes an electronic storage element described in the claims.
　ブロックＳＲＡＭ６１を所定数（例えば８個）一纏めにして単位メモリとしての単位ＳＲＡＭ６２が構成されている。この単位ＳＲＡＭ６２は、例えば６４ｂｉｔのデータを入出力するポートを有する。単位ＳＲＡＭ６２の記憶容量は、例えば６４ｂｉｔ×５１２レコードであるとする。 (4) A predetermined number (for example, eight) of block SRAMs 61 are grouped together to constitute a unit SRAM 62 as a unit memory. The unit SRAM 62 has a port for inputting and outputting 64-bit data, for example. It is assumed that the storage capacity of the unit SRAM 62 is, for example, 64 bits × 512 records.
　可変容量記憶部４１には、単位ＳＲＡＭ６２を、所定ロジックに応じて複数組み合わせることで小容量から大容量まで任意の記憶容量の記憶領域を構成可能となっている。図７に示すように、記憶部４１は、複数の単位ＳＲＡＭ６２ａ，６２ｂ，６２ｃ，６２ｄ，６２ｅと、各単位ＳＲＡＭ６２ａ～６２ｅを接続するための１×２セレクタ６３と、２×１セレクタ６４と、入力ポートｉ１～ｉ４側のクロスバーＳＷ（switch）６５と、出力ポートｏ１～ｏ４側のクロスバーＳＷ６６とを備えて構成されている。 (4) In the variable capacity storage unit 41, a storage area having an arbitrary storage capacity from a small capacity to a large capacity can be configured by combining a plurality of unit SRAMs 62 according to a predetermined logic. As shown in FIG. 7, the storage unit 41 includes a plurality of unit SRAMs 62a, 62b, 62c, 62d, and 62e, a 1 × 2 selector 63 for connecting the unit SRAMs 62a to 62e, a 2 × 1 selector 64, A crossbar SW (switch) 65 for the input ports i1 to i4 and a crossbar SW66 for the output ports o1 to o4 are provided.
　１×２セレクタ６３は、データ入力側の１つの可動部６３ａが、第１固定部６３ｂ及び第２固定部６３ｃの何れかに接続されて、データを第１固定部６３ｂから出力するか、第２固定部６３ｃから出力するかを選択できる構成となっている。なお、可動部６３ａ、第１固定部６３ｂ及び第２固定部６３ｃの符号６３ａ～６３ｃは、図面最左側の１×２セレクタ６３に代表して示す。 The 1 × 2 selector 63 determines whether one movable portion 63a on the data input side is connected to one of the first fixed portion 63b and the second fixed portion 63c and outputs data from the first fixed portion 63b. It is configured to be able to select whether to output from the second fixed unit 63c. Reference numerals 63a to 63c of the movable portion 63a, the first fixed portion 63b, and the second fixed portion 63c are representatively shown as the 1 × 2 selector 63 on the leftmost side of the drawing.
　２×１セレクタ６４は、データ入力側の第１固定部６４ａ及び第２固定部６４ｂの何れかに、データ出力側の１つの可動部６４ｃを接続して、第１固定部６４ａから入力されたデータを可動部６４ｃから出力するか、第２固定部６４ｂから入力されたデータを可動部６４ｃから出力するかを選択できる構成となっている。なお、第１固定部６４ａ及び第２固定部６４ｂ、可動部６４ｃの符号６４ａ～６４ｃは、図面最左側の２×１セレクタ６４に代表して示す。 The 2 × 1 selector 64 connects one of the movable portions 64c on the data output side to one of the first fixed portion 64a and the second fixed portion 64b on the data input side, and is input from the first fixed portion 64a. The configuration is such that it is possible to select whether to output data from the movable section 64c or to output data input from the second fixed section 64b from the movable section 64c. Reference numerals 64a to 64c of the first fixed portion 64a, the second fixed portion 64b, and the movable portion 64c are representatively shown as the 2 × 1 selector 64 on the leftmost side of the drawing.
　クロスバーＳＷ６５は、４つのパスＰ１～Ｐ４のデータが入力される入力ポートｉ１～ｉ４に接続された４本の入力バーと、データを出力する５本の出力バーとが離間状に交差した構成を備える。その４本の入力バーは、図面上側から順に、第１入力バー、第２入力バー、第３入力バー、第４入力バーという。５本の出力バーは、図面左側から順に、第１出力バー、第２出力バー、第３出力バー、第４出力バー、第５出力バーという。このクロスバーＳＷ６５は、容量可変制御に係る割当量が入力されると、割当量に応じて交差するバーが接続され、この接続により、何れかの入力ポートｉ１～ｉ４から入力されたデータを、何れかの出力バーから出力する構成となっている。 The crossbar SW65 has a configuration in which four input bars connected to input ports i1 to i4 to which data of four paths P1 to P4 are input and five output bars for outputting data are spaced apart from each other. Is provided. The four input bars are referred to as a first input bar, a second input bar, a third input bar, and a fourth input bar in order from the top of the drawing. The five output bars are referred to as a first output bar, a second output bar, a third output bar, a fourth output bar, and a fifth output bar in order from the left side of the drawing. When the quota related to the variable capacity control is input, the crossbar SW65 is connected to bars that intersect according to the quota, and by this connection, the data input from any of the input ports i1 to i4 is It is configured to output from any output bar.
　クロスバーＳＷ６６は、４つのパスＰ１～Ｐ４のデータが出力される出力ポートｏ１～ｏ４に接続された４本の出力バーと、データを入力する５本の入力バーとが離間状に交差した構成を備える。その４本の出力バーは、図面上側から順に、第１出力バー、第２出力バー、第３出力バー、第４出力バーという。また、５本の入力バーは、図面左側から順に、第１入力バー、第２入力バー、第３入力バー、第４入力バー、第５入力バーという。このクロスバーＳＷ６６は、割当量に応じて交差するバーが接続されることにより、何れかの入力バーから入力されたデータを、何れかの出力バーを介して出力ポートｏ１～ｏ４へ出力する構成となっている。 The crossbar SW 66 has a configuration in which four output bars connected to output ports o1 to o4 to which data of four paths P1 to P4 are output and five input bars for inputting data are spaced apart from each other. Is provided. The four output bars are referred to as a first output bar, a second output bar, a third output bar, and a fourth output bar in order from the top of the drawing. The five input bars are referred to as a first input bar, a second input bar, a third input bar, a fourth input bar, and a fifth input bar in order from the left side of the drawing. The crossbar SW 66 is configured to output data input from any of the input bars to the output ports o1 to o4 via any of the output bars by connecting the crossing bars according to the assigned amount. It has become.
　各単位ＳＲＡＭ６２ａ～６２ｅは、隣り合う２つの単位ＳＲＡＭ６２が、１組の１×２セレクタ６３及び２×１セレクタ６４を介して接続されている。全ての１×２セレクタ６３の第１固定部６３ｂと、２×１セレクタ６４の第１固定部６４ａとは導電接続されている。単位ＳＲＡＭ６２ａのデータ入力端は、クロスバーＳＷ６５の第１出力バーに接続されている。単位ＳＲＡＭ６２ｅのデータ出力端は、クロスバーＳＷ６６の第５入力バーに接続されている。 (2) In each of the unit SRAMs 62a to 62e, two adjacent unit SRAMs 62 are connected via a set of 1 × 2 selector 63 and 2 × 1 selector 64. The first fixed portions 63b of all the 1 × 2 selectors 63 and the first fixed portions 64a of the 2 × 1 selector 64 are conductively connected. The data input end of the unit SRAM 62a is connected to the first output bar of the crossbar SW65. The data output end of the unit SRAM 62e is connected to the fifth input bar of the crossbar SW66.
　単位ＳＲＡＭ６２ａ，６２ｂ間の１×２セレクタ６３の第２固定部６３ｃは、クロスバーＳＷ６６の第１入力バーに接続され、２×１セレクタ６４の第２固定部６４ｂは、クロスバーＳＷ６５の第２出力バーに接続されている。 The second fixed portion 63c of the 1 × 2 selector 63 between the unit SRAMs 62a and 62b is connected to the first input bar of the crossbar SW 66, and the second fixed portion 64b of the 2 × 1 selector 64 is connected to the second input bar of the crossbar SW65. Connected to output bar.
　単位ＳＲＡＭ６２ｂ，６２ｃ間の１×２セレクタ６３の第２固定部６３ｃは、クロスバーＳＷ６６の第２入力バーに接続され、２×１セレクタ６４の第２固定部６４ｂは、クロスバーＳＷ６５の第３出力バーに接続されている。 The second fixed portion 63c of the 1 × 2 selector 63 between the unit SRAMs 62b and 62c is connected to the second input bar of the crossbar SW 66, and the second fixed portion 64b of the 2 × 1 selector 64 is connected to the third Connected to output bar.
　単位ＳＲＡＭ６２ｃ，６２ｄ間の１×２セレクタ６３の第２固定部６３ｃは、クロスバーＳＷ６６の第３入力バーに接続され、２×１セレクタ６４の第２固定部６４ｂは、クロスバーＳＷ６５の第４出力バーに接続されている。 The second fixed part 63c of the 1 × 2 selector 63 between the unit SRAMs 62c and 62d is connected to the third input bar of the crossbar SW 66, and the second fixed part 64b of the 2 × 1 selector 64 is connected to the fourth input bar of the crossbar SW65. Connected to output bar.
　単位ＳＲＡＭ６２ｄ，６２ｅ間の１×２セレクタ６３の第２固定部６３ｃは、クロスバーＳＷ６６の第４入力バーに接続され、２×１セレクタ６４の第２固定部６４ｂは、クロスバーＳＷ６５の第５出力バーに接続されている。 The second fixed portion 63c of the 1 × 2 selector 63 between the unit SRAMs 62d and 62e is connected to the fourth input bar of the crossbar SW 66, and the second fixed portion 64b of the 2 × 1 selector 64 is connected to the fifth input bar of the crossbar SW65. Connected to output bar.
　割当量が、例えばパスＰ１の２つの単位ＳＲＡＭ６２のパス量を示すものである場合、可変容量記憶部４１は、図７に示す状態から図８に示す状態に次のように切り替えて設定する。即ち、単位ＳＲＡＭ６２ｂ，６２ｃ間の１×２セレクタ６３の可動部６３ａを第２固定部６３ｃに接続する。また、クロスバーＳＷ６５を●ｋ１で示すように、入力ポートｉ１に繋がる第１入力バーと、第１出力バーとを接続する（接続点ｋ１）と共に、クロスバーＳＷ６６を●ｋ５で示すように、前記第２固定部６３ｃに繋がる第２入力バーと、出力ポートｏ１に繋がる第１出力バーとを接続する（接続点ｋ５）。 If the assigned amount indicates, for example, the path amount of the two unit SRAMs 62 of the path P1, the variable capacity storage unit 41 switches and sets the state shown in FIG. 7 to the state shown in FIG. 8 as follows. That is, the movable portion 63a of the 1 × 2 selector 63 between the unit SRAMs 62b and 62c is connected to the second fixed portion 63c. The crossbar SW65 is indicated by ● k1, the first input bar connected to the input port i1 is connected to the first output bar (connection point k1), and the crossbar SW66 is indicated by ● k5. The second input bar connected to the second fixing portion 63c is connected to the first output bar connected to the output port o1 (connection point k5).
　この接続によって、パスＰ１のデータ伝送経路が、入力ポートｉ１からクロスバーＳＷ６５の接続点ｋ１を通って２つの単位ＳＲＡＭ６２ａ，６２ｂを経由し、１×２セレクタ６３からクロスバーＳＷ６６の接続点ｋ５を通って出力ポートｏ１へ抜けるように形成される。つまり、図９（ａ）に示すように、可変容量記憶部４１に、入力ポートｉ１から出力ポートｏ１へ抜ける間の２つの単位ＳＲＡＭ６２ａ，６２ｂによる記憶領域が形成される。この形成は、通信中の通信装置２０ａ，２０ｂを停止することなく動的に行われる。以降の記憶領域の形成も同様に動的に行われる。 With this connection, the data transmission path of the path P1 passes from the input port i1 through the connection point k1 of the crossbar SW65, passes through the two unit SRAMs 62a and 62b, and connects the connection point k5 of the 1 × 2 selector 63 to the crossbar SW66. It is formed so as to pass through to the output port o1. That is, as shown in FIG. 9A, a storage area is formed in the variable capacity storage unit 41 by the two unit SRAMs 62a and 62b during the passage from the input port i1 to the output port o1. This formation is performed dynamically without stopping the communicating communication devices 20a and 20b. The subsequent formation of the storage area is also performed dynamically.
　次に、割当量が、例えばパスＰ２の１つの単位ＳＲＡＭ６２のパス量を示すものである場合、記憶部４１は、単位ＳＲＡＭ６２ｃの入力側の２×１セレクタ６４の可動部６３ａを第２固定部６３ｃに接続し、単位ＳＲＡＭ６２ｃの出力側の１×２セレクタ６３の可動部６３ａを第２固定部６３ｃに接続する。また、クロスバーＳＷ６５を●ｋ２で示すように、入力ポートｉ２に繋がる第２入力バーと、第３出力バーとを接続する（接続点ｋ２）と共に、クロスバーＳＷ６６を●ｋ６で示すように、前記第２固定部６３ｃに繋がる第３入力バーと、出力ポートｏ２に繋がる第２出力バーとを接続する（接続点ｋ６）。 Next, when the assigned amount indicates, for example, the path amount of one unit SRAM 62 of the path P2, the storage unit 41 replaces the movable unit 63a of the 2 × 1 selector 64 on the input side of the unit SRAM 62c with the second fixed unit. 63c, and the movable portion 63a of the 1 × 2 selector 63 on the output side of the unit SRAM 62c is connected to the second fixed portion 63c. The crossbar SW65 is indicated by ● k2, the second input bar connected to the input port i2 is connected to the third output bar (connection point k2), and the crossbar SW66 is indicated by ● k6. The third input bar connected to the second fixing portion 63c is connected to the second output bar connected to the output port o2 (connection point k6).
　この接続によって、パスＰ２のデータ伝送経路が、入力ポートｉ２からクロスバーＳＷ６５の接続点ｋ２を通って１つの単位ＳＲＡＭ６２ｃを経由し、この単位ＳＲＡＭ６２ｃの出力側の１×２セレクタ６３からクロスバーＳＷ６６の接続点ｋ６を通って出力ポートｏ２へ抜けるように形成される。つまり、図９（ｂ）に示すように、記憶部４１に、入力ポートｉ２から出力ポートｏ２へ抜ける間の１つの単位ＳＲＡＭ６２ｃによる記憶領域が動的に形成される。 With this connection, the data transmission path of the path P2 passes from the input port i2 through the connection point k2 of the crossbar SW 65 to one unit SRAM 62c, and from the 1 × 2 selector 63 on the output side of the unit SRAM 62c to the crossbar SW 66 Through the connection point k6 to the output port o2. That is, as shown in FIG. 9B, a storage area of one unit SRAM 62c is dynamically formed in the storage unit 41 during the passage from the input port i2 to the output port o2.
　同様に、割当量が、パスＰ３の１つの単位ＳＲＡＭ６２のパス量を示すものである場合、記憶部４１は、単位ＳＲＡＭ６２ｄの入力側が２×１セレクタ６４を介してクロスバーＳＷ６５の接続点ｋ３に接続され、単位ＳＲＡＭ６２ｄの出力側が１×２セレクタ６３を介してクロスバーＳＷ６６の接続点ｋ７に接続される。 Similarly, when the allocation amount indicates the path amount of one unit SRAM 62 of the path P3, the storage unit 41 stores the input side of the unit SRAM 62d at the connection point k3 of the crossbar SW 65 via the 2 × 1 selector 64. The output side of the unit SRAM 62 d is connected to the connection point k 7 of the crossbar SW 66 via the 1 × 2 selector 63.
　この接続によって、パスＰ３のデータ伝送経路が、入力ポートｉ３から接続点ｋ３を通って１つの単位ＳＲＡＭ６２ｄを介してこの出力側の１×２セレクタ６３から接続点ｋ７を通って出力ポートｏ２へ抜けるように形成される。つまり、図９（ｃ）に示すように、記憶部４１に、入力ポートｉ３から出力ポートｏ３へ抜ける間の１つの単位ＳＲＡＭ６２ｄによる記憶領域が動的に形成される。 With this connection, the data transmission path of the path P3 passes from the input port i3 through the connection point k3, through one unit SRAM 62d, and from the 1 × 2 selector 63 on the output side to the output port o2 through the connection point k7. It is formed as follows. That is, as shown in FIG. 9C, a storage area by one unit SRAM 62d is dynamically formed in the storage unit 41 during the passage from the input port i3 to the output port o3.
　また、割当量が、パスＰ４の１つの単位ＳＲＡＭ６２のパス量を示すものである場合、記憶部４１は、単位ＳＲＡＭ６２ｅの入力側が２×１セレクタ６４を介してクロスバーＳＷ６５の接続点ｋ４に接続され、単位ＳＲＡＭ６２ｅの出力側がクロスバーＳＷ６６の接続点ｋ８に接続される。 When the assigned amount indicates the path amount of one unit SRAM 62 of the path P4, the storage unit 41 connects the input side of the unit SRAM 62e to the connection point k4 of the crossbar SW 65 via the 2 × 1 selector 64. Then, the output side of the unit SRAM 62e is connected to the connection point k8 of the crossbar SW66.
　この接続によって、パスＰ４のデータ伝送経路が、入力ポートｉ４から接続点ｋ４を通って１つの単位ＳＲＡＭ６２ｅを介して接続点ｋ８を通って出力ポートｏ４へ抜けるように形成される。つまり、図９（ｄ）に示すように、記憶部４１に、入力ポートｉ４から出力ポートｏ４へ抜ける間の１つの単位ＳＲＡＭ６２ｅによる記憶領域が動的に形成される。 By this connection, the data transmission path of the path P4 is formed so as to pass from the input port i4 through the connection point k4, through one unit SRAM 62e, through the connection point k8 to the output port o4. That is, as shown in FIG. 9D, a storage area of one unit SRAM 62e is dynamically formed in the storage unit 41 during the passage from the input port i4 to the output port o4.
　このような記憶領域の動的な形成によれば、図２に示すように、容量可変制御部４２は、パス番号Ｐ４に係る無瞬断送受信部４４ａからのパスＰ４状態のパス量に応じた割当量で容量可変制御を行うことにより、可変容量記憶部４１にパスＰ４の記憶領域４１ａを増設又は減設して割り当てることが可能となる。 According to such dynamic formation of the storage area, as shown in FIG. 2, the variable capacity control unit 42 responds to the path amount in the path P4 state from the uninterrupted transmission / reception unit 44a related to the path number P4. By performing the variable capacity control based on the allocated amount, the storage area 41 a of the path P <b> 4 can be allocated to the variable-capacity storage unit 41 by increasing or decreasing.
　同様に、制御部４２は、パス番号Ｐ３に係る無瞬断送受信部４４ｂからのパスＰ３状態のパス量に応じた割当量により、記憶部４１にパスＰ３の記憶領域４１ｂを割り当てることが可能となる。同様に、制御部４２は、パス番号Ｐ１に係る無瞬断送受信部４４ｃからのパスＰ１状態のパス量に応じた割当量により、記憶部４１にパスＰ１の記憶領域４１ｃを割り当てることが可能となる。 Similarly, the control unit 42 can allocate the storage area 41b of the path P3 to the storage unit 41 with the allocation amount according to the path amount in the path P3 state from the hitless transmission / reception unit 44b related to the path number P3. Become. Similarly, the control unit 42 can allocate the storage area 41c of the path P1 to the storage unit 41 with the allocation amount according to the path amount in the path P1 state from the hitless transmission / reception unit 44c related to the path number P1. Become.
　つまり、単位ＳＲＡＭ６２の数を変えて記憶容量を可変できるので、記憶部４１の最大記憶容量内であれば、記憶容量の増設又は減設を自由に行うことが可能となる。なお、単位ＳＲＡＭ６２に代え、単位ＳＤＲＡＭを用いてもよい。 In other words, since the storage capacity can be varied by changing the number of unit SRAMs 62, the storage capacity can be freely increased or decreased within the maximum storage capacity of the storage unit 41. Note that a unit SDRAM may be used instead of the unit SRAM 62.
＜実施形態の動作＞
　上述した構成のメモリ装置４０によるメモリ容量動的可変の動作を、図１０のフローチャートを参照して説明する。 <Operation of Embodiment>
The operation of dynamically changing the memory capacity by the memory device 40 having the above-described configuration will be described with reference to the flowchart of FIG.
　前提条件として、図１に示す通信装置２０ａ，２０ｂの双方で新たに通信を行う場合、双方でメモリ装置４０の記憶領域を増設する。この際、双方はパスＰ４の左回り経路と右回り経路とで接続されている。但し、通信装置２０ａ側での増設を代表して説明する。 As a prerequisite, when new communication is performed by both of the communication devices 20a and 20b shown in FIG. 1, the storage area of the memory device 40 is increased by both. At this time, both are connected by a left-handed route and a right-handed route of the path P4. However, the description will be made on the assumption that the communication device 20a is expanded.
　ステップＳ１において、通信装置２０ａ，２０ｂの容量可変制御部４２に、外部から記憶容量の可変を行う指示信号が入力される。これによって制御部４２が容量可変制御を行うことが可能となる。 In step S1, an instruction signal for externally changing the storage capacity is input to the variable capacity control unit 42 of each of the communication devices 20a and 20b. Thereby, the control unit 42 can perform the variable capacity control.
　ステップＳ２において、制御部４２は、容量可変制御の可能を無瞬断送受信部４４ａへ通知し、無瞬断送受信部４４ａが切替部５５及び複製部５２を容量可変制御対応状態（図５参照）に切り替える。 In step S2, the control unit 42 notifies the capacity variable control to the hitless transmission / reception unit 44a, and the hitless transmission / reception unit 44a sets the switching unit 55 and the copy unit 52 to the capacity variable control compatible state (see FIG. 5). Switch to
　ステップＳ３において、無瞬断送受信部４４ａは、特定パケット削除部５４ａ，５４ｂの削除処理及び特定パケット挿入部５３ａ，５３ｂの挿入処理を有効とする。 In step S3, the hitless transmission / reception unit 44a validates the deletion processing of the specific packet deletion units 54a and 54b and the insertion processing of the specific packet insertion units 53a and 53b.
　次に、ステップＳ４において、例えば通信装置２０ｂにおける無瞬断送受信部４４ａ２（図３）の特定パケット挿入部５３ａ，５３ｂが、シーケンス番号（例えば５番）を付けた特定パケットを生成し、この特定パケットを同時に左右の経路へ送信する。 Next, in step S4, for example, the specific packet insertion units 53a and 53b of the hitless transmission / reception unit 44a2 (FIG. 3) in the communication device 20b generate a specific packet with a sequence number (for example, No. 5), and The packet is transmitted to the right and left routes at the same time.
　次に、ステップＳ５において、通信装置２０ａにおける無瞬断送受信部４４ａ１（図３）の特定パケット削除部５４ａ，５４ｂが、左右の経路から送信されてきた番号付きの特定パケットを受信し、この双方の受信時刻を容量可変制御部４２へ通知する。この出力後に特定パケットを削除する。 Next, in step S5, the specific packet deletion units 54a and 54b of the hitless transmission / reception unit 44a1 (FIG. 3) in the communication device 20a receive the numbered specific packets transmitted from the left and right paths. Is notified to the variable capacity control unit 42. After this output, the specific packet is deleted.
　ステップＳ６において、制御部４２は、右左双方の特定パケット受信時刻から受信時刻差を求め、この受信時刻差に応じてパス量（データ容量）を求め、このパス量に対応する割当量を求める。この割当量は、パスＰ１の２つの単位ＳＲＡＭ６２ａ，６２ｂ｛図９（ａ）参照｝のパス量であるとする。 In step S6, the control unit 42 obtains a reception time difference from both the right and left specific packet reception times, obtains a path amount (data capacity) according to the reception time difference, and obtains an allocation amount corresponding to the path amount. It is assumed that this allocation amount is the path amount of the two unit SRAMs 62a and 62b of the path P1 (see FIG. 9A).
　次に、ステップＳ７において、制御部４２は、その割当量でメモリ装置４０の可変容量記憶部４１に対して容量可変制御を行う。 Next, in step S7, the control unit 42 performs variable capacity control on the variable capacity storage unit 41 of the memory device 40 using the allocated amount.
　ステップＳ８において、可変容量記憶部４１は、その容量可変制御に応じてパスＰ１の記憶領域４１ｃ（図２）を次のように増設する。即ち、図８に示す可変容量記憶部４１は、容量可変制御に応じて、単位ＳＲＡＭ６２ｂ，６２ｃ間の１×２セレクタ６３の可動部６３ａを第２固定部６３ｃに接続する。更に、クロスバーＳＷ６５の交点を接続して接続点ｋ１を形成し、クロスバーＳＷ６６の交点を接続して接続点ｋ５を形成する。 In step S8, the variable capacity storage unit 41 expands the storage area 41c (FIG. 2) of the path P1 according to the variable capacity control as follows. That is, the variable capacity storage unit 41 shown in FIG. 8 connects the movable unit 63a of the 1 × 2 selector 63 between the unit SRAMs 62b and 62c to the second fixed unit 63c according to the variable capacity control. Furthermore, a connection point k1 is formed by connecting the intersections of the crossbar SW65, and a connection point k5 is formed by connecting the intersections of the crossbar SW66.
　この接続によって、パスＰ４のデータ伝送経路が、入力ポートｉ１から接続点ｋ１を通って２つの単位ＳＲＡＭ６２ａ，６２ｂを経由し、１×２セレクタ６３から接続点ｋ５を通って出力ポートｏ１へ抜けるように形成される。つまり、可変容量記憶部４１に、入力ポートｉ１から出力ポートｏ１へ抜ける間の２つの単位ＳＲＡＭ６２ａ，６２ｂによるパスＰ１の記憶領域４１ｃが形成される。 With this connection, the data transmission path of the path P4 passes from the input port i1 to the output port o1 via the connection point k1 and the two unit SRAMs 62a and 62b, and from the 1 × 2 selector 63 to the output port o1 via the connection point k5. Formed. That is, the storage area 41c of the path P1 by the two unit SRAMs 62a and 62b during the passage from the input port i1 to the output port o1 is formed in the variable capacity storage unit 41.
　この記憶領域４１ａの形成完了後、ステップＳ９において、制御部４２は、容量可変制御の終了を無瞬断送受信部４４ａへ通知する。 (4) After the formation of the storage area 41a is completed, in step S9, the control unit 42 notifies the non-instantaneous interruption transmission / reception unit 44a of the end of the variable capacity control.
　ステップＳ１０において、上記通知により、無瞬断送受信部４４ａは、切替部５５及び複製部５２を通常動作状態に戻し、特定パケット挿入部５３ａ，５３ｂの特定パケットの挿入処理を停止し、特定パケット削除部５４ａ，５４ｂの特定パケットの削除処理を停止する。 In step S10, based on the above notification, the hitless transmission / reception unit 44a returns the switching unit 55 and the duplication unit 52 to the normal operation state, stops the specific packet insertion processing of the specific packet insertion units 53a and 53b, and deletes the specific packet. The processing of deleting the specific packet by the units 54a and 54b is stopped.
＜実施形態の効果＞
　本実施形態に係る動的可変容量メモリ装置４０の効果について説明する。動的可変容量メモリ装置４０は、双方向のパスを介して互いに通信を行う複数の通信装置２０ａ～２０ｄに搭載され、データを記憶可能な回路構成を可変できるゲートアレイである電子回路により構成されている。このメモリ装置４０を次のように構成した。 <Effects of Embodiment>
The effect of the dynamic variable capacity memory device 40 according to the present embodiment will be described. The dynamic variable capacity memory device 40 is mounted on a plurality of communication devices 20a to 20d that communicate with each other via a bidirectional path, and is configured by an electronic circuit that is a gate array capable of changing a circuit configuration capable of storing data. ing. This memory device 40 was configured as follows.
　（１）動的可変容量メモリ装置４０は、データを記憶可能なゲートアレイである電子回路による記憶回路（ＦＰＧＡ）を用いた記憶部４１を備える。また、通信装置２０ａ～２０ｄ間のパスを伝送可能なデータ容量に対応する割当量を求め、当該割当量に応じた記憶容量の記憶領域を、記憶部４１に記憶回路で形成する容量可変制御を行う制御部４２を備える構成とした。 (1) The dynamic variable-capacity memory device 40 includes a storage unit 41 using a storage circuit (FPGA) using an electronic circuit, which is a gate array capable of storing data. In addition, a capacity variable control for forming a storage area of a storage capacity according to the allocated amount in the storage unit 41 by a storage circuit is performed by obtaining an allocated amount corresponding to a data capacity capable of transmitting a path between the communication devices 20a to 20d. And a control unit 42 for performing the control.
　この構成によれば、メモリ装置４０は、データを記憶する記憶回路の構成が可変できる記憶部４１を備える。そして、制御部４２で、通信装置２０ａ～２０ｄ間のパスを伝送可能なデータ容量に対応する割当量を求める。更に、制御部４２で、その割当量に応じた容量可変制御によって、記憶部４１に当該パスのデータを記憶する記憶領域を記憶回路で形成することが可能となる。このため、通信装置２０ａ～２０ｄを停止すること無くデータの記憶容量を可変して記憶領域を増設又は減設することができる。 According to this configuration, the memory device 40 includes the storage unit 41 that can change the configuration of the storage circuit that stores data. Then, the control unit 42 calculates an assigned amount corresponding to the data capacity that can be transmitted through the path between the communication devices 20a to 20d. Further, the control unit 42 can form a storage area for storing the data of the path in the storage unit 41 by the storage circuit by the capacity variable control according to the allocated amount. Therefore, it is possible to increase or decrease the storage area by changing the data storage capacity without stopping the communication devices 20a to 20d.
　従来ではメモリ容量が固定だった為に、宛先のノードである通信装置数が固定となっていた。しかし、本実施形態では、宛先の通信装置数が増加しても、増加に応じて記憶容量を拡張できる。 (4) Conventionally, the number of communication devices as destination nodes was fixed because the memory capacity was fixed. However, in this embodiment, even if the number of destination communication devices increases, the storage capacity can be expanded in accordance with the increase.
　（２）記憶回路は、ブロックＳＲＡＭ等の電子記憶素子を複数纏めた単位ＳＲＡＭ６２等の単位メモリを複数用いて構成されている。この記憶回路において、割当量に応じた記憶容量に対応する数の単位メモリが接続されて記憶領域が形成される構成とした。 (2) The storage circuit is configured using a plurality of unit memories such as a unit SRAM 62 in which a plurality of electronic storage elements such as a block SRAM are integrated. In this storage circuit, a configuration is employed in which a storage area is formed by connecting a number of unit memories corresponding to a storage capacity corresponding to the allocated amount.
　この構成によれば、通信装置２０ａ～２０ｄ間のパスを伝送可能なデータ容量に対応する割当量に応じて、記憶部４１に該当パスのデータ容量を収容可能な記憶領域を容易に形成できる。 According to this configuration, a storage area capable of accommodating the data capacity of the corresponding path can be easily formed in the storage unit 41 in accordance with the assigned amount corresponding to the data capacity that can be transmitted through the path between the communication devices 20a to 20d.
　（３）動的可変容量メモリ装置４０は、挿入部（特定パケット挿入部５３ａ，５３ｂ）と、削除部（特定パケット削除部５４ａ，５４ｂ）とを備える。挿入部は、容量可変制御が可能な場合において、固有番号（シーケンス番号）を付けた特定パケットを生成して双方向のパスへ送信する。削除部は、容量可変制御が可能な場合において、双方向のパスから送信されてきた固有番号付きの特定パケットを受信時に、当該双方向のパス毎の受信時刻を制御部４２へ通知し、この通知後に特定パケットを削除する。更に、制御部４２は、双方向のパス毎の受信時刻から受信時刻差を求め、この受信時刻差に応じてパスのデータ容量を求め、このデータ容量に対応する割当量を求める構成とした。 (3) The dynamic variable capacity memory device 40 includes an insertion unit (specific packet insertion units 53a and 53b) and a deletion unit (specific packet deletion units 54a and 54b). The inserter generates a specific packet with a unique number (sequence number) and transmits the specific packet to a bidirectional path when the variable capacity control is possible. The deletion unit notifies the control unit 42 of the reception time of each bidirectional path when receiving the specific packet with the unique number transmitted from the bidirectional path when the variable capacity control is possible. Delete the specific packet after notification. Further, the control unit 42 is configured to calculate the reception time difference from the reception time for each bidirectional path, obtain the data capacity of the path according to the reception time difference, and obtain the assigned amount corresponding to the data capacity.
　この構成によれば、通信装置２０ａ～２０ｄ間のパスをデータが伝送中に、このパスのデータ容量に対応する割当量を求めることができる。このため、実際のパスのデータ容量に応じて記憶部４１の記憶容量を可変できるので、記憶部４１の記憶サイズを最小限で構成できる。 According to this configuration, while data is being transmitted on the path between the communication devices 20a to 20d, it is possible to obtain an assigned amount corresponding to the data capacity of this path. For this reason, the storage capacity of the storage unit 41 can be changed according to the data capacity of the actual path, so that the storage size of the storage unit 41 can be minimized.
　この他、図１１に示すように、容量可変制御部４２は、動的可変容量メモリ装置４０内の可変容量記憶部４１以外のＦＰＧＡによる他ＧＡ回路記憶部４７を、データ記憶用の記憶部として用いてもよい。つまり、他ＧＡ回路記憶部４７は、動的可変容量メモリ装置４０内の未使用のＦＰＧＡを記憶部として用いたものである。なお、他ＧＡ回路記憶部４７は、請求項記載の他記憶部を構成する。 In addition, as shown in FIG. 11, the variable capacity control unit 42 uses the other GA circuit storage unit 47 of the FPGA other than the variable capacity storage unit 41 in the dynamic variable capacity memory device 40 as a storage unit for data storage. May be used. That is, the other GA circuit storage unit 47 uses an unused FPGA in the dynamic variable capacity memory device 40 as a storage unit. The other GA circuit storage unit 47 constitutes another storage unit described in the claims.
　他ＧＡ回路記憶部４７に、パス量に応じた記憶容量の記憶領域を割り当てる場合の動作制御も、上述した記憶部４１における制御と同じである。この構成によれば、記憶部４１の記憶領域を全て使用した場合等に他ＧＡ回路記憶部４７に記憶領域を割り当てることができる。このため、メモリ装置４０において記憶容量を動的に容易に増加することができる。 Operation control in the case where a storage area having a storage capacity corresponding to the pass amount is assigned to the other GA circuit storage unit 47 is the same as the control in the storage unit 41 described above. According to this configuration, the storage area can be allocated to the other GA circuit storage unit 47 when the entire storage area of the storage unit 41 is used. Therefore, the storage capacity of the memory device 40 can be easily increased dynamically.
　その他、具体的な構成について、本発明の主旨を逸脱しない範囲で適宜変更が可能である。 In addition, the specific configuration can be appropriately changed without departing from the gist of the present invention.
　１０　通信ＮＷ
　２０ａ～２０ｄ　通信装置
　３０　通信制御部
　４０　動的可変容量メモリ装置
　４１　可変容量記憶部
　４２　容量可変制御部
　４３　ラベルスイッチ
　４４ａ～４４ｃ　無瞬断送受信部
　４５　イーサネットスイッチ
　４７　他ＧＡ回路記憶部
　５１　シーケンスナンバ挿入部
　５２　２レーンデータ複製部
　５３ａ，５３ｂ　特定パケット挿入部
　５４ａ，５４ｂ　特定パケット削除部
　５５　ヒットレス切替部
　５６　シーケンスナンバ削除部
　６１　ブロックＳＲＡＭ
　６２，６２ａ～６２ｅ　単位ＳＲＡＭ
　６３　１×２セレクタ
　６４　２×１セレクタ
　６５，５５　クロスバーＳＷ 10 Communication NW
20a to 20d Communication device 30 Communication control unit 40 Dynamic variable capacity memory device 41 Variable capacity storage unit 42 Variable capacity control unit 43 Label switch 44a to 44c Uninterrupted transmission / reception unit 45 Ethernet switch 47 Other GA circuit storage unit 51 Sequence number insertion Unit 52 2-lane data duplication unit 53a, 53b Specific packet insertion unit 54a, 54b Specific packet deletion unit 55 Hitless switching unit 56 Sequence number deletion unit 61 Block SRAM
62, 62a-62e Unit SRAM
63 1 × 2 selector 64 2 × 1 selector 65, 55 Crossbar SW

Claims (5)

  1. 　双方向のパスを介して互いに通信を行う複数の通信装置に搭載され、データを記憶可能な回路構成を可変できる電子回路により構成された動的可変容量メモリ装置であって、
    　前記電子回路による記憶回路を用いた記憶部と、
    　前記通信装置間のパスを伝送可能なデータ容量に対応する割当量を求め、当該割当量に応じた記憶容量の記憶領域を前記記憶部に記憶回路で形成する容量可変制御を行う制御部と
    　を備えることを特徴とする動的可変容量メモリ装置。     A dynamic variable-capacity memory device that is mounted on a plurality of communication devices that communicate with each other via a bidirectional path and is configured by an electronic circuit capable of changing a circuit configuration capable of storing data,
    A storage unit using a storage circuit by the electronic circuit,
    A control unit that obtains an assigned amount corresponding to a data capacity capable of transmitting a path between the communication devices and forms a storage area of a storage capacity according to the assigned amount in the storage unit by a storage circuit and performs a variable capacity control. A dynamic variable capacity memory device comprising:
  2. 　前記記憶回路は、電子記憶素子を複数纏めた単位メモリを複数用いて構成され、前記割当量に応じた記憶容量に対応する数の単位メモリが接続されて記憶領域が形成される
    　ことを特徴とする請求項１に記載の動的可変容量メモリ装置。     The storage circuit is configured by using a plurality of unit memories each including a plurality of electronic storage elements, and a storage area is formed by connecting a number of unit memories corresponding to a storage capacity according to the allocation amount. The dynamic variable capacity memory device according to claim 1, wherein
  3. 　前記容量可変制御が可能な場合において、固有番号を付けた特定パケットを生成して前記双方向のパスへ送信する挿入部と、
    　前記双方向のパスから送信されてきた固有番号付きの特定パケットを受信時に、当該双方向のパス毎の受信時刻を前記制御部へ通知し、この通知後に特定パケットを削除する削除部と
    　を備え、
    　前記制御部は、前記双方向のパス毎の受信時刻から受信時刻差を求め、この受信時刻差に応じたパスのデータ容量を求め、このデータ容量に対応する割当量を求める
    　ことを特徴とする請求項１又は２に記載の動的可変容量メモリ装置。     When the variable capacity control is possible, an insertion unit that generates a specific packet with a unique number and transmits the generated packet to the bidirectional path,
    When receiving a specific packet with a unique number transmitted from the bidirectional path, the control unit notifies the control unit of the reception time of each bidirectional path, and deletes the specific packet after the notification. ,
    The control unit obtains a reception time difference from reception times of the bidirectional paths, obtains a data capacity of the path according to the reception time difference, and obtains an allocation amount corresponding to the data capacity. The dynamic variable capacity memory device according to claim 1.
  4. 　前記記憶部以外の未使用の電子回路を他記憶部として用い、
    　前記制御部は、前記割当量に応じて、前記他記憶部に前記パスのデータを記憶する記憶容量の記憶領域を形成する
    　ことを特徴とする請求項１～３の何れか１項に記載の動的可変容量メモリ装置。     Using an unused electronic circuit other than the storage unit as another storage unit,
    The control unit according to any one of claims 1 to 3, wherein the control unit forms a storage area of a storage capacity for storing the data of the path in the other storage unit according to the allocation amount. Dynamic variable capacity memory device.
  5. 　双方向のパスを介して互いに通信を行う複数の通信装置に搭載され、データを記憶可能な回路構成を可変できる電子回路により構成された動的可変容量メモリ装置による記憶容量動的可変方法であって、
    　前記動的可変容量メモリ装置は、
    　前記電子回路による記憶回路を搭載し、当該記憶回路の構成が可変できる記憶部を備え、
    　前記通信装置間のパスを伝送するデータ容量に対応する割当量を求めるステップと、
    　前記割当量に応じた記憶容量の記憶領域を前記記憶部に記憶回路で形成する容量可変制御を行うステップと
    　を実行することを特徴とする記憶容量動的可変方法。     A dynamic storage capacity variable method using a dynamic variable capacity memory device that is mounted on a plurality of communication devices that communicate with each other via a bidirectional path and is configured by an electronic circuit capable of changing a circuit configuration capable of storing data. hand,
    The dynamic variable capacity memory device,
    Equipped with a storage unit mounted with a storage circuit by the electronic circuit, the configuration of the storage circuit can be changed,
    Obtaining an assigned amount corresponding to a data capacity for transmitting a path between the communication devices;
    Performing a variable capacity control for forming a storage area of a storage capacity according to the allocated amount in the storage unit by a storage circuit.
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