WO2020000979A1 - 空间滤波器的建模方法 - Google Patents

空间滤波器的建模方法 Download PDF

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WO2020000979A1
WO2020000979A1 PCT/CN2018/125127 CN2018125127W WO2020000979A1 WO 2020000979 A1 WO2020000979 A1 WO 2020000979A1 CN 2018125127 W CN2018125127 W CN 2018125127W WO 2020000979 A1 WO2020000979 A1 WO 2020000979A1
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algorithm
formula
spatial filter
iteration
signal
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French (fr)
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刘若鹏
赵治亚
曹春柳
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深圳光启尖端技术有限责任公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H21/00—Adaptive networks
    • H03H21/0012—Digital adaptive filters
    • H03H21/0043—Adaptive algorithms
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H21/00—Adaptive networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H21/00—Adaptive networks
    • H03H21/0012—Digital adaptive filters
    • H03H21/0043—Adaptive algorithms
    • H03H2021/0049—Recursive least squares algorithm
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H21/00—Adaptive networks
    • H03H21/0012—Digital adaptive filters
    • H03H2021/007—Computation saving measures; Accelerating measures

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  • the present invention relates generally to the technical field of digital signal processing, and more particularly, to a method for modeling a spatial filter.
  • Spatial filtering is an image enhancement method that uses filtering. Its theoretical basis is spatial convolution and spatial correlation. The goal is to improve image quality, including removing high-frequency noise and interference, as well as image edge enhancement, linear enhancement, and deblurring. Divided into low-pass filtering (smoothing), high-pass filtering (sharpening) and band-pass filtering. There are two processing methods: computer processing (digital filtering) and optical information processing.
  • FIG. 1 is a schematic diagram of the implementation of the LMS algorithm. As shown in Figure 1, the LMS algorithm has a simple implementation structure and is robust to changes in the statistical characteristics of the signal, and has been widely used.
  • the LMS algorithm can be completely expressed by the following three formulas:
  • x (n) is the input vector or training sample
  • w (n) is the weight vector
  • d (n) is the reference signal, that is, the expected output
  • y (n) is the actual output signal
  • e (n) Is the error
  • w (n) is the weight vector
  • ⁇ is the learning efficiency
  • n is the number of iterations.
  • the LMS algorithm has a very wide range of applications in the field of adaptive beamforming, but it is not suitable for high-speed signal processing systems. If you want to improve the real-time processing speed of the signal, you should make the signal achieve parallel processing, that is, research and develop the inherent parallelism in the existing serial algorithm, and then overcome the inherent sequentiality of the algorithm.
  • the LMS algorithm uses serial sampling to update the system iteratively. It cannot be implemented in a pipeline or in parallel, which greatly affects its operating speed. If the real-time processing speed is increased, it is necessary to improve the algorithm form into an unrelated or indirectly related relationship.
  • DSP relies on sequential pointers to run programs.
  • hardware multiply-accumulate modules have been added, and a variety of dedicated acceleration coprocessors have been added, a large number of hardware structure improvements have been performed, but because they work in the order of CPU instruction execution, Caused its speed bottleneck.
  • DSP system developers want to use FPGA for digital signal processing, they only need to write Verilog HDL or VHDL language code. The process is complicated and the development efficiency is low, which is very difficult.
  • a hardware description language such as VHDL or Verilog HDL is used to write the underlying code. The development method is very inefficient, which seriously hinders its practical application.
  • the present invention provides a modeling method for a spatial filter capable of solving the above-mentioned problems in view of the defects that the existing LMS algorithm uses a serial sampling method and a DSP CPU sequence execution greatly affects the filtering speed.
  • a method for modeling a spatial filter including: obtaining a formula of an adaptive filtering algorithm; and changing the formula of the adaptive filtering algorithm to a pipelined adaptive filtering algorithm formula, wherein, the The pipeline adaptive filtering algorithm formula estimates the current expected signal based on the input signal and the error signal before the predetermined time to realize the parallel operation.
  • the adaptive filtering algorithm includes a least mean square (LMS) algorithm, wherein the modeling method includes: obtaining the minimum mean square algorithm formula; and using a relaxation delay technique and a relaxation technique to modify the A minimum mean square algorithm formula to obtain a pipeline minimum mean square (PIPLMS) algorithm formula, wherein the pipeline minimum mean square algorithm formula estimates a current expected signal based on an input signal and an error signal before the predetermined time.
  • LMS least mean square
  • PIPLMS pipeline minimum mean square
  • the adaptive filtering algorithm further includes a recursive least squares (RLS) algorithm, wherein the modeling method includes: obtaining the formula of the recursive least squares algorithm; and using a relaxation delay technique and a relaxation technique, Modifying the recursive least squares algorithm formula to obtain a pipeline minimum mean square (PIPLMS) algorithm formula, wherein the pipeline minimum mean square algorithm formula estimates a current expected signal based on an input signal and an error signal before the predetermined time.
  • RLS recursive least squares
  • PIPLMS pipeline minimum mean square
  • estimating the current expected signal based on the input signal and the error signal before the predetermined time further includes estimating the current expected signal based on the input signal and the error signal of D 2 before the current time as follows:
  • w (n) w (nD 2 ) + ⁇ ′e * (nD 1 ) x (nD 1 )
  • D 1 kD 2 ;
  • n is the current number of iterations;
  • w (n), w (nD 2 ) are the weight vector at the n-th iteration and the weight vector at time D 2 before the n-th iteration;
  • x (n), x (n-kD 2 ) are the input signal at the n-th iteration and the input signal at time D 1 before the n-th iteration, and
  • d (n) is the desired output signal;
  • e (n), e (n-kD 2 ) is the error signal at the n-th iteration and the error signal at time D 1 before the n-th iteration;
  • ⁇ ′ is the learning efficiency; and
  • D 1 and D 2 are delays.
  • the relaxation delay technique is as follows: under the condition that e (n) x (n) is slowly changing, that is,
  • n is the current number of iterations; w (n) and w (nD 2 ) are the weight vector of the nth iteration and the weight vector at time D 2 before the nth iteration; the weight vector; x (n ), X (nD 1 ), and x (nD 1 -i) are the input signal at the nth iteration, the input signal at time D 1 before the nth iteration, and (D 1 + i before the nth iteration) Input signals at time); e * (n), e * (nD 1 -i), and e * (ni) are the error signals of the nth iteration, and the times of (D 1 + i) before the nth iteration, respectively.
  • the sum-relaxation technique is as follows: Assume that e * (n) x (n) is slowly changing, that is,
  • the summation formula performs a sum relaxation transformation as described below to reduce the number of terms of the sum:
  • n is the current number of iterations
  • x (n), x (ni), and x (nD 1 ) are the input signal at the nth iteration, the input signal at time i before the nth iteration, and the nth iteration Input signals at the previous D 1 time
  • e * (n), e * (nD 1 ), and e * (ni) are the error signals at the n-th iteration, and the error signals at the D 1 time before the n-th iteration , And the error signal at time i before the nth iteration
  • D 1 and D 2 are delays.
  • the pipeline minimum mean square algorithm formula is modeled graphically based on a DSP Buider to obtain a system model of the spatial filter with a reduced amount of hardware.
  • the pipeline minimum mean square algorithm formula is modeled graphically based on a DSPBuilder to obtain the system model of the spatial filter further comprising: according to the pipeline minimum mean square algorithm formula, updating a loop at a weight A delay module is introduced to obtain an update subsystem of the pipeline minimum mean square algorithm; and an input of the update subsystem is set to an array of n elements to obtain a system model of the spatial filter, where n is An integer greater than or equal to (delay + 1).
  • the n-array element array is a 4-16 array element array.
  • the spatial filter is simulated using Modelsim and a first simulation result is recorded; and the spatial filter is simulated using Matlab / Simulink and a second simulation result is recorded, wherein the first simulation result is related to all The second simulation result is consistent.
  • the modeling method of the spatial filter provided by the present invention adopts a relaxation delay technique and a relaxation technique, and the serial algorithm is modified into a pipelined adaptive filtering algorithm that can be processed in parallel, thereby increasing the speed through parallel operations.
  • using FPGA to replace DSP for digital signal processing has great advantages in speed.
  • FIG. 1 is a schematic diagram of an existing LMS algorithm implementation structure
  • FIG. 2 is a flowchart of a method for modeling a spatial filter according to an embodiment of the present invention
  • FIG. 3 is a diagram of a PIPLMS algorithm weight update iteration subsystem according to an embodiment of the present invention
  • FIG. 4 is a diagram of a DSPBuilder system model of a PIPLMS algorithm according to an embodiment of the present invention
  • 5 is an input signal diagram of each element of the 8-element PIPLMS algorithm according to an embodiment of the present invention.
  • FIG. 6 is a waveform diagram of an output error curve and an output signal of a simulation based on Matlab / Simulink according to an embodiment of the present invention
  • FIG. 7 is a waveform diagram of an output error curve and an output signal of a simulation based on Modelsim according to an embodiment of the present invention.
  • This patent uses the digital signal processing tool software DSPBuilder of FPGA.
  • Altera DSPBuilder integrates the algorithm development, simulation, and verification functions of MathWorks MATLAB and Simulink system-level design tools with VHDL synthesis, simulation, and Altera development tools to achieve Integration of these tools.
  • DSPBuilder helps designers generate DSP design hardware representations in an algorithm-friendly development environment, thereby shortening the DSP design cycle.
  • DSPBuilder supports a common development platform for system, algorithm and hardware design. Combined with a variety of other EDA software, the airspace filter of the adaptive beam algorithm was modeled and simulated, which greatly improved the design efficiency.
  • the smart antenna itself is equivalent to a spatial filter, and can adaptively perform the optimal weight modulation according to the spatial environment characteristics of the signal, suppress the interference signals and noise, and reduce the interference to the desired signal.
  • the spatial filter will be described in detail with reference to the drawings.
  • FIG. 1 is a principle diagram of an existing LMS algorithm implementation structure. Hereinafter, it will be described with reference to FIG. 1.
  • a method 200 for modeling a spatial filter includes: in step 202, obtaining a formula of an adaptive filtering algorithm; and in step 204, adaptively filtering
  • the formula of the algorithm is changed to a pipelined adaptive filtering algorithm formula, wherein the pipelined adaptive filtering algorithm formula estimates a current expected signal based on an input signal and an error signal before a predetermined time to implement a parallel operation.
  • the modeling method of the spatial filter (also referred to as a spatial domain filter) provided by the present invention adopts a relaxation delay technique and a relaxation technique, and the serial algorithm is modified into a pipeline-type adaptive filtering algorithm that can be processed in parallel.
  • the filtering speed is greatly improved through parallel operations.
  • the adaptive filtering algorithm includes a least mean square (LMS) algorithm.
  • the modeling methods include: obtaining the minimum mean square algorithm formula; and using the relaxation delay technology and the relaxation technology, modifying the minimum mean square algorithm formula to obtain the pipeline minimum mean square (PIPLMS, pipelined LMS) algorithm formula, wherein the pipeline minimum mean square (PIPLMS) algorithm formula estimates a current expected signal based on an input signal and an error signal before a predetermined time.
  • the relaxation technology reduces the amount of hardware.
  • the pipeline least mean square algorithm formula is modeled graphically to obtain a system model of the spatial filter.
  • the system model of the pipeline minimum mean square algorithm formula based on the DSP Builderer to graphically obtain a spatial filter system model further includes: according to the pipeline minimum mean square algorithm formula, introducing a delay module in the weight update loop to An update subsystem that obtains a pipelined minimum mean square algorithm; and an input of the update subsystem is set to an n-element array to obtain a system model of a spatial filter, where n is an integer greater than or equal to (delay + 1).
  • the n-element array is a 4-16 element array.
  • the n-element array is an eight-element array.
  • the system model based on DSPBuilder is converted into a hardware description language (VHDL) language for parallel operation through FPGA (Field-Programmable Gate Array).
  • VHDL hardware description language
  • FPGA Field-Programmable Gate Array
  • the adaptive filtering algorithm further includes a recursive least squares (RLS) algorithm.
  • the modeling method includes obtaining the RLS algorithm formula; and using the relaxation delay technology and the relaxation technology, modifying the RLS algorithm formula to obtain the RLS algorithm formula, wherein the RLS algorithm formula is based on the The input and error signals estimate the current expected signal.
  • the error signal amount e (n) and the array received signal x (n) are multiplied by the Product module and sent to the adder module, which completes the previous weight coefficient together with the delay module. Update.
  • the input signal x (n) is weighted by the Product module to obtain the array output, that is, the accumulation of all single-array element outputs is the array output.
  • weights can be updated in advance for each sample of D 2 .
  • the general equation for updating weights is:
  • e * (ni) is a function of w (ni-1).
  • D 2 always depends on e * (n), e * (n-1), e * (n-2) ... It is calculated that the delay relaxation reduces its number, thereby reducing the complexity of the formula, where n is the current number of iterations; w (n) and w (nD 2 ) are the weight vector and the nth iteration, respectively.
  • weight vector at time D 2 before n iterations weight vector; x (n), x (nD 1 ), and x (nD 1 -i) are the input signal of the nth iteration and the nth iteration
  • the input signal at the previous time D 1 and the input signal at the time (D 1 + i) before the nth iteration; e * (n), e * (nD 1 -i), and e * (ni) are the nth Error signal at iterations, error signal at time (D 1 + i) before the nth iteration, or error signal at time i before the nth iteration;
  • ⁇ is the learning efficiency; and D 1 and D 2 are delays ;
  • E * (ni) is a function of w (ni-1), in Under the premise of slow change, D 2 always depends on e * (n), e * (n-1), e * (n-2). « number.
  • He relaxation technology He relaxation reduces hardware. Assuming e * (n) x (n) is slowly changing, then:
  • n is the current number of iterations
  • x (n), x (ni), and x (nD 1 ) are the input signal at the nth iteration, and i before the nth iteration.
  • the input signal at time and the input signal at time D 1 before the n-th iteration; e * (n), e * (nD 1 ), and e * (ni) are the error signals of the n-th iteration, and the n-th iteration iterative error signal before the time D 1, and the error signal before the time i n th iteration; and D 1 and D 2 are delay.
  • D 1 kD 2 ;
  • n is the current number of iterations;
  • w (n), w (nD 2 ) are the weight vector at the n-th iteration and the weight vector at time D 2 before the n-th iteration;
  • x (n), x (n-kD 2 ) are the input signal at the n-th iteration and the input signal at time D 1 before the n-th iteration, and
  • d (n) is the desired output signal;
  • e (n), e (n-kD 2 ) is the error signal at the n-th iteration and the error signal at time D 1 before the n-th iteration;
  • ⁇ ′ is the learning efficiency; and
  • D 1 and D 2 are delays.
  • ⁇ ′ includes and relaxes the modification factor, and relaxation and advance modification lead to the pipeline LMS (PIPLMS) algorithm.
  • PIPLMS pipeline LMS
  • the DLMS algorithm can estimate the current expected signal through the input signal and error output before D times.
  • the LMS adaptive algorithm expressed by Formula 1 and the schematic diagram of its implementation structure shown in Figure 1 We know that the LMS algorithm estimates the current expected signal by the input signal and error output signal at the previous moment, from the time correlation From a perspective, the performance of the DLMS algorithm will be better than the LMS algorithm, and the introduction of the delay D will not affect the steady-state performance of the algorithm much.
  • the selection of the step factor ⁇ is still a key factor affecting the steady-state performance of the algorithm. To ensure the convergence of the DLMS algorithm, it must meet:
  • the DLMS algorithm Compared with the LMS algorithm's step factor ⁇ range 0 ⁇ ⁇ 2 / ⁇ max , the DLMS algorithm has stricter requirements on the value of the step factor ⁇ . Even so, by selecting the appropriate step size, the required delay D can still be flexibly selected. This compromise is necessary in high-speed real-time processing.
  • the number of array elements is 4 and 8.
  • the LMS algorithm adaptive beam of the 8-element array shown in Figure 4 Form a system model:
  • this is an 8-element adaptive beamforming system with 5 input ports, Input 1 (Input 1), Input 2 (Input 2), Input 4 (Input 3), and Input 4 ( Input4), Input5 (Input5), Input6 (Input6), Input7 (Input7), Input8 (Input8) are used to input the sampled input signals x 1 (n), x 2 (n), x 3 (n), x 4 (n), x 5 (n), x 6 (n), x 7 (n), x 8 (n), send each input port signal to the weight update subsystem to complete Weight updates.
  • Input 10 (Input10) is used to input the reference signal.
  • the delay module (Delay) and the addition module (Adder) output part of the output of the beamforming system and send it to the Output1 port for subsequent analysis and research; the other part is sent to another adder to obtain the error signal e (n).
  • the bus control module (AltBus) can complete data type conversion and complete data bit width control.
  • the SignalComplier module in the figure is used to complete the conversion of the entire model file, converting the .mdl file form into a VHDL file.
  • the TestBench test generated file is consistent with the simulation stimulus of the DSP module in Simulink.
  • the Clock module is used to set the system clock sampling frequency.
  • FIG. 5 is an input signal waveform diagram of the array elements 1, 2, 3,... 8.
  • Figure 6 is a simulation of the output error curve and output signal waveform diagram based on Matlab / Simulink.
  • FIG. 7 is a waveform diagram of an output error curve and an output signal of a simulation based on Modelsim.
  • the running speed of the spatial filter based on the pipeline minimum mean square algorithm is higher than that of the spatial filter based on the minimum mean square algorithm.
  • the running speed of the pipelined minimum mean square algorithm is 112.4% higher than that of the minimum mean square algorithm.
  • the running speed of the pipeline minimum mean square algorithm is 12.5 times faster than that of the extended minimum mean square algorithm.
  • the input signal be 50MHz
  • the interference signal be 50MHz
  • the sampling frequency is 1000MHz.
  • the Cyclone IV series EP4CE15F23C6 chip is also selected to obtain the hardware resource consumption and operating speed of the 8-element array adaptive airspace filter based on the above-mentioned PIPLMS algorithm simulation conditions.
  • the operating speed of the adaptive airspace filter using the PIPLMS algorithm is significantly higher than that of the adaptive airspace filter based on the LMS algorithm.
  • the PIPLMS algorithm has a maximum increase of nearly 112.4% over the LMS algorithm and a maximum increase of nearly 12.5% over the DLMS algorithm.
  • the FPGA hardware resources consumed also increase significantly.
  • the filtering method includes: creating a spatial filter according to the modeling method of the spatial filter described above; and performing filtering using the spatial filter.
  • the spatial filter is created according to the modeling method of the spatial filter described above and will be implemented and run on the FPGA platform, that is, filtering is performed by the spatial filter.
  • the establishment of the PIPLMS algorithm DSPBuilder system model because it is an iterative algorithm, it is necessary to first express the weighted iterative formula as a model, then model the entire formula, model the formula in a graphical form, and convert it into VHDL , For FPGA platform to realize processing.
  • the modeling method of the spatial filter provided by the present invention adopts the relaxation delay technology and the relaxation technology, and the serial algorithm is modified into a pipeline adaptive filtering algorithm that can be processed in parallel.
  • the filtering speed is greatly improved through parallel operations.
  • the modeling method and filtering method of the present invention can be applied to modules such as smart antennas, array antennas, and spatial filters, and can be widely used in communication, radar and other systems; the programming method provided by the present invention can save programming 5.

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Abstract

一种空间滤波器的建模方法。空间滤波器的建模方法包括：获取自适应滤波算法的公式（202）；以及将自适应滤波算法的公式改变为流水线型自适应滤波算法公式，其中，所述流水线型自适应滤波算法公式基于预定时刻之前的输入信号和误差信号估计当前的期望信号以实现并行运算（204）。本方法采用放宽延时技术与和放宽技术，串行算法修改为可以并行处理的流水线型自适应滤波算法，从而通过并行运算大幅度提高的滤波速度。

Description

空间滤波器的建模方法 技术领域
本发明一般地涉及数字信号处理技术领域，更具体地，涉及一种空间滤波器建模方法。
背景技术
空间滤波是一种采用滤波处理的影像增强方法。其理论基础是空间卷积和空间相关。目的是改善影像质量，包括去除高频噪声与干扰，及影像边缘增强、线性增强以及去模糊等。分为低通滤波(平滑化)、高通滤波(锐化)和带通滤波。处理方法有计算机处理(数字滤波)和光学信息处理两种。
20世纪60年代，B.Widrow等人提出了最小均方(LMS)算法。图1为LMS算法实现原理图。如图1所示，LMS算法实现结构简单且对信号的统计特性变化具有一定稳健性，获得了极为广泛的应用。LMS算法可以由以下三个公式完整表示：
Figure PCTCN2018125127-appb-000001
其中，x(n)为输入向量或者称为训练样本；w(n)为权值向量；d(n)为参考信号，即，期望输出；y(n)为实际输出信号；e(n)为误差；w(n)为权值向量；μ为学习效率；以及n为迭代次数。
LMS算法在自适应波束形成领域有着非常广泛的应用，但其并不适用于高速信号处理系统。若想提高信号实时处理速度，则应使信号实现并行处理，即研究开发已有串行算法中内在的并行性，进而克服算法固有的顺序性。LMS算法利用串行采样方式进行系统迭代更新，不能够流水线或者并行实现，这就大大影响了其运行速度。若提高实时处理速度，就要改进成为不相关或间接存在相关关系的算法形式。
另外，DSP靠顺序指针来运行程序，虽然已经增加了硬件乘法累加模块， 加入多种专用加速协处理器等，进行了大量硬件结构提升工作，但因为其以CPU指令顺序执行的方式进行工作，导致了其速度瓶颈。DSP系统开发人员若想用FPGA进行数字信号处理只有采用编写Verilog HDL或者VHDL语言代码的方式，过程复杂且开发效率低，难度很大。现有技术中，基于FPGA实现系统设计时，是用VHDL或者Verilog HDL等硬件描述语言通过编写底层代码进行的，开发方式效率很低，严重阻碍了其走向实用化。
发明内容
本发明针对现有的LMS算法利用串行采样方式以及DSP的CPU指令顺序执行均大幅度影响滤波速度等缺陷，提供了能够解决上述问题的空间滤波器的建模方法。
根据本发明的一方面，提供了一种空间滤波器的建模方法包括：获取自适应滤波算法的公式；以及将自适应滤波算法的公式改变为流水线型自适应滤波算法公式，其中，所述流水线型自适应滤波算法公式基于预定时刻之前的输入信号和误差信号估计当前的期望信号以实现并行运算。
优选地，所述自适应滤波算法包括最小均方(LMS)算法，其中，所述建模方法包括：获取所述最小均方算法公式；以及使用放宽延时技术与和放宽技术，修改所述最小均方算法公式以获得流水线最小均方(PIPLMS)算法公式，其中，所述流水线最小均方算法公式基于所述预定时刻之前的输入信号和误差信号估计当前的期望信号。
优选地，所述自适应滤波算法还包括递归最小二乘(RLS)算法，其中，所述建模方法包括：获取所述递归最小二乘算法公式；以及使用放宽延时技术与和放宽技术，修改所述递归最小二乘算法公式以获得流水线最小均方(PIPLMS)算法公式，其中，所述流水线最小均方算法公式基于所述预定时刻之前的输入信号和误差信号估计当前的期望信号。
优选地，基于预定时刻之前的输入信号和误差信号估计当前的期望信号进一步包括基于当前时刻之前的D 2的输入信号和误差信号来估计当前的期望信号如下：
w(n)＝w(n-D 2)+μ′e *(n-D 1)x(n-D 1)
e(n)＝d(n)-w H(n-D 2)x(n)
其中，D 1＝kD 2；n为当前迭代次数；w(n)、w(n-D 2)分别为第n次迭代时的权值向量和第n次迭代之前的D 2时刻的权值向量；x(n)、x(n-kD 2)分别为第n次迭代时的输入信号和第n次迭代之前的D 1时刻的输入信号，d(n)为期望输出信号；e(n)、e(n-kD 2)分别为第n次迭代时的误差信号和第n迭代之前的D 1时刻的误差信号；μ′为学习效率；以及D 1和D 2均为延时。
优选地，所述放宽延时技术如下：在e(n)x(n)是慢变的条件下，即，
e *(n)x(n)≈e *(n-D 1)x(n-D 1)
通过如下所述延时放宽变换修改权值公式以降低权值公式的复杂性：
Figure PCTCN2018125127-appb-000002
被修改为
Figure PCTCN2018125127-appb-000003
其中，n为当前迭代次数；w(n)和w(n-D 2)分别为第n次迭代的权值向量和第n次迭代之前的D 2时刻的权值向量；权值向量；x(n)、x(n-D 1)、以及x(n-D 1-i)分别为第n次迭代的输入信号、第n次迭代之前的D 1时刻的输入信号以及第n次迭代之前的(D 1+i)时刻的输入信号；e*(n)、e*(n-D 1-i)以及e*(n-i)分别为第n次迭代的误差信号、第n次迭代之前的(D 1+i)时刻的误差信号以及或第n次迭代之前的i时刻的误差信号；μ为学习效率；以及D 1和D 2是延时；e *(n-i)是w(n-i-1)的函数，在
Figure PCTCN2018125127-appb-000004
是慢变的前提下，D 2总取决于e *(n)、e *(n-1)、e *(n-2)······需要被计算出来，延时放宽减少了其数目。
优选地，所述和放宽技术如下：假设e *(n)x(n)是慢变的，即，
e *(n)x(n)≈e *(n-D 1)x(n-D 1)
求和公式进行如下所述和放宽变换以减少和的项数：
Figure PCTCN2018125127-appb-000005
其中，n为当前迭代次数；x(n)、x(n-i)、x(n-D 1)分别为第n次迭 代时的输入信号、第n次迭代之前的i时刻的输入信号以及第n次迭代之前的D 1时刻的输入信号；e*(n)、e*(n-D 1)、以及e*(n-i)分别为第n次迭代的误差信号，第n次迭代之前的D 1时刻的误差信号，以及第n次迭代之前的i时刻的误差信号；以及D 1和D 2是延时。
优选地，基于DSP Buider对所述流水线最小均方算法公式以图形化形式进行建模以获得具有减少硬件数量的所述空间滤波器的系统模型。
优选地，基于DSP Builder对所述流水线最小均方算法公式以图形化形式进行建模以获得所述空间滤波器的系统模型进一步包括：根据所述流水线最小均方算法公式，在权值更新回路中引入延时模块以获得所述流水线最小均方算法的更新子系统；以及将所述更新子系统的输入设置为n阵元阵列，以获得所述空间滤波器的系统模型，其中，n为大于等于(延时+1)的整数。
优选地，所述n阵元阵列为4-16阵元阵列。
优选地，利用Modelsim对所述空间滤波器进行仿真并记录第一仿真结果；以及利用Matlab/Simulink对所述空间滤波器进行仿真并记录第二仿真结果，其中，所述第一仿真结果与所述第二仿真结果一致。
本发明所提供的空间滤波器的建模方法采用放宽延时技术与和放宽技术，串行算法修改为可以并行处理的流水线型自适应滤波算法，从而通过并行运算提高速度。另外，通过FPGA替代DSP来进行数字信号处理在速度上有很大优势。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是现有的LMS算法实现结构的原理图；
图2是根据本发明的实施例的空间滤波器的建模方法的流程图；
图3是根据本发明的实施例的PIPLMS算法权值更新迭代子系统的示图；
图4是根据本发明的实施例的PIPLMS算法的DSP Builder系统模型的 示图；
图5是根据本发明的实施例的8阵元PIPLMS算法的各个阵元的输入信号图；以及
图6是根据本发明的实施例的基于Matlab/Simulink进行仿真的输出误差曲线与输出信号的波形图；
图7是根据本发明的实施例的基于Modelsim进行仿真的输出误差曲线与输出信号的波形图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本专利用FPGA的数字信号处理专用工具软件DSP Builder，其中，Altera DSP Builder将MathWorks MATLAB和Simulink系统级设计工具的算法开发、仿真和验证功能与VHDL综合、仿真和Altera开发工具整合在一起，实现了这些工具的集成。DSP Builder在算法友好的开发环境中帮助设计人员生成DSP设计硬件表征，从而缩短了DSP设计周期。DSP Builder支持系统、算法和硬件设计共享一个公共开发平台。结合其他多种EDA软件，对自适应波束算法的空域滤波器进行了建模仿真，使设计效率得到了极大地提高。
智能天线(自适应天线阵列)本身相当于空间滤波器，能够依据信号空间环境特征自适应地进行最优权值的调制，抑制掉干扰信号和噪声，降低对期望信号的干扰。下文中，参照附图对空间滤波器进行详细描述。
图1是现有的LMS算法实现结构的原理图。下文中，将参照图1对其进行描述。
如图2所示，根据本发明的实施例，提供一种空间滤波器的建模方法200，包括：在步骤202中，获取自适应滤波算法的公式；以及在步骤204中，将自 适应滤波算法的公式改变为流水线型自适应滤波算法公式，其中，流水线型自适应滤波算法公式基于预定时刻之前的输入信号和误差信号估计当前的期望信号以实现并行运算。
本发明所提供的空间滤波器(又称空域滤波器)的建模方法采用放宽延时技术与和放宽技术，串行算法修改为可以并行处理的流水线型自适应滤波算法。从而通过并行运算大幅度提高的滤波速度。
根据本发明的实施例，自适应滤波算法包括最小均方(LMS，least mean square)算法。当自适应滤波算法为最小均方(LMS)算法时，建模方法包括：获取最小均方算法公式；以及使用放宽延时技术与和放宽技术，修改最小均方算法公式以获得流水线最小均方(PIPLMS，pipelined LMS)算法公式，其中，流水线最小均方(PIPLMS)算法公式基于预定时刻之前的输入信号和误差信号估计当前的期望信号。其中，和放宽技术减少硬件的数量。
基于DSP Buider对流水线最小均方算法公式以图形化形式进行建模以获得空间滤波器的系统模型。具体地，基于DSP Builder对流水线最小均方算法公式以图形化形式进行建模以获得空间滤波器的系统模型进一步包括：根据流水线最小均方算法公式，在权值更新回路中引入延时模块以获得流水线最小均方算法的更新子系统；以及将更新子系统的输入设置为n阵元阵列，以获得空间滤波器的系统模型，其中，n为大于等于(延时+1)的整数。在优选实施例中，n阵元阵列为4-16阵元阵列。在进一步优选实施例中，n阵元阵列为8阵元阵列。接下来，将基于DSP Builder的系统模型转化成硬件描述语言(VHDL)语言以通过FPGA(Field－Programmable Gate Array，即现场可编门阵列)进行并行运算。这样创建的空间滤波器可用于智能天线或阵列天线。
综上所述，PIPLMS算法DSP Builder系统模型的建立，因为是迭代算法，要先将权重迭代公式用模型方式表现出来，再将整个公式进行建模，把公式用图形化形式建模，并且转化成VHDL语言，供FPGA平台实现处理。
在另一实施例中，自适应滤波算法还包括递归最小二乘(RLS，Recursive Least Square)算法等。当自适应滤波算法为RLS算法时，建模方法包括获取RLS算法公式；以及使用放宽延时技术与和放宽技术，修改RLS算法公式以获得RLS算法公式，其中，RLS算法公式基于预定时刻之前的输入信号和误差信号估计当前的期望信号。
接下来，将参照图3-4对空间滤波器的建模方法的实例进行详细描述。
如图3中LMS算法权值更新子系统所示，误差信号额e(n)和阵列接收信号x(n)经Product模块相乘之后，送给加法器模块，同延迟模块一起完成前权系数更新。输入信号x(n)经过Product模块完成加权，获得阵列输出，即所有单阵元输出的累加即为阵列输出。
由以上公式1得到：
Figure PCTCN2018125127-appb-000006
依据必要的信息，权值能够被预先更新D 2各样本。一般等式更新权值公式为：
Figure PCTCN2018125127-appb-000007
因为e *(n-i)是w(n-D 2)的函数，所以应用w(n-D 2)表示e *(n-i)比较困难。以下通过放宽延迟，放宽和，使得LMS的流水线结构是可行的。
放宽延时技术：采用假设e(n)x(n)在D 1的采样期间内是慢变的，即
e *(n)x(n)≈e *(n-D 1)x(n-D 1)      公式4
原来的更新公式3改变为
Figure PCTCN2018125127-appb-000008
超前技术的复杂性在于e *(n-i)是w(n-i-1)的函数。在e *(n)x(n)是慢变的前提下，D 2总取决于e *(n)、e *(n-1)、e *(n-2)······需要被计算出来，延时放宽减少了其数目，从而降低了公式的复杂性，其中，n为当前迭代次数；w(n)和w(n-D 2)分别为第n次迭代的权值向量和第n次迭代之前的D 2时刻的权值向量；权值向量；x(n)、x(n-D 1)、以及x(n-D 1-i)分别为第n次迭代的输入信号、第n次迭代之前的D 1时刻的输入信号以及第n次迭代之前的(D 1+i)时刻的输入信号；e*(n)、e*(n-D 1-i)以及e*(n-i)分别为第n次迭代的误差信号、第n次迭代之前的(D 1+i)时刻的误差信号以及或第n次 迭代之前的i时刻的误差信号；μ为学习效率；以及D 1和D 2是延时；e *(n-i)是w(n-i-1)的函数，在
Figure PCTCN2018125127-appb-000009
是慢变的前提下，D 2总取决于e *(n)、e *(n-1)、e *(n-2)······需要被计算出来，延时放宽减少了其数目。
和放宽技术：和放宽减少了硬件，假设e *(n)x(n)是慢变的，则：
Figure PCTCN2018125127-appb-000010
则和的项数被减少了，其中，n为当前迭代次数；x(n)、x(n-i)、x(n-D 1)分别为第n次迭代时的输入信号、第n次迭代之前的i时刻的输入信号以及第n次迭代之前的D 1时刻的输入信号；e*(n)、e*(n-D 1)、以及e*(n-i)分别为第n次迭代的误差信号，第n次迭代之前的D 1时刻的误差信号，以及第n次迭代之前的i时刻的误差信号；以及D 1和D 2是延时。
因此，应用延迟与和放宽技术，将LMS算法的修改，得到PIPLMS算法，PIPLMS算法结构中，当LA＝1、D 1＝kD 2时，该权值迭代公式变化为：
Figure PCTCN2018125127-appb-000011
e(n)＝d(n)-w H(n-D 2)x(n)            公式8
其中，D 1＝kD 2；n为当前迭代次数；w(n)、w(n-D 2)分别为第n次迭代时的权值向量和第n次迭代之前的D 2时刻的权值向量；x(n)、x(n-kD 2)分别为第n次迭代时的输入信号和第n次迭代之前的D 1时刻的输入信号，d(n)为期望输出信号；e(n)、e(n-kD 2)分别为第n次迭代时的误差信号和第n迭代之前的D 1时刻的误差信号；μ′为学习效率；以及D 1和D 2均为延时。
应用延迟和和放宽技术，算法的修改如下：
Figure PCTCN2018125127-appb-000012
μ'包括和放宽修改因子，和放宽超前修改引出了流水线LMS(PIPLMS)算法，由式9可得误差信号为
Figure PCTCN2018125127-appb-000013
假设μ'足够小，并替换w(n-D 2-1)＝w(n-D 2)，误差信号可以表示为：
e(n)＝d(n)-w H(n-D 2)x(n)    公式11
但是，分析全部形式的PIPLMS算法是非常复杂的，通常，只对几种典型算法结构进行分析讨论。一般地，只对LA＝1的情况进行讨论，此时PIPLMS算法表示为：
应用延迟和和放宽技术，将LMS算法的修改，得到PIPLMS算法，PIPLMS算法结构中，当LA＝1、D 1＝kD 2时，该权值迭代公式变化为：
w(n)＝w(n-D 2)+μ'e *(n-kD 2)x(n-kD 2)   公式12
e(n)＝d(n)-w H(n-D 2)x(n)公式13
DLMS算法：如公式12和13描述的流水线LMS(PIPLMS)算法，当LA＝1,D 2＝1，D 1＝D时，PIPLMS算法成为DLMS算法，其更新公式如下所示：
w(k)＝w(k-1)+μ'e *(k-D)x(k-D)           公式14
e(k)＝d(k)-w H(k-1)x(k)公式15
我们能够发现DLMS算法可以通过D个时刻以前的输入信号和误差输出来估计当前的期望信号。相对地，由公式1表述的LMS自适应算法以及图1所表示的其实现结构原理图我们知道，LMS算法是通过前一时刻输入信号和误差输出信号来估计当前的期望信号，从时间相关性的角度来看，DLMS算法的性能将优于LMS算法，且延时D的引入并不会对算法的稳态性能造成太大影响。
对于DLMS算法，步长因子μ的选取仍是影响算法稳态性能的关键因素。要保证DLMS算法收敛必须满足：
Figure PCTCN2018125127-appb-000014
与LMS算法的步长因子μ范围0<μ<2/λ max相比，DLMS算法对步长因子μ的取值要求更严格。即便如此，通过选取合适的步长，仍然能够灵活地选择需要的延迟D，高速实时处理中，这种折中是必要的。
采用上述权值更新子系统，结合LMS算法原理与结构，令阵列阵元数为 4和8，在MATALB/Simulink中基于DSP Builder建立了如4所示的8阵元阵列的LMS算法自适应波束形成系统模型：
从图4所示模型图可以看出，此为8阵元的自适应波束形成系统，有5个输入端口，输入1(Input1)、输入2(Input2)、输入4(Input3)、输入4(Input4)、输入5(Input5)、输入6(Input6)、输入7(Input7)、输入8(Input8)分别用来输入各阵列单元采样后的输入信号x 1(n)、x 2(n)、x 3(n)、x 4(n)、x 5(n)、x 6(n)、x 7(n)、x 8(n)，将各输入端口信号送入权值更新子系统以完成权值更新。输入10(Input10)用来输入参考信号。延迟模块(Delay)，加法模块(Adder)输出一部分为波束形成系统的输出，送给Output1端口，以便后续分析研究；另一部分送给另一加法器，用来获得误差信号e(n)。乘法模块(Product)与步长常数μ相乘，此处设置成：μ＝0.001。总线控制模块(AltBus)，能够完成数据类型转换，完成数据位宽控制。图中的信号编译器(SignalComplier)模块用来完成整个模型文件的转化，将.mdl文件形式转化成VHDL文件。TestBench测试生成文件与该DSP模块在Simulink中的仿真激励相一致。Clock模块用来设置系统时钟采样频率等。
下文中，参照图5-7对仿真结果进行描述。图5是阵元1、2、3、…8的输入信号波形图。图6为基于Matlab/Simulink进行仿真的输出误差曲线与输出信号的波形图。图7为基于Modelsim进行仿真的输出误差曲线与输出信号的波形图。
利用Modelsim对空间滤波器进行仿真并记录第一仿真结果；以及利用Matlab/Simulink对空间滤波器进行仿真并记录第二仿真结果，其中，第一仿真结果与第二仿真结果一致。基于流水线最小均方算法的空间滤波器的运行速度高于基于最小均方算法的空间滤波器的运行速度。流水线最小均方算法的运行速度比最小均方算法的运行速度提高112.4％。流水线最小均方算法的运行速度比延伸最小均方算法的运行速度提高12.5。
分别利用Modelsim与Matlab/Simulink进行仿真验证，结果基本一致，当D 1＝4,D 2＝4、D 1＝4,D 2＝2、D 1＝4,D 2＝1时，输出结果稳定收敛，输出信号波形与期望信号基本一致；当D 1＝4,D 2＝3时，输出误差、输出信号波形不再收敛，系统不能进行良好地滤波。
采用上述仿真信号，令输入信号为50MHz，干扰信号为50MHz，阵列间距为d＝0.5λ，假设期望信号以0 °入射，干扰信号以40 °方向入射。采样频率为 1000MHz，利用QuartusII软件，同样选取Cyclone IV系列EP4CE15F23C6芯片，得到了基于上述PIPLMS算法仿真条件的8阵元阵列自适应空域滤波器的硬件资源消耗和运行速度情况。
表1不同算法空域滤波器系统硬件性能分析比较
Figure PCTCN2018125127-appb-000015
由以上表格所示出的结果数据可知，在同等仿真条件下，采用PIPLMS算法的自适应空域滤波器的运行速度较基于LMS算法自适应空域滤波器均有明显提高。当PIPLMS算法延时D 1＝4,D 2＝1时，即为延时D＝4时的DLMS，因此系统运行速度基本一致。PIPLMS算法较LMS算法最大提高近112.4％，较DLMS算法最大提高近12.5％。由于系统运行速度的提高，所消耗的FPGA硬件资源也在大幅度增加。
下面，将对空间滤波器的滤波方法进行描述。
根据本发明的另一实施例，滤波方法包括：根据上文所述的空间滤波器的建模方法创建空间滤波器；使用所述空间滤波器进行滤波。根据上文所述的空间滤波器的建模方法创建空间滤波器并将在FPGA平台上实现并运行该空间滤波器，即，通过该空间滤波器进行滤波。例如，PIPLMS算法DSP Builder系统模型的建立，因为是迭代算法，要先将权重迭代公式用模型方式表现出来，再将整个公式进行建模，把公式用图形化形式建模，并且转化成VHDL语言，供FPGA平台实现处理。
本发明所提供的空间滤波器的建模方法采用放宽延时技术与和放宽技术，串行算法修改为可以并行处理的流水线型自适应滤波算法。从而通过并行运算大幅度提高的滤波速度。
本发明的建模方法和滤波方法可以应用于智能天线、阵列天线、空间滤波 器等模块上，在通信、雷达等系统中都可以广泛应用；应用本发明提供的建模方法可以省去编程序、写代码带来的繁杂工作量和克服编程方式带来的开发难度；并且具有常规DSP不具备的高速、高效率的特点，可以在FPGA平台上实现并行运行实现。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

  1. 一种空间滤波器的建模方法，其特征在于，包括：
    获取自适应滤波算法的公式；以及
    将所述自适应滤波算法的公式改变为流水线型自适应滤波算法公式，其中，所述流水线型自适应滤波算法公式基于预定时刻之前的输入信号和误差信号估计当前的期望信号以实现并行运算。
  2. 根据权利要求1所述的空间滤波器的建模方法，其特征在于，所述自适应滤波算法包括最小均方(LMS)算法，其中，所述建模方法包括：
    获取所述最小均方算法公式；以及
    使用放宽延时技术与和放宽技术，修改所述最小均方算法公式以获得流水线最小均方(PIPLMS)算法公式，其中，所述流水线最小均方算法公式基于所述预定时刻之前的输入信号和误差信号估计当前的期望信号。
  3. 根据权利要求2所述的空间滤波器的建模方法，其特征在于，所述自适应滤波算法还包括递归最小二乘(RLS)算法，其中，所述建模方法包括：
    获取所述递归最小二乘算法公式；以及
    使用放宽延时技术与和放宽技术，修改所述递归最小二乘算法公式以获得流水线最小均方(PIPLMS)算法公式，其中，所述流水线最小均方算法公式基于所述预定时刻之前的输入信号和误差信号估计当前的期望信号。
  4. 根据权利要求3所述的空间滤波器的建模方法，其特征在于，基于预定时刻之前的输入信号和误差信号估计当前的期望信号进一步包括基于当前时刻之前的D 2的输入信号和误差信号来估计当前的期望信号如下：
    w(n)＝w(n-D 2)+μ′e *(n-D 1)x(n-D 1)
    e(n)＝d(n)-w H(n-D 2)x(n)
    其中，D 1＝kD 2；n为当前迭代次数；w(n)、w(n-D 2)分别为第n次迭代时的权值向量和第n次迭代之前的D 2时刻的权值向量；x(n)、x(n-kD 2)分别为第n次迭代时的输入信号和第n次迭代之前的D 1时刻的输入信号，d(n)为期望输出信号；e(n)、e(n-D 1)分别为第n次迭代时的误差信号和第n迭代之前的D 1时刻的误差信号；μ′为学习效率；以及D 1和D 2均为延时。
  5. 根据权利要求2所述的空间滤波器的建模方法，其特征在于，所述放 宽延时技术如下：
    在e(n)x(n)是慢变的条件下，即，
    e *(n)x(n)≈e *(n-D 1)x(n-D 1)
    通过如下所述延时放宽变换修改权值公式以降低权值公式的复杂性：
    Figure PCTCN2018125127-appb-100001
    被修改为
    Figure PCTCN2018125127-appb-100002
    其中，n为当前迭代次数；w(n)和w(n-D 2)分别为第n次迭代的权值向量和第n次迭代之前的D 2时刻的权值向量；权值向量；x(n)、x(n-D 1)、以及x(n-D 1-i)分别为第n次迭代的输入信号、第n次迭代之前的D 1时刻的输入信号以及第n次迭代之前的(D 1+i)时刻的输入信号；e*(n)、e*(n-D 1-i)以及e*(n-i)分别为第n次迭代的误差信号、第n次迭代之前的(D 1+i)时刻的误差信号以及或第n次迭代之前的i时刻的误差信号；μ为学习效率；以及D 1和D 2是延时；e *(n-i)是w(n-i-1)的函数，在e *(n)x(n)是慢变的前提下，D 2总取决于e *(n)、e *(n-1)、e *(n-2)······需要被计算出来，延时放宽减少了其数目。
  6. 根据权利要求2所述的空间滤波器的建模方法，其特征在于，所述和放宽技术如下：
    假设e *(n)x(n)是慢变的，即，
    e *(n)x(n)≈e *(n-D 1)x(n-D 1)
    求和公式进行如下所述和放宽变换以减少和的项数：
    Figure PCTCN2018125127-appb-100003
    其中，n为当前迭代次数；x(n)、x(n-i)、x(n-D 1)分别为第n次迭代时的输入信号、第n次迭代之前的i时刻的输入信号以及第n次迭代之前的D 1时刻的输入信号；e*(n)、e*(n-D 1)、以及e*(n-i)分别为第n次迭代的误差信号，第n次迭代之前的D 1时刻的误差信号，以及第n次迭代之前的 i时刻的误差信号；以及D 1和D 2是延时。
  7. 根据权利要求6所述的空间滤波器的建模方法，其特征在于，基于DSPBuider对所述流水线最小均方算法公式以图形化形式进行建模以获得具有减少硬件数量的所述空间滤波器的系统模型。
  8. 根据权利要求7所述的空间滤波器的建模方法，其特征在于，基于DSPBuilder对所述流水线最小均方算法公式以图形化形式进行建模以获得所述空间滤波器的系统模型进一步包括：
    根据所述流水线最小均方算法公式，在权值更新回路中引入延时模块以获得所述流水线最小均方算法的更新子系统；以及
    将所述更新子系统的输入设置为n阵元阵列，以获得所述空间滤波器的系统模型，其中，n为大于等于(延时+1)的整数。
  9. 根据权利要求8所述的空间滤波器的建模方法，其特征在于，所述n阵元阵列为4-16阵元阵列。
  10. 根据权利要求7所述的空间滤波器的建模方法，其特征在于，其中，
    利用Modelsim对所述空间滤波器进行仿真并记录第一仿真结果；以及
    利用Matlab/Simulink对所述空间滤波器进行仿真并记录第二仿真结果，其中，所述第一仿真结果与所述第二仿真结果一致。
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