WO2019244271A1

WO2019244271A1 - Frequency converter

Info

Publication number: WO2019244271A1
Application number: PCT/JP2018/023444
Authority: WO
Inventors: 萩原　達也; 孝信藤原; 充弘下澤
Original assignee: 三菱電機株式会社
Priority date: 2018-06-20
Filing date: 2018-06-20
Publication date: 2019-12-26
Also published as: JP6771852B2; JPWO2019244271A1

Abstract

A frequency converter is provided with: frequency conversion elements 1 to 4 that perform voltage-current conversion on an RF signal, perform frequency conversion by use of an LO signal and output an IF signal; a DC potential detection circuit 20 that detects the DC potentials of the frequency conversion elements 1 to 4; and a bias generation circuit 21 that, on the basis of the DC potentials detected by the DC potential detection circuit 20, generates bias voltages to be applied to the frequency conversion elements 1 to 4, wherein, according to increases of the DC potentials detected by the DC potential detection circuit 20, the bias generation circuit 21 increases the bias voltages.

Description

Frequency converter

The present invention relates to a frequency converter, and more particularly to a frequency converter used in satellite communication, terrestrial microwave communication, mobile communication, and the like.

Patent Document 1 discloses a Gilbert cell type conventional frequency converter.

The Gilbert cell type frequency converter includes an input-stage transistor (hereinafter referred to as a Gm-stage transistor) that performs voltage-current conversion on an input RF (Radio-Frequency) signal, and a local oscillator (LO (Local Oscillator)). A switch stage transistor for performing a frequency conversion using the LO signal from the converter to convert an RF signal into an IF (Intermediate Frequency) signal, and an output stage transistor having a load impedance element for performing current-voltage conversion on the IF signal. Are stacked vertically.

However, in recent years, with the miniaturization of semiconductor processes, the voltage of circuits has been reduced. As described above, since the Gilbert cell type frequency converter has a plurality of transistors stacked vertically, there is a problem that as the voltage is reduced, the voltage headroom of the transistors becomes insufficient and the output signal is distorted. Was. Note that the voltage headroom indicates a margin of a voltage amplitude at which a signal can be extracted from an output terminal without distortion.

Therefore, Patent Document 2 discloses a frequency converter configured to directly input an RF signal to a source terminal of a switch transistor. In the frequency converter described in Patent Literature 2, since no Gm stage transistor is provided, the number of vertically stacked transistors is smaller than that of a Gilbert cell type frequency converter. Thereby, the voltage headroom of the transistor is secured, and high linearity of the output signal can be obtained. Further, in the frequency converter disclosed in Patent Document 2, by setting the gate bias voltage of the switch-stage transistor to be high, an overdrive voltage is secured, and deterioration of linearity due to a distortion component of the transistor is suppressed.

JP-A-2002-252811 Japanese Patent No. 4536737

As described above, the Gilbert cell-type frequency converter described in Patent Document 1 has a plurality of transistors stacked vertically. Therefore, when the voltage is reduced, the voltage headroom of the transistors becomes insufficient, and the output signal becomes low. However, there was a problem that it was distorted.

{Circle around (2)} As described above, the frequency converter described in Patent Literature 2 suppresses distortion of the output signal by reducing the number of stages of vertically stacked transistors. Further, by setting the gate bias voltage of the switch-stage transistor high, high linearity of the output signal can be obtained even at a low power supply voltage. However, there is a problem that setting the gate bias voltage high increases idle current.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a frequency converter that can realize high linearity of an output signal while suppressing an idle current.

According to the present invention, there is provided a frequency conversion element that receives an RF signal and an LO signal, performs voltage-current conversion on the RF signal, performs frequency conversion using the LO signal, and outputs an IF signal. A DC potential detection circuit that detects a DC potential of the frequency conversion element that changes according to the input power of the RF signal, and applies the DC potential to the frequency conversion element based on the DC potential detected by the DC potential detection circuit. And a bias generation circuit that generates a bias voltage to be applied to the power supply. The bias generation circuit is a frequency converter that increases the bias voltage in accordance with an increase in the DC potential detected by the DC potential detection circuit.

According to the frequency converter of the present invention, high linearity of the output signal can be realized while suppressing the idle current.

FIG. 1 is a configuration diagram showing a configuration of a frequency converter according to Embodiment 1 of the present invention. FIG. 3 is a configuration diagram showing another configuration example of the frequency converter according to Embodiment 1 of the present invention. FIG. 7 is a configuration diagram showing a configuration of a frequency converter according to Embodiment 2 of the present invention. FIG. 2 is a configuration diagram showing a configuration of a comparative example with respect to the frequency converter according to Embodiment 1 of the present invention.

Hereafter, in order to explain this invention in greater detail, the preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration of the frequency converter according to Embodiment 1 of the present invention. Before describing the first embodiment, the configuration of a comparative example will be described with reference to FIG. 4 so that the features of the first embodiment can be more easily understood.

FIG. 4 is a diagram showing a comparative example for comparison with the first embodiment. FIG. 4 shows a configuration of a general Gilbert cell type frequency converter as a comparative example. As shown in FIG. 4, the frequency converter includes Gm-

stage transistors

101 and 102, switch-stage transistors 103 to 106, RF differential signal input terminals 107 and 108, and LO differential signal input terminals 109 and 110. , IF differential

signal output terminals

111 and 112,

load impedance elements

113 and 114, DC cut capacitors 115 to 118, a current source 119, and a power supply terminal 120.

Next, the operation of the frequency converter shown in FIG. 4 will be described. The RF signals input from the RF differential signal input terminals 107 and 108 are subjected to voltage-current conversion by the

Gm stage transistors

101 and 102. Next, the RF signal is frequency-converted by the switch transistors 103 to 106 that perform a switching operation based on the LO signal, and becomes an IF signal. Next, the IF signal is subjected to current-voltage conversion by the

load impedance elements

113 and 114 and output from the IF differential

signal output terminals

111 and 112.

Thus, in the Gilbert cell type frequency converter shown in FIG. 4, the Gm-stage transistor, the switch-stage transistor, and the load impedance element are vertically stacked. Therefore, as described above, when the voltage is reduced due to the miniaturization of the semiconductor process, the voltage headroom of the vertically stacked transistors becomes insufficient, and the output signal is distorted.

Therefore, the frequency converter according to the first embodiment has a configuration for solving the above-described problem. Hereinafter, the frequency converter according to the first embodiment will be described.

As shown in FIG. 1, the frequency converter according to the first embodiment includes frequency conversion elements 1 to 4, RF differential

signal input terminals

5 and 6, LO differential

signal input terminals

7 and 8, an IF Differential

signal output terminals

9 and 10,

load impedance elements

11 and 12, DC cut capacitors 13 to 16,

current sources

17 and 18, power supply terminal 19, DC potential detection circuit 20, bias generation circuit 21 It is configured with.

Hereinafter, each component of FIG. 1 will be described.

ＲＦ An RF signal is externally input to the RF differential

signal input terminals

5 and 6.

ＬＯ LO signals are input to the LO differential

signal input terminals

7 and 8 from an external device such as a local oscillator.

IF differential

signal output terminals

9 and 10 output IF signals to the outside.

Each of the frequency conversion elements 1 to 4 includes, for example, an NMOS (n-Channel Metal-Oxide Semiconductor) transistor. Each of the frequency conversion elements 1 to 4 has a source terminal, a gate terminal, and a drain terminal.

The DC cut capacitor 13 is connected between the RF differential signal input terminal 5 and the source terminals of the

frequency conversion elements

1 and 2.

The DC cut capacitor 14 is connected between the RF differential signal input terminal 6 and the source terminals of the

frequency conversion elements

3 and 4.

The DC cut capacitor 15 is connected between the LO differential signal input terminal 7 and the gate terminals of the

frequency conversion elements

1 and 4.

The DC cut capacitor 16 is connected between the LO differential signal input terminal 8 and the gate terminals of the

frequency conversion elements

2 and 3.

ＲＦ An RF signal is input to the source terminal of the frequency conversion element 1 from the RF differential signal input terminal 5 via the DC cut capacitor 13. Further, a LO signal is input to the gate terminal of the frequency conversion element 1 from the LO differential signal input terminal 7 via the DC cut capacitor 15. Further, the frequency conversion element 1 outputs an IF signal from the drain terminal to the IF differential signal output terminal 10.

(4) An RF signal is input to the source terminal of the frequency conversion element 2 from the RF differential signal input terminal 5 via the DC cut capacitor 13. Further, an LO signal is input to the gate terminal of the frequency conversion element 2 from the LO differential signal input terminal 8 via the DC cut capacitor 16. Further, the frequency conversion element 2 outputs an IF signal from the drain terminal to the IF differential signal output terminal 9.

(4) An RF signal is input to the source terminal of the frequency conversion element 3 from the RF differential signal input terminal 6 via the DC cut capacitor 14. Further, the LO signal is input to the gate terminal of the frequency conversion element 3 from the LO differential signal input terminal 8 via the DC cut capacitor 16. Further, the frequency conversion element 3 outputs an IF signal from the drain terminal to the IF differential signal output terminal 10.

(4) An RF signal is input to the source terminal of the frequency conversion element 4 from the RF differential signal input terminal 6 via the DC cut capacitor 14. Further, a LO signal is input to the gate terminal of the frequency conversion element 4 from the LO differential signal input terminal 7 via the DC cut capacitor 15. Further, the frequency conversion element 4 outputs an IF signal from the drain terminal to the IF differential signal output terminal 9.

(4) The load impedance element 11 is connected between the power supply terminal 19 and the IF differential signal output terminal 10, and performs current-voltage conversion on the IF signals output from the drain terminals of the

frequency conversion elements

1 and 3.

(4) The load impedance element 12 is connected between the power supply terminal 19 and the IF differential signal output terminal 9 and performs current-voltage conversion on the IF signals output from the drain terminals of the

frequency conversion elements

2 and 4.

The current source 17 is connected to the source terminals of the

frequency conversion elements

1 and 2. Hereinafter, a connection point between the current source 17 and the source terminals of the

frequency conversion elements

1 and 2 is referred to as a connection point 40.

The current source 18 is connected to the source terminals of the

frequency conversion elements

3 and 4. Hereinafter, a connection point between the current source 18 and the source terminals of the

frequency conversion elements

3 and 4 is referred to as a connection point 41.

The DC potential detection circuit 20 is connected between the DC cut capacitor 13 and the connection point 40, and is connected between the DC cut capacitor 14 and the connection point 41. The DC potential detection circuit 20 detects the DC potential at the source terminals of the frequency conversion elements 1 to 4 and outputs a signal corresponding to the detected DC potential to the bias generation circuit 21.

The bias generation circuit 21 is connected between the DC cut capacitor 15 and the gate terminals of the

frequency conversion elements

1 and 4, and is connected between the DC cut capacitor 16 and the gate terminals of the

frequency conversion elements

2 and 3. I have. The bias generation circuit 21 controls the gate bias voltages of the frequency conversion elements 1 to 4 based on the value of the DC potential detected by the DC potential detection circuit 20. Specifically, the bias generation circuit 21 increases the gate bias voltage according to the increase in the DC potential detected by the DC potential detection circuit 20, and responds to the decrease in the DC potential detected by the DC potential detection circuit 20. To reduce the gate bias voltage. The relationship between the DC potential and the gate bias voltage may be represented by a linear function such as a proportional relationship, or may be represented by a non-linear function.

Here, as can be seen by comparing FIG. 1 with FIG. 4, the frequency converter according to the first embodiment does not include the Gm-

stage transistors

101 and 102 in FIG. Therefore, in FIG. 1, since the number of vertically stacked transistors is small, the voltage headroom can be ensured and the occurrence of distortion of the IF signal can be suppressed.

Next, the operation of the frequency converter according to the first embodiment shown in FIG. 1 will be described. The RF signal is input from RF differential

signal input terminals

5 and 6. The RF signal is applied to the source terminals of the frequency conversion elements 1 to 4. The LO signal is input from the LO differential

signal input terminals

7 and 8. The LO signal is applied to the gate terminals of the frequency conversion elements 1 to 4. As a result, the frequency conversion elements 1 to 4 perform voltage-current conversion on the RF signal and perform switching operation using the LO signal to convert the frequency to an IF signal. The IF signal is subjected to current-voltage conversion by the

load impedance elements

11 and 12 and output from IF differential

signal output terminals

9 and 10. At this time, the DC potential detection circuit 20 detects the DC potential at the source terminals of the frequency conversion elements 1 to 4, and outputs a voltage corresponding to the detected DC potential. Further, the bias generation circuit 21 generates a gate bias voltage to be applied to the frequency conversion elements 1 to 4 according to the output voltage of the DC potential detection circuit 20.

Next, the operation principle of the frequency converter according to the first embodiment will be described.

(4) The currents from the

current sources

17 and 18 are kept at a constant value. Therefore, when the input power input to the RF differential signal input terminals 5 and 6 (hereinafter, referred to as RF input power) increases, the DC potential at the source terminals of the frequency conversion elements 1 to 4 increases. Therefore, the gate-source voltages of the frequency conversion elements 1 to 4 decrease, and the overdrive voltage becomes insufficient. As a result, the distortion components of the signals output from the frequency conversion elements 1 to 4 increase. In order to prevent this, the distortion component of the IF signal can be suppressed by setting the gate bias voltages of the frequency conversion elements 1 to 4 high. However, the idle current increases as the gate bias voltage increases. This problem occurs in the comparative example shown in FIG.

Therefore, in the first embodiment, the following method operates so that the gate-source voltages of the frequency conversion elements 1 to 4 do not decrease even when the RF input power increases.

In the frequency converter according to the first embodiment, the DC potential detection circuit 20 detects an increase in DC potential at the source terminals of the frequency conversion elements 1 to 4 due to an increase in RF input power. The DC potential detection circuit 20 outputs a voltage corresponding to the detected DC potential to the bias generation circuit 21. The bias generation circuit 21 increases the gate bias voltages of the frequency conversion elements 1 to 4 according to the output voltage from the DC potential detection circuit 20.

、 Thus, in the frequency converter according to the first embodiment, when the RF input power increases, the gate-source voltages of the frequency conversion elements 1 to 4 can be increased accordingly. As a result, an overdrive voltage is secured, and distortion components of the IF signal can be suppressed. Thereby, high linearity of the IF signal can be obtained.

As described above, since the bias generation circuit 21 controls the gate bias voltage, the gate bias voltage during the idle operation can be set low. For example, when the RF input power is increased, good linearity can be obtained by setting the overdrive voltage of the frequency conversion elements 1 to 4 to 0.2 V to 0.3 V. The gate bias voltage is reduced so as to be 2 V or less. Therefore, the frequency converter can be operated with a low idle current, so that an increase in power consumption can be suppressed.

Also, when the RF input power increases, high linearity can be obtained by increasing the gate bias voltage accordingly. In addition, the gate bias voltage is increased by the amount corresponding to the increase in the RF input power, so that the power consumption during the idle operation, which occupies most of the operation period, can be suppressed.

As described above, the frequency converter according to the first embodiment includes the DC potential detection circuit 20 that detects a change in the DC potential at the source terminals of the frequency conversion elements 1 to 4 that input the RF signal, A bias generation circuit 21 for generating a gate bias voltage. As a result, even when the bias voltage during idle operation is set low and the frequency converter operates at low idle current, the gate bias voltage can be increased when the RF input power is increased. High linearity can be realized.

In the first embodiment, an example has been described in which the frequency conversion elements 1 to 4 include an NMOS transistor. However, the present invention is not limited to such an example, and the frequency conversion elements 1 to 4 may be, for example, bipolar transistors. (BJT: Bipolar Junction Transistor). Even in that case, the same effect can be obtained. In that case, the gate, drain and source of the NMOS transistor are replaced with the base, collector and emitter of the BJT.

The DC potential detection circuit 20 according to the first embodiment may be configured to output a DC voltage from a middle point of a resistor connected between the differentials. In this case, by setting the resistance value sufficiently higher than the RF input impedance, the DC potential can be detected without affecting the RF input matching.

FIG. 2 is a circuit diagram showing a modification of the frequency converter according to the first embodiment of the present invention. The difference between FIG. 1 and FIG. 2 is that, in FIG. 2, the

impedance elements

31 and 32 are added, and the current source 18 in FIG. 1 is not provided. The

impedance elements

31 and 32 are connected in series. Hereinafter, the connection point of the

impedance elements

31 and 32 will be referred to as a connection point 42. Further, the DC potential detection circuit 20 is connected between the connection point 42 and the current source 17.

The impedance element 31 is connected to the source terminals of the

frequency conversion elements

1 and 2. The impedance element 32 is connected to the source terminals of the

frequency conversion elements

3 and 4. The

impedance elements

31 and 32 perform RF input matching on RF signals input to the RF differential

signal input terminals

5 and 6. The DC potential detection circuit 20 is connected to a connection point 42 between the

impedance elements

31 and 32 that is a virtual ground point for the RF signal. Therefore, the DC potential detection circuit 20 can detect the DC potential fluctuation of the source terminals of the frequency conversion elements 1 to 4 without affecting the differential type RF signal.

において In the first embodiment, any of the configurations shown in FIGS. 1 and 2 may be employed. In either configuration, the same operation is performed, and the same effect is obtained.

Embodiment 2 FIG.
FIG. 3 is a diagram showing a configuration of the frequency converter according to Embodiment 2 of the present invention. In the frequency converter according to the second embodiment, as shown in FIG. 3, the bias generation circuit 21 according to the first embodiment includes a temperature-proportional current source 22, a first transistor 23, The

third transistor

24, 25, the fourth transistor 26, and the

bias resistors

27, 28 are provided.

Hereinafter, each component of the bias generation circuit 21 will be described.

The temperature-proportional current source 22 is provided in the frequency converter, and outputs a current proportional to the device temperature of the frequency converter using power from an external power supply supplied to the power supply terminal 19. Note that the device temperature of the frequency converter is a junction temperature of a transistor included in the frequency converter.

The first transistor 23 includes, for example, an NMOS transistor. The output voltage from the DC potential detection circuit 20 is input to the gate terminal of the first transistor 23. The source terminal of the first transistor 23 is grounded, and the drain terminal is connected to the second transistor 24 and the third transistor 25. The first transistor 23 changes the drain current output from the drain terminal according to the output voltage output from the DC potential detection circuit 20. Specifically, in the first transistor 23, when the output voltage output from the DC potential detection circuit 20 increases, the drain current output from the drain terminal increases accordingly. Hereinafter, the drain current is referred to as a first current.

Here, as described in the first embodiment, when the RF input power increases, the DC potential at the source terminals of the frequency conversion elements 1 to 4 increases. The DC potential detection circuit 20 outputs a voltage according to the DC potential. Therefore, when the RF input power increases, the first current output from the first transistor 23 increases.

{Circle around (2)} The second transistor 24 and the third transistor 25 include, for example, a PMOS transistor (p-channel metal-oxide semiconductor). The second transistor 24 and the third transistor 25 form a current mirror circuit using the first current from the first transistor 23 as a reference current. The current mirror circuit is hereinafter referred to as a first current mirror circuit. The second transistor 24 and the third transistor 25 output the first current from the first transistor 23 at a preset current mirror ratio, and add the first current to the output current output from the temperature proportional current source 22. Let it. Hereinafter, the current after the addition is referred to as a second current.

The transistor size ratio of the second and

third transistors

24 and 25 may be 1: 1 and the current mirror ratio may be 1. Alternatively, the transistor size ratio of the second and

third transistors

24 and 25 is 1: M, where M is an arbitrary natural number of 2 or more. As described above, the current mirror ratio M may be set to 2 or more by setting the transistor size ratio to 1: M. In this case, the amount of increase in the gate bias voltage with respect to the amount of increase in the DC potential detected by the DC potential detection circuit 20 can be increased, so that higher linearity can be obtained.

The bias resistor 27 is connected between the fourth transistor 26 and the gate terminals of the

frequency conversion elements

2 and 3.

The bias resistor 28 is connected between the fourth transistor 26 and the gate terminals of the

frequency conversion elements

1 and 4.

(4) The fourth transistor 26 includes, for example, an NMOS transistor. The fourth transistor 26 and the frequency conversion elements 1 to 4 form a current mirror circuit using the second current as a reference current. Hereinafter, the current mirror circuit is referred to as a second current mirror circuit. The second current is supplied to the fourth transistor 26. The fourth transistor 26 outputs a second current at a preset current mirror ratio via

bias resistors

27 and 28, and applies a bias voltage to the gate terminals of the frequency conversion elements 1 to 4. The transistor size ratio between the fourth transistor 26 and the frequency conversion elements 1 to 4 may be 1: 1 and the current mirror ratio may be 1. Alternatively, the transistor size ratio between the fourth transistor 26 and the frequency conversion elements 1 to 4 may be 1: M.

Next, the operation of the frequency converter according to the second embodiment will be described.

(1) The first transistor 23 outputs a first current corresponding to the output voltage output from the DC potential detection circuit 20. The second transistor 24 and the third transistor 25 output the first current from the first transistor 23 at a preset current mirror ratio to output current output from the temperature proportional current source 22. The second current is output by the addition. At this time, the temperature proportional current source 22 outputs a current proportional to the device temperature of the frequency converter. The fourth transistor 26 generates a bias voltage using the second current, and applies the bias voltage to the gate terminals of the frequency conversion elements 1 to 4.

As described above, also in the second embodiment, similarly to the first embodiment, the bias voltage is controlled according to the output voltage output from the DC potential detection circuit 20. The bias voltage during the idle operation can be set low. Further, even when the frequency converter operates at a low idle current, the gate bias voltage can be increased when the RF input power is increased, so that high linearity of the IF signal can be realized.

(4) In the second embodiment, the temperature proportional current source 22 is used. In the second embodiment, by providing the temperature proportional current source 22, the gate bias voltage applied to the frequency conversion elements 1 to 4 can be made proportional to the device temperature. Thereby, even when the device temperature becomes higher than the threshold value, it is possible to suppress the deterioration of the linearity.

The current source does not necessarily have to be a temperature proportional current source. Instead of a temperature proportional current source, a constant current source that does not depend on the device temperature may be used. However, when a current is supplied by a constant current source, when the device temperature rises above a preset threshold, the overdrive voltage of the frequency conversion elements 1 to 4 decreases. As a result, the distortion component of the output signal slightly increases. As described above, when the device temperature rises, the linearity of the output signal of the frequency converter is slightly deteriorated as compared with that at normal temperature. Therefore, it is more desirable to use a temperature proportional current source.

As described above, also in the second embodiment, since the DC potential detection circuit 20 and the bias generation circuit 21 are provided, the same effects as in the first embodiment can be obtained.

In the second embodiment, when the RF input power increases, the first current output from the first transistor 23 increases according to the increase in the DC potential at the source terminals of the frequency conversion elements 1 to 4. The first current is added to the current supplied from the temperature-proportional current source 22 via the first current mirror circuit to become a second current. Next, the second current mirror circuit applies a bias voltage to the frequency conversion elements 1 to 4 using the second current. As a result, as in the first embodiment, the gate-source voltages of the frequency conversion elements 1 to 4 increase. As a result, an overdrive voltage can be secured, so that a distortion component of the output signal of the frequency converter can be suppressed. As described above, the linearity of the frequency converter can be improved.

Further, in the second embodiment, the transistor size ratio of the second and

third transistors

24 and 25 may be 1: M, M may be an arbitrary natural number of 2 or more, and the current mirror ratio M may be 2 or more. In that case, the amount of increase in the gate bias voltage with respect to the amount of increase in the DC potential detected by the DC potential detection circuit 20 can be increased, so that higher linearity can be obtained.

According to the second embodiment, the bias generation circuit 21 includes the temperature-proportional current source 22. Therefore, it is possible to compensate for a rise in device temperature in the gate bias voltages of the frequency conversion elements 1 to 4. As a result, in low idle current operation, there is an effect of suppressing linearity degradation both when the RF input power is increased and when the device is at a high temperature.

Within the scope of the present invention, the present invention can freely combine any of the embodiments, modify any of the constituent elements of each of the embodiments, or omit any of the constituent elements of each of the embodiments. is there.

1, 2, 3, 4 frequency conversion element, 5, 6 RF differential signal input terminal, 7, 8 LO differential signal input terminal, 9, 10 IF differential signal output terminal, 11, 12 load impedance element, 13, 14, 15, 16 DC cut capacitance, 17, 18 current source, 19 power supply terminal, 20 DC potential detection circuit, 21 bias generation circuit, 22 temperature proportional current source, 23 first transistor, 24 second transistor, 25 second 3 transistor, 26 # fourth transistor, 27, 28 # bias resistor, 31, 32 # impedance element.

Claims

A frequency conversion element that receives an RF signal and an LO signal, performs voltage-current conversion on the RF signal, performs frequency conversion using the LO signal, and outputs an IF signal;
A DC potential detection circuit that detects a DC potential of the frequency conversion element that changes according to the input power of the RF signal;
A bias generation circuit that generates a bias voltage to be applied to the frequency conversion element based on the DC potential detected by the DC potential detection circuit,
The bias generation circuit increases the bias voltage in accordance with an increase in the DC potential detected by the DC potential detection circuit.
Frequency converter.
The bias generation circuit includes:
A current source;
A first transistor that outputs a first current corresponding to the DC potential detected by the DC potential detection circuit;
Configuring a first current mirror circuit using the first current as a reference current, and adding the first current to a current supplied from the current source based on a preset current mirror ratio. A second transistor and a third transistor that output a second current;
And a fourth transistor configured to form a second current mirror circuit together with the frequency conversion element using the second current as a reference current to generate the bias voltage applied to the frequency conversion element. 2. The frequency converter according to 1.
The size ratio between the second transistor and the third transistor is set to 1: 1 and the current mirror ratio is 1.
The frequency converter according to claim 2.
The size ratio between the second transistor and the third transistor is set to 1: M, where M is an arbitrary natural number of 2 or more, and the current mirror ratio is M.
The frequency converter according to claim 2.
The current source is configured by a temperature proportional current source that outputs a current proportional to the internal temperature of the frequency converter,
A frequency converter according to any one of claims 2 to 4.