WO2019242109A1 - 一种液晶显示面板的驱动电路及液晶显示器 - Google Patents

一种液晶显示面板的驱动电路及液晶显示器 Download PDF

Info

Publication number
WO2019242109A1
WO2019242109A1 PCT/CN2018/104265 CN2018104265W WO2019242109A1 WO 2019242109 A1 WO2019242109 A1 WO 2019242109A1 CN 2018104265 W CN2018104265 W CN 2018104265W WO 2019242109 A1 WO2019242109 A1 WO 2019242109A1
Authority
WO
WIPO (PCT)
Prior art keywords
data line
sub
node
pixel electrode
data
Prior art date
Application number
PCT/CN2018/104265
Other languages
English (en)
French (fr)
Inventor
刘林峰
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2019242109A1 publication Critical patent/WO2019242109A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the invention relates to the technical field of liquid crystal display panels, in particular to a driving circuit of a liquid crystal display panel and a liquid crystal display.
  • liquid crystal displays have gradually become an important role of consumer electronic products, and they are widely used in displays of devices such as mobile terminals with high-resolution color screens.
  • thin film transistor liquid crystal displays are one of the main liquid crystal displays.
  • FIG. 1 is a schematic structural diagram of a liquid crystal display panel and a driving circuit thereof in the prior art.
  • a plurality of sub-pixel electrodes R, G, and B sub-pixel electrodes
  • a plurality of scanning lines and a plurality of data lines are arranged on the display panel.
  • Each column of sub-pixel electrodes on the display panel is connected to each data line.
  • the driving circuit in FIG. 1 includes two data buses (111, 112), and an output end of each data bus (111, 112) is connected to a common input end of three columns of data lines. The polarity of the data signals output by adjacent data buses is opposite. As shown in FIG.
  • the data signal output by the first data bus 111 is positive, and the data signal output by the adjacent second data bus 112 is negative.
  • the control terminals (SWR, SWG, SWB) of the switch (such as thin film transistors) are connected to the scanning lines (131, 132, 133). By controlling the opening and closing of the switch, the thin film transistors are controlled.
  • the data lines are transmitted to the corresponding sub-pixel electrodes (151, 152, 153, 154, 155, 156) on the display panel, and the input of the data bus is time-division multiplexed, which can reduce the number of source driver chips. And reduce related costs.
  • the The data lines connected to the pixel electrodes are added with four sets of through holes g1-g4 to realize the above-mentioned positive and negative inversions of the adjacent sub-pixel electrodes.
  • the first data bus 111 is connected to the first data line 121, the second data line 122, and the third data line 123, respectively
  • the second data bus 112 is connected to the fourth data line 124, the fifth data line 125, and the first data line, respectively. ⁇ ⁇ ⁇ 126 ⁇ Six data lines 126.
  • the first data line 121 is connected to the first thin film transistor 141
  • the second data line 122 is connected to the second thin film transistor 142
  • the third data line 123 is connected to the third thin film transistor 143
  • the fourth data line 124 is connected to the fourth thin film transistor 144
  • the fifth data line 125 is connected to the fifth thin film transistor 145
  • the sixth data line 126 is connected to the sixth thin film transistor 146.
  • a first node g1 is provided on the second data line 122
  • a fourth node g4 is provided on the fifth data line 125.
  • the first node g1 is connected to the drain of the second thin film transistor 143.
  • the node g1 is connected to the third node g3 connected to the fifth sub-pixel electrode 155 (that is, an odd-numbered sub-pixel electrode) through a metal trace passing through the gate insulating layer, thereby realizing the second connection to the first data bus 111
  • the data line 122 is connected to the fifth sub-pixel electrode 155 (that is, an odd-numbered column of sub-pixel electrodes).
  • the fourth node g4 is connected to the drain of the fifth thin film transistor 145, and the fourth node g4 is connected to the second sub-pixel electrode 152 (that is, the even-numbered sub-nodes) through a metal trace passing through the gate insulating layer.
  • Pixel electrode connected to the second node g2, so that the fifth data line 125 connected to the second data bus 112 is connected to the second sub-pixel electrode 152 (ie, even-numbered sub-pixel electrodes).
  • the data signals output by the first data bus 111 and having a positive polarity are respectively transmitted to the odd-numbered sub-pixel electrodes, for example, the odd-numbered sub-pixel electrodes (151, 153, 155) (that is, R, B, and G).
  • the data signals output by the second data bus 112 and having a negative polarity are respectively transmitted to the even-numbered sub-pixel electrodes, such as the even-numbered sub-pixel electrodes (152, 154, 156) (also That is, the polarities of G, R, and B) are all negative, thereby realizing the positive and negative inversion of the adjacent sub-pixel electrodes.
  • the above-mentioned second data line 122 and fifth data line 125 are prone to generate contact resistance due to the connection setting of the via (or via), and thus further cause the first data
  • the impedance of the line to the sixth data line is uneven, and a difference in load and a subsequent difference in charging are formed.
  • An object of the present invention is to provide a driving circuit and a liquid crystal display for a liquid crystal display panel, wherein the driving circuit provides a constant impedance design of a DEMUX circuit, and the contact resistance is solved by appropriately increasing the impedance of other data lines. Inconsistent problems, so as to achieve the effect of consistent load.
  • the present invention provides a driving circuit for a liquid crystal display panel.
  • the driving circuit includes at least two adjacent first data buses and a second data bus, and the first data buses respectively pass a first A data line, a second data line, and a third data line transmit a first type of data signal to a first subpixel electrode, a third subpixel electrode, and a fifth subpixel electrode of the liquid crystal display panel,
  • the second data bus transmits a second type of data signal to a fourth sub-pixel electrode and a second data signal of the liquid crystal display panel through a fourth data line, a fifth data line, and a sixth data line, respectively.
  • a sub-pixel electrode and a sixth sub-pixel electrode wherein the polarities of the first type of data signal and the second type of data signal are opposite;
  • the second data line passes through a first group of via structures to make all The second data line is connected to the fifth sub-pixel electrode, and the fifth data line passes a second group of via structures to connect the fifth data line to the second sub-pixel electrode;
  • the first group of via structures includes: on the second data line A first node is provided, the first node is connected to the drain of a thin film transistor connected to the second data line, and the first node is connected to the and through a metal trace passing through a gate insul
  • a third node connected to the fifth sub-pixel electrode; the second group of via structure openings includes: a fourth node is provided on the fifth data line, and the fourth node is connected to the fifth node; A drain of a thin film transistor connected to five data lines, the fourth node is connected to a second node connected to the second sub-pixel electrode through a metal trace passing through the gate insulating layer; First impedance structure, said second impedance Configuration, the third impedance and the fourth impedance structure is the same structure.
  • the driving circuit includes at least: two adjacent first data buses and a second data bus, and the first data buses pass through a first A data line, a second data line, and a third data line transmit a first type of data signal to a first subpixel electrode, a third subpixel electrode, and a fifth subpixel electrode of the liquid crystal display panel.
  • the second data bus transmits a second type of data signal to a fourth sub-pixel electrode and a first data signal of the liquid crystal display panel through a fourth data line, a fifth data line, and a sixth data line, respectively.
  • the second data line passes through a first group of via structures so that The second data line is connected to the fifth sub-pixel electrode, and the fifth data line passes a second group of via structures to connect the fifth data line to the second sub-pixel electrode; wherein, The first data line Is connected to the first sub-pixel electrode through a first impedance structure, the third data line is connected to the third sub-pixel electrode through a second impedance structure, and the fourth data line is through a third impedance structure Connected to the fourth sub-pixel electrode, and the sixth data line is connected to the sixth sub-pixel electrode through a fourth impedance structure.
  • the first group of via structures includes: a first node is provided on the second data line, and the first node is connected to a first node connected to the second data line; The drain of the thin film transistor, the first node is connected to a third node connected to the fifth sub-pixel electrode through a metal trace passing through a gate insulating layer; the second group of via structure openings
  • the method includes: a fourth node is provided on the fifth data line, the fourth node is connected to a drain of a thin film transistor connected to the fifth data line, and the fourth node passes through the fifth
  • the metal trace of the gate insulation layer is connected to a second node connected to the second sub-pixel electrode.
  • the first impedance structure includes: a fifth node is provided on the first data line, and the fifth node is connected to a thin film transistor connected to the first data line The fifth node is connected to a sixth node connected to the first sub-pixel electrode through a metal trace passing through the gate insulation layer;
  • the second impedance structure includes: A seventh node is provided on the three data lines, the seventh node is connected to the drain of a thin film transistor connected to the third data line, and the seventh node passes through a metal trace passing through the gate insulating layer Connected to an eighth node connected to the third sub-pixel electrode.
  • the third impedance structure includes: a ninth node is provided on the fourth data line, and the ninth node is connected to a thin film transistor connected to the fourth data line The ninth node is connected to a tenth node connected to the fourth sub-pixel electrode through a metal trace passing through the gate insulating layer;
  • the fourth impedance structure includes: An eleventh node is provided on the six data lines, the eleventh node is connected to the drain of a thin film transistor connected to the sixth data line, and the eleventh node is connected through a gate insulating layer.
  • the metal trace is connected to a twelfth node connected to the sixth sub-pixel electrode.
  • the first impedance structure is configured as an arcuate structure
  • the second impedance structure is configured as an arcuate structure
  • the third impedance structure is configured as an arcuate structure
  • the fourth impedance structure is configured as an arcuate structure
  • the first impedance structure, the second impedance structure, the third impedance structure, and the fourth impedance structure are the same.
  • the thin film transistor is an N-type thin film transistor or a P-type thin film transistor.
  • the present invention also provides a liquid crystal display.
  • the liquid crystal display includes the foregoing driving circuit and a liquid crystal display panel.
  • the liquid crystal display panel includes a plurality of data lines, a plurality of scanning lines, and a plurality of pixels.
  • the pixel includes a plurality of sub-pixel electrodes; the driving circuit is configured to drive the liquid crystal display panel.
  • the driving circuit of the liquid crystal display panel of the present invention provides an equi-impedance design of the DEMUX line.
  • the impedance of other data lines is appropriately increased to solve the problem of inconsistent contact resistance, thereby avoiding load differences and charging differences, and achieving the effect of consistent loads .
  • FIG. 1 is a schematic connection diagram of a driving circuit in the prior art.
  • FIG. 2 is a connection schematic diagram of a driving circuit of a liquid crystal display panel in a first embodiment of the present invention.
  • FIG. 3 is a connection schematic diagram of a driving circuit of a liquid crystal display panel in a second embodiment of the present invention.
  • the present invention provides a driving circuit for a liquid crystal display panel.
  • the driving circuit includes at least: two adjacent first data buses 111 and a second data bus 112.
  • a data bus 111 transmits the first type of data signals to the first sub-pixel electrode 151, the third sub-pixel electrode 153, and the first sub-pixel electrode 151 of the liquid crystal display panel through the first data line 121, the second data line 122, and the third data line 123, respectively.
  • the five sub-pixel electrodes 155 and the second data bus 112 transmit the second type of data signals to the fourth sub-pixel electrode 154 and the first sub-pixel electrode 154 of the liquid crystal display panel through the fourth data line 124, the fifth data line 125, and the sixth data line 126, respectively.
  • the two sub-pixel electrodes 152 and the sixth sub-pixel electrode 156 wherein the polarities of the data signals of the first type and the data signals of the second type are opposite.
  • the first subpixel electrode 151 is a red subpixel electrode R
  • the third subpixel electrode 153 is a blue subpixel electrode B
  • the fifth subpixel electrode 155 is a green subpixel electrode G.
  • the first subpixel electrode 151 may be a blue subpixel electrode B or a green subpixel electrode G
  • the third subpixel electrode 153 may be a red subpixel electrode R or a green subpixel electrode G
  • the fifth subpixel electrode 155 may be a red sub-pixel electrode R or a blue sub-pixel electrode B
  • the fourth subpixel electrode 154 is a red subpixel electrode R
  • the second subpixel electrode 152 is a green subpixel electrode G
  • the sixth subpixel electrode 156 is a blue subpixel electrode B.
  • the first subpixel electrode 151 and the third subpixel are The electrode 153 and the fifth sub-pixel electrode 155 each receive a data signal with a positive polarity, and the fourth sub-pixel electrode 154, the second sub-pixel electrode 152, and the sixth sub-pixel electrode 156 each receive a negative polarity Data signal.
  • the polarity received by each sub-pixel electrode is the same as that described above. in contrast.
  • the second data line 122 passes through the first group of via structures 161 to connect the second data line 122 to the fifth sub-pixel electrode 155
  • the fifth data line 125 passes through the second group of via structures 162
  • the fifth data line 125 is connected to the second sub-pixel electrode 152.
  • the first group of via structures 161 includes: a first node g1 is provided on the second data line 122, and the first node g1 is connected to the drain of the thin film transistor 142 connected to the second data line 122
  • the first node g1 is connected to the third node g3 connected to the fifth sub-pixel electrode 155 through a metal trace passing through the gate insulating layer, so that the second data line 122 connected to the first data bus 111 is connected to The fifth sub-pixel electrode 155 (which is an odd-numbered column of sub-pixel electrodes).
  • the second group of via structure 162 includes: a fourth node g4 is provided on the fifth data line 125, and the fourth node g4 is connected to the drain of the thin film transistor 145 connected to the fifth data line 125;
  • the four node g4 is connected to the second node g2 connected to the second sub-pixel electrode 152 through a metal trace passing through the gate insulating layer, so that the fifth data line 125 connected to the second data bus 112 is connected to the second node
  • the sub-pixel electrode 152 (which is an even-numbered column of sub-pixel electrodes).
  • the data signals output by the first data bus 111 and having a positive polarity are respectively transmitted to the odd-numbered columns.
  • Pixel electrodes at this time, the polarities of the sub-pixel electrodes (R, B, G) in the odd-numbered columns are all positive; the data signals output by the second data bus 112 and having a negative polarity are transmitted to the even-numbered sub-pixel electrodes, respectively.
  • the polarity of the sub-pixel electrodes (G, R, B) in the even-numbered columns is negative, the positive and negative inversions of the adjacent sub-pixel electrodes are achieved.
  • the second data line 122 and the fifth data line 125 may be affected by the design of the first group of via structures 161 and the second group of via structures 162.
  • the contact resistance is generated, which further causes the impedance of the green data line to be different from that of the other two data lines (red data line and blue data line), that is, the impedances of the first to sixth data lines 121 to 126 are uneven, and Form load difference and charge difference.
  • an impedance is set on the first data line 121 and the third data line 123, respectively.
  • Structure (171, 172) so that the impedance of the data line remains the same.
  • an impedance structure (173, 174) is also provided on the fourth data line 124 and the sixth data line 126, so that the impedances of the data lines remain the same.
  • first data line 121 is connected to the first sub-pixel electrode 151 through a first impedance structure 171
  • the third data line 123 is connected to the third sub-pixel electrode 153 through a second impedance structure 172.
  • the fourth data line 124 is connected to the fourth sub-pixel electrode 154 through a third impedance structure 173
  • the sixth data line 126 is connected to the sixth sub-pixel electrode 156 through a fourth impedance structure 174.
  • the first impedance structure 171 is designed as follows, which includes: a fifth node r1 is provided on the first data line 121, and the fifth node r1 is connected to the first node
  • the fifth node r1 of the thin film transistor 141 connected to the data line 121 is connected to the sixth node r2 connected to the first sub-pixel electrode 151 through a metal trace passing through the gate insulating layer.
  • the second impedance structure 172 is designed as follows, which includes: a seventh node b1 is provided on the third data line 123, and the seventh node b1 is connected to the thin film transistor 143 connected to the third data line 123 The seventh node b1 is connected to the eighth node b2 connected to the third sub-pixel electrode 153 through a metal trace passing through the gate insulating layer.
  • the impedance value generated by the first impedance structure 171 (that is, the red data line impedance value) and the impedance generated by the second impedance structure 172
  • the value (that is, the impedance value of the blue data line) is consistent with the impedance value of the green data line, so that the impedance of the data line is uniform, and the difference in load and charge are avoided.
  • the contact resistance generated by the first group of via structures 161 can be obtained by using a dedicated electronic measurement device at the first node and the third node of the first group of via structures 161 to obtain a voltage value, and according to the voltage and current Calculate the formula to obtain the corresponding resistance value of the contact resistance (that is, the impedance value of the green data line).
  • the impedance values obtained at the fifth node and the sixth node in the first impedance structure 171 may be based on the green data line impedance value. Make adjustments accordingly.
  • the impedance values (ie, the blue data line impedance value) obtained by the seventh node and the eighth node in the second impedance structure 172 may be based on the green color. Adjust the data line impedance accordingly.
  • the third impedance structure 173 is designed as follows, which includes: a ninth node r3 is provided on the fourth data line 124, and the ninth node r3 is connected to the fourth data
  • the ninth node r3 of the thin film transistor 144 connected to the line 124 is connected to the tenth node r4 connected to the fourth sub-pixel electrode 154 through a metal trace passing through the gate insulating layer.
  • the fourth impedance structure 174 is designed as follows, which includes: an eleventh node b3 is provided on the sixth data line 126, and the eleventh node b3 is connected to a film connected to the sixth data line 126 The eleventh node b3 of the transistor 126 is connected to the twelfth node b4 connected to the sixth sub-pixel electrode 156 through a metal trace passing through the gate insulating layer.
  • the impedance value of the contact resistance ie, the green data line impedance value
  • the impedance value (ie, the impedance value of the blue data line) generated by the four-impedance structure 174 is consistent with the impedance value of the green data line, so that the impedance of the data line is uniform, and the difference in load and charge are avoided.
  • the impedance value obtained by the ninth node and the tenth node in the third impedance structure 173 may be based on Adjust the green data line impedance accordingly.
  • the impedance values obtained by the eleventh node and the twelfth node in the fourth impedance structure 174 may be Make corresponding adjustments based on the green data line impedance.
  • the first impedance structure 171 to the fourth The impedance structure 174 is designed to be the same, so that the impedance of each data line connected to two data buses with different polarities is equal, which effectively overcomes the problem of load difference and charge difference, and has good uniformity.
  • the above-mentioned thin film transistor is an N-type thin film transistor or a P-type thin film transistor, and can be adjusted accordingly according to the actual situation.
  • the thin film transistor is used as a switching device, and the data signal output by the data bus is transmitted to the corresponding sub-display on the display panel through the data line through the on or off mode (that is, the switching device is turned on or off).
  • Pixel electrode In other embodiments, other types of switching devices may also be used, and are not limited to thin film transistors.
  • the driving circuit of the liquid crystal display panel shown in FIG. 2 is only a part of the driving circuit of the present invention.
  • the number of data buses can be set according to the actual needs of the display panel.
  • This embodiment Taking only two adjacent data buses as an example, the present invention cannot be considered to include only two data buses.
  • the number of data lines connected to the data bus and the number of sub-pixel electrodes connected to the data lines are also adaptively adjusted.
  • the remaining component structures are the same.
  • the first impedance structure 181 and the second impedance structure 182 are designed as follows, which are configured as an arcuate structure. Through the design of the bow structure, not only the impedance value generated by the first impedance structure 181 (ie, the red data line impedance value) and the impedance value generated by the second impedance structure 182 (ie, the blue data line impedance value) and the green data can be made. The line impedance values are consistent, and the space of the printed circuit board where the data lines are located can be effectively used.
  • the design of the first impedance structure 181 and the second impedance structure 182 is not limited to an arcuate structure, and may be another shape structure, as long as the impedance value and the first impedance structure 181 generated by the first impedance structure 181 are satisfied.
  • the impedance value generated by the two impedance structure 182 may be equal to the impedance value of the green data line.
  • the contact resistance generated by the first group of via structures 161 can be obtained by using a dedicated electronic measurement device at the first node and the third node of the first group of via structures 161 to obtain a voltage value, and according to the voltage and current Calculate the formula to obtain the corresponding resistance value of the contact resistance (that is, the impedance value of the green data line).
  • the impedance value obtained by the first impedance structure 181 may be adjusted according to the green data line impedance value.
  • the impedance value (ie, the blue data line impedance value) obtained by the second impedance structure 182 can be adjusted according to the green data line impedance value.
  • the third impedance structure 183 and the fourth impedance structure 184 are configured as arcuate structures.
  • the first impedance structure 181, the second impedance structure 182, the third impedance structure 183, and the fourth impedance structure 184 are set to the same arcuate structure shape, so that the impedance of the data line is uniform.
  • the (red) impedance value obtained by the third impedance structure 183 can be adjusted accordingly according to the green data line impedance value.
  • the impedance value obtained by the fourth impedance structure 184 (that is, the blue data line impedance value) can be adjusted accordingly according to the green data line impedance value.
  • the present invention also provides a liquid crystal display.
  • the liquid crystal display includes the above-mentioned driving circuit and a liquid crystal display panel.
  • the liquid crystal display panel includes a plurality of data lines, a scan line, and a plurality of pixels.
  • the pixels include a plurality of sub-pixels. Electrodes; the driving circuit is used to drive the liquid crystal display panel.
  • the driving circuit in this embodiment may be any one of the driving circuits in FIG. 2 to FIG. 3. For details, refer to FIG. 2 to FIG. 3 and the foregoing specific description, and details are not described herein again.
  • the driving circuit and liquid crystal display of the liquid crystal display panel of the present invention provide an equi-impedance design of the DEMUX line.
  • the impedance of other data lines is appropriately increased to solve the problem of inconsistent contact resistance, thereby avoiding the load difference and charging difference, and reaching the load. Consistent effect.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种液晶显示面板的驱动电路及液晶显示器，驱动电路包括：第一数据总线（111）和第二数据总线（112），第一数据总线（111）通过第一数据线（121）、第二数据线（122）、第三数据线（123）将第一类数据信号传送至第一子像素电极（151）、第三子像素电极（153）和第五子像素电极（155），第二数据总线（112）通过第四数据线（124）、第五数据线（125）、第六数据线（126）将第二类数据信号传送至第四子像素电极（154）、第二子像素电极（152）和第六子像素电极（156）；第二数据线（122）通过第一组过孔结构（161）以使第二数据线（122）连接第五子像素电极（155），第五数据线（125）通过第二组过孔结构（162）以使第五数据线（125）连接至第二子像素电极（152）；第一数据线（121）通过第一阻抗结构（171）连接至第一子像素电极（151），第三数据线（123）通过第二阻抗结构（172）连接至第三子像素电极（153），第四数据线（124）通过第三阻抗结构（173）连接至第四子像素电极（154），第六数据线（126）通过第四阻抗结构（174）连接至第六子像素电极（156），通过适当增加其他数据线的阻抗以解决接触电阻不一致的问题，从而达到负荷一致的效果。

Description

一种液晶显示面板的驱动电路及液晶显示器 技术领域
本发明涉及液晶显示面板技术领域，尤其涉及一种液晶显示面板的驱动电路及液晶显示器。
 背景技术
目前，液晶显示器逐渐地成为消费电子产品的重要角色，其广泛应用于具有高分辨率彩色屏幕的移动终端等设备的显示器中，其中，薄膜晶体管液晶显示器是主要的液晶显示器之一。
参阅图1，图1是现有技术中液晶显示面板及其驱动电路的结构示意图。如图1所示，显示面板上设置有若干个子像素电极（R、G、B子像素电极）、多条扫描线和多条数据线交错设置。显示面板上的每一列子像素电极与每条数据线相连。图1中的驱动电路包括两条数据总线（111，112），每一条数据总线（111，112）的输出端与三列数据线的公共输入端相连。相邻数据总线输出的数据信号的极性为相反，如图1所示，例如第一数据总线111输出的数据信号为正，相邻的第二数据总线112输出的数据信号为负。另外，如图1所示，switch开关（例如薄膜晶体管）的控制端（SWR,SWG,SWB）与扫描线（131，132，133）相连，通过控制switch开关的开启和闭合，即控制薄膜晶体管（141，142，143，144，145，146）的导通和截止，从而根据薄膜晶体管（141，142，143，144，145，146）的导通和截止以使数据总线所输出的数据信号通过数据线传送至显示面板上相应的子像素电极（151，152，153，154，155，156），并且实现了对数据总线的输入进行时分多工，这样能够减少源极驱动芯片的数量，并且降低相关成本。
如图1所示，为了保证显示面板上相邻两列的两个子像素电极上的数据信号的极性相反，以实现显示面板的点反转，因此，在现有技术中，例如与绿色子像素电极相连的数据线增加四组转接孔g1-g4，来实现上述的相邻列子像素电极的正负反转。具体地，第一数据总线111分别连接至第一数据线121、第二数据线122、第三数据线123，第二数据总线112分别连接至第四数据线124、第五数据线125、第六数据线126。第一数据线121与第一薄膜晶体管141相连，第二数据线122与第二薄膜晶体管142相连，第三数据线123与第三薄膜晶体管143相连，第四数据线124与第四薄膜晶体管144相连，第五数据线125与第五薄膜晶体管145相连，第六数据线126与第六薄膜晶体管146相连。在第二数据线122上分别设有第一节点g1，在第五数据线125上设有第四节点g4，所述第一节点g1与所述第二薄膜晶体管143的漏极相连，第一节点g1通过一穿过栅极绝缘层的金属走线连接至与第五子像素电极155（即奇数列子像素电极）相连的第三节点g3，从而实现与第一条数据总线111相连的第二数据线122连接至第五子像素电极155（即奇数列子像素电极）。另外，所述第四节点g4与所述第五薄膜晶体管145的漏极相连，第四节点g4通过一穿过栅极绝缘层的金属走线连接至与第二子像素电极152（即偶数列子像素电极）相连的第二节点g2，从而实现与第二数据总线112相连的第五数据线125连接至第二子像素电极152（即偶数列子像素电极）。这样，第一数据总线111所输出的且极性为正的数据信号分别传送至奇数列子像素电极，例如此时奇数列的子像素电极（151、153、155）（亦即R，B，G）的极性均为正；第二数据总线112所输出的且极性为负的数据信号分别传送至偶数列子像素电极，例如此时偶数列的子像素电极（152、154、156）（亦即G，R，B）的极性均为负，进而实现相邻列子像素电极的正负反转。
 技术问题
由于如此配置，使得上述第二数据线122和第五数据线125（此处为绿线）因转接孔（或称过孔）的连接设置而容易产生接触电阻，因此，进一步造成第一数据线至第六数据线的阻抗不均，并且形成负荷差异及随之产生的充电差异。
 技术解决方案
本发明的目的在于，本发明提供了一种液晶显示面板的驱动电路及液晶显示器，其中所述驱动电路提供出一种DEMUX线路的等阻抗设计，通过适当增加其他数据线的阻抗以解决接触电阻不一致的问题，从而达到负荷一致的效果。
为了实现上述目的，本发明提供一种液晶显示面板的驱动电路，所述驱动电路至少包括：两条相邻的第一数据总线和第二数据总线，所述第一数据总线分别通过一第一数据线、一第二数据线、一第三数据线将一第一类数据信号传送至所述液晶显示面板的一第一子像素电极、一第三子像素电极和一第五子像素电极，所述第二数据总线分别通过一第四数据线、一第五数据线、一第六数据线将一第二类数据信号传送至所述液晶显示面板的一第四子像素电极、一第二子像素电极和一第六子像素电极，其中，所述第一类数据信号和所述第二类数据信号的极性相反；所述第二数据线通过一第一组过孔结构以使所述第二数据线连接至所述第五子像素电极，所述第五数据线通过一第二组过孔结构以使所述第五数据线连接至所述第二子像素电极；其中，所述第一数据线通过一第一阻抗结构连接至所述第一子像素电极，所述第三数据线通过一第二阻抗结构连接至所述第三子像素电极，所述第四数据线通过一第三阻抗结构连接至所述第四子像素电极，所述第六数据线通过一第四阻抗结构连接至所述第六子像素电极；所述第一组过孔结构包括：在所述第二数据线上设有一第一节点，所述第一节点连接至与所述第二数据线相连的一薄膜晶体管的漏极，所述第一节点通过一穿过一栅极绝缘层的金属走线连接至与所述第五子像素电极相连的一第三节点；所述第二组过孔结构口包括：在所述第五数据线上设有一第四节点，所述第四节点连接至与所述第五数据线相连的一薄膜晶体管的漏极，所述第四节点通过一穿过所述栅极绝缘层的金属走线连接至与所述第二子像素电极相连的一第二节点；所述第一阻抗结构、所述第二阻抗结构、所述第三阻抗结构和所述第四阻抗结构为相同。
本发明的另一目的在于，提供一种液晶显示面板的驱动电路，所述驱动电路至少包括：两条相邻的第一数据总线和第二数据总线，所述第一数据总线分别通过一第一数据线、一第二数据线、一第三数据线将一第一类数据信号传送至所述液晶显示面板的一第一子像素电极、一第三子像素电极和一第五子像素电极，所述第二数据总线分别通过一第四数据线、一第五数据线、一第六数据线将一第二类数据信号传送至所述液晶显示面板的一第四子像素电极、一第二子像素电极和一第六子像素电极，其中，所述第一类数据信号和所述第二类数据信号的极性相反；所述第二数据线通过一第一组过孔结构以使所述第二数据线连接至所述第五子像素电极，所述第五数据线通过一第二组过孔结构以使所述第五数据线连接至所述第二子像素电极；其中，所述第一数据线通过一第一阻抗结构连接至所述第一子像素电极，所述第三数据线通过一第二阻抗结构连接至所述第三子像素电极，所述第四数据线通过一第三阻抗结构连接至所述第四子像素电极，所述第六数据线通过一第四阻抗结构连接至所述第六子像素电极。
在本发明的一实施例中，所述第一组过孔结构包括：在所述第二数据线上设有一第一节点，所述第一节点连接至与所述第二数据线相连的一薄膜晶体管的漏极，所述第一节点通过一穿过一栅极绝缘层的金属走线连接至与所述第五子像素电极相连的一第三节点；所述第二组过孔结构口包括：在所述第五数据线上设有一第四节点，所述第四节点连接至与所述第五数据线相连的一薄膜晶体管的漏极，所述第四节点通过一穿过所述栅极绝缘层的金属走线连接至与所述第二子像素电极相连的一第二节点。
在本发明的一实施例中，所述第一阻抗结构包括：在所述第一数据线上设有一第五节点，所述第五节点连接至与所述第一数据线相连的一薄膜晶体管的漏极，所述第五节点通过一穿过栅极绝缘层的金属走线连接至与所述第一子像素电极相连的一第六节点；所述第二阻抗结构包括：在所述第三数据线上设有一第七节点，所述第七节点连接至与所述第三数据线相连的一薄膜晶体管的漏极，所述第七节点通过一穿过栅极绝缘层的金属走线连接至与所述第三子像素电极相连的一第八节点。
在本发明的一实施例中，所述第三阻抗结构包括：在所述第四数据线上设有一第九节点，所述第九节点连接至与所述第四数据线相连的一薄膜晶体管的漏极，所述第九节点通过一穿过栅极绝缘层的金属走线连接至与所述第四子像素电极相连的一第十节点；所述第四阻抗结构包括：在所述第六数据线上设有一第十一节点，所述第十一节点连接至与所述第六数据线相连的一薄膜晶体管的漏极，所述第十一节点通过一穿过栅极绝缘层的金属走线连接至与所述第六子像素电极相连的一第十二节点。
在本发明的一实施例中，所述第一阻抗结构设置为一弓形结构，所述第二阻抗结构设置为一弓形结构。
在本发明的一实施例中，所述第三阻抗结构设置为一弓形结构，所述第四阻抗结构设置为一弓形结构。
在本发明的一实施例中，所述第一阻抗结构、所述第二阻抗结构、所述第三阻抗结构和所述第四阻抗结构为相同。
在本发明的一实施例中，所述薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管。
另外，本发明还提供一种液晶显示器，所述液晶显示器包括上述的驱动电路和一液晶显示面板，所述液晶显示面板包括多条数据线、多条扫描线及多个像素，所述多个像素包括多个子像素电极；所述驱动电路用于驱动所述液晶显示面板。
 有益效果
本发明液晶显示面板的驱动电路提供出一种DEMUX线路的等阻抗设计，通过适当增加其他数据线的阻抗以解决接触电阻不一致的问题，从而避免了负荷差异及充电差异，并且达到负荷一致的效果。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中的一种驱动电路的连接示意图。
图2是本发明第一实施例中的液晶显示面板的驱动电路的连接示意图。
图3是本发明第二实施例中的液晶显示面板的驱动电路的连接示意图。
 本发明的最佳实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书以及上述附图中的术语“第一”、“第二”、“第三”等（如果存在）是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应当理解，这样描述的对象在适当情况下可以互换。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含。
在本专利文档中，下文论述的附图以及用来描述本发明公开的原理的各实施例仅用于说明，而不应解释为限制本发明公开的范围。所属领域的技术人员将理解，本发明的原理可在任何适当布置的系统中实施。将详细说明示例性实施方式，在附图中示出了这些实施方式的实例。此外，将参考附图详细描述根据示例性实施例的终端。附图中的相同附图标号指代相同的元件。
本发明说明书中使用的术语仅用来描述特定实施方式，而并不意图显示本发明的概念。除非上下文中有明确不同的意义，否则，以单数形式使用的表达涵盖复数形式的表达。在本发明说明书中，应理解，诸如“包括”、“具有”以及“含有”等术语意图说明存在本发明说明书中揭示的特征、数字、步骤、动作或其组合的可能性，而并不意图排除可存在或可添加一个或多个其他特征、数字、步骤、动作或其组合的可能性。附图中的相同参考标号指代相同部分。
参见图2所示，在第一实施例中，本发明提供一种液晶显示面板的驱动电路，所述驱动电路至少包括：两条相邻的第一数据总线111和第二数据总线112，第一数据总线111分别通过第一数据线121、第二数据线122、第三数据线123将第一类数据信号传送至液晶显示面板的第一子像素电极151、第三子像素电极153和第五子像素电极155，第二数据总线112分别通过第四数据线124、第五数据线125、第六数据线126将第二类数据信号传送至液晶显示面板的第四子像素电极154、第二子像素电极152和第六子像素电极156，其中，第一类数据信号和第二类数据信号的极性相反。如图2所示，第一子像素电极151为红色子像素电极R、第三子像素电极153为蓝色子像素电极B、第五子像素电极155为绿色子像素电极G，当然在其他部分实施例中，第一子像素电极151可以为蓝色子像素电极B或绿色子像素电极G，第三子像素电极153可以为红色子像素电极R或绿色子像素电极G，第五子像素电极155可以为红色子像素电极R或蓝色子像素电极B。同样，第四子像素电极154为红色子像素电极R、第二子像素电极152为绿色子像素电极G、第六子像素电极156为蓝色子像素电极B。另外，在本实施例中，由于第一数据总线111所输出的数据信号为正，第二数据总线112所输出的数据信号为负，因此，所述第一子像素电极151、第三子像素电极153和第五子像素电极155均接收到极性为正的数据信号，所述第四子像素电极154、第二子像素电极152和第六子像素电极156均接收到极性为负的数据信号。当然，在其他部分实施例中，当第一数据总线111所输出的数据信号为负，第二数据总线112所输出的数据信号为正，则每一子像素电极接收到的极性与上述情况相反。
另外，在本实施例中，第二数据线122通过第一组过孔结构161以使第二数据线122连接至第五子像素电极155，第五数据线125通过第二组过孔结构162以使第五数据线125连接至第二子像素电极152。具体地，所述第一组过孔结构161包括：在第二数据线122上设有第一节点g1，所述第一节点g1连接至与第二数据线122相连的薄膜晶体管142的漏极，第一节点g1通过一穿过栅极绝缘层的金属走线连接至与第五子像素电极155相连的第三节点g3，从而实现与第一数据总线111相连的第二数据线122连接至第五子像素电极155（其为一奇数列子像素电极）。所述第二组过孔结构162口包括：在第五数据线125上设有第四节点g4，所述第四节点g4连接至与第五数据线125相连的薄膜晶体管145的漏极，第四节点g4通过一穿过栅极绝缘层的金属走线连接至与第二子像素电极152相连的第二节点g2，从而实现与第二数据总线112相连的第五数据线125连接至第二子像素电极152（其为一偶数列子像素电极）。也就是说，通过上述的所述第一组过孔结构161和所述第二组过孔结构162的设计，第一数据总线111所输出的且极性为正的数据信号分别传送至奇数列子像素电极，此时奇数列的子像素电极（R，B，G）的极性均为正；第二数据总线112所输出的且极性为负的数据信号分别传送至偶数列子像素电极，此时偶数列的子像素电极（G，R，B）的极性均为负，进而实现相邻列子像素电极的正负反转。
由于如此设置，使得第二数据线122和第五数据线125（在本实施例中，为绿线数据线）因第一组过孔结构161和第二组过孔结构162的设计而可能会产生接触电阻，因此进一步导致绿色数据线与其他两种数据线（红色数据线和蓝色数据线）的阻抗不同，亦即，第一数据线121至第六数据线126的阻抗不均，并且形成负荷差异及充电差异。
为了有效地保证每一组数据线阻抗均匀，亦即，红色数据线、蓝色数据线和绿色数据线的阻抗一致，因此，在第一数据线121和第三数据线123上分别设置一阻抗结构（171，172），以使得数据线的阻抗保持一致。同样，在第四数据线124和第六数据线126上也分别设置一阻抗结构（173，174），以使得数据线的阻抗保持一致。进一步而言，所述第一数据线121通过一第一阻抗结构171连接至第一子像素电极151，所述第三数据线123通过一第二阻抗结构172连接至第三子像素电极153，所述第四数据线124通过一第三阻抗结构173连接至第四子像素电极154，所述第六数据线126通过一第四阻抗结构174连接至第六子像素电极156。
具体地，在第一实施例中，将所述第一阻抗结构171设计为如下，其包括：在第一数据线121上设有第五节点r1，所述第五节点r1连接至与第一数据线121相连的薄膜晶体管141的漏极，第五节点r1通过一穿过栅极绝缘层的金属走线连接至与第一子像素电极151相连的第六节点r2。同样，将所述第二阻抗结构172设计为如下，其包括：在第三数据线123上设有第七节点b1，所述第七节点b1连接至与第三数据线123相连的薄膜晶体管143的漏极，第七节点b1通过一穿过栅极绝缘层的金属走线连接至与第三子像素电极153相连的第八节点b2。于是，根据上述第一组过孔结构161而产生的接触电阻的阻抗值，以使得第一阻抗结构171所产生的阻抗值（即红色数据线阻抗值）和第二阻抗结构172所产生的阻抗值（即蓝色数据线阻抗值）与绿色数据线阻抗值一致，从而使得数据线阻抗均匀，并且避免负荷差异和充电差异。需说明的是，第一组过孔结构161产生的接触电阻可以通过使用专属电子测量装置在第一组过孔结构161中的第一节点和第三节点取点获得电压值，并且根据电压电流计算公式而获得接触电阻相应的阻抗值（即绿色数据线阻抗值）。为了使得红色数据线阻抗值与绿色数据线阻抗值一致，在第一阻抗结构171中的第五节点和第六节点所获得的阻抗值（即红色数据线阻抗值）可以根据绿色数据线阻抗值做相应的调整。同样，为了使得蓝色数据线阻抗值与绿色数据线阻抗值一致，在第二阻抗结构172中的第七节点和第八节点所获得的阻抗值（即蓝色数据线阻抗值）可以根据绿色数据线阻抗值做相应的调整。
同样，在第一实施例中，将所述第三阻抗结构173设计为如下，其包括：在第四数据线124上设有第九节点r3，所述第九节点r3连接至与第四数据线124相连的薄膜晶体管144的漏极，第九节点r3通过一穿过栅极绝缘层的金属走线连接至与第四子像素电极154相连的第十节点r4。同样，将所述第四阻抗结构174设计为如下，其包括：在第六数据线126上设有第十一节点b3，所述第十一节点b3连接至与第六数据线126相连的薄膜晶体管126的漏极，第十一节点b3通过一穿过栅极绝缘层的金属走线连接至与第六子像素电极156相连的第十二节点b4。于是，根据上述第二组过孔结构162而产生的接触电阻的阻抗值（即绿色数据线阻抗值），以使得第三阻抗结构173所产生的阻抗值（即红色数据线阻抗值）和第四阻抗结构174所产生的阻抗值（即蓝色数据线阻抗值）与绿色数据线阻抗值一致，从而使得数据线阻抗均匀，并且避免负荷差异和充电差异。需说明的是，为了使得红色数据线阻抗值与绿色数据线阻抗值一致，在第三阻抗结构173中的第九节点和第十节点所获得的阻抗值（即红色数据线阻抗值）可以根据绿色数据线阻抗值做相应的调整。同样，为了使得蓝色数据线阻抗值与绿色数据线阻抗值一致，在第四阻抗结构174中的第十一节点和第十二节点所获得的阻抗值（即蓝色数据线阻抗值）可以根据绿色数据线阻抗值做相应的调整。
优选地，当第一组过孔结构161和第二组过孔结构162所产生的接触电阻的阻抗值（即绿色数据线阻抗值）相等时，于是，可以将第一阻抗结构171至第四阻抗结构174设计为相同，从而使得与两个极性不同的数据总线相连的每一数据线的阻抗均为相等，有效地克服负荷差异和充电差异的问题，具有良好的统一性。
另外，在第一实施例中，上述薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管，可以根据实际情况而相应的调整。当然，在本实施例中，薄膜晶体管作为一开关器件，通过导通或截止方式（即开关器件的闭合或开启）而使得数据总线所输出的数据信号通过数据线传送至显示面板上相应的子像素电极。在其他部分实施例中，也可以使用其他类型的开关器件，不限于薄膜晶体管。
另外，可以理解的是，图2所示液晶显示面板的驱动电路仅仅是本发明的驱动电路的一部分，在实际显示面板中，数据总线的数量可以根据显示面板的实际需求进行设置，本实施例仅以相邻的两条数据总线为例，但不能认为本发明仅包含两条数据总线。相应的，与数据总线相连的数据线以及与数据线相连的子像素电极的数量也进行适应性的调整。
 本发明的实施方式
在第二实施例中，除了第一阻抗结构181、第二阻抗结构182、第三阻抗结构183、第四阻抗结构184与第一实施例中的第一阻抗结构171、第二阻抗结构172、第三阻抗结构173、第四阻抗结构174不同之外，其余的组件结构为相同。
将所述第一阻抗结构181和所述第二阻抗结构182设计为如下，其设置为弓形结构。通过弓形结构的设计，不仅能够使得第一阻抗结构181所产生的阻抗值（即红色数据线阻抗值）和第二阻抗结构182所产生的阻抗值（即蓝色数据线阻抗值）与绿色数据线阻抗值一致，而且能够有效地利用数据线所在的印刷电路板的空间。当然，在其他部分实施例中，所述第一阻抗结构181和第二阻抗结构182的设计不限于弓形结构，也可以为其他形状结构，只要满足第一阻抗结构181所产生的阻抗值和第二阻抗结构182所产生的阻抗值与绿色数据线阻抗值相等即可。需说明的是，第一组过孔结构161产生的接触电阻可以通过使用专属电子测量装置在第一组过孔结构161中的第一节点和第三节点取点获得电压值，并且根据电压电流计算公式而获得接触电阻相应的阻抗值（即绿色数据线阻抗值）。为了使得红色数据线阻抗值与绿色数据线阻抗值一致，第一阻抗结构181所获得的阻抗值（即红色数据线阻抗值）可以根据绿色数据线阻抗值做相应的调整。同样，为了使得蓝色数据线阻抗值与绿色数据线阻抗值一致，第二阻抗结构182所获得的阻抗值（即蓝色数据线阻抗值）可以根据绿色数据线阻抗值做相应的调整。
同样，将所述第三阻抗结构183和所述第四阻抗结构184设置为弓形结构。当然，优选地，将第一阻抗结构181、所述第二阻抗结构182、所述第三阻抗结构183和所述第四阻抗结构184设置为相同的弓形结构形状，从而使得数据线阻抗均匀。为了使得（红色）阻抗值与绿色数据线阻抗值一致，第三阻抗结构183所获得的（红色）阻抗值可以根据绿色数据线阻抗值做相应的调整。同样，为了使得蓝色数据线阻抗值与绿色数据线阻抗值一致，第四阻抗结构184所获得的阻抗值（即蓝色数据线阻抗值）可以根据绿色数据线阻抗值做相应的调整。
另外，本发明还提供一种液晶显示器，所述液晶显示器包括上述的驱动电路和液晶显示面板，所述液晶显示面板包括多条数据线、扫描线及多个像素，所述像素包括多个子像素电极；所述驱动电路用于驱动所述液晶显示面板。本实施例中的驱动电路可以为图2至图3中任意一种驱动电路，具体请参阅图2至图3及上述的具体说明，在此不再赘述。
本发明液晶显示面板的驱动电路及液晶显示器提供出一种DEMUX线路的等阻抗设计，通过适当增加其他数据线的阻抗以解决接触电阻不一致的问题，从而避免了负荷差异及充电差异，并且达到负荷一致的效果。
以上对本发明实施例所提供的一种液晶显示面板的驱动电路及液晶显示器进行了详细介绍。应理解，本文所述的示例性实施方式应仅被认为是描述性的，用于帮助理解本发明的方法及其核心思想，而并不用于限制本发明。在每个示例性实施方式中对特征或方面的描述通常应被视作适用于其他示例性实施例中的类似特征或方面。尽管参考示例性实施例描述了本发明，但可建议所属领域的技术人员进行各种变化和更改。本发明意图涵盖所附权利要求书的范围内的这些变化和更改。

Claims (10)

  1. 一种液晶显示面板的驱动电路，至少包括：两条相邻的第一数据总线和第二数据总线，所述第一数据总线分别通过一第一数据线、一第二数据线、一第三数据线将一第一类数据信号传送至所述液晶显示面板的一第一子像素电极、一第三子像素电极和一第五子像素电极，所述第二数据总线分别通过一第四数据线、一第五数据线、一第六数据线将一第二类数据信号传送至所述液晶显示面板的一第四子像素电极、一第二子像素电极和一第六子像素电极，其中，所述第一类数据信号和所述第二类数据信号的极性相反；所述第二数据线通过一第一组过孔结构以使所述第二数据线连接至所述第五子像素电极，所述第五数据线通过一第二组过孔结构以使所述第五数据线连接至所述第二子像素电极；其中，所述第一数据线通过一第一阻抗结构连接至所述第一子像素电极，所述第三数据线通过一第二阻抗结构连接至所述第三子像素电极，所述第四数据线通过一第三阻抗结构连接至所述第四子像素电极，所述第六数据线通过一第四阻抗结构连接至所述第六子像素电极；所述第一组过孔结构包括：在所述第二数据线上设有一第一节点，所述第一节点连接至与所述第二数据线相连的一薄膜晶体管的漏极，所述第一节点通过一穿过一栅极绝缘层的金属走线连接至与所述第五子像素电极相连的一第三节点；所述第二组过孔结构口包括：在所述第五数据线上设有一第四节点，所述第四节点连接至与所述第五数据线相连的一薄膜晶体管的漏极，所述第四节点通过一穿过所述栅极绝缘层的金属走线连接至与所述第二子像素电极相连的一第二节点；所述第一阻抗结构、所述第二阻抗结构、所述第三阻抗结构和所述第四阻抗结构为相同。
  2. 一种液晶显示面板的驱动电路，至少包括：两条相邻的第一数据总线和第二数据总线，所述第一数据总线分别通过一第一数据线、一第二数据线、一第三数据线将一第一类数据信号传送至所述液晶显示面板的一第一子像素电极、一第三子像素电极和一第五子像素电极，所述第二数据总线分别通过一第四数据线、一第五数据线、一第六数据线将一第二类数据信号传送至所述液晶显示面板的一第四子像素电极、一第二子像素电极和一第六子像素电极，其中，所述第一类数据信号和所述第二类数据信号的极性相反；所述第二数据线通过一第一组过孔结构以使所述第二数据线连接至所述第五子像素电极，所述第五数据线通过一第二组过孔结构以使所述第五数据线连接至所述第二子像素电极；其中，所述第一数据线通过一第一阻抗结构连接至所述第一子像素电极，所述第三数据线通过一第二阻抗结构连接至所述第三子像素电极，所述第四数据线通过一第三阻抗结构连接至所述第四子像素电极，所述第六数据线通过一第四阻抗结构连接至所述第六子像素电极。
  3. 根据权利要求2所述的液晶显示面板的驱动电路，其中，所述第一组过孔结构包括：在所述第二数据线上设有一第一节点，所述第一节点连接至与所述第二数据线相连的一薄膜晶体管的漏极，所述第一节点通过一穿过一栅极绝缘层的金属走线连接至与所述第五子像素电极相连的一第三节点；所述第二组过孔结构口包括：在所述第五数据线上设有一第四节点，所述第四节点连接至与所述第五数据线相连的一薄膜晶体管的漏极，所述第四节点通过一穿过所述栅极绝缘层的金属走线连接至与所述第二子像素电极相连的一第二节点。
  4. 根据权利要求2所述的液晶显示面板的驱动电路，其中，所述第一阻抗结构包括：在所述第一数据线上设有一第五节点，所述第五节点连接至与所述第一数据线相连的一薄膜晶体管的漏极，所述第五节点通过一穿过栅极绝缘层的金属走线连接至与所述第一子像素电极相连的一第六节点；所述第二阻抗结构包括：在所述第三数据线上设有一第七节点，所述第七节点连接至所述与第三数据线相连的一薄膜晶体管的漏极，所述第七节点通过一穿过栅极绝缘层的金属走线连接至与所述第三子像素电极相连的一第八节点。
  5. 根据权利要求2所述的液晶显示面板的驱动电路，其中，所述第三阻抗结构包括：在所述第四数据线上设有一第九节点，所述第九节点连接至与所述第四数据线相连的一薄膜晶体管的漏极，所述第九节点通过一穿过栅极绝缘层的金属走线连接至与所述第四子像素电极相连的一第十节点；所述第四阻抗结构包括：在所述第六数据线上设有一第十一节点，所述第十一节点连接至与所述第六数据线相连的一薄膜晶体管的漏极，所述第十一节点通过一穿过栅极绝缘层的金属走线连接至与所述第六子像素电极相连的一第十二节点。
  6. 根据权利要求2所述的液晶显示面板的驱动电路，其中，所述第一阻抗结构设置为一弓形结构，所述第二阻抗结构设置为一弓形结构。
  7. 根据权利要求2所述的液晶显示面板的驱动电路，其中，所述第三阻抗结构设置为一弓形结构，所述第四阻抗结构设置为一弓形结构。
  8. 根据权利要求2所述的液晶显示面板的驱动电路，其中，所述第一阻抗结构、所述第二阻抗结构、所述第三阻抗结构和所述第四阻抗结构为相同。
  9. 根据权利要求2所述的液晶显示面板的驱动电路，其中，所述薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管。
  10. 一种液晶显示器，其中，所述液晶显示器包括权利要求2至9中任意一项所述的驱动电路和一液晶显示面板，所述液晶显示面板包括多条数据线、多条扫描线及多个像素，所述多个像素包括多个子像素电极；所述驱动电路用于驱动所述液晶显示面板。
PCT/CN2018/104265 2018-06-21 2018-09-06 一种液晶显示面板的驱动电路及液晶显示器 WO2019242109A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810645429.4A CN108831391A (zh) 2018-06-21 2018-06-21 一种液晶显示面板的驱动电路及液晶显示器
CN201810645429.4 2018-06-21

Publications (1)

Publication Number Publication Date
WO2019242109A1 true WO2019242109A1 (zh) 2019-12-26

Family

ID=64142964

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/104265 WO2019242109A1 (zh) 2018-06-21 2018-09-06 一种液晶显示面板的驱动电路及液晶显示器

Country Status (2)

Country Link
CN (1) CN108831391A (zh)
WO (1) WO2019242109A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111477139A (zh) * 2020-04-08 2020-07-31 福建华佳彩有限公司 一种节省功耗的显示屏架构及驱动方法
CN112068374B (zh) * 2020-09-15 2022-11-29 昆山龙腾光电股份有限公司 显示面板、显示装置及驱动方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010050665A1 (en) * 2000-06-08 2001-12-13 Lg. Philips Lcd Co., Ltd Liquid crystal display and driving method thereof
CN1667684A (zh) * 2004-03-09 2005-09-14 统宝光电股份有限公司 资料驱动器及驱动方法
CN103886844A (zh) * 2013-12-31 2014-06-25 深圳市华星光电技术有限公司 显示面板组件及其调节方法、显示装置
CN104952418A (zh) * 2015-07-27 2015-09-30 武汉华星光电技术有限公司 一种显示面板驱动装置及制造方法
CN106896547A (zh) * 2017-04-01 2017-06-27 武汉华星光电技术有限公司 一种液晶显示面板的驱动电路及液晶显示器
CN107039467A (zh) * 2017-05-15 2017-08-11 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060003968A (ko) * 2004-07-05 2006-01-12 삼성전자주식회사 어레이 기판과 이를 갖는 표시 장치와, 이의 구동장치 및방법
KR20080042378A (ko) * 2006-11-09 2008-05-15 삼성전자주식회사 표시 기판 및 이의 제조 방법
CN101673003B (zh) * 2009-10-15 2012-10-17 友达光电股份有限公司 扇出线路以及显示面板
CN103149753B (zh) * 2013-03-28 2016-03-30 深圳市华星光电技术有限公司 阵列基板及其扇出线结构
KR102275693B1 (ko) * 2014-12-22 2021-07-09 엘지디스플레이 주식회사 선택회로 및 이를 구비한 표시장치
CN104810002B (zh) * 2015-05-19 2017-12-05 武汉华星光电技术有限公司 一种显示装置
CN106444199A (zh) * 2016-12-23 2017-02-22 厦门天马微电子有限公司 阵列基板、显示面板和显示装置
CN107450225B (zh) * 2017-09-22 2020-03-24 昆山龙腾光电股份有限公司 显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010050665A1 (en) * 2000-06-08 2001-12-13 Lg. Philips Lcd Co., Ltd Liquid crystal display and driving method thereof
CN1667684A (zh) * 2004-03-09 2005-09-14 统宝光电股份有限公司 资料驱动器及驱动方法
CN103886844A (zh) * 2013-12-31 2014-06-25 深圳市华星光电技术有限公司 显示面板组件及其调节方法、显示装置
CN104952418A (zh) * 2015-07-27 2015-09-30 武汉华星光电技术有限公司 一种显示面板驱动装置及制造方法
CN106896547A (zh) * 2017-04-01 2017-06-27 武汉华星光电技术有限公司 一种液晶显示面板的驱动电路及液晶显示器
CN107039467A (zh) * 2017-05-15 2017-08-11 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置

Also Published As

Publication number Publication date
CN108831391A (zh) 2018-11-16

Similar Documents

Publication Publication Date Title
TWI529695B (zh) 顯示面板及其中之信號傳送方法
US10971091B2 (en) Array substrate, display panel and driving method thereof, and display device
CN103927962B (zh) 一种显示装置的驱动电路及其驱动方法
US10699623B2 (en) Source drive IC, display device and drive method therefor
KR100556284B1 (ko) 액정표시장치
US11705043B2 (en) Display panel
EP3543988A1 (en) Data line demultiplexer, display substrate, display panel, and display apparatus
CN107942556B (zh) 阵列基板、液晶显示面板及其驱动方法
US20060250332A1 (en) Data de-multiplexer and control method thereof
US20190088185A1 (en) Driving method for display panel
US11450292B2 (en) Charge sharing circuit and method for liquid crystal display panel to improve display effect
WO2018196085A1 (zh) 数据驱动电路与显示面板
CN106896547A (zh) 一种液晶显示面板的驱动电路及液晶显示器
US9524685B2 (en) Display apparatus and method for driving the same
JP2002196726A (ja) 表示駆動装置および表示装置モジュール
US10424259B2 (en) Demultiplexer circuit, signal line circuit and corresponding output circuit and display device
WO2019242109A1 (zh) 一种液晶显示面板的驱动电路及液晶显示器
WO2019214090A1 (zh) Demux显示面板及oled显示器
CN108254986A (zh) 显示装置
US11423859B2 (en) Display control apparatus and display device
WO2020093447A1 (zh) 一种显示装置的驱动电路
CN114664227A (zh) 驱动电路及驱动方法
US20240161712A1 (en) Display panel and display device
KR100920346B1 (ko) 박막 트랜지스터 표시판 및 이를 포함하는 액정 표시 장치
TWI406257B (zh) 用於一顯示器之顯示電路及顯示器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18923460

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18923460

Country of ref document: EP

Kind code of ref document: A1