WO2019234414A1 - Système de communication série - Google Patents

Système de communication série Download PDF

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Publication number
WO2019234414A1
WO2019234414A1 PCT/GB2019/051547 GB2019051547W WO2019234414A1 WO 2019234414 A1 WO2019234414 A1 WO 2019234414A1 GB 2019051547 W GB2019051547 W GB 2019051547W WO 2019234414 A1 WO2019234414 A1 WO 2019234414A1
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Prior art keywords
binary
payload
bit
bus
sampling
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PCT/GB2019/051547
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English (en)
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Kenneth William Tindell
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Canis Automotive Labs Limited
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Publication of WO2019234414A1 publication Critical patent/WO2019234414A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/417—Bus networks with decentralised control with deterministic access, e.g. token passing

Definitions

  • the invention relates to a serial communication system and method for communicating data over a Controlled Area Network [CAN] Bus.
  • a Controller Area Network [CAN] bus is historically a robust Automotive Networking bus protocol, which is designed to allow microcontrollers and devices to communicate with each other in system applications without the need of a host computer.
  • the CAN bus is based upon a message based protocol and is relatively cheap to implement within a communication system.
  • the CAN bus operates theoretically up to 1 Mbit/sec, but in practice it is more likely to be no faster than 500Kbit/sec and carries short message payloads of 0 to 8 bytes.
  • CAN FD provides an increased bandwidth of 8Mbit/sec, which in practice is no faster than 2Mbit/sec but provides up to 64 bytes in a single message.
  • the increase in bandwidth comes from observing that the restriction on CAN bit times is due to the propagation delays in the arbitration phase. After arbitration is complete these restrictions are no longer necessary and bit times for the rest of the message can be shortened, leading to higher bandwidth.
  • CAN FD is backward compatible with the original CAN bus protocol, therefore CAN-FD can also receive regular CAN bus based messages.
  • This article explains how their method inserts new bits of data in the propagation segment of actual CAN payload bits and how these new bits are effectively invisible to existing CAN controllers. However it does not disclose how it overcomes the problem where a CAN payload has two sequential bits of logic level T, and a new bit is inserted into the second CAN payload bit: this insertion would cause a false synchronisation point for the next bit in the CAN payload leading to a breakdown of the CAN protocol. It also does not observe the opportunity to locate many more extra bits outside of the propagation segment in circumstances where the CAN protocol rules prohibit synchronisation.
  • the invention provides a serial communication system for communicating data over a Controller Area Network [CAN] Bus comprising:
  • said frame further comprises a first binary payload wherein each bit of said first payload further comprises a second binary payload;
  • said system node further comprises the means for obtaining said first and second binary payloads from received CAN data frame
  • said predetermined configuration of CAN data frame further comprises a predetermined binary bit configuration.
  • This configuration is advantageous because the system nodes which have regular CAN controllers will process the regular CAN bus payload only.
  • the regular CAN controllers connected to the system will not extract any additional payloads and will not malfunction as a result of the additional payloads being present.
  • the system to be compatible with existing CAN communication networks, without replacing the existing hardware components e.g. existing transceivers and/or controller devices.
  • the system enables larger binary payloads to be communicated within a CAN bus system.
  • payloads of 32 bytes instead of the conventional 8 byte payloads, can be carried across a CAN bus system.
  • the message with increased data payloads provide more bandwidth which can be applied to the CAN controllers that require it, therefore leaving the regular CAN controllers to operate at conventional CAN speeds.
  • the increased data payloads provide more bandwidth which can be applied to the CAN controllers that require it, therefore leaving the regular CAN controllers to operate in the normal way.
  • the improved bandwidth may be a factor of 4 or more and does not require the need for expensive multiple networks and gateway hardware.
  • said predetermined binary bit configuration is an eight byte payload.
  • the value of the binary payload is predetermined, so if an unexpected binary value is determined for a CAN frame received at a node, then this is an indication that an error or corruption has occurred with CAN frame itself.
  • said predetermined binary bit configuration is 30 00 00 00 00 00 00 00 hex.
  • the synchronisation of each bit of said first payload within said data frame initiates the communication of said second binary payload to each said bit of said first payload.
  • This configuration is advantageous because it synchronises the communication of binary information from the second binary payload, into the time interval for the intended bit of the first binary payload.
  • each said bit of the first binary payload further comprises a time period in which said second binary payload is not present and a sampling point for said CAN bus, which in use is employed by a sampling means; whereby said time period cooperates with said sampling point to determine the logic state of each said bit of first binary payload.
  • This configuration is advantageous because it enables a regular CAN bus receiver to sample each bit of the first payload [a regular CAN Frame payload], during the time period incorporated within the bit interval of the first payload.
  • a regular CAN bus receiver to determine the logic level of each bit of the first payload, independently from the second payload [an additional CAN frame payload of the invention] contained therein.
  • said secondary binary payload is not communicated to each said bit of said first payload, when said sample point is indicative of said CAN bus comprising a logic level T.
  • This configuration is advantageous because when the CAN bus receiver device determines that the sample point comprises a logic level , the CAN bus receiver device will interpret this as the time interval has now lapsed for the intended bit, within the regular CAN payload. Therefore preventing the communication of binary information from the second binary payload [an additional CAN frame payload of the invention] from being communicated outside the intended time interval of the first binary payload [a regular CAN Frame payload].
  • the communication of said secondary binary payload to each said bit of said first payload is provided when said sample point comprises a logic level ⁇ ’ and said CAN bus comprises a plurality of negative edges.
  • This configuration is advantageous because when the CAN bus receiver device determines that the sample point comprises a logic level O’, the CAN bus receiver will interpret this as the time interval for the intended bit within the regular CAN payload, is now present. Therefore enabling the communication of binary information from the second payload [an additional CAN frame payload of the invention] into the intended bit time interval of the first binary payload [a regular CAN Frame payload].
  • said time period is an adjustable time period thereby providing a means of adjusting the position of binary bits within said second payload.
  • This configuration is advantageous because it enables the width of the time period to be adjusted to counter the effect of any timing errors due to tolerances or clock drifting of any oscillators incorporated within the system, slew rates of the CAN bus transceiver devices within the system; and jitter noise in the nominal sample point due to the time quantum polling for the falling edge of the CAN frame synchronisation.
  • said time period is a static time period and thereby providing a means of fixing the position of a number of binary bits within said second payload.
  • This configuration is advantageous because it reduces the complexity of the logic design to implement the communication of the binary bits from the second payload in a trade off against the number of binary bits required for the bit interval in the first binary payload.
  • said binary bits of said second binary payload are encoded in accordance with a serial encoding protocol.
  • This configuration is advantageous because it enables the binary bits from the second binary payload [an additional CAN frame payload of the invention] to be communicated to the intended bit of the first binary payload [a regular CAN Frame payload] via an asynchronous serial communication means.
  • the encoding may conform to either the“Non-Return-to Zero”
  • This configuration is advantageous because it enables binary bits within the second binary payload [an additional CAN frame payload of the invention] to provide a known verification code/value. Thus if the expected verification code/value transmitted is not received at the receiver, the received binary bits may have then been altered during transmission and therefore contain an error.
  • said CAN data frame is retransmitted if said CAN data frame is no longer in accordance with said predefined payload.
  • This configuration is advantageous because if the CAN receiver device does not receive the expected CAN frame configuration, the received CAN frame will be deemed as erroneous and the error recovery and retransmission feature of the CAN protocol can be utilized by the sending of a CAN error flag. Thus the CAN frame will be retransmitted along the CAN bus.
  • said processing means is an integrated circuit.
  • this configuration is advantageous because it enables this integrated circuit device to be placed between a microprocessor device and a conventional CAN bus transceiver. Thus this device can be retrospectively located on an existing CAN bus circuit, without requiring the replacement of any of the existing devices.
  • this configuration employs a Field Programmable Gate Array Device [FPGA], which provides configurable logic blocks that implement the functionality to reduce up-front integrated circuit development costs.
  • a more appropriate second embodiment of this invention is within an Application Specific Integrated Circuit, [ASIC] that is integrated into a single electronic package also containing a CAN transceiver.
  • ASIC Application Specific Integrated Circuit
  • the invention provides a serial communication method for communicating data over a Controller Area Network [CAN] bus comprising the steps of:
  • This method is advantageous because it provides a CAN data frame with a predetermined configuration comprising a first binary payload and a pre-determined CAN identifier [CAN ID]
  • CAN ID a table of CAN ID ranges is implemented and the host microcontroller [with a Central Processing Unit (CPU)] is told which entry in the table has been triggered so can supply the right payload.
  • a second binary payload [an additional CAN frame payload of the invention] is communicated to the device via an external chip to chip communication means, such as Serial Peripheral Interface [SPI] bus.
  • SPI Serial Peripheral Interface
  • the second binary payload is then communicated to the relevant bit within the first binary payload of the CAN data frame, prior to it being transmitted to a system node via a CAN data bus.
  • a serial communication method for communicating data over a Controller Area Network [CAN] bus further comprising the steps of:
  • the invention provides a serial communication system for communicating data over a Controller Area Network [CAN] Bus comprising:
  • a switching means for switching to a first sampling means for sampling said received binary bit pulse when said asymmetric delay is less than a predetermined value; and switching to a second sampling means for sampling said received binary bit pulse when said asymmetric delay is greater than said predetermined value.
  • This configuration is advantageous because it enables the adequate sampling of a received binary bit pulse which comprises a asymmetric delay, i.e. clock drift. If the clock drift is excessive, the set sampling point may be missed so the second sampling means is employed to ensure the received binary bit pulse is adequately sampled. The first sampling means is employed to ensure the received binary bit pulse, with minimal asymmetric delay, is adequately sampled.
  • said first sampling means further comprises a means for providing a time delay within said received binary bit pulse, which in use determines the sampling point within said received pulse.
  • This configuration is advantageous because time delayed sample point, ensures the sampling of the received binary bit pulse when no or minimal asymmetric delays occurs.
  • said second sampling means further comprises a means for detecting a rising edge of said received binary bit pulse which is indicative of the start of bit, which in use provides a sampled binary T value for said sampled binary bit pulse.
  • a means for detecting a rising edge of said received binary bit pulse which is indicative of the start of bit, which in use provides a sampled binary T value for said sampled binary bit pulse.
  • said value of asymmetric delay is in the region of 40nanoseconds [ns] to 80ns.
  • This configuration is advantageous because it enables the adequate sampling of a received binary pulse, which comprises an asymmetric delay within this region.
  • Figure 1 shows a timing diagram of a prior art CAN signal comprising two bits.
  • Figure 2 shows a timing diagram of extra data bits [fast bits] that are injected into the CAN bit stream.
  • Figure 3 shows a timing diagram of a CAN carrier frame that has a fixed length and payload for carrying fast bits.
  • Figure 4 shows a timing diagram for timing of fast bits for a six CAN bit interval.
  • Figure 5 shows a circuit diagram of the preferred embodiment of the invention.
  • Figure 6 shows a logic analyser trace of an example communication of the preferred embodiment.
  • Figure 7 shows a more detailed view of the trace given in figure 6.
  • Figure 1 shows a timing diagram of an example CAN signal consisting of two bits (1).
  • the level indicated by (4) is the recessive state of the bus (a logic 1 level) and that indicated by (5) is the dominant state of the bus (a logic 0 level).
  • (2) Indicates the time quanta that drive the CAN protocol state machine (illustrated is a system configured to have 8 time quanta per bit).
  • (3) is the time quantum that is configured to be the sample point - where the logic level is sampled and the value of the CAN bit determined.
  • the timing diagram therefore shows a CAN bit of 0 followed by a CAN bit of 1.
  • the falling edge (6) is where a CAN soft synchronisation point takes place: if the falling edge occurs earlier or later than expected then the sample point is adjusted relative to this edge.
  • Figure 2 gives an example of how fast bits are injected to modify the CAN bitstream without disrupting a standard CAN receiver.
  • the fast bits (7) overwrite the CAN levels but none are injected around the sample points so that the logic levels of the samples (8) and (9) taken by a CAN receiver matches the same as for the unmodified CAN bit stream (3) in figure 1.
  • the soft sync in the modified CAN bitstream (6) takes place in the same place as the unmodified CAN bitstream (figure 1). No additional soft sync takes place because of the rules of the CAN protocol. This is an important property: if a falling edge of a fast bit caused another soft sync in a CAN receiver then the sample point would be modified and likely result in the wrong logic level being sampled and therefore an error.
  • the CAN protocol defines that there can be at most only one soft sync per CAN bit. This means that the falling edge of any fast bit (10) between the start of the bit and the sample point (8) cannot cause a soft sync.
  • the CAN protocol defines that there cannot be a soft sync if the previously sampled logic level was 0. This means that the falling edges of any fast bit (11) after a sample point sampling a logic level 0 (8) cannot cause a soft sync.
  • No fast bits can be injected (12) after a sample point sampling a logic level 1 (9) and before a falling edge in the unmodified CAN bitstream because these would induce additional soft sync points in the wrong places.
  • the fast bits are in the parts of a CAN bit where the CAN controller’s bit sample point will not see them. Exploiting the sample point and sync rules means fast bits are invisible to a regular CAN controller; The CAN controller will receive a CAN frame as normal and not malfunction. According to the sync rules of the CAN protocol, the extra edges of fast bits won’t cause a spurious sync if they are injected in the right place, such as:
  • Figure 3 shows part of an example CAN carrier frame that has a fixed length and payload that is designed to carry fast bits.
  • the frame has a payload of 8 bytes (and so the CAN frame Data Length Code [DLC] field (13) is in binary 1000), a payload (14) with the first byte in binary of 001 10000 and the remaining payload bytes with a binary value of 00000000.
  • the CAN protocol adds a number of extra stuff bits (15).
  • the payload ends with the beginning of the CAN frame Cyclic Redundancy Check [CRC] field (16). This particular pattern produces the maximum space for fast bit injection: thirteen intervals of six CAN bits (five logic ⁇ ’ CAN bit times and one logic T level due to a stuff bit).
  • the CAN carrier frame has a predetermined payload of 30 00 00 00 00 00 00 00 00 hex.
  • Figure 4 shows an example of the timing of fast bits (26) for a six CAN bit interval.
  • the CAN protocol defines a bit timing model and each controller is configured by setting parameters according to the results of calculations on the timing limits due to electrical and timing properties of the physical bus and clock accuracies of each device.
  • the placement of fast bits takes a similar approach and figure 4 illustrates these timing parameters.
  • the unmodified CAN bitstream (17) is shown for reference above the modified CAN bitstream (18).
  • the falling edge at the start of the interval (6) causes a soft sync and all the CAN receivers adjust their sample points.
  • the modified CAN bit stream includes keep-out windows where no fast bits are inserted (i.e. the logic level of the modified bitstream must be the same as the logic level of the unmodified bitstream).
  • the first window (19) is long enough to ensure that each CAN receiver sees a falling edge and triggers a soft sync (6).
  • the remaining windows (20, 21 , 22, 23, 24, 25) are set to ensure that all CAN receivers sample the same logic level as the unmodified CAN bitstream.
  • the calculation of the placement and width of the windows depends on the specific properties of the CAN bus (including the tolerances of the oscillators at the transmitter and each receiver, the difference in propagation delays for dominant-to-recessive and recessive-to- dominant for specific CAN transceiver devices selected, different relative sample points in different controllers, and jitter in the nominal sample point due to time quantum polling for the falling edge (6) of the soft sync).
  • sample point windows (20, 21 , 22, 23, 24, 25) are sized differently for each CAN bit within the interval to exploit differences in the worst-case clock drift between transmitter and receivers (the clock drift for each successive sample is larger due to the longer time elapsed since the soft sync (6) when the CAN clocks were synchronised).
  • all windows may be set to the same size to reduce the number of logic gates required to implement fast bits in a trade-off against the number of fast bits per interval.
  • the fast bits (26) can be encoded using any scheme such as NRZ or Manchester Code that are appropriate for a serial bus.
  • the bits are sent with NRZ encoding with start and stop bits (i.e.
  • the soft sync (6) at the beginning of an interval acts as the start bit and the fast bits (27) before the next five windows (20, 21 , 22, 23, 24) are always at logic 1 and act as stop bits.
  • some of the fast bits are used as an error checking code such as a CRC such that each receiver of fast bits checks that the fast bits have been received without having been altered by a disturbance to the bus and where an error is detected a standard CAN error frame is transmitted to trigger the retransmission of the container frame according to the CAN protocol.
  • an error frame is also sent if the container frame fails to match its predefined pattern in order to resolve a known weakness in the CAN CRC scheme; reference [Tran, Eushiuan & Koopman, Philip. (1999). Multi-Bit Error Vulnerabilities in the Controller Area Network Protocol, Research report series, Carnegie Mellon University, Institute for Complex Engineered Systems]
  • a CAN sample point window is a fast bit‘keep-out’ window in which any given receiver could take its CAN sample.
  • the precise sample point at each device may differ due to implementation differences.
  • a network specification therefore usually gives a range (e.g.“sample point must be between 75- 80 %").
  • the relative accuracies of the clock in each device implies the keep-out window duration will grow over time:
  • the first window is of the shortest duration because it is nearest in time to the CAN sync point at the start of the interval of 6 bits; each receiver’s clock will drift relative to the transmitter so the duration of the window in which receivers will take a sample increases as the interval proceeds.
  • the size of the sample point window is also affected by CAN protocol time quantum polling: CAN soft sync operates by polling for a falling edge and this polling introduces a jitter in the sample point that can pull the sample point forwards by up to 1 time quantum at a receiver.
  • the size of the last sample point window is additionally affected by the CAN transceivers: Regular CAN transceivers take approximately 65ns longer to switch from 0 to 1 than the other way, so the last fast bit needs to finish early enough to allow for this.
  • stop and start bits to provide clock synchronisation points in a similar way to asynchronous serial line transmission.
  • the falling edge at the start of the interval begins a start bit and the duration of this bit is long enough to exceed the longest time quantum of any CAN receiver to ensure all CAN receivers sampling for a falling edge are sure to see one.
  • a stop bit is the last fast bit before each keep-out window and the falling edge provides a clock synchronisation point.
  • FIG. 5 shows a typical embodiment of the invention.
  • a conventional microcontroller host device (41) containing an inter-IC communications controller (42) such as SPI and a standard CAN controller (28) are connected by an inter-IC bus (38) and standard CAN signals (29, 30) to an integrated circuit (31) that embodies the invention [i.e. a fast bits controller].
  • the standard CAN signals CANTX (29) that transmits an unmodified CAN bitstream and CANRX (30) that receives a signal from the CAN bus are connected to the fast bits controller (31) and the fast bits controller is in turn connected to a standard CAN transceiver (32) with a CANTX signal containing a modified CAN bitstream with fast bits (33) and CANRX receiving both modified and unmodified CAN signals from devices on the network (34).
  • the transceiver connects to the CAN bus (35) using CANH and CANL signals (36, 37) in the normal way.
  • the fast bits controller (31) contains a state machine (39) for receiving CAN frames from the host device (41 ) and the CAN bus (34) according to the standard CAN protocol and uses this to determine if the CAN frame is a container frame and whether it is being transmitted or received (in a typical embodiment this is by using the CAN ID as an index into a predefined table of container frames).
  • a state machine for receiving CAN frames from the host device (41 ) and the CAN bus (34) according to the standard CAN protocol and uses this to determine if the CAN frame is a container frame and whether it is being transmitted or received (in a typical embodiment this is by using the CAN ID as an index into a predefined table of container frames).
  • To send an enhanced frame the host device (41 ) puts a container frame in the CAN controller (28).
  • the fast bits controller (31) receives the part of the CAN frame containing the identifier and control fields and determines that the container frame is being transmitted. It then uses the inter-IC interface to request the host to provide the
  • the fast bits controller transmits this payload as fast bits injected into the remaining part of the container frame according to the method described in figure 4.
  • the fast bits controller (31) receives the part of the CAN frame containing the identifier and control fields and determines that the container frame is being received. It then extracts the fast bits in the container frame according to the method described in figure 4 and then uses the inter-IC interface to request the host to take the corresponding application payload over the inter-IC bus.
  • the CAN bus payload may be increased from a typical 32 bytes.
  • the size of CAN payload is determined by bit timing parameters that are chosen for the system.
  • Figure 4 describes the model: for each of the six CAN bits in an interval, there is a keep-away zone, each zone grows in size/width to compensate/allow for clock drift). Extra binary bits are inserted into the spare area around each zone, with the number and the width of these extra bits varying.
  • the timing parameters are therefore an implicit specification of how many bits can be placed around each window 20, 21 , 22,23,24,25, and with what safety margins.
  • FIG. 6 shows a logic analyser trace of a specific instance of a CAN carrier frame modified by an embodiment of the invention.
  • the signals included in the logic analyser trace are the SPI master clock [SCK] at the transmitting host (50), the CANTX signal at the transmitting host (51), the resulting signal on the CAN bus after the fast bits have been injected (52), an internal signal from inside the integrated circuit embodying the invention at the receiver showing when the CAN state machine sampled the CAN bit (53), an internal signal showing the logic values that the receiving state machine sampled from the CAN bus (54), and the SPI master clock of the receiving host (55).
  • SCK SPI master clock
  • the trace depicts the transmission of the carrier CAN frame and shows the Start Of Frame [SOF] falling edge (43), the most significant bit of the DLC field (44), the first bit of the CRC field (45), and the start of the End Of Frame [EOF] field (46).
  • the transmitter SCK signal shows the transfer of payload bytes to the integrated circuit embodying the invention and the CAN bus signal (52) shows the result of the injection of fast bits into the carrier frame.
  • the sampled logic level signal (54) shows what a receiver CAN controller sees [i.e. only the logic level of the original CAN frame (51)] and therefore is not disturbed by the fast bits injected into the carrier frame (52).
  • the receiving host device is requested to upload the payload over SPI.
  • the receiver SCK signal (55) shows this transfer taking place (49). There is unused space in the carrier CAN frame between the last fast bit (48) and the beginning of the CAN CRC field (45) that could be used to contain more fast bits.
  • Figure 7 expands upon the logic analyser trace of figure 6 with the same signals included (58, 59, 60, 61 , 62, 63) and shows a six CAN bit interval containing fast bits.
  • the interval begins with a falling edge (56) on the CAN bus (60) that is offset in time from the falling edge of transmitter CAN controller CANTX signal (59) due to the propagation delay through the CAN bus.
  • the figure also shows the fast bits that are used as stop bits (57) to synchronise the receiver clock with the transmitter clock.
  • the CAN sample point signal (61) and CAN sampled value signal (62) shows how a receiver CAN controller sees only logic values corresponding to the original CAN signal. For example, the sample before the six CAN bit interval starts (64) samples a logic ‘r value (65).
  • the CAN protocol requires that a CAN controller go through bus integration when it comes online (either from power-on reset or when recovering from a bus-off error state). This involves polling for 11 recessive bits in a row, which should only happen if the bus is idle or at the end of frame. This is done so that the controller can synchronise with the state of the bus and not try and jump in part way through an on-going message transmission.
  • a dominant CAN bit might not be read as a dominant bit by a controller that is in a bus integration state: because it is not synchronised with the CAN frame it might read at any point in a CAN bit, and this could return any arbitrary value due the fast bits containing arbitrary payload values.
  • the initial skip from the falling edge at the start of a carrier frame interval can be extended to the end of the first sample point window. This ensures that the falling edge triggers a hard sync in the CAN controller (according to the bus integration rules) and then the sample point is guaranteed to read a dominant bit. This resets the 11 recessive bits counter. It is not possible for the counter to reach 11 during a carrier frame because the intervals are 6 bits long and the first bit of each interval will always reset the counter.
  • a barrier to high speed performance is the problem of reflections due to mismatched impedance on the bus causing glitches due to bus wiring choices taken to reduce cost.
  • the problem is caused by reflections off unterminated ends of the bus and side stubs where these reflections come through the CAN transceiver as glitches that can appear anywhere in a bit: at high speeds, the duration of a bit is much shorter than the time taken for a signal to propagate up the bus, reflect off an end, and come back down. This is a major problem for CAN FD operating at higher speeds (see Schreiner et a l: https://www.can- cia.org/fileadmin/resources/documents/proceedings/2015_schreiner.pdf).
  • Figure 8 shows another problem specific to CAN is bit asymmetry due to the electrical characteristics of standard CAN transceivers.
  • the propagation time of a transceiver is different for transitions from 0-to-1 (dominant to recessive) 70 and 1-to-0 (recessive to dominant) 71 and the effect of this is to shorten a recessive bit 72.
  • the bit shortening is a fixed time, depending on the characteristics of the transceivers at the transmitter and the receiver. A figure of 60ns is typical. This would mean that a 200ns bit (i.e. 5Mbit/sec bit rate) would have a sampling window 73 of 140s but a 100ns bit - or 10Mbit/sec - would have a sample window of just 40ns, making it very difficult (or impossible) to set a sample point that can reliably determine the bit value.
  • Figure 9 shows a sampling system generally indicated by arrow 80, in which a low pass filter 83 is used to de-glitch the signal 81, which is connected via a CAN transceiver 82, and feeds an edge detector 84.
  • the low pass filter 84 is a simple moving average that can be easily implemented in hardware with a shift register, an up/down counter, and a comparator.
  • the falling edge signal 85 is used to detect the falling edge of a stop bit and uses this to synchronise the receivers bit sampling clock 86.
  • the rising and falling edge detection has a constant delay from the filter signal so that the timing of these signals can be used to measure a pulse width.
  • the filter 83 will change the length of the waveform because reflected glitches will contribute towards the filtered output. But the pulse distortion from glitches due to reflections will generally be consistent for a given placement of the sender and receiver on the bus.
  • the rising edge signal 87 is used to detect a shortened recessive bit 88 as follows:
  • the bit is also sampled at a fixed time offset during the bit.
  • Figure 10 shows a binary bit pattern for 0 1 0, in which the rising edge 91 is latched and the latch is inspected at the end of the bit/start bit 93: the middle bit is shortened from a hypothetical end bit/ start bit rising edge, to the actual rising edge 91 and is sampled 92 and is deemed a binary 1.
  • Figure 1 1 shows a binary bit pattern for 1 1 0, in which there is no rising edge latched means, therefore the bit is sampled 92 as a 1.
  • Figure 12 shows that when the sending transceiver and the receiving transceiver have very little asymmetry, the rising edge 91 may then always come early in the bit:
  • the rising edge method for determining a bit value is less tolerant to clock drift than simply sampling the bit at an offset: if the clock at the receiver drifts and the end/beginning of the bit time moves to after the rising edge then the edge will not be latched and the bit will be misread. This is shown in Figure 13:
  • Figure 14 shows the bit sampling method (fixed offset vs. rising edge latching) most tolerant to clock drift is determined by the asymmetry 98: when the asymmetry is more than 1/3 rd of a nominal bit time then the rising edge method is best. Sampling point 92, falling edge end of bit / start of new bit 93, rising edge 91 and hypothetical end of bit / start of new bit 90.
  • the best method to use will be a function of the transmitter and the receiver: a different transmitter or receiver will have different bit asymmetry due to the transceiver hardware at either end and the specific effect of the topology on the filtered waveform due to reflections.
  • the parameters for the bit sampling are looked up in a calibration table at each receiver using the CAN ID of the frame (the same table of claim 2 above can be used).
  • the enhanced payload is defined to include a calibration pulse of the nominal bit time (NBT) at the start.
  • the sample point is set to the end of the bit less half the pulse width (i.e. NBT - W/2).
  • W + W/2 i.e. pulse width x 1.5
  • the rising edge method is used (i.e. rising edge if W + W/2 ⁇ NBT).
  • step 4 can be implemented with a right shift, an adder and a comparator.
  • Measuring the pulse width W in step 2 can be done by simply counting clock cycles between rising and falling edge events.

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Abstract

L'invention concerne un système de communication série pour communiquer des données sur un bus de réseau de zone de controleur [CAN] (Controller Area Network) comprenant : un moyen de traitement pour fournir une trame de données CAN qui comprend une configuration prédéterminée; un moyen pour communiquer ladite charge utile prédéterminée à un nœud de système par l'intermédiaire d'un bus CAN; ladite trame comprenant en outre une première charge utile binaire; et caractérisé en ce que chaque bit de ladite première charge utile comprend en outre une seconde charge utile binaire; ledit nœud système comprend en outre les moyens d'obtention desdites première et seconde charges utiles binaires à partir de la trame de données CAN reçue.
PCT/GB2019/051547 2018-06-06 2019-06-04 Système de communication série WO2019234414A1 (fr)

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GBGB1809308.8A GB201809308D0 (en) 2018-06-06 2018-06-06 A serial communication system

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EP4336785A1 (fr) * 2022-09-08 2024-03-13 The Consortium Team SA Réseau de communication asynchrone série, module d'interface de réseau et procédés pour transmettre et recevoir des messages sur le réseau

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EP3855683A1 (fr) * 2020-01-21 2021-07-28 Nxp B.V. Contrôleur de réseau de zone de commande et émetteur-récepteur
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