WO2019227785A1 - 显示器驱动系统 - Google Patents

显示器驱动系统 Download PDF

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Publication number
WO2019227785A1
WO2019227785A1 PCT/CN2018/106609 CN2018106609W WO2019227785A1 WO 2019227785 A1 WO2019227785 A1 WO 2019227785A1 CN 2018106609 W CN2018106609 W CN 2018106609W WO 2019227785 A1 WO2019227785 A1 WO 2019227785A1
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Prior art keywords
frame
chip
display data
display
picture
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Ceased
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PCT/CN2018/106609
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English (en)
French (fr)
Inventor
郑燕旋
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US16/308,481 priority Critical patent/US11049478B2/en
Publication of WO2019227785A1 publication Critical patent/WO2019227785A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present invention relates to the field of display technology, and in particular, to a display driving system.
  • liquid crystal display devices LCD
  • CRT cathode Ray Tube
  • the liquid crystal display device has many advantages such as a thin body, power saving, and no radiation, and has been widely used.
  • a liquid crystal display panel includes a color filter (CF) substrate, a thin film transistor (TFT) array substrate, a liquid crystal (LC) and a sealant sandwiched between the color film substrate and the thin film transistor array substrate.
  • Frame (Sealant) composition The working principle of a liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many small vertical and horizontal wires in the middle of the two glass substrates. The liquid crystal molecules are controlled to change direction by turning on or off, and the light of the backlight module is changed. Refracted to produce a picture.
  • display data needs to be processed by a field programmable logic gate array (FPGA) chip for related image processing and then output to the display to drive the display.
  • FPGA field programmable logic gate array
  • the usual method is to use an FPGA chip to buffer several frames of display data in memory. Then, the FPGA chip reads the data buffered in the memory and converts it to output.
  • High resolution and high refresh rate require higher memory bandwidth and higher speed and more channels of high-speed transmission interfaces.
  • the storage bandwidth and number of transmission interfaces of an FPGA chip are limited, which results in only setting One FPGA chip cannot meet the design of high resolution and high refresh rate. Therefore, two or more FPGA chips need to be set.
  • a frame is divided into multiple regions, and multiple regions correspond to multiple FPGA chips.
  • Multiple memories are provided for multiple FPGA chips, and each FPGA chip stores the display data of the corresponding area of the multi-frame display screen in the corresponding memory for multiple frames, and then reads the data in the corresponding memory and converts it to output.
  • This design can adapt to high-resolution and high-refresh design, but it does not guarantee that the data output by multiple FPGAs belong to the same frame, resulting in abnormal display of the screen.
  • An object of the present invention is to provide a display driving system capable of converting display data by using a plurality of chips to eliminate abnormal screen display caused by a plurality of chips being out of synchronization.
  • the present invention provides a display driving system including M chips, M memories, an input terminal, and a display, where M is a positive integer greater than 2;
  • the input terminal is electrically connected to M chips; the display is electrically connected to M chips; each memory is correspondingly electrically connected to a chip; each memory includes N storage units arranged in sequence, Where N is a positive integer greater than 1; one of the M chips is defined as a master chip, and the rest are defined as slave chips, and each slave chip is electrically connected to the master chip;
  • the input terminal receives display data of multiple frames, each frame includes M regions, and each region corresponds to a chip; the input terminal transmits the display data of corresponding regions of the multiple frames to M chips;
  • the chip sequentially and sequentially caches the display data of the corresponding area of the multi-frame picture to the N storage units of the memory connected to the chip, and sequentially reads the display data of the corresponding area of the multi-frame picture stored in the N storage units in sequence. And transfer to the display after conversion;
  • the main chip caches the display data of the corresponding area of one frame of the picture by using the memory connected to the main chip, it marks the serial number of the storage unit that caches the display data of the corresponding area of the frame of the picture in N storage units.
  • the serial numbers of the read storage units in the N storage units are generated, and a corresponding synchronization signal is generated and transmitted to each slave chip to control the frame of the frame.
  • the display data of the M areas are synchronously buffered to the same number of storage units in the M memories, and the master chip and the slave chip are synchronized to read the display of the corresponding area of a frame of the picture stored in the same number of storage units in the respective connected memories. data.
  • Each frame includes M regions arranged in order along the horizontal direction.
  • Each frame includes M regions arranged in sequence along the vertical direction.
  • the M areas have the same area.
  • the M chips are all FPGA chips.
  • the input terminal receives the display frame input signal of the multi-frame picture while receiving the input frame start signal of the multi-frame picture.
  • the input terminal also transmits the display data of the corresponding area of the multi-frame picture to the main chip and simultaneously The input frame start signal is transmitted to the main chip;
  • the main chip processes an input frame start signal of a multi-frame picture to generate an output frame start signal of a corresponding multi-frame picture;
  • the main chip When the main chip caches the display data of the corresponding area of one frame of the picture by using the memory connected to the main chip, it marks the serial number of the storage unit that caches the display data of the corresponding area of the frame of the picture in N storage units.
  • the serial numbers of the read storage units in the N storage units are marked, and the specific process of generating corresponding synchronization signals is as follows: At the rising edge of the start signal, the master chip uses the memory connected to the master chip to cache the display data of the corresponding area of the frame of the frame, and at the same time, the master chip transmits to the slave chips a high-precedence sequence with a first preset duration.
  • Level pulses A high-level pulses with a second preset duration and a low-level pulse with a third preset duration, where A is equal to N storage units that buffer display data of the corresponding area of the frame
  • the storage unit storing the display data of the corresponding area of the other frame is read, and at the same time, the master chip transmits to each slave chip a high-level pulse with a fourth preset duration and B Two high-level pulses of a predetermined duration and one low-level pulse of a third predetermined duration, where B is equal to the sequence number of the storage unit that buffers display data of the corresponding area of the other frame picture among the N storage units.
  • the master chip also transmits a pulsed clock signal to each slave chip
  • a period of the pulse signal with the first preset duration equal to 3 times
  • the second preset duration is equal to a period of a pulse signal
  • the fourth preset duration is equal to 5 times the period of the pulse signal.
  • the display driving system of the present invention sets a master chip and a plurality of slave chips, and causes the master chip to cache the display area corresponding to a frame when using the memory connected to the display chip to cache the display data of the frame corresponding to the frame.
  • the serial number of the storage unit that displays the data is not limited to a master chip and a plurality of slave chips.
  • a slave chip controls the display data of a frame of picture to be synchronously cached to a plurality of memory cells with the same serial number, and controls the master chip and the slave chip to synchronously read a frame stored in the memory cell with the same serial number in the respective connected memories.
  • the display data of the corresponding area of the screen is conducive to the design of high resolution and high refresh rate, and can eliminate the abnormal display of the screen caused by the asynchronous of multiple chips.
  • FIG. 1 is a schematic structural diagram of a display driving system of the present invention
  • FIG. 2 is a schematic structural diagram of a memory of a display driving system according to the present invention.
  • FIG. 3 is a waveform diagram of a synchronization signal and a clock signal of the display driving system of the present invention.
  • the present invention provides a display driving system including M chips 1, M memories 2, input terminals 3, and a display 4, where M is a positive integer greater than 2.
  • the input terminal 3 is electrically connected to the M chips 1.
  • the display 4 is electrically connected to the M chips 1.
  • Each memory 2 is correspondingly electrically connected to a chip 1; each memory 2 includes N storage units 21 arranged in sequence, where N is a positive integer greater than 1.
  • One of the M chips 1 is defined as a master chip 11, and the rest are defined as slave chips 12, and each slave chip 12 is electrically connected to the master chip 11.
  • the input terminal 3 receives display data of a plurality of frames, and each frame includes M regions, and each region corresponds to a chip 1.
  • the input terminal 3 transmits the display data of the corresponding area of the multi-frame picture to the M chips 1 respectively.
  • the chip 1 sequentially caches the display data of the corresponding area of the multi-frame picture to the N storage units 21 of the memory 2 connected to it sequentially, and performs the display data of the corresponding area of the multi-frame picture stored in the N storage units 21. Sequentially read and converted to the display 4 after conversion.
  • the serial number of the storage unit 21 that caches the display data of the corresponding area of the frame of the picture is marked in the N storage units 21.
  • the serial number of the storage unit 21 in the N storage units 21 marked when the display data of a frame corresponding to a frame stored in a storage unit 21 in the memory 2 is read is generated, and a corresponding synchronization signal is transmitted to each slave.
  • the display data of the M areas of a frame are synchronously buffered to the storage units 21 with the same serial number in the M memories 2, and the master chip 11 and the slave chip 12 are synchronously read the serial numbers in the respective connected memories 2. Display data of a frame corresponding to a frame stored in the same storage unit 21.
  • each frame of the picture may include M regions that are sequentially arranged in a horizontal direction or a vertical direction.
  • the areas of the M regions are the same.
  • M 2 that is, in the embodiment shown in FIG. 1, the display driving system includes two chips, one of which is defined as the main chip 11 and the other is defined as The slave chip 12, correspondingly, each frame of the picture includes two regions, which correspond to the master chip 11 and the slave chip 12, respectively.
  • the M chips 1 are all FPGA chips.
  • the input terminal 3 receives the display frame input signal of the multi-frame picture while receiving the display data of the multi-frame picture, and the input terminal 3 transmits the display data of the corresponding area of the multi-frame picture to the main chip 11 at the same time
  • the input frame start signal of the multi-frame picture is also transmitted to the main chip 11.
  • the main chip 11 processes an input frame start signal of a multi-frame picture through its internal algorithm to generate an output frame start signal of a corresponding multi-frame picture.
  • the main chip 11 uses the memory 2 connected to the main chip 11 to cache the display data of a frame corresponding area of the frame
  • the storage of the display data corresponding to the frame corresponding area of the frame is marked.
  • the number of the unit 21 in the N storage units 21 is used to mark the storage unit 21 that is read when the display data of a frame corresponding to a frame of the picture stored in the storage unit 21 in the memory 2 is read in the N storage units.
  • the serial number in 21, the specific process of generating the corresponding synchronization signal is: at the rising edge of the input frame start signal of a frame, the main chip 11 uses the memory 2 connected to it to cache the display of the corresponding area of the frame.
  • A is equal to the serial numbers of the storage units 21 that cache the display data of the corresponding area of the one-frame picture among the N storage units 21.
  • the one high-level pulse with a first preset duration indicates that the rising edge of the input frame start signal of the frame is coming, and the A high-level pulse with a second preset duration indicates that the corresponding one frame is buffered.
  • the serial number of the storage unit 21 of the display data in the area is N among the N storage units 21. For example, as shown in FIG.
  • the storage unit 21 of the display data of the corresponding area of the frame of the frame is stored in the N storage units 21 at this time.
  • the serial number in is 3.
  • the one low level with the third preset duration indicates the end of the transmission. Then, the rising edge of the output start signal of another frame of picture arrives.
  • the main chip 11 reads the storage unit 21 connected to the memory 2 and stores the display data of the corresponding area of the frame of the other picture.
  • the master chip 11 transmits to the slave chip 12 a high-level pulse having a fourth preset duration, B high-level pulses having a second preset duration, and a low-level pulse having a third preset duration.
  • B is equal to the number of the storage units 21 in the N storage units 21 that cache the display data of the corresponding area of the other frame picture.
  • the one high-level pulse with a fourth preset duration indicates that the rising edge of the output frame start signal of the other frame picture is coming, and the B high-level pulses with a second preset duration indicate that the other frame is buffered
  • the storage unit 21 of the display data corresponding area of the screen among the N storage units 21 is B.
  • the storage unit 21 of the display data of the corresponding area of the other frame of the screen is stored in N
  • the serial number in the storage unit 21 is 1, and the low level with the third preset duration indicates the end of the transmission.
  • the master chip 11 further transmits a pulsed clock signal to each slave chip 12.
  • the first preset duration is equal to 3 times the period of the pulse signal
  • the second preset duration is equal to the period of the pulse signal
  • the third preset duration is equal to or greater than the period of the pulse signal
  • the fourth preset duration is equal to a period of a pulse signal of 5 times.
  • one master chip 11 and multiple slave chips 12 are provided, and the master chip 11 uses the memory 2 connected to the master chip 11 to cache the display data of a frame corresponding area of the frame.
  • the serial number of the storage unit 21 of the display data in the corresponding area of the frame screen when reading the display data of the corresponding area of the frame in the storage unit 21 in the memory 2, the serial number of the storage unit 21 marked as read, Generate a corresponding synchronization signal and transfer it to each slave chip 12 to control the display data of a frame of the picture to be synchronized to multiple storage units 21 in the same serial number in the memory 2 and control the master chip 11 and the slave chip 12 to read and connect to each other synchronously.
  • the display data of the corresponding area of one frame of the picture stored in the storage unit 21 with the same serial number in the memory 2 can realize the synchronous driving of multiple chips 1, which is conducive to the design of high resolution and high refresh rate, and can eliminate multiple chips.
  • the screen display is abnormal due to non-synchronization, and the design is simple. Only one synchronization signal needs to be set.
  • the display driving system of the present invention sets a master chip and a plurality of slave chips, and causes the master chip to cache the display area corresponding to a frame when using the memory connected to the display chip to cache the display data of the corresponding frame.
  • the serial number of the storage unit that displays the data is not limited to a master chip and a plurality of slave chips.
  • a slave chip controls the display data of a frame of picture to be synchronously cached to a plurality of memory cells with the same serial number, and controls the master chip and the slave chip to synchronously read a frame stored in the memory cell with the same serial number in the respective connected memories.
  • the display data of the corresponding area of the screen is conducive to the design of high resolution and high refresh rate, and can eliminate the abnormal display of the screen caused by the asynchronous of multiple chips.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示器驱动系统，通过设置一个主芯片（11）及多个从芯片（12），并使主芯片（11）在利用与其连接的存储器（2）缓存一帧画面对应区域的显示数据时标记缓存该一帧画面对应区域的显示数据的存储单元（21）的序号，在对与存储器（2）中的一存储单元（21）中存储的一帧画面对应区域的显示数据进行读取时标记读取的存储单元（21）的序号，产生对应的同步信号传输至每一从芯片（12）中，控制一帧画面的显示数据同步缓存至多个存储器（2）中序号相同的存储单元（21）中，并控制主芯片（11）及从芯片（12）同步读取各自相连的存储器（2）中序号相同的存储单元（21）中存储的一帧画面对应区域的显示数据，有利于实现高分辨率高刷新率的设计，且能够消除多个芯片（1）不同步导致的画面显示异常。

Description

显示器驱动系统 技术领域
本发明涉及显示技术领域，尤其涉及一种显示器驱动系统。
背景技术
在显示技术领域，液晶显示装置(Liquid Crystal Display，LCD)等平板显示装置已经逐步取代阴极射线管(Cathode Ray Tube，CRT)显示装置。液晶显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括液晶显示面板及背光模组(backlight module)。通常液晶显示面板由彩膜(Color Filter，CF)基板、薄膜晶体管(Thin Film Transistor，TFT)阵列基板、夹于彩膜基板与薄膜晶体管阵列基板之间的液晶(Liquid Crystal，LC)及密封胶框(Sealant)组成。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
现有技术中，显示数据需要经过现场可编程逻辑门阵列(FPGA)芯片进行相关的图像处理后再输出至显示器中对显示器进行驱动，通常的做法是利用FPGA芯片将几帧显示数据缓存在存储器内，而后FPGA芯片对存储器内缓存的数据进行读取并转换后输出。随着视频显示技术的不断更新，高分辨率高刷新率的设计越来越普遍。高分辨率高刷新率要求更高的存储带宽和更高速率更多通道的高速传输接口，而在实际设计中，一个FPGA芯片的存储带宽及传输接口的数量是有限的，这就导致仅设置一个FPGA芯片无法满足高分辨率高刷新率设计，因此需要设置两个或更多的FPGA芯片，通常做法会将一帧画面分割为多个区域，多个区域分别与多个FPGA芯片对应，且对应多个FPGA芯片设置多个存储器，每一FPGA芯片均将多帧显示画面对应区域的显示数据在对应的存储器中存储多帧，而后读取对应存储器中的数据并转换后输出。这种设计能够适应高分辨率高刷新率的设计，但并不能保证多个FPGA各自输出的数据均属于同一帧画面，从而导致画面的显示异常。
发明内容
本发明的目的在于提供一种显示器驱动系统，能够利用多个芯片对显示数据进行转换，消除多个芯片不同步导致的画面显示异常。
为实现上述目的，本发明提供一种显示器驱动系统，包括M个芯片、M个存储器、输入端及显示器，其中，M为大于2的正整数；
所述输入端与M个芯片均电性连接；所述显示器与M个芯片均电性连接；每一存储器对应与一芯片电性连接；每一存储器均包括依序设置的N个存储单元，其中N为大于1的正整数；所述M个芯片中的一个定义为主芯片，其余定义为从芯片，每一从芯片均与所述主芯片电性连接；
所述输入端接收多帧画面的显示数据，每一帧画面均包括M个区域，每一区域与一芯片对应；所述输入端向M个芯片分别传输多帧画面对应区域的显示数据；所述芯片将多帧画面对应区域的显示数据依序循环缓存至与其连接的存储器的N个存储单元中，并对N个存储单元中存储的多帧画面对应区域的显示数据进行依序循环读取并进行转换后传输至显示器；
所述主芯片在利用与其连接的存储器缓存一帧画面对应区域的显示数据时标记缓存该一帧画面对应区域的显示数据的存储单元在N个存储单元中的序号，在对与存储器中的一存储单元中存储的一帧画面对应区域的显示数据进行读取时标记读取的存储单元在N个存储单元中的序号，产生对应的同步信号传输至每一从芯片中，控制一帧画面的M个区域的显示数据同步缓存至M个存储器中序号相同的存储单元中，并控制主芯片及从芯片同步读取各自相连的存储器中序号相同的存储单元中存储的一帧画面对应区域的显示数据。
M＝2。
每一帧画面均包括沿水平方向依次排列的M个区域。
每一帧画面均包括沿竖直方向依次排列的M个区域。
所述M个区域的面积相同。
所述M个芯片均为FPGA芯片。
N＝4。
所述输入端接收多帧画面的显示数据的同时还接收多帧画面的输入帧起始信号，所述输入端将多帧画面对应区域的显示数据传输至主芯片的同时还将多帧画面的输入帧起始信号传输至主芯片；
所述主芯片对多帧画面的输入帧起始信号进行处理，产生对应的多帧画面的输出帧起始信号；
所述主芯片在利用与其连接的存储器缓存一帧画面对应区域的显示数 据时标记缓存该一帧画面对应区域的显示数据的存储单元在N个存储单元中的序号，在对与存储器中的一存储单元中存储的一帧画面对应区域的显示数据进行读取时标记读取的存储单元在N个存储单元中的序号，产生对应的同步信号的具体过程为：在一帧画面的输入帧起始信号的上升沿时刻，所述主芯片利用与其连接的存储器缓存该一帧画面对应区域的显示数据，同时所述主芯片向每一从芯片传输依次产生的一个具有第一预设时长的高电平脉冲、A个具有第二预设时长的高电平脉冲及一个具有第三预设时长的低电平，其中，A等于缓存该一帧画面对应区域的显示数据的存储单元在N个存储单元中的序号，而后另一帧画面的输出起始信号的上升沿时刻到来，所述主芯片对与其连接的存储器中存储有该另一帧画面对应区域的显示数据的存储单元进行读取，同时所述主芯片向每一从芯片传输依次产生的一个具有第四预设时长的高电平脉冲、B个具有第二预设时长的高电平脉冲及一个具有第三预设时长的低电平，其中，B等于缓存该另一帧画面对应区域的显示数据的存储单元在N个存储单元中的序号。
所述主芯片还向每一从芯片传输脉冲的时钟信号；
所述第一预设时长等于3倍的脉冲信号的周期；
所述第二预设时长等于脉冲信号的周期；
所述第三预设时长大于等于4倍的脉冲信号的周期；
所述第四预设时长等于5倍的脉冲信号的周期。
本发明的有益效果：本发明显示器驱动系统通过设置一个主芯片及多个从芯片，并使主芯片在利用与其连接的存储器缓存一帧画面对应区域的显示数据时标记缓存该一帧画面对应区域的显示数据的存储单元的序号，在对与存储器中的一存储单元中存储的一帧画面对应区域的显示数据进行读取时标记读取的存储单元的序号，产生对应的同步信号传输至每一从芯片中，控制一帧画面的显示数据同步缓存至多个存储器中序号相同的存储单元中，并控制主芯片及从芯片同步读取各自相连的存储器中序号相同的存储单元中存储的一帧画面对应区域的显示数据，有利于实现高分辨率高刷新率的设计，且能够消除多个芯片不同步导致的画面显示异常。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的显示器驱动系统的结构示意图；
图2为本发明的显示器驱动系统的存储器的结构示意图；
图3为本发明的显示器驱动系统的同步信号及时钟信号的波形图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种显示器驱动系统包括M个芯片1、M个存储器2、输入端3及显示器4，其中，M为大于2的正整数。
所述输入端3与M个芯片1均电性连接。所述显示器4与M个芯片1均电性连接。每一存储器2对应与一芯片1电性连接；每一存储器2均包括依序设置的N个存储单元21，其中N为大于1的正整数。所述M个芯片1中的一个定义为主芯片11，其余定义为从芯片12，每一从芯片12均与所述主芯片11电性连接。
所述输入端3接收多帧画面的显示数据，每一帧画面均包括M个区域，每一区域与一芯片1对应。所述输入端3向M个芯片1分别传输多帧画面对应区域的显示数据。所述芯片1将多帧画面对应区域的显示数据依序循环缓存至与其连接的存储器2的N个存储单元21中，并对N个存储单元21中存储的多帧画面对应区域的显示数据进行依序循环读取并进行转换后传输至显示器4。
所述主芯片11在利用与其连接的存储器2缓存一帧画面对应区域的显示数据时标记缓存该一帧画面对应区域的显示数据的存储单元21在N个存储单元21中的序号，在对与存储器2中的一存储单元21中存储的一帧画面对应区域的显示数据进行读取时标记读取的存储单元21在N个存储单元21中的序号，产生对应的同步信号传输至每一从芯片12中，控制一帧画面的M个区域的显示数据同步缓存至M个存储器2中序号相同的存储单元21中，并控制主芯片11及从芯片12同步读取各自相连的存储器2中序号相同的存储单元21中存储的一帧画面对应区域的显示数据。
具体地，每一帧画面可以均包括沿水平方向或者竖直方向依次排列的M个区域。
优选地，所述M个区域的面积相同。
具体地，在图1所示的实施例中，M＝2，也即图1所示的实施例中， 所述显示器驱动系统包括2个芯片，其中一个定义为主芯片11，另一个定义为从芯片12，相应地，每一帧画面均包括两个区域，该两个区域分别与主芯片11及从芯片12对应。
具体地，所述M个芯片1均为FPGA芯片。
具体地，请参阅图2，在发明的优选实施例中，N＝4，也即每一存储器2均包括依序设置的4个存储单元，同时能够存储四帧画面对应区域的显示数据。
具体地，所述输入端3接收多帧画面的显示数据的同时还接收多帧画面的输入帧起始信号，所述输入端3将多帧画面对应区域的显示数据传输至主芯片11的同时还将多帧画面的输入帧起始信号传输至主芯片11。
所述主芯片11通过其内部算法对多帧画面的输入帧起始信号进行处理，产生对应的多帧画面的输出帧起始信号。
请参阅图3，在本发明的一优选实施例中，所述主芯片11在利用与其连接的存储器2缓存一帧画面对应区域的显示数据时标记缓存该一帧画面对应区域的显示数据的存储单元21在N个存储单元21中的序号，在对与存储器2中的一存储单元21中存储的一帧画面对应区域的显示数据进行读取时标记读取的存储单元21在N个存储单元21中的序号，产生对应的同步信号的具体过程为：在一帧画面的输入帧起始信号的上升沿时刻，所述主芯片11利用与其连接的存储器2缓存该一帧画面对应区域的显示数据，同时所述主芯片11向每一从芯片12传输依次产生的一个具有第一预设时长的高电平脉冲、A个具有第二预设时长的高电平脉冲及一个具有第三预设时长的低电平，其中，A等于缓存该一帧画面对应区域的显示数据的存储单元21在N个存储单元21中的序号。该一个具有第一预设时长的高电平脉冲表示该一帧画面的输入帧起始信号的上升沿到来，该A个具有第二预设时长的高电平脉冲表示缓存该一帧画面对应区域的显示数据的存储单元21在N个存储单元21中的序号为A，例如，如图3所示，此时缓存该一帧画面对应区域的显示数据的存储单元21在N个存储单元21中的序号为3。该一个具有第三预设时长的低电平表示传输结束。而后另一帧画面的输出起始信号的上升沿时刻到来，所述主芯片11对与其连接的存储器2中存储有该另一帧画面对应区域的显示数据的存储单元21进行读取，同时所述主芯片11向每一从芯片12传输依次产生的一个具有第四预设时长的高电平脉冲、B个具有第二预设时长的高电平脉冲及一个具有第三预设时长的低电平，其中，B等于缓存该另一帧画面对应区域的显示数据的存储单元21在N个存储单元21中的序号。该一个具有第四预设时长的高电平脉 冲表示该另一帧画面的输出帧起始信号的上升沿到来，该B个具有第二预设时长的高电平脉冲表示缓存该另一帧画面对应区域的显示数据的存储单元21在N个存储单元21中的序号为B，例如，如图3所示，此时缓存该另一帧画面对应区域的显示数据的存储单元21在N个存储单元21中的序号为1，该一个具有第三预设时长的低电平表示传输结束。
进一步地，在本发明的一优选实施例中，所述主芯片11还向每一从芯片12传输脉冲的时钟信号。请参阅图3，所述第一预设时长等于3倍的脉冲信号的周期，所述第二预设时长等于脉冲信号的周期，所述第三预设时长大于等于4倍的脉冲信号的周期，所述第四预设时长等于5倍的脉冲信号的周期。
需要说明的是，本发明的显示器驱动系统通过设置一个主芯片11及多个从芯片12，并使主芯片11在利用与其连接的存储器2缓存一帧画面对应区域的显示数据时标记缓存该一帧画面对应区域的显示数据的存储单元21的序号，在对与存储器2中的一存储单元21中存储的一帧画面对应区域的显示数据进行读取时标记读取的存储单元21的序号，产生对应的同步信号传输至每一从芯片12中，控制一帧画面的显示数据同步缓存至多个存储器2中序号相同的存储单元21中，并控制主芯片11及从芯片12同步读取各自相连的存储器2中序号相同的存储单元21中存储的一帧画面对应区域的显示数据，能够实现多个芯片1的同步驱动，有利于实现高分辨率高刷新率的设计，且能够消除多个芯片1不同步导致的画面显示异常，且设计简单，同步信号仅需要设置一个即可。
综上所述，本发明的显示器驱动系统通过设置一个主芯片及多个从芯片，并使主芯片在利用与其连接的存储器缓存一帧画面对应区域的显示数据时标记缓存该一帧画面对应区域的显示数据的存储单元的序号，在对与存储器中的一存储单元中存储的一帧画面对应区域的显示数据进行读取时标记读取的存储单元的序号，产生对应的同步信号传输至每一从芯片中，控制一帧画面的显示数据同步缓存至多个存储器中序号相同的存储单元中，并控制主芯片及从芯片同步读取各自相连的存储器中序号相同的存储单元中存储的一帧画面对应区域的显示数据，有利于实现高分辨率高刷新率的设计，且能够消除多个芯片不同步导致的画面显示异常。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (9)

  1. 一种显示器驱动系统，包括M个芯片、M个存储器、输入端及显示器，其中，M为大于2的正整数；
    所述输入端与M个芯片均电性连接；所述显示器与M个芯片均电性连接；每一存储器对应与一芯片电性连接；每一存储器均包括依序设置的N个存储单元，其中N为大于1的正整数；所述M个芯片中的一个定义为主芯片，其余定义为从芯片，每一从芯片均与所述主芯片电性连接；
    所述输入端接收多帧画面的显示数据，每一帧画面均包括M个区域，每一区域与一芯片对应；所述输入端向M个芯片分别传输多帧画面对应区域的显示数据；所述芯片将多帧画面对应区域的显示数据依序循环缓存至与其连接的存储器的N个存储单元中，并对N个存储单元中存储的多帧画面对应区域的显示数据进行依序循环读取并进行转换后传输至显示器；
    所述主芯片在利用与其连接的存储器缓存一帧画面对应区域的显示数据时标记缓存该一帧画面对应区域的显示数据的存储单元在N个存储单元中的序号，在对与存储器中的一存储单元中存储的一帧画面对应区域的显示数据进行读取时标记读取的存储单元在N个存储单元中的序号，产生对应的同步信号传输至每一从芯片中，控制一帧画面的M个区域的显示数据同步缓存至M个存储器中序号相同的存储单元中，并控制主芯片及从芯片同步读取各自相连的存储器中序号相同的存储单元中存储的一帧画面对应区域的显示数据。
  2. 如权利要求1所述的显示器驱动系统，其中，M＝2。
  3. 如权利要求1所述的显示器驱动系统，其中，每一帧画面均包括沿水平方向依次排列的M个区域。
  4. 如权利要求1所述的显示器驱动系统，其中，每一帧画面均包括沿竖直方向依次排列的M个区域。
  5. 如权利要求1所述的显示器驱动系统，其中，所述M个区域的面积相同。
  6. 如权利要求1所述的显示器驱动系统，其中，所述M个芯片均为FPGA芯片。
  7. 如权利要求1所述的显示器驱动系统，其中，N＝4。
  8. 如权利要求1所述的显示器驱动系统，其中，所述输入端接收多帧画面的显示数据的同时还接收多帧画面的输入帧起始信号，所述输入端将 多帧画面对应区域的显示数据传输至主芯片的同时还将多帧画面的输入帧起始信号传输至主芯片；
    所述主芯片对多帧画面的输入帧起始信号进行处理，产生对应的多帧画面的输出帧起始信号；
    所述主芯片在利用与其连接的存储器缓存一帧画面对应区域的显示数据时标记缓存该一帧画面对应区域的显示数据的存储单元在N个存储单元中的序号，在对与存储器中的一存储单元中存储的一帧画面对应区域的显示数据进行读取时标记读取的存储单元在N个存储单元中的序号，产生对应的同步信号的具体过程为：在一帧画面的输入帧起始信号的上升沿时刻，所述主芯片利用与其连接的存储器缓存该一帧画面对应区域的显示数据，同时所述主芯片向每一从芯片传输依次产生的一个具有第一预设时长的高电平脉冲、A个具有第二预设时长的高电平脉冲及一个具有第三预设时长的低电平，其中，A等于缓存该一帧画面对应区域的显示数据的存储单元在N个存储单元中的序号，而后另一帧画面的输出起始信号的上升沿时刻到来，所述主芯片对与其连接的存储器中存储有该另一帧画面对应区域的显示数据的存储单元进行读取，同时所述主芯片向每一从芯片传输依次产生的一个具有第四预设时长的高电平脉冲、B个具有第二预设时长的高电平脉冲及一个具有第三预设时长的低电平，其中，B等于缓存该另一帧画面对应区域的显示数据的存储单元在N个存储单元中的序号。
  9. 如权利要求8所述的显示器驱动系统，其中，所述主芯片还向每一从芯片传输脉冲的时钟信号；
    所述第一预设时长等于3倍的脉冲信号的周期；
    所述第二预设时长等于脉冲信号的周期；
    所述第三预设时长大于等于4倍的脉冲信号的周期；
    所述第四预设时长等于5倍的脉冲信号的周期。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10983553B2 (en) * 2018-08-24 2021-04-20 Synaptics Incorporated System and method for synchronizing sensing signals of integrated circuit chips
CN109509424B (zh) 2019-01-28 2021-12-24 京东方科技集团股份有限公司 显示驱动装置、其控制方法及显示装置
TWI739437B (zh) * 2020-05-21 2021-09-11 瑞昱半導體股份有限公司 影像播放系統及其具有同步資料傳輸機制的影像資料傳輸裝置及方法
CN113851080B (zh) * 2021-11-29 2022-02-18 南京浣轩半导体有限公司 一种Mini-LED驱动方法和显示系统
CN114822347B (zh) * 2022-03-29 2023-03-21 北京奕斯伟计算技术股份有限公司 源极驱动系统、其信号同步方法及显示装置
US12062313B2 (en) * 2022-07-08 2024-08-13 Apple Inc. Systems and methods for clock frequency control during low display refresh rates in electronic devices
CN117912397B (zh) * 2022-10-11 2024-10-25 荣耀终端有限公司 显示面板和电子设备
CN116741121B (zh) * 2023-06-14 2026-03-24 维沃移动通信有限公司 显示控制系统、电子设备和显示方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1734539A (zh) * 2004-08-02 2006-02-15 冲电气工业株式会社 显示面板驱动装置
US20120086681A1 (en) * 2010-10-11 2012-04-12 Mc Technology Co., Ltd. Driving apparatus and display divice including the same
CN105245759A (zh) * 2015-11-23 2016-01-13 广东威创视讯科技股份有限公司 一种实现图像同步显示的方法及装置
CN105549933A (zh) * 2015-12-16 2016-05-04 广东威创视讯科技股份有限公司 显卡信号同步方法和系统
CN106716519A (zh) * 2014-09-17 2017-05-24 夏普株式会社 显示装置及其驱动方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100759972B1 (ko) * 2001-02-15 2007-09-18 삼성전자주식회사 액정 표시 장치와 이의 구동 장치 및 방법
JP2002296561A (ja) * 2001-03-30 2002-10-09 Optrex Corp 液晶パネルの貼り合わせ方法
JP2003084722A (ja) * 2001-09-12 2003-03-19 Matsushita Electric Ind Co Ltd 表示装置の駆動回路
US8994700B2 (en) * 2006-03-23 2015-03-31 Mark J. Foster Artifact-free transitions between dual display controllers
KR101642849B1 (ko) * 2009-06-02 2016-07-27 삼성디스플레이 주식회사 구동 장치의 동기화 방법 및 이를 수행하기 위한 표시 장치
CN105118448A (zh) * 2015-07-01 2015-12-02 深圳市华星光电技术有限公司 显示面板及其驱动方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1734539A (zh) * 2004-08-02 2006-02-15 冲电气工业株式会社 显示面板驱动装置
US20120086681A1 (en) * 2010-10-11 2012-04-12 Mc Technology Co., Ltd. Driving apparatus and display divice including the same
CN106716519A (zh) * 2014-09-17 2017-05-24 夏普株式会社 显示装置及其驱动方法
CN105245759A (zh) * 2015-11-23 2016-01-13 广东威创视讯科技股份有限公司 一种实现图像同步显示的方法及装置
CN105549933A (zh) * 2015-12-16 2016-05-04 广东威创视讯科技股份有限公司 显卡信号同步方法和系统

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