WO2019224431A1

WO2019224431A1 - Zero voltage switching power converters

Info

Publication number: WO2019224431A1
Application number: PCT/FI2019/050400
Authority: WO
Inventors: Jyrki Penttonen
Original assignee: Vensum Power Oy
Priority date: 2018-05-24
Filing date: 2019-05-23
Publication date: 2019-11-28

Abstract

The invention relates to a power converter (4) comprising a primary half bridge (31) with a first switch (M1 43A) and a second switch (M2 43B), wherein the primary half bridge (41) is configured to provide output power, and wherein the power converter (4) further comprises a charge injector (42) coupled to one or more switch node of the primary half bridge (41) through a resonant inductor (L1 50), and wherein the charge injector (42) is configured to generate a resonant current pulse corresponding to a charging time and a discharging time of the resonant inductor (L2 50) during dead time when both the first switch (M1 43A) and the second switch (M2 43B) are turned off for facilitating zero voltage switching condition.The power converter (4) further comprises a timing circuit (21) configured to control trigger timing and time length of the resonant current pulse, wherein the time length of the resonant current pulse corresponds to a charging time or a discharging time of the parasitic capacitances of the first switch (M1 43A) and the second switch (M2 43B) during the dead time; and wherein the resonant current pulse is injected to at least one of the one or more switch node of the primary half bridge (41) to equate the switch node voltage of the primary half bridge (41) to a source voltage, driving the voltage across the at least one switch to zero and turning on the first switch or the second switch at zero voltage switching.

Description

ZERO VOLTAGE SWITCHING POWER CONVERTERS

BACKGROUND

Power converters implemented with power electronics are used widely in many energy systems of today and the market is growing fast. Examples of markets where efficient power conversion plays a role comprise electric vehicles, solar generation, cloud server farms, motor drives and led lighting. The power converters are important in the transformation into a greener society. Great efforts are being made on multiple fronts in order to try to improve the electronic power converters according to a variety of optimization criteria, such as size, efficiency, reliability and costs. Some of these criteria are contradictory. For example, efficiency may be improved at the expense of size and costs.

A way to decrease the size of a power converter is to increase switching frequency as it means the filter capacitors and inductors get smaller. This, however, reduces efficiency as the power electronics switching elements in power converters contain parasitic capacitance the energy of which dissipates to the switching element, when closing the switch at non zero voltage - often called hard switching. These switching losses increase linearly according to frequency and this sets a limit to how high frequencies may be used. Typically, the limit may be a few hundred kHz.

During the last decades, technologies utilizing zero voltage switching (also known as soft switching) have been developed to facilitate increasing switching frequency without sacrificing on efficiency. Generally, at zero voltage switching, switching elements close when there is zero voltage over the switch. Therefore, capacitive energy loss may be eliminated and the switching frequency may be increased. However, implementations of typical zero voltage technologies are complex and their components may cause additional losses.

SUMMARY

It is an objective to provide a new type of zero voltage switching power converter. The objective may be achieved by the features of the independent claims. Some embodiments are described by the dependent claims.

According to a first aspect, there is provided a power converter. The power converter comprises a primary half bridge with a first switch and a second switch , wherein the primary half bridge is configured to provide output power , and wherein the power converter further comprises a charge injector coupled to one or more switch node of the primary half bridge through a resonant inductor, wherein the charge injector is configured to generate a resonant current pulse corresponding to a charging time and a discharging time of the resonant inductor during dead time when both the first switch and the second switch are turned off for facilitating zero voltage switching condition, wherein the power converter further comprises a timing circuit configured to control trigger timing and time length of the resonant current pulse, wherein the time length of the resonant current pulse corresponds to a charging time or a discharging time of the parasitic capacitances of the first and the second switch during the dead time; and wherein the resonant current pulse is injected to at least one of the one or more switch node of the primary half bridge to equate the switch node voltage of the primary half bridge to a source voltage, driving the voltage across the at least one switch to zero and turning on the first switch or the second switch at zero voltage switching. An embodiment may provide high efficient zero voltage switching in power converters. The embodiment may be implemented in various power converter topologies comprising of at least one half bridge for the power conversion. In an embodiment, the timing circuit is beneficial as it ensures that the generated resonant current pulse is not triggered or initiated too early. High speed logic gates with the time delay present in the timing circuit that the charging and discharging of the parasitic capacitance does not start until the current through the resonant inductor has completely reached to zero, This establishes that the circuit work at high frequency in a continuous manner and avoid any undesirable drift of the switching elements in the circuit. Furthermore, in order to achieve an efficient zero voltage switching, the system requires a precise trigger delay. As the trigger and gate drive signal (for switching on the MOSFET) have different times delays there is an inherent time difference between the trigger position and the gate drive signal. This can result in jitter in the output voltage V₀ut- To overcome this, the timing circuit compensates for the delay differences between the trigger and the gate drive signal.

In an embodiment, in addition or alternatively, the timing circuit configured to control switching frequency, wherein the switching frequency is a function of the time length of the resonant current pulse, and wherein the switching frequency is set above the natural resonance of the power converter.

In an embodiment, the charge injector comprises a secondary half bridge comprising a third switch and a fourth switch; and a resonant inductor coupled between switch nodes of the primary half bridge and the secondary half bridge; wherein at least one of the third switch or the fourth switch is configured to turn on for a time period corresponding a charging time of the resonant inductor during the dead time when the first and the second switch are turned off to generate the resonant current pulse. Thus, a sufficient and an appropriately timed current pulse may be injected to charge or discharge parasitic capacitances of the first and the second switches for zero voltage switching. The charge injector has simple design, which enables avoiding unnecessary additional losses and costs. In an embodiment, in addition or alternatively, the third and the fourth switch have significantly lower parasitic capacitances than the first and the second switch. The embodiment enables minimizing switching losses in the power converter.

In an embodiment, in addition or alternatively, the first and the second switch have substantially lower drain-source on resistance than the third and the fourth switch. The embodiment enables minimizing conduction losses in the power converter.

In an embodiment, in addition or alternatively, the power converter comprises a plurality of the primary half bridges connected in parallel. Thus, conduction losses may be further decreased for very high efficiency.

In an embodiment, in addition or alternatively, the resonant inductor is a printed circuit board trace inductor. The embodiment enables that no additional component is required. Thus, the charge injector may be a compact and low-cost solution for zero voltage switching. In an embodiment, in addition or alternatively, the power converter is operated at high frequency. The embodiment enables that very high switching frequencies may be used. Further, inductance and capacitance values of filtering components may decrease inversely proportional to the frequency. Thus, the filtering components of the power converted may be selected so that the size and cost of the power converter is significantly decreased. In an embodiment, in addition or alternatively, the power converter further comprises a timing circuit configured to control timing of the current pulse such that the pulse is initiated before or at the beginning of the dead time of the first and the second switch depending on a load current, and a time length of the current pulse is sufficient to charge or discharge parasitic capacitances of the first and the second switch substantially during the dead time. The embodiment enables generating an appropriately timed current pulse for zero voltage switching.

In an embodiment, in addition or alternatively, the timing circuit control timing of the current pulse depending on the load current. The average inductor current may be equal to the output (load) current. For a given constant load level, the inductor current may ramp above and below this level as the electronic switch is turned on and off. The output current is the average value of the inductor current, which varies between current maxima and minima. As the timing circuit control the time length of the resonant current pulse and therefore, the frequency, the higher frequency allows higher load current for a fixed inductance level. Thus, the embodiment enables for the higher load current and the reduced ripple in the output load current. In an embodiment, in addition or alternatively, the timing circuit is programmable and comprises digital logic gates to control the timing of the current pulse. The embodiment enables that delays can be tuned with low resolution. This may allow the generation of the current pulse of the right length. In an embodiment, in addition or alternatively, the power converter comprises more than one charge injector coupled in parallel. The embodiment enables further increasing the efficiency of the power converter by decreasing the switching and conduction losses. According to a second aspect, there is provided a system comprising the power converter according to the first aspect. The high efficiency, compact and low-cost zero voltage switching power converter may be used in different kinds of systems utilizing power converters comprising of at least one half bridge.

According to a third aspect, a method for zero voltage switching converter is provided. The power converter comprises a primary half bridge with a first and a second switch for power conversion and a charge injector coupled to a switch node of the primary half bridge, the method comprising causing both the first and the second switch to turn off at the same time for facilitating a dead time; and generating a resonant current pulse by the charge injector during the dead time for zero voltage switching; wherein the resonant current pulse is generated at least one of to the switch node to raise the switch node voltage for turning on the first switch or from the switch node to lower the switch node voltage for turning on the second switch. An embodiment may provide high efficient zero voltage switching in power converters. The embodiment may be implemented in various power converter topologies comprising of at least one half bridge for the power conversion. BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and constitute a part of this specification, illustrate embodiments of the invention and together with the description help to explain the principles of the invention. In the drawings: FIG. 1 illustrates a schematic representation of a block diagram of a zero voltage switching power converter according to an embodiment. FIG. 2 illustrates a schematic representation of circuit diagram of a buck converter comprising a charge injector for zero voltage switching according to an embodiment.

FIG. 3 illustrates a schematic representation of a circuit diagram of a buck converter comprising a charge injector for zero voltage switching according to another embodiment.

FIG. 4 illustrates a schematic representation of a circuit diagram of a boost converter comprising a charge injector for zero voltage switching according to an embodiment. FIG. 5 illustrates a schematic representation of a charge injector in operation according to an embodiment.

FIG. 6 illustrates a schematic representation of a generated current pulse for zero voltage switching according to an embodiment.

FIG. 7 illustrates a schematic representation of a timing diagram of the zero voltage switching power converter according to FIG. 3.

FIG. 8 illustrates a schematic representation of a circuit diagram of a programmable timing control circuit according to an embodiment.

FIG. 9 illustrates a schematic representation of timing signals generation by a programmable circuit according to an embodiment. FIG. 10 illustrates a schematic representation of a circuit diagram of a buck converter comprising more than one charge injector according to an embodiment.

FIG. 11 illustrates a schematic representation of a circuit diagram of a zero voltage switching converter with a plurality of half bridges for power conversion according to an embodiment. FIG. 12 illustrates a schematic representation of a single phase inverter coupled to charge injectors for zero voltage switching according to an embodiment.

FIG. 13 illustrates a schematic representation of a zero voltage switching full bridge converter according to an embodiment.

FIG. 14 illustrates a schematic representation of a circuit diagram of an on- chip zero voltage switching power converter according to an embodiment.

FIG. 15 illustrates a schematic representation of a circuit diagram of a charge injector according to an embodiment. FIG. 16 illustrates a schematic representation of a circuit diagram of a buck and boost charge injector according to an embodiment.

FIG. 17 illustrates a schematic representation of a circuit diagram of a flyback charge injector according to an embodiment.

FIG. 18 illustrates a schematic representation of a circuit diagram of a pulse forming network charge injector according to an embodiment.

FIG. 19 illustrates a schematic representation of a timing control according to an embodiment.

DETAILED DESCRIPTION

Most of power conversion systems comprises of half bridges. The half bridges comprise two switching elements, such as MOSFETs, IGBTs, IGCTs, or GaN transistors. Between the two switching elements is a switch node with a rapidly changing voltage based on whether the high or low side switch is on. For example, the voltage at the switch node may vary between a source voltage E and ground with a duty cycle D, thus providing an average voltage of DE at the switch node. This pulse width- modulated (PWM) square voltage may be filtered, for example, with an inductor and an output filter capacitor providing regulated output voltage. However, because many components of the power converter, such as the switching elements and a printed circuit board, contain parasitic capacitances and inductances, they have a significant impact on the efficiency of the power converter. The parasitic elements of the switching elements, for example MOSFETs, impacting switching performance of power converters may be loop inductances and a capacitance

formed between drain-to-source. The loop inductances are mainly caused due to component packaging and may vary between 1 nH to 20 nH. The parasitic capacitance CDS is the more influencing element, since the energy of the capacitance is lost when the MOSFET turns on while there is voltage over the MOSFET. This may be called hard switching. The loop inductances further increase the amount of energy loss, because they cause oscillation (also called ringing). The oscillation leads to a situation where also magnetic energy of the inductances get dissipated at the switching operation. Hence, conversion efficiency may further deteriorate. In addition to the switching losses caused by the parasitic elements, efficiency of the power conversion should be considered. When the MOSFET is turned on and conducting, there is an on-state resistance R-DSON between the drain and source of the MOSFET. According to a first aspect, the power converter comprises a primary half bridge with a first switch and a second switch , wherein the primary half bridge is configured to provide output power, and wherein the power converter further comprises a charge injector coupled to one or more switch node of the primary half bridge through a resonant inductor, wherein the charge injector is configured to generate a resonant current pulse corresponding to a charging time and a discharging time of the resonant inductor during dead time when both the first switch and the second switch are turned off for facilitating zero voltage switching condition. The power converter further comprises a timing circuit configured to control trigger timing and time length of the resonant current pulse, wherein the time length of the resonant current pulse corresponds to a charging time or a discharging time of the parasitic capacitances of the first and the second switch during the dead time, and wherein the resonant current pulse is injected to at least one of the one or more switch node of the primary half bridge to equate the switch node voltage of the primary half bridge to a source voltage, driving the voltage across the at least one switch to zero and turning on the first switch or the second switch at zero voltage switching.

Table 1 illustrates a relationship of parasitic capacitances and on-state resistances of exemplary MOSFETs.

Table 1

Table 1 comprises characteristics of six MOSFETs. In the table 1, Coss comprises CDS and a gate drive capacitance CGD^ ^vDS refers to a voltage over the drain and source of the MOSFET and I is a drain current. The contents of the Table 1 illustrate that there is an approximate inverse relationship between the CDS and ^RDSON· This means, that decreasing conduction losses may mean concurrently increasing switching losses. For every switching frequency, there may be an optimal R-DSON value to minimize the MOSFET losses. The value of the optimal R-DSON increases when the switching frequency increases. For example, for 100 khlz R_QSO may be 11.6 ohm, while for 10 MFIz the optimal RQSO ^may be 100 ohm. Thus, the resulting power loss increases rapidly as the frequency increases.

On the other hand, the size and efficiency are dependent on the switching frequency of the converter. With higher frequencies, smaller input/output capacitors and an output inductor may be selected. For example, capacitance of an output capacitor and inductance of an output inductor in a Buck converter may decrease inversely proportional to the switching frequency. Further, volume of the output inductor may decrease significantly because the volume is proportional to the switching frequency f 1-5. Flowever, as the switching losses increase proportional to the frequency, there is a natural point where the increase of frequency is no longer beneficial.

An embodiment enables a zero voltage switching power converter by ensuring that a switch node voltage changes so that the voltage of a switching element becomes zero at the time it turns on. The embodiment comprises a circuit which injects an accurately timed current pulse to or from the switch node, which current pulse charges or discharges parasitic capacitances of the switching elements of a half bridge of the power converter. Consequently, switching losses of the half bridge may be significantly reduced. The power converter may be implemented with lower RDSO MOSFETS. Thus, also conduction losses may be reduced. In addition, the power converter may be operated at higher frequencies and the size of the converter may be reduced as smal ler components ca n be selected . FIG. 1 illustrates a schematic representation of a block diagram of a zero voltage switching power converter 2 according to an embodiment. In FIG.12 the power converter 2 comprises a control module 20, a timing module 21 and a power module 22. The control module 20 is configured to receive values indicating an output voltage and, in response to the received values, control a pulse-width-modulation (PWM) output. The power module 22 comprises a half bridge for power conversion, a charge injector for facilitating zero voltage switching, and a sensing element for determining the output voltage values for the control module. The timing module 21 is configured to control timing of switches of the power converter by generating gate-drive signals. The timing module 21 may comprise, for example, digital logic gates configured to generate delays and trigger a current pulse. The delay signals may be generated to delay turn on and turn off times of the switches to prevent the switches from conducting at the same time. The timing module 21 is configured to facilitate a sufficient dead time when neither of the half bridge switches are on, thus avoiding a short circuit from the high side to the ground through the two switches. The current pulse is generated by the charge injector and it may be triggered by the timing module 21 so that it is generated during the dead time. In an embodiment, the time length of the current pulse may be configured to last for a sufficient time to charge or discharge parasitic capacitances of the switches during the dead time.

FIG. 2 illustrates a schematic representation of circuit diagram of a buck converter 3 comprising a charge injector 32 for zero voltage switching according to an embodiment. In FIG. 2, the buck power converter 3 comprises a primary half bridge 31 for power conversion and a charge injector II 32 for facilitating zero voltage switching. The buck converter 3 may further comprise an inductor and a capacitor for filtering an output voltage. The primary half bridge 31 comprises a first switch M l 33A and a second switch M2 33B configured to provide the output power. The charge injector II 32 is coupled to the switch node 36 of the primary half bridge 31 and configured to facilitate zero voltage switching by generating a resonant current pulse when both the first switch M l 33A and the second switch M2 33B are turned off, i.e. during dead time. The current pulse may be generated to the switch node 36 to raise the switch node voltage to turn on the first switch Ml 33A at a zero voltage switching condition. The generated current pulse may raise the switch node voltage to a supply voltage level by providing a positive current pulse to the switch node 36, which positive current pulse discharges parasitic capacitance of the first switch Ml 33A and charges parasitic capacitance of the second switch M2 33B. In an embodiment, the power converter 3 may comprise a buck module 30 comprising the primary half bridge 31, the inductor LI 34 and the capacitor Cl 35. The buck module 30 may be coupled to the charge injector II 32 for zero voltage switching.

In an embodiment, the power converter 3 may be, for example, a boost converter. In the embodiment, the current pulse may be generated from the switch node 36, meaning that a negative current pulse is generated, to turn on the second switch M2 33B at zero voltage condition. When the negative current pulse is provided, the parasitic capacitance of the first Ml 33A is charged and the parasitic capacitance of the second switch M2 33B is discharged. Thus, the switch node voltage decreases to zero. Hence, the charge injector II 32 may be configured to act as a current source as well as a current sink. Operational phases of the zero voltage switching buck converter 3 illustrated in FIG. 2 are now explained. At phase 1, the first switch M l 33A is turned on. The second switch M2 33B and the charge injector II 34 are on offstate. During phase 1, the inductor LI 34 is charged and power is delivered to the output.

At phase 2, zero voltage switching is facilitated for the second switch M2 33B. The switches Ml 33A, M2 33B and the charge injector II 32 are all on off-state. Consequently, the first Ml 33A and the second switch M2 33B are open, and no current pulse is generated. During the dead time, current of the inductor LI 34 discharges parasitic capacitance of the second switch M2 33B and charges the parasitic capacitance of the first switch Ml 33A.

At phase 3, the second switch M2 33B turns on while the first switch Ml 33A and the charge injector II 32 remain off. During the operation phase 3, the inductor LI 34 is discharged. Because the second switch M2 33B turns on at the zero voltage condition, switching losses may be eliminated. Also, conduction losses of a body diode of the second switch M2 33B may be eliminated, because the second switch M2 33B turns on before the body diode starts conducting.

At phase 4, zero voltage switching is facilitated for the first switch Ml 33A. The second switch M2 33B turns off and the charge injector II 34 turns on, while the first switch M l 33A remains on off mode. During this dead time, the charge injector II 32 charges parasitic capacitance of the second switch M2 33B and discharges the parasitic capacitance of the first switch M l 33A by generating an appropriately timed current pulse to the switch node 36.

Hence, the charge injector II 32 enables turning on the high side (first) switch Ml 33A at zero voltage switching. With the illustrated implementation, the efficiency of the power converter 3 may be improved while the charge injector II 32 also serves as a traditional snubber limiting over voltages and voltage stress to the switching elements. In many power supply designs a RC snubber circuit may be used to dampen the transient but it may reduce efficiency since excess energy is absorbed to the dampening resistor of the snubber circuit. The charge injector implementation enables that the switch node voltage changes smoothly and without oscillations. Thus, high frequency spectra may be low and therefore electromagnetic interference (EMI) is minimized.

FIG. 3 illustrates a schematic representation of a circuit diagram of a buck converter 4 comprising a charge injector 42 for zero voltage switching according to another embodiment. In FIG. 3, the buck converter 4 comprises a primary half bridge 41 with a first Ml 43A and a second switch M2 43B for converting an input voltage to an output voltage. The buck converter 4 may comprise an output inductor and an output filter capacitor for filtering the output voltage. Further, the power converter 4 comprises a charge injector 42 comprising a secondary half bridge 47 with a third M3 48A and a fourth switch M4 48B, and a resonant inductor L2 50. Both the primary 41 and the secondary half bridges 47 may be implemented, for example, with MOSFETs. Alternatively, the fourth switch M4 48B may be a diode. A switch node 49 of the secondary half bridge 47 is coupled to a switch node 46 of the primary half bridge 41 via the resonant inductor L2 50. In an embodiment, the power converter 4 may comprise a buck module 40 coupled to the charge injector 42. The buck module 40 may comprise the primary half bridge 41 with the first Ml and second switches M2 43A, 43B, the output inductor and the output filter capacitor for power conversion. The charge injector 42 is configured to generate a resonant current pulse to the switch node 46 of the primary half bridge 41 during dead time of the primary half bridge 41 to turn on the first switch Ml 43A at zero voltage switching condition. The current pulse may be generated by turning on the third switch M3 48A for a time period corresponding to a charging time of the resonant inductor L2 50. In an embodiment, also some load current may be passed via the third switch M3 48A. After the resonant inductor L2 50 is charged, the third switch M3 48A is turned off and the fourth switch M4 48B is turned on. The charge in the resonant inductor L2 50 is then injected to the switch node 46 of the primary half bridge 41 as the inductor L2 50 discharges. The zero voltage switching condition may be facilitated for the first switch Ml 43A with the charge injector 42 as the current pulse discharges and charges parasitic capacitances of the first Ml 43A and second switch M2 43B, and thereby, raises the voltage between the first Ml 43A and second switch M2 43B to a supply voltage level. The energy stored in the resonant inductor L2 50 resonates with the parallel combination of the parasitic capacitances of the first switch Ml 43A and the second switch M2 43B, causing the switch node voltage to ring towards the supply voltage level. This ring discharges the parasitic capacitance of first switch Ml 43A, diminishes the gate-to-drain (Miller) charge of first switch Ml 43A and charges the parasitic capacitance of the second switch M2 43B. This allows first switch Ml 43A to turn on in a lossless manner when the switch node voltage is nearly equal to supply voltage level.

In an embodiment, in addition or alternatively, the timing circuit 21 control timing of the current pulse depending on the load current. The average inductor current may be equal to the output (load) current. For a given constant load level, the inductor current may ramp above and below this level as the electronic switch is turned on and off. The output current is the average value of the inductor current, which varies between current maxima and minima. As the timing circuit control the time length of the resonant current pulse and therefore, the frequency, the higher frequency allows higher load current for a fixed inductance level. Thus, the embodiment enables for the higher load current and the reduced ripple in the output load current. In FIG.3, the resonant capacitance Cl 45 is in parallel combination with the resonant inductor LI 44. The Impedance of the parallel combination of the resonant inductor LI 44 and the resonant capacitance Cl 45 is a function of switching frequency. Resonance can happen between the parasitic elements in the circuit, such as leakage inductances and CQSS of the MOSFET being turned on, or among the main components of the circuit for example, the resonant capacitance Cl 45 and resonant inductor LI 44 in the present disclosure. In the former case, the operating frequency is constant. The switching sequence (frequency) is controlled by the timing circuit to achieve zero voltage turn on. The latter case, where resonance is achieved among the non-parasitic elements of the circuit, requires variable frequency operation. At resonant frequency (f_r), the resonant impedance reaches its minimum and the normalized output voltage gain becomes unity. The switching frequency must be set above the natural resonance of the circuit to present an inductive load. This ensures that the current is negative at the zero crossover of the fundamental component of the supply voltage level.

For the frequency region above the resonance, the total input impedance will appear inductive, which makes the input current lag the input voltage, and thus ZVS condition is attainable. ZVS is preferable for converters that use MOSFETs and diodes, since it minimizes the switching losses and the EMI effect. On the contrary, below the resonant frequency is the capacitive impedance region, where Zero Current Switching (ZCS) can be achieved. The ZCS condition is more favorable for reducing the switching losses for IGBT devices, but cannot reduce the switching loss in MOSFET converters. The peak gain of the parallel combination is affected by the load resistance. The peak gains occur at a frequency below the resonant frequency, and the peak frequency will be lower for a heavier load condition. The peak value can be larger or smaller than 1, which allows the converter to work in a wider gain range. The Output-voltage is controlled with higher frequency than resonant frequency at no - load condition. The aforementioned parallel combination of the resonant inductor LI 44 and the resonant capacitance Cl 45 can be further advantageous for the applications: which have a narrow input voltage range and a relatively constant load to maintain the working point near the maximum design power are more appropriate, which have low-output-voltage and high-output current applications.

The switching losses during the turn on of the first switch Ml 43A may be eliminated. When the first switch M l 43A turns off, the charge in the capacitances of the first Ml 43A and the second switch M2 43B may be transferred to a load via the output inductor LI 44. Thus, the parasitic capacitances of the first Ml 43A and the second switch M2 43B may serve as an intermediate storage of energy.

The third M3 and fourth M4 switches 48A, 48B may have parasitic capacitances and therefore they are not lossless. In an embodiment, the parasitic capacitances of the third M3 and fourth M4 switches 48A, 48B may be significantly smaller than the parasitic capacitances of the first Ml and second M2 switches 43A, 43B of the primary half bridge 41. Thus, the switching losses may be much smaller than compared to running the power converter hard switched. The switching losses may be reduced 95% compared to the hard switching. Due to the smaller parasitic capacitance values, the third M3 and fourth M4 switches 48A, 48B may have higher RQSO ^an the first Ml and the second M2 switch 43A, 43B. Small part of the total power may be transferred via the higher resistance switches M3 48A, M4 48B to achieve zero voltage switching. The power transfer takes place during short time period, for example 25 ns, and thus the resistive losses are small compared to the switching losses in hard switching low RDSO (and high Coss) MOSFETs. Thus, with the small additional loss, a major reduction in the total loss of the power converter is achieved.

In an embodiment, the resonant inductor L2 50 may have a small inductance value, for example 20 nH. Thus, the resonant inductor L2 50 may be implemented in a printed circuit board trace. Using the printed circuit board inductor enables that no additional component is required, and the charge injector 42 may be a compact and low-cost solution for zero voltage switching.

Because the switching losses of the first M l and second M2 switches 43A, 43B may be eliminated, R-DSON of the first Ml and second M2 switches 43A,

43B may be substantially smaller than RQSO of the third M3 and fourth M4 switches 48A, 48B. For example, MOSFETs with the lowest available RQSO values may be selected. Typically, MOSFETs are selected for a specific frequency based on their losses for the selected frequency. As an example, in an apparatus operated at a specific frequency and with a 10 A current, 30 ohm RQSO MOSFETS may have been forced to be used due to the optimization criteria. Therefore, conduction losses of the apparatus would be 3 W (and the switching losses). When the switching losses are eliminated, the MOSFETs may be selected based on a low RQSO value to minimize the conduction losses. In other words, one optimization criteria may be eliminated in selecting the switching elements. Therefore, with the charge injection scheme, the exemplary apparatus could be implemented, for example, with 2 ohm RQSO MOSFETS, which means that the conduction losses would decrease to 200mW. Further, the power converter may be operated at very high frequencies, for example above 1 MFIz. In an embodiment, the power converter may be operated at high frequency, which may be between 500 khlz - 30 MFIz. In another embodiment, the power converter may be operated between 500 kHz - 3 MHz. This enables selecting smaller input/output capacitors and output inductor. In addition, air core inductors may be used, which eliminates losses related to magnetic core inductors. Further, long life cycle ceramic capacitors may be used. Hence, the size and cost of the power converter may be significantly decreased.

For an example, a certain converter operating at 1 MHz frequency may be implemented with a 1.9 uH inductor and a 4 uF capacitor. If a converter with same requirements is operated at 10 kHz switching frequency, the converter would require a 187 uH inductor and a 333 uF capacitor. When the capacitance increases above tens of uF, an electrolytic type may need to be selected as the output capacitor. With smaller capacitances, the output capacitor may be implemented with long life cycle ceramic capacitor. The electrolytic capacitors may have mean time to failure only a few years, while the ceramic capacitors may have a life cycle of tens of years. With smaller inductance also the size of the inductor gets smaller, as the inductors effective cross-sectional area is inversely proportional to the switching frequency. For example, the volume of the 10 kHz converter inductor may be 22 cm2, and the volume of the 1 MHz converter inductor may be 0.7 cm^. Thus, in terms of volume, the 1 MHz inductor is 3 % of the volume of the 10 kHz inductor. Hence, by increasing the frequency, the size and costs of the power converter may be significantly decreased.

FIG. 4 illustrates a schematic representation of a circuit diagram of a boost converter 5 comprising a charge injector 52 for zero voltage switching according to an embodiment. In FIG. 4, the boost converter 5 comprises a primary half bridge 61 with a first M5 53A and a second switch M6 53B for converting an input voltage into an output voltage. The first M5 and the second M6 switch 53A, 53B may be, for example, MOSFETs. Alternatively, the first switch M5 53A may be a diode. The boost converter 5 may further comprise an inductor L3 54 coupled to a switch node 56 of the primary half bridge 61 on a supply side for raising the output voltage. In addition, the boost converter 5 may comprise an output filter capacitor C5 55. In an embodiment, the power converter 5 may comprise a boost module 51 coupled to the charge injector 52. The boost module 51 may comprise the primary half bridge 61 with the first M5 and second switches M6 53A, 53B, the inductor L3 54 and the output filter capacitor C5 55 for power conversion. The charge injector 52 may be coupled to the boost module 51 for zero voltage switching. The charge injector 52 may comprise a secondary half bridge 57 comprising a third D3 58A and a fourth switch M7 58B, and a resonant inductor L4 60. The third D3 58A and the fourth switch M7 58A may be, for example, MOSFETs. Alternatively, the third switch D3 58A may be a diode. The charge injector 52 is configured to decrease the switch node voltage of the primary half bridge 61 for facilitating zero voltage switching condition for the second switch M6 53B. The zero voltage condition may be implemented by generating a negative current pulse to the switch node 56 of the primary half bridge 61 during dead time of the first M5 53A and the second switch M6 53B, the negative current pulse discharging parasitic capacitance of the second switch M6 53B and charging parasitic capacitance of the first switch M5 53A. The negative current pulse may be generated by turning on the fourth switch M7 58B during the dead time of the primary half bridge 61 for a short time period. The time period may be configured to be sufficient for charging the resonant inductor L4 60 with an energy corresponding to the energies of the discharged/charged parasitic capacitances. The implementation of the charge injector 52 illustrated in FIG. 4 is similar to the implementation described for the buck converter 4 (FIG. 3), but the current pulse is reversed.

FIG. 5 illustrates a schematic representation of a charge injector 62 in operation according to an embodiment. The charge injector 62 may be coupled to a buck converter as illustrated in FIG. 3. The charge injector 62 may comprise a secondary half bridge with a third 68A and a fourth switch 68B. Due to illustrative purposes of the operational phases of the charge injector 62, the secondary half bridge is not shown as a whole in FIG. 5. The charge injector 62 may further comprise a resonant inductor L2 64 for charging and/or discharging parasitic capacitances of a primary half bridge 67 configured to power conversion. The primary 67 and the secondary half bridges may be coupled from their switch nodes 66, 65 via the resonant inductor L2 64. At the first operation phase of the charge injector 62, the third switch 68A turns on when both a first switch 63A and a second switch 63B of the primary half bridge 67 are turned off. The third switch 68A may be, for example, a MOSFET. For optimal performance, the third switch 68A may have significantly lower parasitic capacitance than the first 63A and the second switch 63A. The third switch 68A may also have higher resistance than the first 63A and the second switch 63B. Thus, the switching losses of the third switch 68A are very small, but conduction losses are higher than in the first 63A and second switch 63B. The current path during the first operation phase comprising the resistive loss of the third switch 68A during on-time is illustrated with a resistance R3 in FIG. 5. While the third switch 68A is on, the resonant inductor L2 64 is being charged. The third switch 68A may be closed until the inductor L2 64 is fully charged. Once the resonant inductor L2 64 is fully charged, the third switch 68A may be turned off. At the next phase, the resonant inductor L2 64 is discharged. The fourth switch 68B may be a diode D4, as illustrated in FIG. 5. Alternatively, the fourth switch 68B may be any other switching component, such as a MOSFET. The fourth switch 68B may be turned off, when the resonant inductor L2 64 is fully discharged. In other words, the resonant inductor L2 64 is charged and then discharged so that the current in the resonant inductor L2 64 is zero at the beginning of charging and at the end of discharging. Thus, the resulting current pulse may be a triangular charge pulse injected to the switch node 66 of the primary half bridge 67. The generated current pulse may discharge the parasitic capacitance of the first switch 63A and charge the parasitic capacitance of the second switch 63B (illustrated with capacitors Cl, C2 in FIG. 65, thereby raising the switch node voltage. As a result, the voltage across the first switch 63A is zero and it may turn on at zero voltage switching condition. The implementation enables that the switch node voltage changes relatively slowly and contain no oscillations compared to traditional hard switching converters. Therefore, there are no issues with electromagnetic compatibility and need for RC snubbers.

FIG. 6 illustrates a schematic representation of a generated current pulse 70 for zero voltage switching according to an embodiment. The current pulse 70 may be generated as described in FIG. 5. The triangular pulse 70 may inject a current, which is approximately Q=I^T, where I is the average current during the pulse 70 and T is the time length of the pulse 70. The loss in the switches of the charge injector may be estimated by

where C is the value of the parasitic capacitances and R is the onstate resistances between the drain and source of the switches of the secondary half bridge. For example, using the MOSFETs of Table 1, the lowest loss may be achieved with MOSFET 5 which RQSO '^S 100 mohm and

C_QSS ^is 100 pF. With this optimal component selection, the loss is 109 nJ.

This compares to a hard switching loss of 2601 nJ, when using the low RDSO with higher parasitic capacitance (MOSFET 1 in Table 1). With 1 MFIz frequency, the hard switching losses would be 2.6 W, while the use of the charge injector reduces the losses to 109 mW, which is only some 4 % of the original loss. Thus, the arrangement substantially improves the efficiency of power conversion. FIG. 7 illustrates a schematic representation of a timing diagram of a zero voltage switching power converter according to FIG. 3. In FIG. 7, T3 and T4 illustrate the timing of the third switch for triggering the current pulse timely by the charge injector. T3 corresponds to the time it takes for the low side second switch of the primary half bridge to open. Flence, it may be ensured that the both switches of the primary half bridge are completely turned off before generating the current pulse. In an embodiment, the third switch may be turned on slightly before the dead time. The time of turning on the third switch may be dependent on the load current such that, for example on high currents, the third switch may be turned on when the second switch has not yet opened. Thus, the conduction time of a body diode of the second switch may be minimized. Also, the optimal switch on time of the third switch may depend on the load current such that the generated pulse is not initiated too early (which causes that the inductor may be charged without charging the parasitic capacitances), and the current pulse is generated substantially during the dead time of the first and the second switch. T4 may be adjusted so that it equals to the time it takes to charge the resonant inductor of the charge injector. The charging time of the inductor may be determined as the time it takes for an inductive energy of the inductor to increase from zero to correspond to the capacitive energies of the first and second switches' parasitic capacitances. This may ensure, that at the end of the charging cycle the current of the resonant inductor is substantially zero. In an embodiment, timing of the fourth switch may be adjusted so that the fourth switch is switched on immediately after the third switch is turned off, and the turn-on time length corresponds to the time length of T4.

T1 corresponds to the dead time during the transition from the low side switch (the second switch) to the high side switch (the first switch). T1 may be set to T1=T3+2*T4. Flence, the current pulse may be generated during the dead time, because the length of the dead time is sufficient to charge and discharge the resonant inductor. This may allow the high side, i .e. the first switch, to turn on at the time when the voltage in the switch node has risen substantially to the level of the supply voltage, and thus, enabling the first switch to close at zero voltage. Timing of T2 corresponds to the dead time du ring the transition from the high side switch to the low side switch. T2 may be adjusted so that the output inductor current completely depletes the parasitic charges in the second switch and charges the parasitic capacitance of the first switch, decreasing the switch node voltage substantially to zero, and thereby facilitating zero voltage switching for the second switch to turn on . The timing of T2 may be load current dependent, but it also enables that a body diode in the second switch does not conduct and therefore the conduction losses may be minimized .

FIG. 8 illustrates a schematic representation of a circuit diagram of a programmable timing control circuit 90 according to an embodiment. In FIG. 8, high speed logic gates 91 may present, for example, 2 ns delays. The digital timing control circuit 90 may comprise, for example, eight buffer gates 91. A central processing unit (CPU) may select which of the eight delay alternatives 91 (i .e. 2 ns, 4 ns, 6 ns, 8 ns, 10 ns, 12 ns, 14 ns or 16 ns) is applied to a PWM signal by setting an output value in three signals. This creates a logic block, which inputs a signal and a codeword that determines the delay assigned to the PWM signal. In an embodiment, the programmable delay may be extended to having, for example, 2-64 ns delay changing incrementally by 2 ns by outputting a 6 bit codeword from the CPU. FIG. 9 illustrates a schematic representation of timing signals generation by a programmable circuit according to an embodiment. In FIG. 9, delay signals are added to PWM timing to allow zero voltage switching operation . The timing circuit in FIG. 9 may comprise the programmable delays 90 presented in FIG. 9 with a few additional gates. Delay TC 102 refers to a delay added to the turn-off time of the first and second switches. Delays TA 100 and TB 101 refer to delays added to the turn-on times of the first and the second switches. Thus, referring to the timing diagram illustrated in FIG. 7, 100 corresponds to T1 and 101- 102=T2. A timing signal for generating a current pulse by a current injector is resulted by adding a delay TD 103 to the PWM timing, during which delay TD 103 the current pulse is generated. The resulted timing signals may be provided to gate drivers of the switching elements. The illustrated current injection scheme may be used in most power converters comprised of one or more half bridges. Thus, different kinds of systems may be implemented using these zero voltage switching power converters. The electronic design may be identical when used in different power converters, and on ly the gate timings need to be changed so that an appropriate current pulse may be generated during dead time. In addition, one or more charge injectors may be coupled in parallel to the half bridge or half bridges of the power converters for further reduction in losses.

FIG. 10 illustrates a schematic representation of a circuit diagram of a buck converter 11 comprising more than one charge injector 112, 114 according to an embodiment. In FIG. 10, the power converter 11 is a buck converter comprising a primary half bridge 126 with a first M3 113A and a second switch M4 113B, an output inductor and an output filter capacitor. The power converter 11 further comprises a first charge injector 1 114 and a second charge injector 2 112, the first and the second charge injector 114, 112 each comprising a secondary half bridge 125, 124 with a third switch M l 117A, M2 115A and fourth switch D1 117B, D2 115B. The first charge injector 1 114 fu rther comprises a first resonant inductor LI 120 arranged between a supply voltage and ground such that the first charge injector 1 114 is coupled from its switch node 119 to the switch node 118 of the second charge injector 2 112 via the first resonant inductor LI 120. The second charge injector 2 112 comprises a second resonant inductor L2 121. The second charge injector 2 112 and the primary half bridge 126 are coupled from their switch nodes 118, 116 via the second resonant inductor L2 121. The first and the second charge injector 114, 112 are configured to generate a current pulse to the switch node 116 of the primary half bridge 126 during dead time of the switches M3 113A, M4 113B of the primary half bridge 126. The generated current pulse discharges parasitic capacitance of the first switch M3 113A and charges parasitic capacitance of the second switch M4 113B, thus facilitating a zero voltage switching condition for the first switch M3 113A. In an embodiment, the power converter 11 may comprise a buck module 110 configured to power conversion, and two cascaded charge injectors 114, 112 coupled to the buck module 110 for facilitating zero voltage switching. With the cascaded charge injection arrangement illustrated in FIG. 10, the conduction losses may be further reduced compared to having one charge injector, as illustrated in FIG. 3.

FIG. 11 illustrates a schematic representation of a circuit diagram of a parallelized buck converter 12 comprising a charge injector 121 according to an embodiment. FIG. 12 comprises similar zero voltage switching power converter with the charge injector as described in FIG. 3. Flowever, the power converter 12 comprises a parallelized buck module 120 with two primary half bridges 122, instead of only one, coupled to the charge injector 121 for facilitating zero voltage switching. Since the switching losses may be eliminated with the charge injector 121, low RQSO MOSFETS M33 123A, M34 123B, M37 124A, M38 124B may be used in parallel in the buck module 120. In an embodiment, the power converter 12 may comprise another power conversion module, instead of the buck module 120, comprising of more than one primary half bridge. Typically, MOSFETs of the primary half bridge(s) are selected based on the lowest possible RDS0I\U depending on the switching losses of the selected MOSFETs. Flowever, inefficiency may be caused by PCB trace resistances as high currents need to be channeled to these MOSFETs having low RDSO ^{a r|}d large dimensions. The parallelized approach enables using a number of smaller MOSFETs with larger RDSON · Thus, parallelization approximately divides the effective resistance by the number of MOSFETs. The parallelized arrangement also reduces an impact of MOSFET package inductance, thus reducing resonant oscillations in transitions. FIG. 11 illustrates a solution with four parallel switches, but the number of switches may be larger, for example 10 switches. Utilizing a plurality of low RDSO MOSFETS in parallel for the power conversion may allow substantial reduction in conduction losses without any additional losses. Flence, high efficiency may be achieved . FIG. 12 illustrates a schematic representation of a single phase inverter 13 coupled to charge injectors 131, 132 for zero voltage switching according to an embodiment. In FIG. 12, the single phase inverter 13 comprises two half bridges 138, 139 with first M 19 133A, M21 134A and second switches M20 133B, M22 134B. A switch node 137, 136 of each half bridge 138, 139 is coupled to a charge injector 131, 132. The charge injectors 131, 132 are configured to generate appropriately timed current pulses to the switch nodes 137, 136 during dead times of the half bridges 138, 139. A first charge injector 131 may be configured to generate the current pulse during dead time of a first primary half bridge 138 to facilitate zero voltage condition by turns to the first M 19 133A and the second switch M20 133B. A second charge injector 132 may be configured to generate the current pulse during dead time a second primary half bridge 139 to facilitate zero voltage condition by turns to the first M21 134A and the second switch M22 134B. The timing and polarity of the charging/sinking current pulses may depend on a phase of an input voltage. In an embodiment, the inverter may be a three phase inverter comprising of three primary half bridges, wherein a charge (sink) injector is coupled to a switch node of each of the primary half bridges for facilitating zero voltage switching.

FIG. 13 illustrates a schematic representation of a zero voltage switching full bridge converter 14 according to an embodiment. In FIG. 13, the full bridge converter 14 comprises a primary side 140 and a secondary side 141. In addition, the power converter 14 comprises two charge injectors 145, 142 coupled to the primary side 140 for zero voltage switching. The primary side 141 comprises two half bridges, a first 148 and a second 149 primary half bridge, with first M8 143A, Mil 144A and second M9 143B, M12 144B switches. Each charge injector 145, 142 is coupled to the switch node 152, 153 of the corresponding primary half bridge 148, 149 for charging or discharging parasitic capacitances of the first M8 143A, Mi l 144A and the second switches M9 143B, M12 144B of the primary half bridges 148, 149. The first primary bridge 148 may be coupled to a first charge injector 145, which first charge injector 145 may be configured to operate as a current source and generate a current pulse for facilitating zero voltage switching condition for the first switch M8 143A of the first primary half bridge 148. The first charge injector 145 may comprise a first secondary half bridge 151 with third and fourth switches M10 147A, D4 147B. The current pulse may be generated during dead time of the first primary half bridge 148 by turning on the third switch M10 147A for a short period to discharge parasitic capacitance of the first switch M8 143A and charge parasitic capacitance of the second switch M9 143B. The second primary half bridge 149 may be coupled to a second charge injector 142, which second charge injector 142 may be configured to operate as a current sink and facilitate zero voltage switching condition for the second switch M12 144B of the second primary half bridge 149. The second charge injector 142 may comprise a second secondary half bridge 150 with third and fourth switches D5 146A, M13 146B. The current pulse may be generated during dead time of the second primary half bridge 149 by turning on the fourth switch M13 146B for a short period to charge parasitic capacitance of the first switch Mi l 144A and discharge parasitic capacitance of the second switch M12 144B.

FIG. 14 illustrates a schematic representation of a circuit diagram of an on- chip zero voltage switching power converter 15 according to an embodiment. The chip illustrated in FIG. 14 comprises a power conversion unit 150, which may be, for example, a buck converter. The chip may further comprise a power controller 151 configured to receive output voltage and current values 154, and drive a PWM signals to control switches of the power converter 15. A zero voltage switching module 152 may be readily integrated on the chip or it may be an add-on module, which may be added to any existing converter chip comprising of a half bridge. The zero voltage switching module 152 may comprise gate drivers to facilitate a deadtime of the power conversion unit 150 and an appropriately timed current pulse during the dead time for zero voltage switching. The timings may be based on a load and a power conversion circuit topology. The zero voltage switching module 152 comprises a charge injector 153 for generating the current pulse. The zero voltage switching module 152 is configured to receive the output signals 154 intended for driving the switches (by the power controller 151) and manipulates the timing of the signals for facilitating the appropriate deadtime and current pulse. FIG. 15 illustrates a schematic representation of a circuit diagram of a charge injector 162 according to an embodiment. In FIG. 15, the charge injector 162 comprises a LC network 164 and two switches M63 161, M64 163. The illustrated charge injector topology may be a generalized view of pulse generation. In an embodiment, the LC network 164 may comprise a single resonant inductor coupled to a switch node 166 of a primary half bridge 160 of a power converter 16. The switch M63 161 may be coupled to a voltage source V4 165. The switches M63 161, M64 163 of the charge inductor 162 may be configured to charge and discharge the resonant inductor during dead time of the primary half bridge 160, thereby generating a current pulse discharging and charging parasitic capacitances of switching elements of the primary half bridge 160. Hence, the charge injector 162 provides zero voltage switching operation for the power converter. FIG. 16 illustrates a schematic representation of a circuit diagram of a buck and boost charge injector 172 according to an embodiment. In FIG. 16, current pulse generation is implemented by a charge injector 172, which may be, a buck and boost configuration. The charge injector 172 may comprise a voltage source VI 175, a first switch M48 171, a second switch M49 173 and a resonant inductor L23 174 arranged between a switch node 177 of the first M48 171 and the second switch M49 173 and ground. The first and the second switches M48 171, M49 173 may be MOSFETs, or the second switch M49 173 may be a diode. The voltage source VI 175 may be negative. In an embodiment, the voltage source VI 175 may be smaller than a supply voltage ( | VI | < | Vsupply | ), which may reduce switching loss in the first switch 48 171. Before dead time of a primary half bridge 170 of a converter 17, the resonant inductor L23 174 may be charged by turning on the first switch M48 171. After a predetermined time period, the first switch 48 171 may be turned off, after which a body diode in the second switch M49 173 starts to conduct. Thereafter, a current pulse is generated to a switch node 176 of the primary half bridge 170 during the dead time as the second switch M49 173 may be turned on, and the resonant inductor L23 174 discharges and charges parasitic capacitances of switching elements of the primary half bridge 170. FIG. 17 illustrates a schematic representation of a circuit diagram of a flyback charge injector 182 according to an embodiment. In FIG. 17, a charge injector pulse for facilitating zero voltage switching may be generated via a flyback. The charge injector 182 is similar to the buck and boost charge injector illustrated in FIG. 16, but the resonant inductor may be replaced by a coupled inductor 181. The coupled inductor 181 may comprise a first inductor L25 183 and a second inductor L27 184, which inductors L25 183, L27 184 may be coupled in reverse direction. The charge injector 182 comprises first M52 187 and second switches DIO 185 and a voltage source V2 188, which may be positive voltage. For reducing switching loss of the first switch M52 183, the voltage source V2 188 may be selected smaller than a supply voltage. The switches M52 187, DIO 185 may be MOSFETs, or the second switch DIO may be a diode. Before dead time of a primary half bridge 180 of a converter 18, the coupled inductor 181 may be charged by turning on the first switch M52 187. After the coupled inductor 181 is sufficiently charged for charging/discharging parasitic capacitances of switching elements of the primary half bridge 180 during the dead time, the first switch M52 181 may be turned off. The magnetic energy is then released via the second inductor L27 184 to a switch node 186 of the primary half bridge 180.

FIG. 18 illustrates a schematic representation of a circuit diagram of a pulse forming network charge injector 192 according to an embodiment. In FIG. 18, the charge injector 192 may comprise a pulse forming network for generating a current pulse to facilitate zero voltage switching. The pulse forming network may comprise a plurality of LC elements L28 194, C21 195, L29 197, C22, 198, L30, 199, C23 200, L31 201, C24 202 in series. The charge injector 192 is coupled to a switch node 196 of a primary half bridge 190 of a converter 19. When a low side switch of the primary half bridge 190 is on, the pulse forming network may be charged by turning on a first switch M59 193 of the charge injector 192. At the end of the charging operation, current of all inductors L28 194, L29 197, L30 199, L31 201 are zero and voltages in all capacitors C21 195, C22 198, C23 200, C24 202 are equal to the voltage of a voltage source V3 191. During dead time of the primary half bridge 190, a second switch M56 203 of the charge injector 192 may be turned on and an almost square pulse is generated to charge/discharge parasitic capacitances of switching elements of the primary half bridge 190. Further, the squared pulse may reduce conduction losses in the primary half bridge 190. Thus, the charge injector for zero voltage switching may be implemented according to various topologies. The described examples of the charge injectors may be used in different kinds of applications. For example, the flyback charge injector may be used for high voltages, because the switches of the charge injector may be operated at low voltage, and thus, reduce switching losses. Further, leakage inductances may be smaller due to small currents. For another example, a charge injector comprising a secondary half bridge and a resonant inductor coupled to a switch node of a primary half bridge of a converter may be suitable for low voltages. Different configurations may be used, as long as an appropriately timed current pulse is injected to the switch node of the power converting half bridge by the charge injector.

FIG. 19 illustrates a schematic representation of a timing control according to an embodiment. In FIG. 19, a CPU 92 may select which delay alternatives (for example, as illustrated in FIG. 8) is applied to a PWM signal by setting an output value in three signals G1-G3. A logic 93 may be configured to convert a binary number such that the output comprises only one zero and the rest are zeros (for example, a binary number 11 may be converted into 1000). Thus, the CPU 92 may not need to have a large number of outputs as the logic 93 may convert the outputs into a larger amount. In an embodiment, the logic 93 may be a shift register. In the embodiment, the CPU 92 may control one output and a clock signal to trigger the control signals, as illustrated in FIG. 8. This may decrease the number of logic gates, and enable more accurate resolution for the timings.

While there have been shown and described and pointed out fundamental novel features as applied to preferred embodiments thereof, it will be understood that various omissions and substitutions and changes in the form and details of the devices and methods described may be made by those skilled in the art without departing from the spirit of the disclosure. For example, it is expressly intended that all combinations of those elements and/or method steps which perform substantially the same function in substantially the same way to achieve the same results are within the scope of the disclosure. Moreover, it should be recognized that structures and/or elements and/or method steps shown and/or described in connection with any disclosed form or embodiments may be incorporated in any other disclosed or described or suggested form or embodiment as a general matter of design choice. Furthermore, in the claims means-plus function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures.

The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole, in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that the disclosed aspects/embodiments may consist of any such individual feature or combination of features. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the disclosure.

Claims

1. A power converter (4) comprising a primary half bridge (31) with a first switch (M l 43A) and a second switch (M2 43B), wherein the primary half bridge (41) is configured to provide output power, and wherein the power converter (4) further comprises a charge injector (42) coupled to one or more switch node of the primary half bridge (41) through a resonant inductor (LI 50), and wherein the charge injector (42) is configured to generate a resonant current pulse corresponding to a charging time and a discharging time of the resonant inductor (L2 50) during dead time when both the first switch (Ml 43A) and the second switch (M2 43B) are turned off for facilitating zero voltage switching condition, characterized in that the power converter (4) further comprises a timing circuit (21) configured to control trigger timing and time length of the resonant current pulse, wherein the time length of the resonant current pulse corresponds to a charging time or a discharging time of the parasitic capacitances of the first switch (M l 43A) and the second switch (M2 43B) during the dead time; and wherein the resonant current pulse is injected to at least one of the one or more switch node of the primary half bridge (41) to equate the switch node voltage of the primary half bridge (41) to a source voltage, driving the voltage across the at least one switch to zero and turning on the first switch or the second switch at zero voltage switching.

2. The power converter (4) of claim 1, wherein the timing circuit (21) is configured to control switching frequency, wherein the switching frequency is a function of the time length of the resonant current pulse, and wherein the switching frequency is set above the natural resonance of the power converter (4).

3. The power converter (4) of claim 1, wherein the charge injector (42) comprises: - a secondary half bridge (47) comprising a third switch (M3 48A) and a fourth switch (M3 48B); and

- a resonant inductor (LI 50) coupled between switch nodes of the primary half bridge (41) and the secondary half bridge (47);

wherein at least one of the third switch (M3 48A) or the fourth switch (M3 48B) is configured to turn on for a time period corresponding a charging time of the resonant inductor (LI 50) during the dead time when the first (Ml 43A) and the second switch (M2 43B) are turned off to generate the resonant current pulse.

4. The power converter of claim 3, wherein the third (M3 48A) and the fourth switch (M3 48B) have significantly lower parasitic capacitances than the first (M l 43A) and the second switch (M2 43B).

5. The power converter (4) of claim 3 or 4, wherein the first (M l 43A) and the second switch (M2 43B) have substantially lower drain-source on resistance than the third (M3 48A) and the fourth switch (M3 48B).

6. The power converter (4) of claim 5, further comprising a plurality of the primary half bridges connected in parallel.

7. The power converter (4) of any of the preceding claims, wherein the resonant inductor (LI 50) comprises a printed circuit board trace inductor.

8. The power converter (4) of any of the preceding claims, wherein the power converter is operated at high frequency.

9. The power converter (4) of any of the preceding claims, wherein the timing module is further configured to control switching operations of the first (M l 43A) and the second switch (M2 43B) according to a load current such that the time length of the dead time is sufficient to charge or discharge the parasitic capacitances of the first switch (Ml 43A) and the second switch (M2 43B).

10. The power converter of any of the preceding claims, wherein the timing circuit is programmable and comprises digital logic gates (91) to control the timing of the current pulse.

11. The power converter (4) of any of the preceding claims, wherein the power converter comprises a plurality of cascaded charge injectors.

12. A system comprising the power converter of any of the preceding claims.

13. A method for zero voltage switching power converter, the power converter (4) comprising a primary half bridge (41) with a first (Ml 43A) and a second switch (M2 43B) for power conversion, wherein the power converter (4) further comprises a charge injector (42) coupled to a one or more switch node of the primary half bridge (41) through a resonant inductor (LI 50), and wherein the charge injector (42) is configured to generate a resonant current pulse corresponding to a charging time and a discharging time of the resonant inductor (L2 50) during dead time when both the first switch (Ml 43A) and the second switch (M2 43B) are turned off for facilitating zero voltage switching condition, characterized in that the method comprises controlling trigger timing and time length of the resonant current pulse, wherein the time length of the resonant current pulse corresponds to a charging time or a discharging time of the parasitic capacitances of the first switch (M l 43A) and the second switch (M2 43B) during the dead time; and wherein the resonant current pulse is injected to at least one of the one or more switch node of the primary half bridge (41) to equate the switch node voltage of the primary half bridge (41) to a source voltage, driving the voltage across the at least one switch to zero and turning on the first switch or the second switch at zero voltage switching.