WO2019217976A3 - Patterning on layer transferred templates - Google Patents

Patterning on layer transferred templates Download PDF

Info

Publication number
WO2019217976A3
WO2019217976A3 PCT/US2019/037992 US2019037992W WO2019217976A3 WO 2019217976 A3 WO2019217976 A3 WO 2019217976A3 US 2019037992 W US2019037992 W US 2019037992W WO 2019217976 A3 WO2019217976 A3 WO 2019217976A3
Authority
WO
WIPO (PCT)
Prior art keywords
gan
growth
patterning
layers
patterned
Prior art date
Application number
PCT/US2019/037992
Other languages
French (fr)
Other versions
WO2019217976A2 (en
Inventor
Dong Seung Lee
Francois J. Henley
Original Assignee
QMAT, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by QMAT, Inc. filed Critical QMAT, Inc.
Publication of WO2019217976A2 publication Critical patent/WO2019217976A2/en
Publication of WO2019217976A3 publication Critical patent/WO2019217976A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
    • H01L33/502—Wavelength conversion materials
    • H01L33/504—Elements with two or more wavelength conversion materials

Abstract

Embodiments pattern layer transferred substrates prior to material growth, improving fabrication of electronic devices, and in particular electro-optic devices. For μ-LED formation, patterned (GaN, GaAs) layers precisely define narrow street widths between adjacent dies without damaging the LEDs, and can minimize side-wall losses otherwise due to dry etching or laser scribing for street formation. For growth of seed layers on GaN donor substrates, patterned GaN layers can minimize wafer curvature and stress accumulation during subsequent HVPE growth, with patterning and/or spacing dictated by expected Coefficient of Thermal Expansion (CTE) mismatch between wafers and the overlying GaN being grown. GaN crystal quality can be enhanced by Epitaxial Lateral Overgrowth (ELOG) effects resulting from the proper pattern shape/spacing with crystal orientation and growth conditions. Embodiments may be utilized for other applications (e.g., high power LEDs, power electronics, vertical transistors), with patterning approaches providing GaN of increased thickness and promoting chemical lift-off techniques.
PCT/US2019/037992 2018-04-26 2019-06-19 Patterning on layer transferred templates WO2019217976A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201862662958P 2018-04-26 2018-04-26
US62/662,958 2018-04-26

Publications (2)

Publication Number Publication Date
WO2019217976A2 WO2019217976A2 (en) 2019-11-14
WO2019217976A3 true WO2019217976A3 (en) 2020-01-09

Family

ID=68468432

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2019/037992 WO2019217976A2 (en) 2018-04-26 2019-06-19 Patterning on layer transferred templates

Country Status (1)

Country Link
WO (1) WO2019217976A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113410344A (en) * 2020-03-16 2021-09-17 重庆康佳光电技术研究院有限公司 LED chip set, display screen and manufacturing method thereof
CN113044809B (en) * 2021-03-22 2022-03-18 南京大学 Vertical Ga2O3 nanotube ordered array and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009519202A (en) * 2005-12-12 2009-05-14 キーマ テクノロジーズ， インク． Group III nitride product and method for producing the same
US20110140072A1 (en) * 2008-08-21 2011-06-16 Nanocrystal Corporation Defect-free group iii - nitride nanostructures and devices using pulsed and non-pulsed growth techniques
US20120241919A1 (en) * 2009-12-11 2012-09-27 Sharp Kabushiki Kaisha Method for manufacturing semiconductor device, and semiconductor device
US20150076450A1 (en) * 2012-01-10 2015-03-19 Norwegian University Of Science And Technology (Ntnu) Nanowire device having graphene top and bottom electrodes and method of making such a device
WO2016205751A1 (en) * 2015-06-19 2016-12-22 QMAT, Inc. Bond and release layer transfer process

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009519202A (en) * 2005-12-12 2009-05-14 キーマ テクノロジーズ， インク． Group III nitride product and method for producing the same
US20110140072A1 (en) * 2008-08-21 2011-06-16 Nanocrystal Corporation Defect-free group iii - nitride nanostructures and devices using pulsed and non-pulsed growth techniques
US20120241919A1 (en) * 2009-12-11 2012-09-27 Sharp Kabushiki Kaisha Method for manufacturing semiconductor device, and semiconductor device
US20150076450A1 (en) * 2012-01-10 2015-03-19 Norwegian University Of Science And Technology (Ntnu) Nanowire device having graphene top and bottom electrodes and method of making such a device
WO2016205751A1 (en) * 2015-06-19 2016-12-22 QMAT, Inc. Bond and release layer transfer process

Also Published As

Publication number Publication date
WO2019217976A2 (en) 2019-11-14

Similar Documents

Publication Publication Date Title
KR101909919B1 (en) Stress relieving semiconductor layer
US8759203B2 (en) Growing III-V compound semiconductors from trenches filled with intermediate layers
JP5244487B2 (en) Gallium nitride growth substrate and method for manufacturing gallium nitride substrate
KR100921789B1 (en) Method for preparing compound semiconductor substrate
US8133803B2 (en) Method for fabricating semiconductor substrates and semiconductor devices
US8877652B2 (en) Substrate structure and method of manufacturing the same
US8652949B2 (en) Method of manufacturing semiconductor wafer
CN101997071A (en) Substrate structures and methods of manufacturing the same
KR102071034B1 (en) Method of fabricating nitride substrate
CN105702562A (en) Method for manufacturing a group iii nitride substrate using a chemical lift-off process
US20100035416A1 (en) Forming III-Nitride Semiconductor Wafers Using Nano-Structures
JP2009231561A (en) Nitride semiconductor crystal thin film and its manufacturing method, and semiconductor device and method of manufacturing the same
WO2019217976A3 (en) Patterning on layer transferred templates
JP5233894B2 (en) Manufacturing method of nitride semiconductor free-standing substrate
Aida et al. Control of initial bow of sapphire substrates for III-nitride epitaxy by internally focused laser processing
KR101157426B1 (en) Base substrate for gallium nitride, fabrication method of base substrate, and fabrication method of gallium nitride
US20150115277A1 (en) Episubstrates for Selective Area Growth of Group III-V Material and a Method for Fabricating a Group III-V Material on a Silicon Substrate
KR20180070781A (en) Method of forming nitride semiconductor substrate and method of forming semiconductor device
JP2014237570A (en) Method of producing nitride semiconductor substrate
KR20030061317A (en) Method of producing 3-5 group compound semiconductor and semiconductor element
KR20100061062A (en) Growing method of nitride single crystal thin film and manufactuing method of nitride semiconductor light emitting devide
JP2012066974A (en) Nitride semiconductor wafer and manufacturing method therefor
KR101967716B1 (en) MANUFACTURING METHOD FOR GaN WAFER
JP4747319B2 (en) Heteroepitaxial growth method
KR20230157470A (en) Semiconductor substrate and its manufacturing method and manufacturing device, semiconductor device and its manufacturing method and manufacturing device, electronic equipment

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19799489

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 09-04-2021)

122 Ep: pct application non-entry in european phase

Ref document number: 19799489

Country of ref document: EP

Kind code of ref document: A2