WO2019215248A1

WO2019215248A1 - Method for replacing a first chip of a multi-pixel led module

Info

Publication number: WO2019215248A1
Application number: PCT/EP2019/061855
Authority: WO
Inventors: Tilman Ruegheimer; Frank Singer
Original assignee: Osram Opto Semiconductors Gmbh
Priority date: 2018-05-09
Filing date: 2019-05-08
Publication date: 2019-11-14
Also published as: DE102018111174A1

Abstract

The invention relates to a method for replacing a first chip of a multi-pixel LED module with a second chip, the first chip being defective. According to the invention, the first chip is identified and then a first conductor track of the multi-pixel LED module is cut through.

Description

PROCESS FOR REPLACING A FIRST CHIP OF A MULTIPIXEL

LED MODULE

DESCRIPTION

The invention relates to a method for replacing a ers th chip of a multi-pixel LED module by a second chip and a multi-pixel LED module, which is adapted to carry out the proceedings.

This patent application takes the priority of the German Pa tentanmeldung 10 2018 111 174.6 from 09.05.2018 to claim, the contents of which is fully incorporated by reference.

During the production of multi-pixel LED modules, if individual chips are found to be defective, they can be reworked by soldering solder joints of the affected chip being softened by local heating. Subsequently, the defective chip can be removed. After a reprocessing of the solder joints, a new chip can be used and soldered. This can be carried out, for example, as surface mounting (SMT).

A disadvantage of this revision method is that this is very complex and thereby ent hen high production costs, should be defective individual chips of the multi-pixel LED module.

Multi-pixel LED modules may comprise between one hundred and four hundred pixels on a substrate, where each pixel may comprise up to four colors (red, green, blue, white). Common are pixels with three colors (red, green, blue).

An object of the invention is to provide an improved method for replacing a chip on a multi-pixel LED module be. Another object of the invention is to provide a corresponding multi-pixel LED module. This object is achieved with the method and the multi-pixel LED module of the independent claims. Further advantageous embodiments before are specified in the dependent patent entitlements.

In a method for replacing a first chip of a multi-pixel LED module with a second chip, the defective, first chip to be replaced is first identified. This may include a functional test of the multi-pixel LED module angeord Neten chips. Subsequently, a first trace of the multi-pixel LED module is severed. The defective first chip can remain in the multi-pixel LED module. The Durchtren NEN of the first conductor can be made such that the ers te chip can no longer be energized.

The fact that the first chip in the multi-pixel LED module can ben ben, eliminating several complex steps of the previously known revision method. The method can therefore be carried out more cheaply.

In one embodiment of the method, the multi-pixel LED module provides pads for the second chip. The second chip is introduced only after identifying the first chip on the contact points of the multi-pixel LED module. It may be provided that the contact Stel len are covered by an insulating layer, wherein the Iso lationsschicht is at least partially removed from the contact points before attaching the second chip. This reduces the number of second chips needed.

In one embodiment of the method, the second chip is already arranged before identifying the first chip on the multi-pixel LED module. In particular, each pixel may already have a second chip. As a result, first and second chips can be integrated in the same process step in the multi-pixel LED module, whereby the manufacturing process is simplified. In one embodiment of the method, the first chip and the second chip are connected in parallel. The first trace is connected to the first chip. By severing the first trace, the electrical connection of the first chip is thus interrupted.

In one embodiment of the method, the first chip and the second chip are connected in series. The first interconnect bridges the second chip or pads for the second chip. Before the first interconnect is cut through, current can flow through the first chip and through the first interconnect; after the first interconnect has been severed, the current flows through the second chip. In this method, in addition, it may be provided that a first bridge is he provides, with the first chip is short-circuited. The first bypass can be created by applying an electrically conductive material.

In one embodiment of the method, the separation of the first conductor track by means of laser ablation takes place. In this case, a laser beam directed to the first conductor who the, wherein material of the first conductor track removed due to the laser beam and thus the first conductor is severed.

In one embodiment of the method, the first chip and the second chip are arranged in a component, wherein the component can be configured as an SMD component. The component has contacts to printed conductors on a printed circuit board, wherein for carrying out the method, the first printed conductor is severed on the printed circuit board. The component can contain further chips, for example for further colors of the pixel.

In one embodiment of the method, the first chip is arranged in a first component and the second chip is arranged in a second component. The components can be designed as SMD components. The components assign contacts Tracks on a circuit board, wherein the implementation of the method, the first trace is severed on the circuit board. The first component may include a third chip, while a fourth chip may be arranged in the second component. These can provide additional colors of the pixel. Further, it can be provided, analogous to the separation of the first conductor track to sever a second conductor, whereby the method is carried out analogously for the third and fourth chip.

A multi-pixel LED module has a printed circuit board, a first chip, pads for a second chip and a first trace. The first conductor track is designed in such a way that the first conductor track can be severed at a predetermined first position. As a result, the method according to the invention can be carried out.

In one embodiment of the multi-pixel LED module, a second chip is connected to the pads. This allows the second chip integrated before the implementation of the inventive method in the multi-pixel LED module who the.

In one embodiment of the multi-pixel LED module, each pixel has a first chip and a first trace.

This allows the method to be applied to all pixels of the multi-pixel LED module.

In one embodiment of the multi-pixel LED module, the first chip is arranged in a first component and the second chip is arranged in a second component. The components can be designed as SMD components. The components have Kon contacts to tracks on a circuit board, wherein for carrying out the method, the first conductor can be cut terplatte on the Lei. The first component contains a third chip, while a fourth chip is arranged in the second component. These provide further colors of the pox. Furthermore, it can be provided, analogous to the separate the first trace to sever a second trace, thereby the method can be carried out analogously for the third and fourth chip.

The above-described features, features and advantages of this invention, as well as the manner in which these are achieved, will become clearer and more clearly understood in connection with the following description of the Ausführungsbei games, the erläu closer in connection with the drawings. This show in each case schematic representation

Fig. 1 is a circuit diagram of a parallel circuit of chips; Fig. FIG. 2 shows a circuit diagram of a series connection of chips, where a first chip bridges a first chip; FIG.

Fig. 3 is a circuit diagram of another series circuit of

Chips, whereby a later to be applied first bridging is possible;

Fig. 4 is a plan view of a first pixel;

Fig. 5 is a plan view of the first pixel after a

Conductor track was severed;

6 shows a first component;

Fig. 7 is a plan view of a second pixel;

Fig. a second component;

9 is a plan view of the second pixel after a

Conductor track was severed;

10 is a plan view of the second pixel after a

Bridging was applied; Fig. 11 is a plan view of contact points of a third Pi xels;

FIG. 12 shows a third component; FIG.

Fig. 13 is a plan view of the third pixel after a

Conductor track was severed and a bridging was brought up;

Fig. 14 is a plan view of pads of a fourth Pi xels;

Fig. 15 is a fourth component;

16 is a plan view of the fourth pixel after a

Conductor track was severed and a bridging was brought up;

Fig. 17 is a multi-pixel LED module.

Fig. 1 shows a circuit diagram 100 of a parallel circuit 101 of chips 110, 120, wherein a first chip 110 is disposed in a first branch 102 of the parallel circuit 101 and a second chip 120 in a second branch 103 of the parallel circuit 101 is arranged. The first branch 102 may be formed by a first conductor track. In the first branch 102, a first interruption point 104 is arranged. If the first chip 110 is identified as defective, the first chip 110 may be replaced by the second chip 120. Since the first branch 102 is interrupted at the first interruption point 104, which can be configured as a severing of a first conductor track. A voltage applied to the parallel circuit 101 is then applied only to the second chip 120. The second chip 120 may be arranged as defective in the second branch 103 before or after identifying the first chip 110. By interrupting the first branch 102 at the first interruption point 104, an electrical contacting of the first chip 110 is interrupted. 2 shows a circuit diagram 100 of a series circuit 105 of a first chip 110 and a second chip 120. The second chip 120 is bridged with a bridging branch 106. In the bridging branch 106, a first interruption point 104 is arranged. First, the first chip 110 is electrically contacted when a voltage is applied to the series circuit 105. Since the resistance of the bridging branch 106 is significantly lower than the resistance of the second chip 120, no or only a very small current flows through the second chip 120. If the bridging branch 106 is interrupted at the first interruption point 104, the current can only continue over flow the second chip 120. As a result, instead of the defective first chip 110, the second chip 120 can be put into operation.

Fig. 3 shows a circuit diagram 100 of a series circuit 105 egg nes first chip 110 and a second chip 120, which corresponds to the circuit diagram of Fig. 2, unless described below differences. A short-circuit branch 107 is arranged parallel to the first chip 110. In addition to the interruption of the bridging branch 106 at the first interrupter 104, the short-circuit branch 107 may be additionally short-circuited to bridge the first chip 110. Thereby, if a defect of the first chip 110 leads to an interruption of the electrical contact within the first chip 110, the second chip 120 can nevertheless be taken into operation. In the diagram of Fig. 2, this would not be possible.

The chips 110, 120 of FIGS. 1 to 3 may be LED chips emitting in an identical wavelength range. The chips 110, 120 may be a pixel or part of a pixel of a multi-pixel LED module. Should the first chip 110 fail, it may be replaced by the second chip 120. The interruption at the first point of interruption can be designed as cutting through a first printed conductor of a multiplying LED module.

Exemplary embodiments of the repair options shown in FIGS. 1 to 3 are shown below, the chips 110, 120 being light-emitting chips in one pixel of a multi-pixel LED module.

FIG. 4 shows a plan view of a first pixel 130. A first contact track 131 serves as an anode and is arranged on an upper side of a carrier 136 visible in FIG. 4. The carrier 136 can be designed as a printed circuit board. A second contact track 132 serves as the first cathode and is arranged within the carrier 136 or on an underside of the carrier 136 and is shown by dashed lines for this reason. Via a first via 161, the second contact path is connected to the top side of the carrier and from there via a first conductor track 141 to a first contact point 151. A second contact point 152 is connected to the first contact track 131 via a second conductor track 142. A first chip 110 is disposed between the first pad 151 and the second pad 152. As a result, the first chip 110 can be driven via the first contact track 131 and the second contact track 132. A third contact point 153 is connected to the first conductor track 141 via a third conductor track 143. A fourth contact point 154 is connected to the second conductor 142 via a fourth conductor 144. A second chip 120 is disposed between the third contact point 153 and the fourth contact point 154. As a result, the second chip 120 can likewise be driven via the first contact track 131 and the second contact track 132. The first chip 110 and the second chip 120 are connected in parallel.

If the first chip 110 is identified as being defective, the first interconnect 141 between the first contact point 151 and the third interconnect 143 may be interrupted so that the connection between the second contact strip 132 and the first chip 110 is interrupted. It can be provided that the second chip 120 is first placed on the third contact point 153 and the fourth contact point 154 after the first chip 110 has been identified as defective. Alternatively, the second chip 120 may have already been placed prior to this identification. The printed conductors 141, 142,

143, 144 and the contact points 151, 152, 153, 154 may be covered with an insulating layer. Then, before the placement of the second chip 120 and before the interruption of the first trace 141, the insulation layer is at least partially removed.

The first chip 110 and the second chip 120 can thereby emit white light or light of a specific color and thereby form a pixel 130 for a monochrome multi-pixel LED module. Several such pixels 130 can be arranged adjacent to each other, wherein the first contact track 131 and the second contact track 132 are each connected to the neigh disclosed pixels and the individual pixels 130 can be controlled via a known matrix drive

The first pixel 130 of FIG. 4 contains further, optional chips 171, 172, 181, 182. A third contact track 133 serves as the second cathode and is connected via a second via 162 and a fifth track 145 to a fifth contact point 155. Between the fifth contact point 155 and the second contact point 152, a third chip 171 is angeord net. The third contact track 133 is connected via a third via 163 and a sixth track 146 with a sixth contact point 156. Between the sixth contact point 156 and the fourth contact point 154, a fourth chip 172 is arranged. Thereby, the third chip 171 and the fourth chip 172 are connected in parallel. By interrupting the fifth interconnect 145, the third chip 171 may be replaced by the fourth chip 172 analogous to replacing the first chip 110 by the second chip 120. Further, a fourth contact path 134 serving as a third cathode is via a fourth via 164 and a seventh trace 147 connected to a seventh pad 157. Between the seventh Contact point 157 and the second contact point 152, a fifth chip 181 is arranged. The fourth contact track 134 is connected to an eighth contact point 158 via a fifth via 165 and an eighth conductor 148. Between the eighth contact point 158 and the fourth contact point 154, a sixth chip 182 is arranged. As a result, the fifth chip 181 and the sixth chip 182 are connected in parallel. By interrupting the seventh conductive line 147, the fifth chip 181 can be replaced by the sixth chip 182, analogous to the setting of the first chip 110 by the second chip 120.

The first chip 110 and the second chip 120 can emit red light here. The third chip 171 and the fourth chip 172 can emit green light. The fifth chip 181 and the sixth chip 182 can emit blue light. The pixel 130 can then be used in an RGB display.

Fig. 5 shows a plan view of the pixel 130 of Fig. 4, in which the first conductor 141, the second conductor 142, the fifth conductor 145 and the seventh conductor 147 are un interrupted. As a result, the first chip 110, the third chip 171 and the fifth chip 181 are no longer contacted.

Although the interruption of the second trace 142 is not absolutely necessary, but allows the reduction of unwanted capacitive effects.

Instead of the arrangement of the chips 110, 120, 171, 172, 181, 182 on the carrier 136, the chips may also be arranged in a component. 6 shows a plan view of a lower side of a component 190. The component 190 contains ent neither the first chip 110, the third chip 171 and the fifth chip 181 or the second chip 120, the fourth chip 172 and the sixth chip 182. The bottom has a first solder pad 191, a second solder pad 192, a third solder pad 193, and a fourth solder pad 194. The first chip 110 or the second chip 120 is disposed between the first solder pad 191 and the second solder pad 192. The third chip 171 and the fourth chip 172 are between the third solder pad 193 and the second solder pad 192 arranged. The fifth chip 181 and the sixth chip 182 is between tween the fourth solder pad 194 and the second solder pad 192 is arranged. This allows the member 190 to the first contact 151, the second contact point 152, the fifth contact point 155 and the seventh contact point 157 or on the third contact point 153, the fourth contact point 154, the sixth contact point 156 and the eighth contact Stel le 158 placed become. The interruption of the conductor tracks can be carried out analogously to FIGS. 4 and 5.

7 shows a plan view of a second pixel 130, in which a first chip 110 and a second chip 120 are not connected in parallel, but in series. The pixel 130, in turn, has a first contact track 131 arranged on a carrier 136, which serves as an anode. Further, a second contact track 132 is disposed on a lower side or within the Trä gers 136 and dashed lines Darge presents for this reason. A first contact point 151 is connected to the first contact track 131. Via a first via 161, the second contact track 132 is connected to a second contact point 152, a third contact point 153 and a fourth contact point 154. Between the first contact point 151 and the second contact point 152, the first chip 110 is arranged. Between the third contact point 153 and the fourth Kon contact point 154, the second chip is arranged. The first conductor track 141 thus forms a first bypass 221 with which the second chip 120 is short-circuited. If a voltage is applied between the first contact track 131 and the second contact track 132, the first chip 110 lights up. If the first chip 110 should be defective due to an internal short circuit, the first track 141 is severed in the region of the first bypass 221 so that now the second chip 120 can be put into operation.

The second pixel 130 of FIG. 7 includes further optional chips 171, 172, 181, 182. A fifth pad 155 is connected to the first contact track 131. A sixth contact point 156 and a seventh contact point 157 are connected to a ner third trace 143 and ver with a second via 162 connected. The second via 162 leads to a third contact track 133. Via a third via 163 and a third track 143, the third contact track 133 is connected to an eighth contact point 158. Between the fifth contact point 155 and the sixth contact point 156, a third chip 171 is angeord net. Between the seventh contact point 157 and the eighth contact point 158, a fourth chip is arranged. The second interconnect 142, the second via 162 and the third contact path 133 between the second via 162 and the third via 163 form a second bypass 222, with which the fourth chip 172 is short-circuited. By severing the second conductor track 142 in the second bypass 222, the fourth chip 172 can be put into operation. A ninth pad 211 is connected to the first contact track 131. A fourth contact track 134 is connected via a fourth via 164 and a fourth interconnect 144 to a tenth contact point 212, an eleventh contact point 213 and a twelfth contact point 214. A fifth chip 181 is disposed between the ninth pad 211 and the tenth pad 212, a sixth chip 182 is disposed between the eleventh pad 213 and the twelfth pad 214. The fourth conductor 144 forms a third bypass 223, with which the sixth chip 182 is short-circuited. By separating the fourth interconnect 144 in the third bypass 223, the sixth chip 182 can be put into operation.

Fig. 8 shows a plan view of an underside of a construction part 190, which may include the first chip 110, the third chip 171 and the fifth chip 181 or the second chip 120, the four th chip 172 and the sixth chip 182. The component has six solder pads 195, the clocking on the first Kon 151, the second contact point 152, the fifth Kon contact point 155, the sixth contact point 156, the ninth contact point 211 and the tenth contact point 212 or the third contact point 153, the fourth contact point 154, the seventh pad 157, the eighth pad 158, the eleventh pad 213, and the twelfth pad 214 may be applied. FIG. 9 shows a top view of the pixel 130 of FIG. 7 in which the first bypass 221, the second bypass 222 and the third bypass 223 have been severed. As a result, the second chip 120, the fourth chip 172 and the sixth chip 182 have been put into operation. The bypasses 221, 222, 223 can also be severed individually.

FIG. 10 shows a plan view of the pixel of FIG. 9, in which additionally a first bridging 231 has been applied between the first printed conductor 141 and the first contact track 131. The first bypass 231 closes the first chip 110 briefly. Further, a second bridging 232 has been applied between tween the first conductor 141 and the second conductor 142, which bridges the third chip 171. A third bypass 233 between the first contact track 131 and the fourth track 144 bridges the fifth chip 181. The bridges 231, 232, 233 can also be applied individually.

It can be provided to arrange all the chips 110, 120, 171, 172, 181, 182 in a component 190.

FIG. 11 shows a plan view of contact points 151, 152, 153, 154, 155, 156, 157 of a third pixel 130. A first contact track 131 is arranged on an upper side of a carrier 136. On an underside of the carrier 136 or inner half of the carrier 136, a second contact track 132 is angeord net. The second contact track 132 is connected via a first via 161 to a first interconnect 141 and via the first interconnect 141 to a first contact point 151 and a second contact point 152. The first conductor 141 forms egg nen first bypass 221 and closes the first contact point 151 with the second contact point 152 briefly. A member mounted on the first pad 151, the second pad 152, and the third pad 153 may include a first chip 110 between the second pad 152 and the third pad 153 and a second chip 120 between the first pad 151 and the second pad 152 included. The circuit of the chips 110, 120 is then ana log for interconnection of the chips 110, 120 of FIG. 7th

Optionally, but also shown in Fig. 11 are further contact points 154, 155, 156, 157, which can serve the contacting wei terer chips. A fourth contact point 154 is connected via a third interconnect 143 to a fourth contact point 154 and via a second via 162 with a third contact path 134. The third interconnect 143 forms a second bypass 222 between the fourth contact point 154 and the fifth contact point 155. A sixth contact point 156 is connected via a fourth interconnect 144 to a seventh contact point 157 and via a third via 163 to a fourth contact path 134. The fourth interconnect 144 forms a third bypass 223 between the six th contact point 156 and the seventh contact point 157 ,

A component placed on the contact points 151, 152, 153, 154, 155, 156, 157 can then each contain two identical chips in series, via the first contact point 151, the second contact point 152 and the third contact point 153 or the fourth contact point 154 , the fifth contact point 155 and the third contact point 153 or the sixth contact point 156, the seventh contact point 157 and the third contact point 153 are contacted.

Fig. 12 shows a plan view of an upper side of a construction part 190, which on the contact points 151, 152, 153, 154, 155, 156, 157 of FIG. 11 can be placed. The component 190 contains a first component contact point 241 and a second component contact point 242, between which a second chip 120 is arranged. A first chip 110 is arranged between the second component contact point 242 and a third component contact point 243. A first component via 251 ver binds the first component pad 241 with a Untersei te of the component 190 and can be connected to the first contact point 151. A second component via 252 connects the second component pad 242 to the underside of the component 190, and thus can communicate with the second pad 152 get connected. A third component via 253 connects the third component contact point 243 to the bottom of the construction part 190 and can thus ver with the third contact point 153 a related party. This results, when the component 190 is placed on the contact points 151, 152, 153, 154, 155, 156, 157 of FIG. 11, an analogous to FIG. 7 contacting the first chip 110 and the second chip 120th Über den first bypass 221 is then the second chip 120 bridges over.

The component 190 further optionally includes a fourth component contact point 244 and a fifth component contact point 245. A third chip 171 is between the fifth component contact point 245 and the third component contact point 243 angeord net. A fourth chip 172 is arranged between the fourth component contact point 244 and the fifth component contact point 245. Via a fourth component via 254, the fourth component contact point 244 is connected to the fourth contact point 154 when the component 190 contacts the contact points 151,

152, 153, 154, 155, 156, 157 of FIG. 11 is placed. Analogously, the fifth component pad 245 is connected via a fifth component via 255 to the fifth pad 155.

In addition, the component 190 comprises a sixth component contact point 246 and a seventh component contact point 247. A fifth chip 181 is disposed between the seventh component contact point 247 and the third component contact point 243. A sixth chip 182 is arranged between the sixth component contact point 246 and the seventh component contact point 247. Via a sixth component via 256, the sixth construction partial contact point 246 is connected to the sixth contact point 156, when the component 190 contacts the contact points 151, 152,

153, 154, 155, 156, 157 of FIG. 11 is placed. Analogously, the seventh component contact point 247 is connected via a seventh construction part via 257 to the seventh contact point 157.

13 shows a plan view of the contact points 151,

152, 153, 154, 155, 156, 157 of the third pixel 130, wherein the bypasses 221, 222, 223 have each been severed to the second chip 120, the fourth chip 172 and the sixth chip 182 to operate. Not all bypasses 221, 222, 223 need to be severed, a severing of the first bypass 221 is sufficient to put the second chip 120 into operation.

The second bypass 222 is guided via a fourth via 164 and a fifth via 165 and via a bypass track 224, wherein the bypass track 224 is not arranged on the upper side of the carrier 136, analogously to, for example, the second contact track 132.

Optionally, but also shown in Fig. 13 is a ers te bridging 231, which connects the first conductor 141 with the second conductor 142. As a result, the first chip 110 is bridged. A second bypass 232 connects the third track 143 with the first contact track 131. A third bridge 233 connects the fourth track 144 with the first contact track 131. Applying the third lock is possible because the second bypass 222 passes via the bypass track 224 below the first track 131 Surface of the carrier 136 is guided.

14 shows a plan view of contact points 151, 152, 153, 154, 155, 156, 157, 158 of a fourth pixel 130, which corresponds to the third pixel 130 of FIG. 11, unless differences are described below. The third contact point 153 is connected to the second conductor track with a fifth contact track 135 guided on the upper side of the carrier 136. An eighth contact point 158 is connected via a fifth interconnect 145 to the first contact path 131 verbun. The second bypass is performed analogously to FIG. 13 via a fourth via 164, a fifth via 165 and a bypass track 224.

15 shows a plan view of a component 190 which can be placed on the contact points 151, 152, 153, 154, 155, 156, 157 of the fourth pixel 130 of FIG. 14 and which corresponds to the component 190 of FIG. 12 unless the differences are described below. The third component contact parts 243 is connected only to the first chip 110, but not to the third chip 171 and the fifth chip 181. The third chip 171 and the fifth chip 181 are connected to an ei ner eighth component pad 248, which via an eighth component via 258 with the eighth contact point 158 can be connected. As a result, the first chip 110 can be referred to as the second chip 120 via the second contact path

132 and the fifth contact track 135 are operated with a different voltage than the further chips 171, 172, 181, 182, via the first contact track 131 and the third contact track

133 and the fourth contact track 134 can be controlled. If the first chip 110 and the second chip 120 emit red light blue or green light is emitted by the further chips 171, 172, 181, 182, this enables a simpler driving of the chips 110, 120, 171, 172, 181, 182.

16 shows the contact points 151, 152, 153, 154, 155,

156, 157, 158 of FIG. 14, wherein the bypasses 221, 222, 223 are severed analogous to FIG. 13. By severing the first bypass 221, the second chip 120 can be put into operation. By severing the second bypass 222, the fourth chip 172 can be put into operation.

By the transection of the third bypass 223, the sixth chip 182 can be put into operation. Optionally, but also shown in Fig. 16 are a first bridge 231 between the first conductor 141 and the second Lei terbahn 142 for bridging the first chip 110, a two te bridging 232 between the third conductor 143 and the first contact path 131 for bridging the third chip 171 and a third bypass 233 between the fourth interconnect 144 and the fifth interconnect 145 for bridging the fifth chip 181.

FIG. 17 shows a plan view of a section of a multi-pixel LED display 260. Four pixels 130 are arranged in a rectangle. In this case, the pixels 130 initially correspond to the pixels as described in FIG. 14, the component 190 of FIG. 15 being respectively connected to the contact points 151, 152, 153, 154, 155, 156, 157, 158 is attached. The contact tracks 131,

132, 133, 134, 135 are thereby continuously passed over adjacent pixels 130, wherein the first contact track 131 and the fifth contact track 135 are formed continuously in a first direction aneinan the adjacent pixels 130 and the second contact track 132, the third contact track 133 and the fourth contact track 134 is configured to be continuous for adjacent pixels 130 in a second direction.

In the pixel 130 bottom right, the first chip 110, the third chip 171 and the fifth chip 181 have been identified as defective. Subsequently, the interconnects forming the bypasses 221, 222, 223 were cut to operate the second chip 120, the fourth chip 172 and the sixth chip 182. Furthermore, the bypasses 231, 232, 233 were applied analogously to FIG. 16 in order to remove the defective chips 110,

171, 181 to bridge.

The separation of the bypasses 221, 222, 223 forming tracks can be done by laser ablation.

For this purpose, it is advantageous if the bypasses 221, 222, 223 have at one point a predetermined minimum distance to the neigh th conductor tracks, so that the material removed by laser ablation material does not lead to short circuits. This minimum distance can assume a predetermined value and be for example between ten and fifty, preferably between twenty and twenty-five microns.

The creation of the bridges 231, 232, 233 can be done by applying a conductive material, for example, via a local evaporation process. In this case, masks can be used to apply the conductive material only to certain areas.

Instead of the fourth pixel 130 of FIG. 14, the above-described exemplary embodiments of the pixels 130 may also be assembled analogously to a multipixel LED display 260. The contact points 151, 152, 153, 154, 155, 156, 157, 158, 211, 212, 213, 214 may be designed as solder pads, whereby a simple attachment of the chips 110, 120, 171, 172, 181, 182 and / or the device 190 with the chips 110, 120, 171, 172, 181, 182 is made possible. In addition, an insulating layer may be applied to the carrier 136 such that the contact points 151, 152, 153, 154, 155, 156, 157, 158, 211, 212, 213, 214 and the printed conductors 141, 142,

143, 144, 145, 146, 147, 148, if present in the pixel 130, are covered by the insulating material and only the chips 110, 120, 171, 172, 181, 182 and / or the components 190 protrude from the insulating material. The contact points 151, 152, 153, 154, 155, 156, 157, 158, 211, 212, 213, 214 and the

Tracks 141, 142, 143, 144, 145, 146, 147, 148, if present in pixel 130, may be referred to as by vapor deposition

and / or electroplating and / or printing on the support formed conductive regions.

Multipixel LED displays 260 may be constructed of tiles of one hundred to four hundred pixels. If tiles with sixteen pixels in a first direction and eighteen pixels in a second direction are used, a tile contains two hundred and eighty-eight pixels. For example, if the production of a pixel with a probability of one percent leads to a defective pixel, the binomial distribution results in only 75 percent of the tiles being produced without any defective pixels. By the described procedural ren for replacing a first chip of a multi-pixel LED module by a second chip can be generated at the same probability for a defective pixel over 99, 9 percent of the tiles without defective pixels. To achieve such a yield without the described method, the defect rate would have to be less than 3.5 pixels per million pixels produced. Consequently, the method described results in significant cost advantages in the production of multi-pixel LED modules.

Although the invention has been illustrated and described in detail by the preferred Ausfüh approximately examples, is the invention is not limited by the disclosed examples, and other variations can be deduced therefrom by those skilled in the art without departing from the scope of the invention.

LIST OF REFERENCE NUMBERS

100 circuit diagram

101 parallel connection

102 first branch

103 second branch

104 first point of interruption

105 series connection

106 Bridging branch

107 short circuit branch

110 first chip

120 second chip

130 pixels

131 first contact track

132 second contact track

133 third contact track

134 fourth contact track

136 carriers

141 first trace

142 second trace

143 third track

144 fourth track

145 fifth trace

146 sixth track

147 seventh track

148th eighth track

151 first contact point

152 second contact point

153 third contact point

154 fourth contact point

155 fifth contact point

156 sixth contact point

157 seventh contact point

158 eighth contact point 161 first Via

162 second via

163 third Via

164 fourth Via

165 fifth via

171 third chip

172 fourth chip

181 fifth chip

182 sixth chip

190 component

191 first solder pad

192 second solder pad

193 third solder pad

194 fourth solder pad

195 solder pad

211 ninth contact point

212 tenth contact point

213 eleventh contact point

214 twelfth contact point

221 first bypass

222 second bypass

223 third bypass

224 Bypass track

231 first bridge

232 second bypass

233 third bridging

241 first component contact point

242 second component contact point

243 third component contact point

244 fourth component contact point

245 fifth component contact point 246 sixth component contact point

247 seventh component contact point

248 eighth component contact point

251 first component via

252 second component via

253 third component via

254 fourth component via

255 fifth component via

256 sixth component via

257 seventh component via

258 eighth component via

260 multi-pixel LED display

Claims

PATENTAN'S REQUEST

A method of replacing a first chip (110) of a

Multi-pixel LED module (260) through a second chip

(120), wherein the first chip (110) is defective, with the following steps:

- identifying the first chip (110);

- severing a first trace (141) of the multi-pixel LED module (260);

wherein the first chip (110) and the second chip (120) are connected in series and wherein the first conductor (141) bridges the second chip (120).

2. The method of claim 1, wherein the multi-pixel LED module

(260) contact points (151, 152, 153, 154, 155, 156, 157, 158, 211, 212, 213, 214) for the second chip (120) BE REITES and the second chip (120) after the Identifi adorn the first chip (110) is mounted on the pads (151, 152, 153, 154, 155, 156, 157, 158, 211, 212, 213, 214) of the multi-pixel LED module (260).

3. The method according to claim 2, wherein the contact points (151,

152, 153, 154, 155, 156, 157, 158, 211, 212, 213, 214) are covered by an insulating layer and wherein before the attachment of the second chip (120), the insulation layer at least partially from the contact points (151, 152 , 153, 154, 155, 156, 157, 158, 211, 212, 213, 214).

4. The method of claim 1, wherein the second chip (120) is already on the multi-pixel LED module (260) before identifying the first fic of the first chip (110) is arranged.

5. The method according to any one of claims 1 to 4, wherein a first bypass (231) is created such that the first chip (110) is short-circuited.

6. The method of claim 5, wherein the first bridge (231) is created by applying an electrically conductive material.

7. The method according to any one of claims 1 to 6, wherein the

Cutting the first conductor (141) takes place by means of Laserab transmission.

8. The method according to any one of claims 1 to 7, wherein the

the first chip (141) is arranged in a first component (190) and the second chip (120) is arranged in a second component (190) and wherein the first component (190) contains a third chip (171), the second construction part (190) includes a fourth chip (172).

A multi-pixel LED module (260) comprising a carrier (136), a first chip (110), pads (151, 152, 153, 154, 155, 156, 157, 158, 211, 212, 213, 214 ) for a second chip (120) and a first conductor track (141), where the first conductor track (141) is designed in such a way that the first conductor track (141) can be severed at a predetermined location, the first chip (110) and the contact points (151, 152, 153, 154, 155,

156, 157, 158, 211, 212, 213, 214) are connected in series and wherein the first conductor track (141) of the bridging of the contact points (151, 152, 153, 154, 155, 156,

157, 158, 211, 212, 213, 214).

10. multi-pixel LED module (260) according to claim 9, wherein a

second chip (120) is connected to the contact points (151, 152, 153, 154, 155, 156, 157, 158, 211, 212, 213, 214).

11. Multi-pixel LED module (260) according to claim 9 or 10, wherein a first bridge (231) on the support (136) in such a way it can be applied that the first chip (110) is bridged by the first bridging (231).

The multi-pixel LED module (260) of any one of claims 9 to 11, wherein each pixel (130) comprises a first chip (110) and a first trace (141).

13. Multi-pixel LED module (260) according to one of claims 9 to 12, wherein the first chip (110) in a first component (190) is arranged and the second chip (120) in a second component (190) is arranged and wherein the first component (190) includes a third chip (171), the second component (190) including a fourth chip (172).