WO2019205328A1 - 发光二极管的倒装芯片及其制造方法和发光方法 - Google Patents

发光二极管的倒装芯片及其制造方法和发光方法 Download PDF

Info

Publication number
WO2019205328A1
WO2019205328A1 PCT/CN2018/097778 CN2018097778W WO2019205328A1 WO 2019205328 A1 WO2019205328 A1 WO 2019205328A1 CN 2018097778 W CN2018097778 W CN 2018097778W WO 2019205328 A1 WO2019205328 A1 WO 2019205328A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
type
current spreading
type layer
flip chip
Prior art date
Application number
PCT/CN2018/097778
Other languages
English (en)
French (fr)
Inventor
邬新根
刘英策
李俊贤
吴奇隆
Original Assignee
厦门乾照光电股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201820604683.5U external-priority patent/CN208797027U/zh
Priority claimed from CN201810382603.0A external-priority patent/CN110416380A/zh
Application filed by 厦门乾照光电股份有限公司 filed Critical 厦门乾照光电股份有限公司
Priority to US16/626,517 priority Critical patent/US11621380B2/en
Publication of WO2019205328A1 publication Critical patent/WO2019205328A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Definitions

  • the invention relates to an LED chip, in particular to a flip chip of a light emitting diode, a manufacturing method thereof and a light emitting method.
  • LEDs have low power consumption, small size and high reliability. In recent years, LEDs have been widely used in daily lighting, vehicle lighting, indication and display. Light-emitting diodes can be divided into light-emitting diodes of flip-chip structure and light-emitting diodes of flip-chip structure according to the manufacturing process of the chip structure, wherein the light-emitting diodes of the flip-chip structure have electrodeless light blocking, low thermal resistance and can withstand The characteristics of high current impact make flip-chip LEDs an important research direction for high-power LEDs.
  • the light-emitting surface of the flip-chip structure has a light-emitting surface on the substrate (for example, a sapphire surface), which determines the emission on the electrode side of the flip-chip structure of the light-emitting diode.
  • the fabrication of the surface becomes an important step in the illumination quality of the light-emitting diodes that affect the flip-chip structure.
  • metallic silver is a highly reflective metal material
  • the light-emitting diodes of the current popular flip chip structure in the market use high-reflection metallic silver as a silver mirror to achieve light reflection of light.
  • metal Silver is a kind of active metal.
  • the silver mirror formed by the metal silver on the electrode side of the flip-chip LED is prone to migration, and once the silver mirror has a bad migration phenomenon, It is bound to affect the light-emitting quality of the light-emitting diode. Therefore, it is necessary to design a diffusion-proof layer for placing the silver mirror to ensure the stability of the silver mirror, and the size of the anti-diffusion layer must be larger than the size of the silver mirror so that the anti-diffusion layer can be completely Cover the silver mirror.
  • the silver mirror can only be disposed on the surface of the P-type gallium nitride, and cannot be disposed at the interval between the N-type electrode and the PN, which limits the brightness of the LED of the flip-chip structure. Improvement.
  • An object of the present invention is to provide a flip chip of a light emitting diode, a method of fabricating the same, and a method of emitting light, wherein the brightness of the light emitting diode can be greatly improved.
  • An object of the present invention is to provide a flip chip of a light emitting diode, a method of fabricating the same, and a method of emitting light, wherein an area of a reflecting surface of the flip chip can be increased to facilitate the brightness of the light emitting diode.
  • An object of the present invention is to provide a flip chip of a light emitting diode, a method of manufacturing the same, and a method of emitting light, wherein a reflectance of a region of the P-type layer of the flip chip that is not covered by the reflective layer can be improved to facilitate The brightness of the light emitting diode is increased.
  • An object of the present invention is to provide a flip chip of a light emitting diode, a method of fabricating the same, and a method of emitting light, wherein the flip chip provides at least one distributed Bragg reflection unit, wherein the distributed Bragg reflection unit is formed in the P
  • the layer is formed to increase the reflectance of the region of the P-type layer that is not covered by the reflective layer, thereby facilitating the improvement of the brightness of the light emitting diode.
  • An object of the present invention is to provide a flip chip of a light emitting diode, a method of fabricating the same, and a method of emitting light, wherein the distributed Bragg reflection unit has an insulating function to isolate the P-type layer and the N-type layer to ensure the The reliability of flip chip.
  • An object of the present invention is to provide a flip-chip of a light emitting diode, a method of fabricating the same, and a method of emitting light, wherein the distributed Bragg reflection unit has an insulating function to isolate the P-type layer and the N-current spreading layer to ensure Describe the reliability of flip chip.
  • An object of the present invention is to provide a flip chip for a light emitting diode, a method of fabricating the same, and a method of emitting light, wherein the distributed Bragg reflector unit has an insulating function to isolate the N current spreading layer and the P current spreading layer to ensure The reliability of the flip chip.
  • the invention provides a flip-chip of a light emitting diode, comprising:
  • At least one reflective layer At least one reflective layer
  • At least one N-type electrode At least one N-type electrode
  • At least one P-type electrode At least one P-type electrode
  • At least one distributed Bragg reflection unit At least one distributed Bragg reflection unit
  • An epitaxial unit wherein the epitaxial unit comprises a substrate, an N-type layer, an active layer, and a P-type layer, the substrate, the N-type layer, the active layer, and the P-type
  • the layers are sequentially stacked, and the epitaxial unit has at least one N-type layer exposed portion, and the N-type layer exposed portion extends from the outer side surface of the P-type layer to the N-type layer via the active layer
  • the reflective layer is formed on the P-type layer, and the distributed Bragg reflection unit is integrally bonded to the N-type layer, the active layer, the P-type layer, and the reflective layer, wherein
  • the N-type electrode is electrically connected to the N-type layer
  • the P-type electrode is electrically connected to the P-type layer.
  • the flip chip further includes a diffusion prevention layer, wherein the diffusion prevention layer is formed on the P-type layer, and the diffusion prevention layer covers at least a portion of the reflective layer Wherein the distributed Bragg reflection unit is integrally bonded to the diffusion prevention layer.
  • the reflective layer is a silver reflective layer, and the anti-diffusion layer completely covers the reflective layer.
  • the diffusion prevention layer is electrically connected to the P-type layer
  • the P-type electrode is electrically connected to the P-type electrode by being electrically connected to the anti-diffusion layer.
  • the P-type layer is electrically connected to the P-type layer.
  • the flip chip further includes at least one N current spreading layer, wherein the N current spreading layer is held in the N-type layer of the epitaxial cell with the N current spreading layer a portion electrically connected to the N-type layer, wherein the N-type electrode is electrically connected to the N-type layer in a manner that the N-type electrode is electrically connected to the N-current spreading layer, wherein A distributed Bragg reflection unit is integrally coupled to the N current spreading layer.
  • the distributed Bragg reflection unit has at least one N-type layer channel and at least one P-type layer channel, wherein the N current spreading layer corresponds to the N-type layer channel, the N-type An electrode is formed on the distributed Bragg reflection unit, and the N-type electrode extends to the N current spreading layer via the N-type layer channel, wherein the anti-diffusion layer corresponds to the P-type layer channel, A P-type electrode is formed on the distributed Bragg reflection unit, and the P-type electrode extends to the diffusion prevention layer via the P-type layer channel.
  • the N current spreading layer extends from the N-type layer toward the P-type layer, and an outer side surface of the N current spreading layer has a height lower than an outer portion of the P-type layer The height of the side.
  • the flip chip further includes at least one N current spreading layer and at least one P current spreading layer, wherein the distributed Bragg reflecting unit has at least one N-type layer channel and at least one P-type layer a channel, wherein the N-type layer corresponds to the N-type layer channel, the N current spreading layer is formed in the distributed Bragg reflection unit, and the N current spreading layer extends to the ground via the N-type layer channel
  • An N-type layer wherein the N-current extension layer is electrically connected to the N-type layer, and the N-type electrode is electrically connected to the N-type electrode in such a manner that the N-type electrode is electrically connected to the N-current extension layer
  • An N-type layer wherein the P-type layer corresponds to the P-type layer channel, the P current spreading layer is formed in the distributed Bragg reflection unit, and the P current spreading layer is via the P-type layer channel Extending to the P-type layer, and the P current spreading layer is electrically connected to the P-type layer, the P-type electrode
  • the flip chip further includes at least one insulating layer, the insulating layer has at least one first channel and at least one second channel, wherein the insulating layer is formed on the N current spreading layer And the P current spreading layer, and the first channel corresponds to the N current spreading layer, and the second channel corresponds to the P current spreading layer, wherein the N-type electrode is via the insulating layer
  • the first channel is electrically connected to the N current spreading layer
  • the P-type electrode is electrically connected to the P current spreading layer via the second channel of the insulating layer.
  • the insulating layer is bonded to the distributed Bragg reflection unit to isolate the N current spreading layer and the P current spreading layer by the insulating layer.
  • the N-type electrode is formed on the insulating layer, and the N-type electrode extends to the N current spreading layer via the first channel of the insulating layer, wherein the P A type electrode is formed on the insulating layer, and the P-type electrode extends to the P current spreading layer via the second channel of the insulating layer.
  • the distributed Bragg reflection unit is formed by a stack of film layers of at least two refractive indices.
  • the film material of the distributed Bragg reflection unit is selected from the group consisting of silicon oxide, titanium oxide, magnesium fluoride, cerium oxide, aluminum oxide, and aluminum nitride.
  • the material of the diffusion prevention layer is selected from the group consisting of titanium tungsten, titanium, platinum, aluminum, nickel, and gold.
  • the material of the N current spreading layer is selected from the group consisting of chromium, aluminum, titanium, platinum, gold, and nickel.
  • the material of the P current spreading layer is selected from the group consisting of chromium, aluminum, titanium, platinum, gold, and nickel.
  • the electrode material of the N-type electrode and the P-type electrode is selected from the group consisting of chromium, aluminum, titanium, platinum, gold, nickel, and gold tin.
  • the N-type layer is an N-type gallium nitride layer
  • the P-type layer is a P-type gallium nitride layer
  • the material of the insulating layer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and aluminum nitride.
  • the structure of the reflective layer is a laminated structure of silver and titanium tungsten.
  • the silver layer of the reflective layer has a thickness ranging from 100 angstroms to 5000 angstroms, wherein the thickness of the titanium tungsten layer of the reflective layer ranges from 200 angstroms to 5000 angstroms.
  • the distributed Bragg reflection unit has a thickness dimension ranging from 0 ⁇ m to 7 ⁇ m.
  • the present invention further provides a method of fabricating a flip chip of a light emitting diode, wherein the manufacturing method comprises the following steps:
  • the method before the step (b), further includes the steps of: forming a diffusion barrier layer on the outer side surface of the P-type layer, wherein the diffusion prevention layer covers the reflective layer And the diffusion prevention layer is electrically connected to the P-type layer, so that in the step (c), the P-type electrode is electrically connected to the anti-diffusion layer by the P-type electrode Electrically connected to the P-type layer.
  • the method before the step (b), further includes the steps of: forming an N current spreading layer on the N-type layer, wherein the N current spreading layer is electrically connected to the N-type layer
  • the N-type electrode is electrically connected to the N-type layer in such a manner that the N-type electrode is electrically connected to the N current spreading layer.
  • the distributed Bragg reflection unit in the step (b), is integrally coupled to the P-type layer, the diffusion prevention layer, and the N current spreading layer.
  • the distributed Bragg reflection unit covers an area of the outer side of the P-type layer that is not covered by the reflective layer, wherein the distributed Bragg reflection unit has at least one N corresponding to the N current spreading layer a type layer channel and at least one P type layer channel corresponding to the anti-diffusion layer, the N-type electrode being electrically connected to the N current spreading layer via the N-type layer channel, the P-type electrode via the The p-type layer channel is electrically connected to the anti-diffusion layer.
  • the N-type electrode is formed on the distributed Bragg reflection unit such that the N-type electrode extends to the N current expansion layer via the N-type layer channel Forming the P-type electrode to the distributed Bragg reflection unit such that the P-type electrode extends to the anti-diffusion layer via the P-type layer channel.
  • the manner in which the distributed Bragg reflection unit is integrally formed on the P-type layer, the diffusion prevention layer, and the N current expansion layer is made
  • the distributed Bragg reflection unit covers an area of the outer side of the P-type layer that is not covered by the reflective layer, wherein the distributed Bragg reflection unit has at least one N-type corresponding to the N-type layer a layer channel and at least one P-type layer channel corresponding to the P-type layer, the N-type electrode being electrically connected to the N-type layer via the N-type layer channel, the P-type electrode via the P-type A layer channel is electrically connected to the P-type layer.
  • the method further comprises the steps of:
  • the above method further comprising the steps of forming an insulating layer on the N current spreading layer, the P current spreading layer, and the distributed Bragg reflecting unit, wherein the insulating layer has Corresponding to at least one first channel of the N current spreading layer and at least one second channel corresponding to the P current spreading layer, the N-type electrode is electrically connected to the N current extension via the first channel a layer, the P-type electrode being electrically connected to the P current spreading layer via the second channel.
  • the N-type electrode is formed on the insulating layer such that the N-type electrode extends to the N current spreading layer via the first channel to form the A P-type electrode is on the insulating layer such that the P-type electrode extends to the P current spreading layer via the second channel.
  • the present invention further provides a method of emitting a flip-chip of a light emitting diode, wherein the method of emitting light comprises the following steps:
  • the reflective layer covers a portion of an outer side of the P-type layer
  • the distributed Bragg reflection unit covers another partial region of an outer side of the P-type layer, thereby
  • both the reflective layer and the distributed Bragg reflection unit are capable of reflecting light generated by the active layer and radiated toward the P-type layer.
  • the distributed Bragg reflection unit is formed by a stack of film layers of at least two refractive indices.
  • the film material of the distributed Bragg reflection unit is selected from the group consisting of silicon oxide, titanium oxide, magnesium fluoride, cerium oxide, aluminum oxide, and aluminum nitride.
  • the distributed Bragg reflection unit has a thickness dimension ranging from 0 ⁇ m to 7 ⁇ m.
  • 1A is a cross-sectional view showing one of manufacturing processes of a flip-chip of an LED according to a preferred embodiment of the present invention.
  • 1B is a top plan view showing one of the manufacturing processes of the flip chip according to the above preferred embodiment of the present invention.
  • 2A is a cross-sectional view showing the second manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • 2B is a top plan view showing the second manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • 3A is a cross-sectional view showing the third manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • Fig. 3B is a top plan view showing the third manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • 4A is a cross-sectional view showing the fourth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • 4B is a top plan view showing the fourth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • Figure 5A is a cross-sectional view showing the fifth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • FIG. 5B is a top plan view showing the fifth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • Fig. 6A is a cross-sectional view showing the sixth manufacturing process of the flip chip according to the above preferred embodiment of the present invention, which also shows a cross-sectional view of the flip chip.
  • 6B is a top plan view showing a sixth manufacturing process of the flip chip according to the above preferred embodiment of the present invention, which simultaneously shows a top view of the flip chip.
  • FIG. 7A is a cross-sectional view showing one of manufacturing processes of a flip-chip of a light emitting diode according to another preferred embodiment of the present invention.
  • FIG. 7B is a top plan view showing one of the manufacturing processes of the flip chip according to the above preferred embodiment of the present invention.
  • Figure 8A is a cross-sectional view showing the second manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • FIG. 8B is a top plan view showing the second manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • Figure 9A is a cross-sectional view showing the third manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • 9B is a top plan view showing the third manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • Figure 10A is a cross-sectional view showing the fourth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • FIG. 10B is a top plan view showing the fourth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • Figure 11A is a cross-sectional view showing the fifth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • Figure 11B is a top plan view showing the fifth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • Figure 12A is a cross-sectional view showing the sixth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • Figure 12B is a top plan view showing the sixth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • Figure 13A is a cross-sectional view showing the seventh manufacturing process of the flip chip according to the above preferred embodiment of the present invention, which simultaneously shows a cross-sectional view of the flip chip.
  • Figure 13B is a top plan view showing the seventh manufacturing process of the flip chip according to the above preferred embodiment of the present invention, which simultaneously shows the top view of the flip chip.
  • the term “a” is understood to mean “at least one” or “one or more”, that is, in one embodiment, the number of one element may be one, and in other embodiments, the element The number can be multiple, and the term “a” cannot be construed as limiting the quantity.
  • FIG. 1A to FIG. 6B a flip-chip of a light emitting diode, a method of fabricating the same, and a method of illuminating according to a preferred embodiment of the present invention are disclosed and illustrated in the following description, wherein In the following description, the flip chip of the light emitting diode is simply referred to as a flip chip, but those skilled in the art should understand that the flip chip of the light emitting diode is simply referred to as the flip chip is only In order to make the description of the present invention more concise and easy to understand, it should not be construed as limiting the scope and scope of the invention.
  • the flip chip includes an epitaxial unit 10, at least one reflective layer 20, at least one anti-diffusion layer 30, at least one N current spreading layer 40, at least one distributed Bragg reflection unit 50, and at least one N-type electrode. 60 and at least one P-type electrode 70.
  • the epitaxial unit 10 is first provided for subsequently forming the reflective layer 20 on the epitaxial unit 10, and the anti-diffusion Layer 30, the N current spreading layer 40 and the distributed Bragg reflection unit 50.
  • the epitaxial unit 10 includes a substrate 11, an N-type layer (N-type conductive layer) 12, an active layer 13, and a P-type layer (P-type conductive layer) 14, wherein the substrate 11.
  • the N-type layer 12, the active layer 13, and the P-type layer 14 are sequentially stacked so that the N-type layer 12 is held on the substrate 11 and the active layer Between 13, the active layer 13 is held between the N-type layer 12 and the P-type layer 14.
  • the active layer 13 is held between the N-type layer 12 and the P-type layer 14, wherein when the N-type layer 12 and the P-type layer 14 are applied with an operating voltage, current Light can be generated in the active layer 13 to be combined, and light generated by the active layer 13 can be radiated to the outside via the substrate 11.
  • the light generated by the active layer 13 is also radiated toward the P-type layer 14, and the reflective layer 20 of the present invention is capable of reflecting light radiated toward the P-type layer 14, the distributed
  • the Bragg reflection unit 50 can further reflect the light radiated toward the P-type layer 14, and the flip chip of the present invention can increase the distributed Bragg reflection unit 50 by providing the distributed Bragg reflection unit 50.
  • the substrate 11 of the epitaxial unit 10 is a transparent substrate to allow light generated by the active layer 13 to be radiated to the outside via the substrate 11.
  • the substrate 11 can be, but is not limited to, a sapphire substrate.
  • the N-type layer 12 of the epitaxial unit 10 may be, but not limited to, an N-type gallium nitride layer.
  • the P-type layer 14 of the epitaxial unit 10 may be, but not limited to, a P-type gallium nitride layer.
  • the epitaxial cell 10 has at least one N-type layer exposed portion 15 wherein the N-type layer exposed portion 15 passes from the outer side surface 141 of the P-type layer 14 via the active layer 13 extends to the N-type layer 12 such that at least a portion of the area of the N-type layer 12 is exposed. That is, the N-type layer 12 and the P-type layer 14 have exposed faces on the same side of the epitaxial unit 10 for subsequent connection to the N-type electrode 60 and the P, respectively.
  • Type electrode 70
  • the N-type layer 12 forms a part of the N-type layer exposed portion 15, that is, the thickness dimension of the N-type layer 12 in the region corresponding to the N-type layer exposed portion 15 is smaller than the N-type
  • the layer 12 has a thickness dimension corresponding to a region of the active layer 13. That is, the N-type layer exposed portion 15 extends from the outer side surface 141 of the P-type layer 14 to the middle portion of the N-type layer 12 via the active layer 13.
  • the manner in which the N-type layer exposed portion 15 is formed on the epitaxial unit 10 is not limited in the flip chip of the present invention.
  • the N-type layer exposed portion 15 may be formed on the epitaxial unit 10 by an etching process.
  • the epitaxial cell 10 is first photolithographically coated with a positive photoresist to expose the region of the epitaxial cell 10 that needs to be etched.
  • the thickness of the photoresist is set to be 3 ⁇ m to 5 ⁇ m (including 3 ⁇ m and 5 ⁇ m).
  • the epitaxial unit 10 can be baked after photolithography of the epitaxial unit 10 using a positive photoresist. Then, the region of the epitaxial cell 10 to be etched is subjected to dry etching, for example, the need for the epitaxial cell 10 by using, but not limited to, an Inductive Coupled Plasma Emission Spectrometer (ICP) The etched region is dry etched.
  • the gas used in the dry etching of the epitaxial unit 10 may be chlorine (Cl 2 ), boron trichloride (BCl 3 ), or argon (Ar).
  • the etching depth of the epitaxial cell 10 for dry etching may be 0.9 ⁇ m - 2 ⁇ m (including 0.9 ⁇ m and 2 ⁇ m) to obtain the outer side surface 141 from the P-type layer 14 extending through the active layer 13 to the The N-type layer exposed portion 15 of the N-type layer 12.
  • the etching is performed on the epitaxial unit 10, and the epitaxial unit 10 is formed from the outer side surface 141 of the P-type layer 14 via the active After the layer 13 extends to the N-type layer exposed portion 15 of the N-type layer 12, the residual photoresist of the surface of the epitaxial unit 10 is removed to obtain the epitaxy shown in FIGS. 1A and 1B. Unit 10.
  • the epitaxial unit 10 has the outer side surface 141 from the P-type layer 14. Extending through the active layer 13 to the N-type layer exposed portion 15 of the N-type layer 12, in the process of manufacturing the flip chip, it is not necessary to re-form the N in the epitaxial unit 10 Type layer bare portion 15.
  • the types of the plurality of N-type layer exposed portions 15 of the epitaxial unit 10 may be different, for example, in the preferred example of the flip-chip shown in FIG. 1B, the epitaxy The unit 10 includes two types of the N-type layer exposed portion 15 , wherein one type of the N-type layer exposed portion 15 has a circular cross section from the P-type layer 14 through the active region 13 Extending to the N-type layer 12, wherein another type of the N-type layer exposed portion 15 has a pad exposed portion and an extended strip exposed portion extending from the exposed portion of the pad, the pad being exposed The portion and the extension strip exposed portion extend from the P-type layer 14 through the active region 13 to the N-type layer 12.
  • the reflective layer 20 is formed on the outer side surface 141 of the P-type layer 14 of the epitaxial unit 10.
  • the reflective layer 20 is a silver reflective layer to increase the reflectivity of the reflective layer 20 to ensure the brightness of the light emitting diode. Specifically, first, a region where the reflective layer 20 needs to be formed is determined at the P-type layer 14 of the epitaxial unit 10, and then the reflective layer 20 is formed in the region such that the reflective layer 20 is disposed at The outer side surface 141 of the P-type layer 14.
  • the reflective layer 20 may be formed in the region by deposition to make the reflective layer 20 is disposed on the outer side surface 141 of the P-type layer 14.
  • a pattern of a reflective layer to be deposited may be photolithographically deposited on the P-type layer 14 of the epitaxial unit 10 using a negative glue, and then a reflective layer may be formed by evaporation or sputtering.
  • the pattern deposits the reflective layer 20, and at this time, the reflective layer 20 is formed on the outer side surface 141 of the P-type layer 14 of the epitaxial unit 10.
  • a negative glue may be used to lithographically pattern the Mirror structure to be deposited on the P-type layer 14 of the epitaxial cell 10, and then use steaming.
  • a Mirror layer is deposited on the outer side surface 141 of the P-type layer 14 of the epitaxial cell 10 by plating or sputter coating. That is, in a specific example of the flip chip of the present invention, the reflective layer 20 formed on the outer side surface 141 of the P-type layer 14 of the epitaxial unit 10 may be formed in The Mirror layer of the outer side surface 141 of the P-type layer 14 of the epitaxial unit 10.
  • the reflective layer 20 is a stacked structure of silver (Ag) and titanium tungsten (TiW), wherein the thickness of the silver (Ag) is 100 angstroms to 5000 angstroms (including 100 angstroms and 5000 angstroms), and titanium tungsten (TiW)
  • the thickness dimension ranges from 200 angstroms to 5,000 angstroms (including 200 angstroms and 5000 angstroms).
  • a pattern of a reflective layer to be deposited is photolithographically deposited on the P-type layer 14 of the epitaxial cell 10 using a negative glue, and a pattern of the reflective layer is photolithographically deposited using an evaporation or sputter coating process
  • a flip chip semi-finished product 100 can be further processed.
  • the excess metal layer is first stripped off, and then the photoresist remaining on the surface of the flip chip blank 100 is removed.
  • the manner in which the excess metal layer of the flip chip blank 100 is peeled off is not limited.
  • the surface of the flip chip semi-finished product 100 may be peeled off by a blue film process. Photoresist.
  • the anti-diffusion layer 30 is formed on the outer side surface 141 of the P-type layer 14 of the epitaxial unit 10, and the anti-diffusion layer 30 is electrically connected to the P-type layer. 14.
  • the anti-diffusion layer 30 covers the reflective layer 20 to prevent the reflective layer 20 from exhibiting a poor migration phenomenon.
  • the diffusion prevention layer 30 completely covers the reflective layer 20. That is, the size of the anti-diffusion layer 30 is larger than the size of the reflective layer 20 to prevent any part of the reflective layer 20 from being exposed by the anti-diffusion layer 30, thereby preventing the reflective layer 20 from being exposed.
  • the phenomenon of migration is unfavorable to ensure the reliability and stability of the flip chip.
  • a region where the diffusion prevention layer 20 needs to be formed is determined in the P-type layer 14 of the epitaxial unit 10, and then the diffusion prevention layer 30 is formed in the region, and the diffusion prevention layer 30 is secured.
  • the reflective layer 20 is completely covered.
  • the anti-diffusion layer 30 may be formed in the region by deposition, and the The diffusion prevention layer 30 completely covers the reflective layer 20.
  • a pattern of the anti-diffusion layer to be deposited may be photolithographically deposited on the P-type layer 14 of the epitaxial unit 10 using a negative glue, and then etched by evaporation or sputtering.
  • a pattern of the diffusion layer deposits the diffusion prevention layer 30.
  • the diffusion prevention layer 30 is formed on the outer side surface 141 of the P-type layer 14 of the epitaxial unit 10, and the diffusion prevention layer 30
  • the reflective layer 20 is completely covered.
  • a Barrier layer to be deposited may be photolithographically deposited on the outer side surface 141 of the P-type layer 14 of the epitaxial unit 10 using a negative glue.
  • the pattern is then deposited on the outer side 141 of the p-type layer 14 of the epitaxial cell 10 by evaporation or sputter coating to completely cover a barrier layer of the reflective layer 20. That is, in a specific example of the flip chip of the present invention, the outer side surface 141 of the P-type layer 14 of the epitaxial unit 10 is formed to completely cover the reflective layer 20
  • the anti-diffusion layer 30 may be the Barrier layer formed on the outer side surface 141 of the P-type layer 14 of the epitaxial unit 10 for completely covering the reflective layer 20.
  • the diffusion prevention layer 30 is a laminated structure, wherein the material forming the diffusion prevention layer 30 is selected from the group consisting of titanium tungsten (TiW), titanium (Ti), platinum (Pt), aluminum (Al), and nickel (Ni). ), a group of materials consisting of gold (Au).
  • the material of the diffusion prevention layer 30 may be selected from the group consisting of titanium tungsten (TiW), titanium (Ti), platinum (Pt), aluminum (Al), nickel (Ni), and gold (Au).
  • Two or more materials selected from the group consisting of titanium tungsten (TiW), titanium (Ti), platinum (Pt), aluminum (Al), nickel (Ni), and gold (Au) may also be selected.
  • the flip chip semi-finished product 100 can be further processed.
  • the excess metal layer is first stripped off, and then the photoresist remaining on the surface of the flip chip blank 100 is removed.
  • the manner in which the excess metal layer of the flip chip blank 100 is peeled off is not limited.
  • the surface of the flip chip semi-finished product 100 may be peeled off by a blue film process. Photoresist.
  • the N-type layer 12 of the epitaxial unit 10 forms the N current spreading layer 40 held inside the N-type layer exposed portion 15. That is, the N current spreading layer 40 extends from the N-type layer 12 toward the P-type layer 14 inside the N-type layer exposed portion 15, and the N current spreading layer 40 is electrically connected to The N-type layer 12.
  • the outer side surface 41 of the N current spreading layer 40 is lower than the outer side surface 141 of the P type layer 14. More preferably, the outer side surface 41 of the N current spreading layer 40 is lower than the contact surface of the active layer 13 and the P type layer 14.
  • the material of the N current spreading layer 40 is not limited in the flip chip of the present invention.
  • the N current spreading layer 40 may be, but not limited to, an N current spreading metal layer.
  • a pattern of the N current spreading layer to be deposited may be photolithographically deposited on the N-type layer 12 of the epitaxial unit 10 using a negative glue, and then photolithographically deposited using evaporation or sputter coating.
  • a pattern of the N current spreading layer deposits the N current spreading layer 40, wherein a peripheral wall of the N current spreading layer 40 and the active layer 13 have a safe distance, and a peripheral wall of the N current spreading layer 40 A safety distance between the P-type layers 14 is avoided to prevent the N current spreading layer 40 from contacting the active layer 13 and to prevent the N current spreading layer 40 from contacting the P-type layer 14.
  • a negative glue may be used to lithographically pattern the N current layer to be deposited on the N-type layer 12 of the epitaxial cell 10, and then The N current spreading layer 40 held by the N-type layer exposed portion 15 is deposited on the N-type layer 12 by vapor deposition or sputter coating.
  • the structure of the N current spreading layer 40 is a chromium (Cr), aluminum (Al), titanium (Ti) platinum (Pt) gold (Au), nickel (Ni) electrode structure.
  • the material forming the N current spreading layer 40 is selected from the group consisting of chromium (Cr), aluminum (Al), titanium (Ti) platinum (Pt) gold (Au), and nickel (Ni).
  • the material of the N current spreading layer 40 may be selected from one of chromium (Cr), aluminum (Al), titanium (Ti) platinum (Pt) gold (Au), and nickel (Ni).
  • Two or more kinds of materials selected from the group consisting of chromium (Cr), aluminum (Al), titanium (Ti) platinum (Pt) gold (Au), and nickel (Ni) are selected.
  • the flip chip semifinished product 100 can be further processed. For example, the excess metal layer is first stripped off, and then the photoresist remaining on the surface of the flip chip blank 100 is removed.
  • the manner in which the excess metal layer of the flip chip blank 100 is peeled off is not limited.
  • the surface of the flip chip semi-finished product 100 may be peeled off by a blue film process. Photoresist.
  • the distributed Bragg Reflector (DBR) 50 is formed on the surface of the flip chip blank 100, wherein the distributed Bragg reflection unit 50 integrally combines the N The pattern layer 12, the active layer 13, the P-type layer 14, the anti-diffusion layer 30, and the N current spreading layer 40. That is, the distributed Bragg reflection unit 50 can fill the N-type layer exposed portion 15. It is worth mentioning that in other possible examples of the flip chip of the present invention, the distributed Bragg reflection unit 50 may also integrally combine only the N-type layer 12, the active layer 13, The diffusion prevention layer 30 and the N current spreading layer 40.
  • the reflective layer 20 formed on the outer side surface 141 of the P-type layer 14 cannot cover the entire area of the outer side surface 141 of the P-type layer 14, this makes the P At least a portion of the outer side surface 141 of the type layer 14 is incapable of reflecting light generated by the active layer 13.
  • a region of the P-type layer 14 not covered by the reflective layer 20 can be further covered by the distributed Bragg reflection unit 50 to increase the formation of the reflective layer 20.
  • the area of the reflecting surface and the reflecting surface formed by the distributed Bragg reflection unit 50 can enhance the reflectivity of the flip chip, which is very important for greatly increasing the overall brightness of the LED.
  • the distributed Bragg reflection unit 50 has at least one N-type layer channel 51 and at least one P-type layer channel 52, wherein the N-type layer channel 51 corresponds to at least a portion of the N-current expansion layer 40, the P The profile channel 52 corresponds to at least a portion of the region of the diffusion barrier layer 30.
  • the N-type electrode 60 formed on the outer side surface 53 of the distributed Bragg reflection unit 50 can be electrically connected to the N current via the N-type layer channel 51 of the distributed Bragg reflection unit 50.
  • the enhancement layer 40 correspondingly, the P-type electrode 70 formed on the outer side surface 53 of the distributed Bragg reflection unit 50 can be electrically charged via the P-type layer channel 52 of the distributed Bragg reflection unit 50. Connected to the diffusion prevention layer 30.
  • the distributed Bragg reflection unit 50 may be formed on the surface of the flip chip blank 100 using an evaporation method to cause the distributed Bragg reflection unit
  • the N-type layer 12, the active layer 13, the P-type layer 14, the diffusion prevention layer 30, and the N current spreading layer 40 can be integrally bonded.
  • the distributed Bragg reflection unit 50 uses a stacked structure of silicon oxide, titanium oxide, magnesium fluoride, cerium oxide, aluminum oxide, aluminum nitride to improve the reflectance of the distributed Bragg reflection unit 50, thereby It is beneficial to increase the overall brightness of the light emitting diode.
  • the distributed Bragg reflection unit 50 is formed of a film layer stack of at least two refractive indices.
  • the material of the film layer of the distributed Bragg reflection unit 50 is selected from the group consisting of silicon oxide, titanium oxide, magnesium fluoride, cerium oxide, aluminum oxide, and aluminum nitride.
  • different pairs of reflective layers can be designed for different wavelengths.
  • the reflective layer pair of the distributed Bragg reflector unit 50 is between 20 pairs and 50 pairs (including 20 pairs and 50 pairs).
  • the distributed Bragg reflection unit 50 When the N-type layer 12, the active layer 13, the P-type layer 14, the anti-diffusion layer 30, and the N-current expansion layer 40 are integrally formed on the surface of the flip-chip semi-finished product 100 After the distributed Bragg reflection unit 50, the distributed Bragg reflection unit 50 is subjected to photolithography and etching processes to form the N-type layer channel 51 and the P-type of the distributed Bragg reflection unit 50.
  • a layer channel 52 wherein the N-type layer channel 51 extends to the N current spreading layer 40 to expose at least a portion of the N current spreading layer 40, and correspondingly, the P-type layer channel 52 extends to The diffusion prevention layer 30 is described to expose at least a portion of the area of the diffusion prevention layer 30.
  • the distributed Bragg reflection unit 50 is first photolithographically coated with a positive photoresist to cause the distributed Bragg reflection unit 50 The area that needs to be etched is bare. The distributed Bragg reflection unit 50 is then etched using an ICP machine to form the N-type layer channel 51 and the P-type layer channel 52 in the distributed Bragg reflection unit 50.
  • the N-type electrode 60 and the P-type electrode 70 are respectively formed in different regions of the outer side surface 53 of the distributed Bragg reflection unit 50, wherein the N-type electrode 60 is via the N-type electrode 60
  • the N-type layer channel 51 of the distributed Bragg reflection unit 50 extends to and is electrically connected to the N current spreading layer 40, and correspondingly, the P-type electrode 70 is via the distributed Bragg reflection unit 50
  • the P-type layer channel 52 extends to and is electrically connected to the anti-diffusion layer 30.
  • the N may be formed by performing negative lithography and lift-off on the outer side surface 53 of the distributed Bragg reflection unit 50.
  • the type electrode 60 and the P-type electrode 70 More specifically, a pattern of electrodes to be deposited may be lithographically patterned on the outer side surface 53 of the distributed Bragg reflection unit 50 using a negative glue, and then the electrode is etched using evaporation or sputter coating. The pattern deposits the N-type electrode 60 and the P-type electrode 70, wherein the N-type electrode 60 extends to and is electrically connected to the N-type layer via 51 of the distributed Bragg reflection unit 50.
  • the N current spreading layer 40 correspondingly, the P-type electrode 70 extends to and is electrically connected to the anti-diffusion layer 30 via the P-type layer channel 52 of the distributed Bragg reflection unit 50.
  • a negative glue is used on the outer side surface 53 of the distributed Bragg reflection unit 50, a pattern of an electrode to be deposited is lithographically patterned, and a pattern of a lithographic electrode is deposited using a process of evaporation or sputter coating.
  • the flip-chip semi-finished product 100 can be further processed to obtain the flip-chip. For example, the excess metal layer is first stripped off, and then the photoresist remaining on the surface of the flip chip blank 100 is removed.
  • the manner in which the excess metal layer of the flip chip blank 100 is peeled off is not limited.
  • the surface of the flip chip semi-finished product 100 may be peeled off by a blue film process. A photoresist is used to obtain the flip chip.
  • the structure of the N-type electrode 60 and the P-type electrode 70 is chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), gold (Au), nickel (Ni), gold. Tin (AuSn) electrode structure. That is, the material of the electrode structure of the N-type electrode 60 and the P-type electrode 70 is selected from the group consisting of chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), gold (Au), A material group consisting of tin (Sn), nickel (Ni), and gold tin (AuSn).
  • the material of the electrode structure of the N-type electrode 60 and the P-type electrode 70 may be selected from chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), gold (Au), and tin. (Sn), nickel (Ni), gold tin (AuSn), a material may also be selected from chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), gold (Au), tin ( Two or more materials of Sn), nickel (Ni), and gold tin (AuSn).
  • the thickness dimension of the N-type electrode 60 and the thickness dimension of the P-type electrode 70 range from 0 ⁇ m to 7 ⁇ m (including 7 ⁇ m).
  • FIG. 6A and FIG. 6B illustrate a specific structure of the flip chip according to a preferred embodiment of the present invention, wherein the flip chip includes the epitaxial unit 10 and the reflective layer 20
  • the substrate 11, the N-type layer 12, the active layer 13, and the P-type layer 14 of the epitaxial unit 10 are sequentially stacked, and the N-type layer of the epitaxial unit 10 is exposed
  • the portion 15 extends from the outer side surface 141 of the P-type layer 14 to the N-type layer 12 via the active layer 13 such that at least a portion of the region of the N-type layer 12 is exposed.
  • the reflective layer 20 is formed on the outer side surface 141 of the P-type layer 14 of the epitaxial unit 10, and the anti-diffusion layer 30 is formed on the outer side of the P-type layer 14 of the epitaxial unit 10.
  • the side surface 141 and the anti-diffusion layer 30 completely covers the reflective layer 20.
  • the N current spreading layer 40 is held at the N-type layer exposed portion 15 of the epitaxial unit 10, and the N current spreading layer 40 is electrically connected to the N-type layer 12 of the epitaxial unit 10.
  • the distributed Bragg reflection unit 50 integrally combines the N-type layer 12, the active layer 13, the P-type layer 14, the anti-diffusion layer 30, and the N current spreading layer 40, and
  • the N-type layer channel 51 of the distributed Bragg reflection unit 50 extends to the N current spreading layer 40 such that a portion of the N current spreading layer 40 is exposed, and the distributed Bragg reflection unit 50
  • the P-type layer channel 52 extends to the anti-diffusion layer 30 such that a portion of the anti-diffusion layer 30 is exposed.
  • the N-type electrode 60 is formed on the outer side surface 53 of the distributed Bragg reflection unit 50, and the N-type electrode 60 extends to and through the N-type layer channel 51 of the distributed Bragg reflection unit 50. It is electrically connected to the N current spreading layer 40.
  • the P-type electrode 70 is formed on the outer side surface 53 of the distributed Bragg reflection unit 50, and the P-type electrode 70 extends to the sum via the P-type layer channel 52 of the distributed Bragg reflection unit 50. It is electrically connected to the diffusion prevention layer 30.
  • the active layer 13 of the epitaxial unit 10 is capable of generating light and radiating to the periphery, wherein the active layer 13 generates
  • the light radiated toward the substrate 11 of the epitaxial unit 10 can be directly radiated to the outside via the substrate 11, and the light generated by the active layer 13 in the direction of the reflective layer 20 can be irradiated
  • the reflective layer 20 is reflected, it is radiated to the outside via the substrate 11, and at the same time, the light generated by the active layer 13 in the direction of the distributed Bragg reflection unit 50 can be used by the distributed Bragg reflection unit 50.
  • the substrate 11 is radiated to the outside. In this way, the reflectivity of the flip chip can be greatly improved, thereby facilitating further improvement of the overall brightness of the LED, which is prior art.
  • the flip chip is unexpected.
  • the substrate 11 of the flip chip shown in FIGS. 1A to 6B, the N-type layer 12, the active layer 13, the P-type layer 14, and the The thicknesses of the reflective layer 20, the anti-diffusion layer 30, the N current spreading layer 40, the distributed Bragg reflection layer 50, the N-type electrode 60, and the P-type electrode 70 are merely examples, and The substrate 11, the N-type layer 12, the active layer 13, the P-type layer 14, the reflective layer 20, the anti-diffusion layer 30, the N-current expansion layer 40, The true thickness of the distributed Bragg reflector layer 50, the N-type electrode 60, and the P-type electrode 70.
  • the true ratio between the distributed Bragg reflector layer 50, the N-type electrode 60, and the P-type electrode 70 is also not as shown in the drawings.
  • the ratio of the size of the N-type electrode 60 and the P-type electrode 70 to the other layers of the flip chip is also not limited to that shown in FIGS. 1A to 6B.
  • the flip chip includes an epitaxial unit 10A, at least one reflective layer 20A, at least one anti-diffusion layer 30A, at least one N current spreading layer 40A, at least one distributed Bragg reflection unit 50A, at least one N-type electrode 60A, and At least one P-type electrode 70A.
  • the epitaxial cell 10A is first provided for subsequently forming the reflective layer 20A on the epitaxial cell 10A.
  • the epitaxial unit 10A includes a substrate 11A, an N-type layer 12A, an active layer 13A, and a P-type layer 14A, wherein the substrate 11A, the N-type layer 12A, and the The source layer 13A and the P-type layer 14A are sequentially stacked so that the N-type layer 12A is held between the substrate 11A and the active layer 13A, and the active layer 13A is held Between the N-type layer 12A and the P-type layer 14A.
  • the active layer 13A isolates between the N-type layer 12A and the P-type layer 14A, wherein when the N-type layer 12A and the P-type layer 14A are applied with an operating voltage,
  • the active layer 13A is capable of generating light, and light generated by the active layer 13A can be radiated to the outside via the substrate 11A.
  • the substrate 11A of the epitaxial unit 10A is a transparent substrate to allow light generated by the active layer 13A to be radiated to the outside via the substrate 11A.
  • the substrate 11A may be, but not limited to, a sapphire substrate.
  • the N-type layer 12A of the epitaxial unit 10A may be, but not limited to, an N-type gallium nitride layer.
  • the P-type layer 14A of the epitaxial unit 10A may be, but not limited to, a P-type gallium nitride layer.
  • the epitaxial cell 10A has at least one N-type layer exposed portion 15A, wherein the N-type layer exposed portion 15A is from the outer side surface 141A of the P-type layer 14A via the active layer 13A extends to the N-type layer 12A such that at least a portion of the area of the N-type layer 12A is exposed. That is, the N-type layer 12A and the P-type layer 14A have exposed faces on the same side of the epitaxial cell 10A for subsequent connection to the N-type electrode 60A and the P, respectively.
  • Type electrode 70A is a.
  • the N-type layer 12A forms a part of the N-type layer exposed portion 15A, that is, the thickness dimension of the N-type layer 12A in the region corresponding to the N-type layer exposed portion 15A is smaller than the N-type
  • the layer 12A has a thickness dimension corresponding to a region of the active layer 13A. That is, the N-type layer exposed portion 15A extends from the outer side surface 141A of the P-type layer 14A via the active layer 13A to the middle of the N-type layer 12A.
  • the manner in which the N-type layer exposed portion 15A is formed on the epitaxial unit 10A is not limited in the flip chip of the present invention.
  • the N-type layer exposed portion 15A may be formed on the epitaxial unit 10A by an etching process.
  • the epitaxial cell 10A is first photolithographically coated with a positive photoresist to expose the region of the epitaxial cell 10A that needs to be etched.
  • the thickness of the photoresist is set to be 3 ⁇ m to 5 ⁇ m (including 3 ⁇ m and 5 ⁇ m).
  • the epitaxial cell 10A may be baked after photolithography of the epitaxial cell 10A using a positive photoresist. Then, the region of the epitaxial cell 10A that needs to be etched is dry etched, for example, the need for the epitaxial cell 10A can be utilized by, but not limited to, an Inductive Coupled Plasma Emission Spectrometer (ICP). The etched region is subjected to dry etching, and the gas used for dry etching the epitaxial cell 10A may be chlorine gas (Cl 2 ), boron trichloride (BCl 3 ), or argon gas (Ar).
  • ICP Inductive Coupled Plasma Emission Spectrometer
  • the etching depth of the epitaxial cell 10A for dry etching may be 0.9 ⁇ m - 2 ⁇ m (including 0.9 ⁇ m and 2 ⁇ m) to obtain the outer side surface 141A from the P-type layer 14A extending through the active layer 13A to the The N-type layer exposed portion 15A of the N-type layer 12A.
  • the etching is performed on the epitaxial unit 10A, and the epitaxial unit 10A is formed from the outer side surface 141A of the P-type layer 14A via the active portion.
  • the residual photoresist of the surface of the epitaxial unit 10A is removed to obtain the epitaxy shown in FIGS. 7A and 7B. Unit 10A.
  • the epitaxial unit 10A if the epitaxial unit 10A is provided has the outer side 141A from the P-type layer 14A.
  • the active layer 13A extending to the N-type layer exposed portion 15A of the N-type layer 12A, in the process of manufacturing the flip chip, it is not necessary to newly form the N in the epitaxial unit 10A.
  • Profile exposed portion 15A is not necessary to newly form the N in the epitaxial unit 10A.
  • the reflective layer 20A is formed on the outer side surface 141A of the P-type layer 14A of the epitaxial unit 10A.
  • the reflective layer 20A is a silver reflective layer to increase the reflectivity of the reflective layer 20A, thereby ensuring the brightness of the light emitting diode. Specifically, first, a region where the reflective layer 20A needs to be formed is determined at the P-type layer 14A of the epitaxial unit 10A, and then the reflective layer 20A is formed in the region such that the reflective layer 20A is disposed at The outer side surface 141A of the P-type layer 14A.
  • the reflective layer 20A may be formed in the region by deposition to make the reflective layer 20A is disposed on the outer side surface 141A of the P-type layer 14A.
  • a pattern of a reflective layer to be deposited may be photolithographically deposited on the P-type layer 14A of the epitaxial cell 10A using a negative glue, and then a reflective layer may be formed by evaporation or sputtering.
  • the pattern deposits the reflective layer 20A, and at this time, the reflective layer 20A is formed on the outer side surface 141A of the P-type layer 14A of the epitaxial unit 10A.
  • a negative glue may be used to lithographically pattern the Mirror structure to be deposited on the P-type layer 14A of the epitaxial cell 10A, and then use steaming.
  • a Mirror layer is deposited on the outer side of the P-type layer 14A of the epitaxial cell 10A by plating or sputter coating. That is, in a specific example of the flip chip of the present invention, the reflective layer 20A formed on the outer side surface 141A of the P-type layer 14A of the epitaxial unit 10A may be formed in The Mirror layer of the outer side surface 141A of the P-type layer 14A of the epitaxial unit 10A.
  • the reflective layer 20A is a stacked structure of silver (Ag) and titanium tungsten (TiW), wherein the thickness of the silver (Ag) is 100 angstroms to 5000 angstroms (including 100 angstroms and 5000 angstroms), and titanium tungsten (TiW)
  • the thickness dimension ranges from 200 angstroms to 5,000 angstroms (including 200 angstroms and 5000 angstroms).
  • a flip chip semi-finished product 100A can be further processed. For example, the excess metal layer is first stripped off, and then the photoresist remaining on the surface of the flip chip blank 100A is removed.
  • the manner of peeling off the excess metal layer of the flip chip blank 100A is not limited, for example, the surface of the flip chip semi-finished product 100A may be peeled off by a blue film process. Photoresist.
  • the anti-diffusion layer 30A is formed on the outer side surface 141A of the P-type layer 14A of the epitaxial unit 10A, and the anti-diffusion layer 30A is electrically connected to the P-type layer. 14A, wherein the diffusion prevention layer 30A covers the reflective layer 20A to prevent the reflective layer 20A from exhibiting a poor migration phenomenon. That is, the size of the diffusion prevention layer 30A is larger than the size of the reflective layer 20A to prevent any part of the reflective layer 20A from being exposed by the diffusion prevention layer 30A, thereby preventing the reflective layer 20A. The phenomenon of migration is unfavorable to ensure the reliability and stability of the flip chip.
  • a region where the diffusion prevention layer 30A needs to be formed is determined in the P-type layer 14A of the epitaxial unit 10A, and then the diffusion prevention layer 30A is formed in the region, and the diffusion prevention layer 30A is secured.
  • the reflective layer 20A is completely covered.
  • the anti-diffusion layer 30A may be formed in the region by deposition, and the The diffusion prevention layer 30A completely covers the reflective layer 20A.
  • a pattern of the anti-diffusion layer to be deposited may be photolithographically deposited on the P-type layer 14A of the epitaxial unit 10A using a negative glue, and then lithographically protected by vapor deposition or sputter deposition.
  • a pattern of the diffusion layer deposits the diffusion prevention layer 30A.
  • the diffusion prevention layer 30A is formed on the outer side surface 141A of the P-type layer 14A of the epitaxial unit 10A, and the diffusion prevention layer 30A The reflective layer 20A is completely covered.
  • a negative glue may be used to lithographically pattern the Barrier layer to be deposited on the outer side of the P-type layer 14A of the epitaxial unit 10A, Then, a barrier layer completely covering the reflective layer 20A is deposited on the outer side surface 141A of the P-type layer 14A of the epitaxial unit 10A by vapor deposition or sputter deposition. That is, in a specific example of the flip chip of the present invention, the outer side surface 141A of the P-type layer 14A of the epitaxial unit 10A is formed to completely cover the reflective layer 20A.
  • the diffusion prevention layer 30A may be the Barrier layer formed on the outer side surface 141A of the P-type layer 14A of the epitaxial unit 10A for completely covering the reflective layer 20A.
  • the diffusion prevention layer 30A is a laminated structure, wherein a material forming the diffusion prevention layer 30A is selected from the group consisting of titanium tungsten (TiW), titanium (Ti), platinum (Pt), aluminum (Al), and nickel (Ni). ), a group of materials consisting of gold (Au).
  • the material of the diffusion prevention layer 30A may be selected from the group consisting of titanium tungsten (TiW), titanium (Ti), platinum (Pt), aluminum (Al), nickel (Ni), and gold (Au).
  • Two or more materials selected from the group consisting of titanium tungsten (TiW), titanium (Ti), platinum (Pt), aluminum (Al), nickel (Ni), and gold (Au) may also be selected.
  • the flip chip semi-finished product 100A can be further processed. For example, the excess metal layer is first stripped off, and then the photoresist remaining on the surface of the flip chip blank 100A is removed.
  • the manner of peeling off the excess metal layer of the flip chip blank 100A is not limited, for example, the surface of the flip chip semi-finished product 100A may be peeled off by a blue film process. Photoresist.
  • the distributed Bragg Reflector (DBR) 50A is formed on the surface of the flip chip blank 100A, wherein the distributed Bragg reflection unit 50A integrally combines the N The pattern layer 12A, the active layer 13A, the P-type layer 14A, and the diffusion prevention layer 30A. Since the reflective layer 20A formed on the outer side surface 141A of the P-type layer 14A cannot cover the entire area of the outer side surface of the P-type layer 14A, the outer side surface 141A of the P-type layer 14A is made. At least a portion of the light is not reflected by the active layer 13A.
  • a region of the P-type layer 14A not covered by the reflective layer 20A can be further covered by the distributed Bragg reflection unit 50A to increase the formation of the reflective layer 20A.
  • the area of the reflecting surface and the reflecting surface formed by the distributed Bragg reflection unit 50A can enhance the reflectivity of the flip chip, which is very important for greatly increasing the overall brightness of the LED.
  • the distributed Bragg reflection unit 50A has at least one N-type layer channel 51A and at least one P-type layer channel 52A, wherein the N-type layer channel 51A corresponds to a portion of the N-type layer 12A, the P-type layer Channel 52A corresponds to a portion of the P-type layer 14A.
  • the distributed Bragg reflection unit 50A may be formed on the surface of the flip chip blank 100A in a construction evaporation manner to cause the distributed Bragg reflection unit
  • the 50A is capable of integrally bonding the N-type layer 12A, the active layer 13A, the P-type layer 14A, and the diffusion prevention layer 30A.
  • the distributed Bragg reflection unit 50A uses a laminated structure of silicon oxide, titanium oxide, magnesium fluoride, cerium oxide, aluminum oxide, aluminum nitride to improve the reflectance of the distributed Bragg reflection unit 50A, thereby It is beneficial to increase the overall brightness of the light emitting diode.
  • the distributed Bragg reflection unit 50A is formed of a film layer stack of at least two refractive indices.
  • the material of the film layer of the distributed Bragg reflection unit 50A is selected from the group consisting of silicon oxide, titanium oxide, magnesium fluoride, cerium oxide, aluminum oxide, and aluminum nitride.
  • the material of the distributed Bragg reflection unit 50A may be selected from silicon oxide, titanium oxide, magnesium fluoride, cerium oxide, aluminum oxide, aluminum nitride, or silicon oxide or titanium oxide. Two or more materials of magnesium fluoride, cerium oxide, aluminum oxide, and aluminum nitride.
  • different pairs of reflective layers can be designed for different wavelengths.
  • the reflective layer pair of the distributed Bragg reflector unit 50A is between 20 pairs and 50 pairs (including 20 pairs and 50 pairs).
  • the distributed Bragg reflection unit 50A is subjected to a photolithography and etching process to form the N-type layer channel 51A and the P-type layer channel 52A of the distributed Bragg reflection unit 50A, wherein the N
  • the type layer channel 51A extends to the N type layer 12A of the epitaxial unit 10A such that at least a portion of the area of the N type layer 12A is exposed
  • the P type layer channel 52A extends to the epitaxial unit 10A
  • the P-type layer 14A is such that at least a portion of the region of the P-type layer 14A is exposed.
  • the distributed Bragg reflection unit 50A is first photolithographically coated with a positive photoresist to cause the distributed Bragg reflection unit 50A The area that needs to be etched is exposed. Then, the distributed Bragg reflection unit 50A is etched by the ICP machine to form the N-type layer channel 51A and the P-type layer channel 52A at the distributed Bragg reflection unit 50A.
  • the N current spreading layer 40A and the at least one P current spreading layer 80A are formed on the outer side surface 53A of the distributed Bragg reflection unit 50A, respectively, wherein the N current spreading layer 40A
  • the N-type layer channel 51A via the distributed Bragg reflection unit 50A extends to and is electrically connected to the N-type layer 12A of the epitaxial unit 10A, and accordingly, the P-current expansion layer 80A is via the The P-type layer channel 52A of the distributed Bragg reflection unit 50A extends to and is electrically connected to the P-type layer 14A of the epitaxial unit 10A.
  • the pattern of the N current spreading layer to be deposited and the pattern of the P current spreading layer may be photolithographically patterned on the outer side surface 53A of the distributed Bragg reflection unit 50A using a negative glue, and then evaporated or splashed using
  • the N current spreading layer 40A and the P current spreading layer 80A are respectively deposited in a pattern of the etched N current spreading layer and a pattern of the P current spreading layer, wherein the N current spreading layer 40A and There is a safe distance between the P current spreading layers 80A.
  • a negative glue may be used to lithographically pattern the N current spreading layer to be deposited on the outer side surface 53A of the distributed Bragg reflection unit 50A.
  • the N-type layer channel 51A of 50A extends to and is electrically connected to the N-type layer 12A of the epitaxial unit 10A, and the P current spreading layer 80A is deposited in a pattern of a P current spreading layer, and The P current spreading layer 80A extends to and is electrically connected to the P-type layer 14A of the epitaxial unit 10A via the P-type layer channel 52A of the distributed Bragg reflection unit 50A.
  • the structure of the N current spreading layer 40A and the structure of the P current spreading layer 80A are both chromium (Cr), aluminum (Al), titanium (Ti) platinum (Pt) gold (Au), and nickel (Ni).
  • Electrode structure That is, the materials forming the N current spreading layer 40A and the P current spreading layer 80A are each selected from the group consisting of chromium (Cr), aluminum (Al), titanium (Ti) platinum (Pt) gold (Au), and nickel. (Ni) composed of material groups.
  • the materials of the N current spreading layer 40A and the P current spreading layer 80A may be selected from chromium (Cr), aluminum (Al), titanium (Ti) platinum (Pt) gold (Au), and nickel (Ni).
  • One of the materials may be selected from two or more of chromium (Cr), aluminum (Al), titanium (Ti) platinum (Pt) gold (Au), and nickel (Ni).
  • the flip chip semifinished product 100A may be further processed. For example, the excess metal layer is first stripped off, and then the photoresist remaining on the surface of the flip chip blank 100A is removed.
  • the manner of peeling off the excess metal layer of the flip chip blank 100A is not limited, for example, the surface of the flip chip semi-finished product 100A may be peeled off by a blue film process. Photoresist.
  • an insulating layer 90A is formed on the outer side of the flip chip blank 100A, wherein the insulating layer 90A integrally bonds the distributed Bragg reflection unit 50A, the N current spreading layer 40A, and The P current spreading layer 80A.
  • the insulating layer 90A is capable of isolating the N current spreading layer 40A and the P current spreading layer 80A.
  • the insulating layer 90A has at least one first channel 91A and at least one second channel 92A, wherein at least a portion of the N current spreading layer 40A corresponds to the first channel 91A of the insulating layer 90A for subsequent Allowing the N-type electrode 60A to extend to and be electrically connected to the N current spreading layer 40A via the first channel 91A of the insulating layer 90A, and correspondingly, at least a portion of the P current spreading layer 80A corresponds to at least a portion of the region
  • the second channel 92A of the insulating layer 90A to subsequently allow the P-type electrode 70A to extend to and be electrically connected to the P current spreading layer via the second channel 92A of the insulating layer 90A. 80A.
  • a plasma enhanced chemical vapor deposition may be used to form an outer side of the flip chip semi-finished product 100A.
  • the insulating layer 90A wherein the gas used may be, but not limited to, monosilane (SiH 4 ), nitrous oxide (N 2 O), and nitrogen (N 2 ).
  • the insulating layer 90A has a thickness ranging from 5,000 angstroms to 20,000 angstroms (including 5000 angstroms and 20,000 angstroms) to ensure reliability and stability of the flip chip.
  • the manner in which the first via 91A and the second via 92A are formed in the insulating layer 90A is not limited in the flip chip of the present invention.
  • the first via 91A and the second via 92A may be formed on the insulating layer 90A by an etching process.
  • the insulating layer 90A is first photolithographically coated with a positive photoresist to expose the region of the insulating layer 90A that needs to be etched.
  • the region of the insulating layer 90A that needs to be etched is dry etched, for example, the region of the insulating layer 90A that needs to be etched may be dry etched using, but not limited to, an ICP machine.
  • the insulating layer 90A forms the first passage 91A and the second passage 92A.
  • the material of the insulating layer 90A is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and aluminum nitride.
  • the insulating layer 90A may be selected from one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and aluminum nitride, and may also be selected from silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. And two or more materials in aluminum nitride.
  • the N-type electrode 60A and the P-type electrode 70A are formed separately from each other in different regions of the outer side surface 93A of the insulating layer 90A, wherein the N-type electrode 60A is via the
  • the first via 91A of the insulating layer 90A extends to and is electrically connected to the N current spreading layer 40A, and correspondingly, the P-type electrode 70A extends to and through the second via 92A of the insulating layer 90A. It is electrically connected to the P current spreading layer 80A.
  • the N-type electrode 60A may be formed by performing negative film lithography and lift-off on the outer side surface 93A of the insulating layer 90A.
  • the P-type electrode 70A More specifically, a pattern of electrodes to be deposited may be photolithographically patterned on the outer side surface 93A of the insulating layer 90A using a negative glue, and then patterned deposition of the photolithographic electrode using evaporation or sputter deposition.
  • the N-type electrode 60A and the P-type electrode 70A are extended, wherein the N-type electrode 60A extends to and is electrically connected to the N-current expansion layer 40A via the first channel 91A of the insulating layer 90A, Accordingly, the P-type electrode 70A extends to and is electrically connected to the P current spreading layer 80A via the second via 92A of the insulating layer 90A.
  • a negative glue is used to etch a pattern of an electrode to be deposited on the outer side of the insulating layer 90A, and a pattern of the etched electrode is used to deposit the N-type electrode 60A and a pattern using an evaporation or sputter coating process.
  • the flip-chip semi-finished product 100A may be further processed to obtain the flip chip.
  • the excess metal layer is first stripped off, and then the photoresist remaining on the surface of the flip chip blank 100A is removed.
  • the manner of peeling off the excess metal layer of the flip chip blank 100A is not limited, for example, the surface of the flip chip semi-finished product 100A may be peeled off by a blue film process. A photoresist is used to obtain the flip chip.
  • the structure of the N-type electrode 60A and the P-type electrode 70A is chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), gold (Au), nickel (Ni), gold. Tin (AuSn) electrode structure. That is, the material of the electrode structure of the N-type electrode 60A and the P-type electrode 70A is selected from the group consisting of chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), gold (Au), A material group consisting of tin (Sn), nickel (Ni), and gold tin (AuSn).
  • the material of the electrode structure of the N-type electrode 60A and the P-type electrode 70A may be selected from chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), gold (Au), tin. (Sn), nickel (Ni), gold tin (AuSn), a material may also be selected from chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), gold (Au), tin ( Two or more materials of Sn), nickel (Ni), and gold tin (AuSn).
  • the thickness dimension of the N-type electrode 60A and the thickness dimension of the P-type electrode 70A range from 0 ⁇ m to 7 ⁇ m (including 7 ⁇ m).
  • FIGS. 13A and 13B illustrate a specific structure of the flip chip according to a preferred embodiment of the present invention, wherein the flip chip includes the epitaxial unit 10A and the reflective layer 20A.
  • the substrate 11A, the N-type layer 12A, the active layer 13A, and the P-type layer 14A of the epitaxial unit 10A are sequentially stacked, and the N-type layer of the epitaxial unit 10A is exposed
  • the portion 15A extends from the outer side surface 141A of the P-type layer 14A to the N-type layer 12A via the active layer 13A such that at least a portion of the region of the N-type layer 12A is exposed.
  • the reflective layer 20A is formed on the outer side surface 141A of the P-type layer 14A of the epitaxial unit 10A, and the anti-diffusion layer 30A is formed on the outer side of the P-type layer 14A of the epitaxial unit 10A.
  • the side surface 141A, and the diffusion prevention layer 30A completely covers the reflective layer 20A.
  • the distributed Bragg reflection unit 50A is integrally coupled to the N-type layer 12A, the active layer 13A, the P-type layer 14A, and the diffusion prevention layer 30A, and at least a portion of the N-type layer 12A
  • the region corresponds to the N-type layer channel 51A of the distributed Bragg reflection unit 50A
  • at least a portion of the P-type layer 14A corresponds to the P-type layer channel 52A of the distributed Bragg reflection unit 50A.
  • the N current spreading layer 40A is formed in the distributed Bragg reflection unit 50A, and the N current spreading layer 40A extends to and is electrically connected via the N-type layer channel 51A of the distributed Bragg reflection unit 50A.
  • the N-type layer 12A Accordingly, the P current spreading layer 80A is formed in the distributed Bragg reflection unit 50A, and the P current spreading layer 80A extends to and from the P-type layer channel 52A of the distributed Bragg reflection unit 50A. Electrically connected to the P-type layer 14A.
  • the N current spreading layer 40A and the P current spreading layer 80A have a safe distance.
  • the insulating layer 90A is integrally coupled to the distributed Bragg reflection unit 50A, the N current spreading layer 40A, and the P current spreading layer 80A, wherein the N current spreading layer 40A corresponds to the insulating layer 90A.
  • the first channel 91A, the P current spreading layer 80A corresponds to the second channel 92A of the insulating layer 90A.
  • the insulating layer 90A further isolates the N current spreading layer 40A and the P current spreading layer 80A.
  • the N-type electrode 60A is formed on the insulating layer 90A, and the N-type electrode 60A extends to and is electrically connected to the N current spreading layer 40A via the first via 91A of the insulating layer 90A.
  • the P-type electrode 70A is formed on the insulating layer 90A, and the P-type electrode 70A extends to and is electrically connected to the P current spreading layer 80A via the second via 92A of the insulating layer 90A.
  • the N-type electrode 60A and the P-type electrode 70A are independent of each other.
  • the active layer 13A of the epitaxial unit 10A is capable of generating light and radiating to the periphery, wherein the active layer 13A generates
  • the light radiated toward the substrate 11A of the epitaxial unit 10A can be directly radiated to the outside via the substrate 11A, and the light generated by the active layer 13A in the direction of the reflective layer 20A can be irradiated
  • the reflective layer 20A is reflected and radiated to the outside via the substrate 11A, while the light generated by the active layer 13A in the direction of the distributed Bragg reflection unit 50A can be subjected to the distributed Bragg reflection unit 50A.
  • the substrate 11A is radiated to the outside. In this way, the reflectivity of the flip chip can be greatly improved, thereby facilitating further improvement of the overall brightness of the LED, which is prior art.
  • the flip chip is unexpected.
  • the substrate 11A, the N-type layer 12A, the active layer 13A, the P-type layer 14A, the flip chip of the flip chip shown in FIGS. 7A to 13B The reflective layer 20A, the diffusion prevention layer 30A, the N current spreading layer 40A, the distributed Bragg reflection layer 50A, the N-type electrode 60A, the P-type electrode 70A, and the P current spreading layer 80A
  • the thickness of the insulating layer 90A is merely an example, and does not mean the substrate 11A, the N-type layer 12A, the active layer 13A, the P-type layer 14A, the reflective layer 20A,
  • the diffusion prevention layer 30A, the N current spreading layer 40A, the distributed Bragg reflection layer 50A, the N-type electrode 60A, the P-type electrode 70A, the P current spreading layer 80A, and the insulating layer The true thickness of the 90A.
  • the true ratio between the distributed Bragg reflection layer 50A, the N-type electrode 60A, the P-type electrode 70A, the P current spreading layer 80A, and the insulating layer 90A is also different from that shown in the drawing. That way.
  • the ratio of the size of the N-type electrode 60A and the P-type electrode 70A to the other layers of the flip chip is also not limited to that shown in FIGS. 7A to 13B.
  • the present invention further provides a method of fabricating a flip chip of a light emitting diode, wherein the manufacturing method comprises the following steps:
  • the present invention further provides a method of emitting a flip-chip of a light emitting diode, wherein the method of emitting light comprises the following steps:

Abstract

一种发光二极管的倒装芯片及其制造方法和发光方法，其中倒装芯片包括至少一反射层（20）、至少一N型电极（60）、至少一P型电极（70）至少一分布式布拉格反射单元（50）以及一外延单元（10），其中外延单元包括一衬底（11）、一N型层（12）、一有源层（13）以及一P型层（14），衬底、N型层、有源层和P型层被依次重叠地设置，并且外延单元具有至少一N型层裸露部（15A），N型层裸露部自P型层的外侧面经由有源层延伸至N型层，其中反射层形成于P型层，分布式布拉格反射单元一体地结合于N型层、有源层、P型层以及反射层，其中N型电极被电连接于N型层，P型电极被电连接于P型层。

Description

发光二极管的倒装芯片及其制造方法和发光方法 技术领域
本发明涉及一LED芯片，特别涉及一发光二极管的倒装芯片及其制造方法和发光方法。
背景技术
由于发光二极管Light-Emitting Diode，LED)具有低耗能、小尺寸以及高可靠性等优点，近年来，发光二极管在日常照明、车辆照明、指示以及显示等领域都得到了大规模的应用。发光二极管按照芯片结构的制作工艺的不同可以被区分为倒装芯片结构的发光二极管和正装芯片结构的发光二极管，其中因为倒装芯片结构的发光二极管具有无电极挡光、热阻低以及可承受大电流冲击的特点，使得倒装芯片结构的发光二极管成为了大功率LED的一个重要的研究方向。
与正装芯片结构的发光二极管的发光面不同的是，倒装芯片结构的发光二极管的出光面在衬底(例如蓝宝石面)，这就决定了在倒装芯片结构的发光二极管的电极侧的发射面的制作成为了影响倒装芯片结构的发光二极管的发光品质的一个重要的步骤。因为金属银是一个高反射金属材料，目前市面上比较流行的倒装芯片结构的发光二极管中使用的是利用高反射金属银作为银镜来实现对光的出光反射，然而，众所周知的是，金属银是一种活泼金属，在一定湿度的环境中金属银在倒装芯片结构的发光二极管的电极侧形成的银镜极易出现迁移的不良现象，而一旦银镜出现了迁移的不良现象，则势必会影响发光二极管的发光品质，因此，必须设计放置银镜迁移的防扩散层用于保证银镜的稳定性，并且防扩散层的尺寸必须大于银镜的尺寸，以使防扩散层能够完全覆盖银镜。由于受到金属银材料本身的限制，银镜只能设置在P型氮化镓的表面，而无法设置在N型电极以及PN之间的间隔位置，这限制了倒装芯片结构的发光二极管的亮度的提升。
发明内容
本发明的一个目的在于提供一发光二极管的倒装芯片及其制造方法和发光 方法，其中所述发光二极管的亮度能够被大幅度地提升。
本发明的一个目的在于提供一发光二极管的倒装芯片及其制造方法和发光方法，其中所述倒装芯片的反射面的面积能够被增加，以有利于提升所述发光二极管的亮度。
本发明的一个目的在于提供一发光二极管的倒装芯片及其制造方法和发光方法，其中所述倒装芯片的P型层中没有被反射层覆盖的区域的反射率能够被提高，以有利于提升所述发光二极管的亮度。
本发明的一个目的在于提供一发光二极管的倒装芯片及其制造方法和发光方法，其中所述倒装芯片提供至少一分布式布拉格反射单元，其中所述分布式布拉格反射单元形成于所述P型层，以提高所述P型层中没有被所述反射层覆盖的区域的反射率，从而有利于提升所述发光二极管的亮度。
本发明的一个目的在于提供一发光二极管的倒装芯片及其制造方法和发光方法，其中所述分布式布拉格反射单元具有绝缘作用，以隔绝所述P型层和N型层，以保证所述倒装芯片的可靠性。
本发明的一个目的在于提供一发光二极管的倒装芯片及其制造方法和发光方法，其中所述分布式布拉格反射单元具有绝缘作用，以隔绝所述P型层和N电流扩展层，以保证所述倒装芯片的可靠性。
本发明的一个目的在于提供一发光二极管的倒装芯片及其制造方法和发光方法，其中所述分布式布拉格反射单元具有绝缘作用，以隔绝所述N电流扩展层和P电流扩展层，以保证所述倒装芯片的可靠性。
依本发明的一个方面，本发明提供一发光二极管的倒装芯片，其包括：
至少一反射层；
至少一N型电极；
至少一P型电极；
至少一分布式布拉格反射单元；以及
一外延单元，其中所述外延单元包括一衬底、一N型层、一有源层以及一P型层，所述衬底、所述N型层、所述有源层和所述P型层被依次层叠地设置，并且所述外延单元具有至少一N型层裸露部，所述N型层裸露部自所述P型层的外侧面经由所述有源层延伸至所述N型层，其中所述反射层形成于所述P型层，所述分布式布拉格反射单元一体地结合于所述N型层、所述有源层、所述P 型层以及所述反射层，其中所述N型电极被电连接于所述N型层，所述P型电极被电连接于所述P型层。
根据本发明的一个实施例，所述倒装芯片进一步包括一防扩散层，其中所述防扩散层形成于所述P型层，并且所述防扩散层包覆所述反射层的至少一部分区域，其中所述分布式布拉格反射单元一体地结合于所述防扩散层。
根据本发明的一个实施例，所述反射层是银反射层，所述防扩散层完全包覆所述反射层。
根据本发明的一个实施例，所述防扩散层被电连接于所述P型层，所述P型电极以所述P型电极被电连接于所述防扩散层的方式被电连接于所述P型层。
根据本发明的一个实施例，所述倒装芯片进一步包括至少一N电流扩展层，其中所述N电流扩展层以所述N电流扩展层被保持在所述外延单元的所述N型层裸露部的方式被电连接于所述N型层，其中所述N型电极以所述N型电极被电连接于所述N电流扩展层的方式被电连接于所述N型层，其中所述分布式布拉格反射单元一体地结合于所述N电流扩展层。
根据本发明的一个实施例，所述分布式布拉格反射单元具有至少一N型层通道和至少一P型层通道，其中所述N电流扩展层对应于所述N型层通道，所述N型电极形成于所述分布式布拉格反射单元，并且所述N型电极经由所述N型层通道延伸至所述N电流扩展层，其中所述防扩散层对应于所述P型层通道，所述P型电极形成于所述分布式布拉格反射单元，并且所述P型电极经由所述P型层通道延伸至所述防扩散层。
根据本发明的一个实施例，所述N电流扩展层自所述N型层向所述P型层方向延伸，并且所述N电流扩展层的外侧面的高度低于所述P型层的外侧面的高度。
根据本发明的一个实施例，所述倒装芯片进一步包括至少一N电流扩展层和至少一P电流扩展层，其中所述分布式布拉格反射单元具有至少一N型层通道和至少一P型层通道，其中所述N型层对应于所述N型层通道，所述N电流扩展层形成于所述分布式布拉格反射单元，并且所述N电流扩展层经由所述N型层通道延伸至所述N型层，且所述N电流扩展层被电连接于所述N型层，所述N型电极以所述N型电极被电连接于所述N电流扩展层的方式被电连接于所述N型层，其中所述P型层对应于所述P型层通道，所述P电流扩展层形成于所 述分布式布拉格反射单元，并且所述P电流扩展层经由所述P型层通道延伸至所述P型层，并且所述P电流扩展层被电连接于所述P型层，所述P型电极以所述P型电极被电连接于所述P电流扩展层的方式被电连接于所述P型层。
根据本发明的一个实施例，所述倒装芯片进一步包括至少一绝缘层，所述绝缘层具有至少一第一通道和至少一第二通道，其中所述绝缘层形成于所述N电流扩展层和所述P电流扩展层，并且所述第一通道对应于所述N电流扩展层，和所述第二通道对应于所述P电流扩展层，其中所述N型电极经由所述绝缘层的所述第一通道被电连接于所述N电流扩展层，所述P型电极经由所述绝缘层的所述第二通道被电连接于所述P电流扩展层。
根据本发明的一个实施例，所述绝缘层结合于所述分布式布拉格反射单元，以藉由所述绝缘层隔离所述N电流扩展层和所述P电流扩展层。
根据本发明的一个实施例，所述N型电极形成于所述绝缘层，并且所述N型电极经由所述绝缘层的所述第一通道延伸至所述N电流扩展层，其中所述P型电极形成于所述绝缘层，并且所述P型电极经由所述绝缘层的所述第二通道延伸至所述P电流扩展层。
根据本发明的一个实施例，所述分布式布拉格反射单元由至少两种折射率的膜层堆叠形成。
根据本发明的一个实施例，所述分布式布拉格反射单元的膜层材料选自：氧化硅、氧化钛、氟化镁、氧化铪、氧化铝、氮化铝组成的材料组。
根据本发明的一个实施例，所述防扩散层的材料选自：钛钨、钛、铂、铝、镍、金组成的材料组。
根据本发明的一个实施例，所述N电流扩展层的材料选自：铬、铝、钛、铂、金、镍组成的材料组。
根据本发明的一个实施例，所述P电流扩展层的材料选自：铬、铝、钛、铂、金、镍组成的材料组。
根据本发明的一个实施例，所述N型电极和所述P型电极的电极材料选自：铬、铝、钛、铂、金、镍、金锡组成的材料组。
根据本发明的一个实施例，所述N型层是N型氮化镓层，所述P型层是P型氮化镓层。
根据本发明的一个实施例，所述绝缘层的材料选自：氧化硅、氮化硅、氮氧 化硅、氧化铝、氮化铝组成的材料组。
根据本发明的一个实施例，所述反射层的结构是银和钛钨的层叠结构。
根据本发明的一个实施例，所述反射层的银层的厚度尺寸范围为：100埃-5000埃，其中所述反射层的钛钨层的厚度尺寸范围为：200埃-5000埃。
根据本发明的一个实施例，所述分布式布拉格反射单元的厚度尺寸范围为：0μm-7μm。
依本发明的另一个方面，本发明进一步提供一发光二极管的倒装芯片的制造方法，其中所述制造方法包括如下步骤：
(a)在一外延单元的一P型层的外侧面形成至少一反射层；
(b)藉由至少一分布式布拉格反射单元覆盖所述P型层的所述外侧面的未被所述反射层覆盖的区域；以及
(c)电连接一P型电极于所述P型层，和电连接一N型电极于所述外延单元的一N型层，以制得所述倒装芯片。
根据本发明的一个实施例，在所述步骤(b)之前，进一步包括步骤：形成一防扩散层于所述P型层的所述外侧面，其中所述防扩散层包覆所述反射层，并且所述防扩散层被电连接于所述P型层，从而在所述步骤(c)中，所述P型电极以所述P型电极被电连接于所述防扩散层的方式被电连接于所述P型层。
根据本发明的一个实施例，在所述步骤(b)之前，进一步包括步骤：形成一N电流扩展层于所述N型层，其中所述N电流扩展层被电连接于所述N型层，从而在所述步骤(c)中，所述N型电极以所述N型电极被电连接于所述N电流扩展层的方式被电连接于所述N型层。
根据本发明的一个实施例，在所述步骤(b)中，以所述分布式布拉格反射单元一体地结合于所述P型层、所述防扩散层和所述N电流扩展层的方式使所述分布式布拉格反射单元覆盖所述P型层的所述外侧面的未被所述反射层覆盖的区域，其中所述分布式布拉格反射单元具有对应于所述N电流扩展层的至少一N型层通道和对应于所述防扩散层的至少一P型层通道，所述N型电极经由所述N型层通道被电连接于所述N电流扩展层，所述P型电极经由所述P型层通道被电连接于所述防扩散层。
根据本发明的一个实施例，在上述方法中，形成所述N型电极于所述分布式布拉格反射单元，以使所述N型电极经由所述N型层通道延伸至所述N电流扩 展层，形成所述P型电极于所述分布式布拉格反射单元，以使所述P型电极经由所述P型层通道延伸至所述防扩散层。
根据本发明的一个实施例，在所述步骤(b)中，以所述分布式布拉格反射单元一体地形成于所述P型层、所述防扩散层和所述N电流扩展层的方式使所述分布式布拉格反射单元覆盖所述P型层的所述外侧面的未被所述反射层覆盖的区域，其中所述分布式布拉格反射单元具有对应于所述N型层的至少一N型层通道和对应于所述P型层的至少一P型层通道，所述N型电极经由所述N型层通道被电连接于所述N型层，所述P型电极经由所述P型层通道被电连接于所述P型层。
根据本发明的一个实施例，在上述方法中，进一步包括步骤：
形成至少一N电流扩展层于所述分布式布拉格反射单元，并且所述N电流扩展层经由所述N型层通道延伸至所述N型层，且所述N电流扩展层被电连接于所述N型层，其中所述N型电极被电连接于所述N电流扩展层；和
形成至少一P电流扩展层于所述分布式布拉格反射单元，并且所述P电流扩展层经由所述P型层通道延伸至所述P型层，并且所述P电流扩展层被电连接于所述P型层，其中所述P型电极被电连接于所述P电流扩展层。
根据本发明的一个实施例，在上述方法中，进一步包括步骤，形成一绝缘层于所述N电流扩展层、所述P电流扩展层和所述分布式布拉格反射单元，其中所述绝缘层具有对应于所述N电流扩展层的至少一第一通道和对应于所述P电流扩展层的至少一第二通道，所述N型电极经由所述第一通道被电连接于所述N电流扩展层，所述P型电极经由所述第二通道被电连接于所述P电流扩展层。
根据本发明的一个实施例，在上述方法中，形成所述N型电极于所述绝缘层，以使所述N型电极经由所述第一通道延伸至所述N电流扩展层，形成所述P型电极于所述绝缘层，以使所述P型电极经由所述第二通道延伸至所述P电流扩展层。
依本发明的另一个方面，本发明进一步提供一发光二极管的倒装芯片的发光方法，其中所述发光方法包括如下步骤：
(A)施加工作电压于所述倒装芯片的一N型电极和一P型电极，以使所述倒装芯片的一有源层产生光线；
(B)允许所述有源层产生的向所述倒装芯片的一衬底方向辐射的光线在穿 过所述衬底后向所述倒装芯片的外界辐射；
(C)藉由至少一反射层反射所述有源层产生的向所述倒装芯片的一P型层方向辐射的光线，以使被反射的光线在穿过所述衬底后向所述倒装芯片的外界辐射；以及
(D)藉由至少一分布式布拉格反射单元反射所述有源层产生的向所述P型层方向辐射的光线，以使被反射的光线在穿过所述衬底后向所述倒装芯片的外界辐射。
根据本发明的一个实施例，所述反射层覆盖所述P型层的外侧面的一部分区域，所述分布式布拉格反射单元覆盖所述P型层的外侧面的另一部分区域，从而在所述步骤(C)和所述步骤(D)中，所述反射层和所述分布式布拉格反射单元均能够反射所述有源层产生的向所述P型层方向辐射的光线。
根据本发明的一个实施例，所述分布式布拉格反射单元由至少两种折射率的膜层堆叠形成。
根据本发明的一个实施例，所述分布式布拉格反射单元的膜层材料选自：氧化硅、氧化钛、氟化镁、氧化铪、氧化铝、氮化铝组成的材料组。
根据本发明的一个实施例，所述分布式布拉格反射单元的厚度尺寸范围为：0μm-7μm。
附图说明
图1A是依本发明的一较佳实施例的一发光二极管的倒装芯片的制造过程之一的剖视示意图。
图1B是依本发明的上述较佳实施例的所述倒装芯片的制造过程之一的俯视示意图。
图2A是依本发明的上述较佳实施例的所述倒装芯片的制造过程之二的剖视示意图。
图2B是依本发明的上述较佳实施例的所述倒装芯片的制造过程之二的俯视示意图。
图3A是依本发明的上述较佳实施例的所述倒装芯片的制造过程之三的剖视示意图。
图3B是依本发明的上述较佳实施例的所述倒装芯片的制造过程之三的俯视 示意图。
图4A是依本发明的上述较佳实施例的所述倒装芯片的制造过程之四的剖视示意图。
图4B是依本发明的上述较佳实施例的所述倒装芯片的制造过程之四的俯视示意图。
图5A是依本发明的上述较佳实施例的所述倒装芯片的制造过程之五的剖视示意图。
图5B是依本发明的上述较佳实施例的所述倒装芯片的制造过程之五的俯视示意图。
图6A是依本发明的上述较佳实施例的所述倒装芯片的制造过程之六的剖视示意图，其同时示出了所述倒装芯片的剖视状态。
图6B是依本发明的上述较佳实施例的所述倒装芯片的制造过程之六的俯视示意图，其同时示出了所述倒装芯片的俯视状态。
图7A是依本发明的另一较佳实施例的一发光二极管的倒装芯片的制造过程之一的剖视示意图。
图7B是依本发明的上述较佳实施例的所述倒装芯片的制造过程之一的俯视示意图。
图8A是依本发明的上述较佳实施例的所述倒装芯片的制造过程之二的剖视示意图。
图8B是依本发明的上述较佳实施例的所述倒装芯片的制造过程之二的俯视示意图。
图9A是依本发明的上述较佳实施例的所述倒装芯片的制造过程之三的剖视示意图。
图9B是依本发明的上述较佳实施例的所述倒装芯片的制造过程之三的俯视示意图。
图10A是依本发明的上述较佳实施例的所述倒装芯片的制造过程之四的剖视示意图。
图10B是依本发明的上述较佳实施例的所述倒装芯片的制造过程之四的俯视示意图。
图11A是依本发明的上述较佳实施例的所述倒装芯片的制造过程之五的剖 视示意图。
图11B是依本发明的上述较佳实施例的所述倒装芯片的制造过程之五的俯视示意图。
图12A是依本发明的上述较佳实施例的所述倒装芯片的制造过程之六的剖视示意图。
图12B是依本发明的上述较佳实施例的所述倒装芯片的制造过程之六的俯视示意图。
图13A是依本发明的上述较佳实施例的所述倒装芯片的制造过程之七的剖视示意图，其同时示出了所述倒装芯片的剖视状态。
图13B是依本发明的上述较佳实施例的所述倒装芯片的制造过程之七的俯视示意图，其同时示出了所述倒装芯片的俯视状态。
具体实施方式
以下描述用于揭露本发明以使本领域技术人员能够实现本发明。以下描述中的优选实施例只作为举例，本领域技术人员可以想到其他显而易见的变型。在以下描述中界定的本发明的基本原理可以应用于其他实施方案、变形方案、改进方案、等同方案以及没有背离本发明的精神和范围的其他技术方案。
本领域技术人员应理解的是，在本发明的揭露中，术语“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系是基于附图所示的方位或位置关系，其仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此上述术语不能理解为对本发明的限制。
可以理解的是，术语“一”应理解为“至少一”或“一个或多个”，即在一个实施例中，一个元件的数量可以为一个，而在另外的实施例中，该元件的数量可以为多个，术语“一”不能理解为对数量的限制。
参考本发明的说明书附图1A至图6B，依本发明的一较佳实施例的一发光二极管的倒装芯片及其制造方法和发光方法在接下来的描述中被揭露和被阐述，其中在接下来的描述中，将所述发光二极管的倒装芯片简称为一倒装芯片，但本领域技术人员应当理解的是，将所述发光二极管的倒装芯片简称为所述倒装芯片 仅是为了使本发明的说明书更为简洁和便于理解，并不应被视为是对本发明的内容和范围的限制。具体地说，所述倒装芯片包括一外延单元10、至少一反射层20、至少一防扩散层30、至少一N电流扩展层40、至少一分布式布拉格反射单元50、至少一N型电极60以及至少一P型电极70。
参考附图1A和图1B，在制造所述倒装芯片的过程中，首先提供所述外延单元10，以供在后续，在所述外延单元10上形成所述反射层20、所述防扩散层30、所述N电流扩展层40和所述分布式布拉格反射单元50。具体地说，所述外延单元10包括一衬底11、一N型层(N型导电层)12、一有源层13以及一P型层(P型导电层)14，其中所述衬底11、所述N型层12、所述有源层13以及所述P型层14被依次层叠地设置，以使得所述N型层12被保持在所述衬底11和所述有源层13之间，所述有源层13被保持在所述N型层12和所述P型层14之间。也就是说，所述有源层13保持在所述N型层12和所述P型层14之间，其中当所述N型层12和所述P型层14被施加工作电压时，电流能够在所述有源层13复合而能够产生光线，并且所述有源层13产生的光线能够经由所述衬底11向外界辐射。另外，所述有源层13产生的光线还会向所述P型层14的方向辐射，本发明的所述反射层20能够反射向所述P型层14方向辐射的光线，所述分布式布拉格反射单元50能够进一步反射向所述P型层14方向辐射的光线，本发明的所述倒装芯片通过提供所述分布式布拉格反射单元50的方式，能够增加所述分布式布拉格反射单元50和所述反射层20形成的反射面的面积，从而有利于大幅度地增加所述倒装芯片的所述P型层14的没有被所述反射层20覆盖的区域的反射率，进而提升所述发光二极管的亮度。
优选地，所述外延单元10的所述衬底11为透明衬底，以允许所述有源层13产生的光线能够经由所述衬底11向外界辐射。例如，所述衬底11可以是但不限于蓝宝石衬底。优选地，所述外延单元10的所述N型层12可以是但不限于N型氮化镓层。优选地，所述外延单元10的所述P型层14可以是但不限于P型氮化镓层。
继续参考附图1A和图1B，所述外延单元10具有至少一N型层裸露部15，其中所述N型层裸露部15自所述P型层14的外侧面141经由所述有源层13延伸至所述N型层12，以使得所述N型层12的至少一部分区域被暴露。也就是说，所述N型层12和所述P型层14在所述外延单元10的同一侧均具有暴露面， 以供在后续能够分别被连接于所述N型电极60和所述P型电极70。
优选地，所述N型层12形成所述N型层裸露部15的一部分，即，所述N型层12在对应于所述N型层裸露部15的区域的厚度尺寸小于所述N型层12在对应于所述有源层13的区域的厚度尺寸。也就是说，所述N型层裸露部15自所述P型层14的所述外侧面141经由所述有源层13延伸至所述N型层12的中部。
值得一提的是，在所述外延单元10上形成所述N型层裸露部15的方式在本发明的所述倒装芯片中不受限制。例如，在本发明的所述倒装芯片的一个具体的示例中，可以通过蚀刻工艺在所述外延单元10上形成所述N型层裸露部15。具体地说，首先使用正胶光刻胶对所述外延单元10进行光刻，以使所述外延单元10的需要被蚀刻的区域裸露。在使用正胶光刻胶对所述外延单元10进行光刻时，设定光刻胶厚度为3μm-5μm(包括3μm和5μm)。优选地，在使用正胶光刻胶对所述外延单元10进行光刻后，可以对所述外延单元10进行烘烤。然后，对所述外延单元10的需要被蚀刻的区域进行干法蚀刻，例如，可以利用但不限于电感耦合等离子体机台((Inductive Coupled Plasma Emission Spectrometer，ICP)对所述外延单元10的需要被蚀刻的区域进行干法蚀刻。在对所述外延单元10进行干法蚀刻时使用到的气体可以是氯气(Cl 2)、三氯化硼(BCl 3)、氩气(Ar)。对所述外延单元10进行干法蚀刻的蚀刻深度可以是0.9μm-2μm(包括0.9μm和2μm)，以得到自所述P型层14的所述外侧面141经由所述有源层13延伸至所述N型层12的所述N型层裸露部15。在对所述外延单元10完成蚀刻而在所述外延单元10形成自所述P型层14的所述外侧面141经由所述有源层13延伸至所述N型层12的所述N型层裸露部15之后，去除所述外延单元10的表面的残余的光刻胶，以得到附图1A和图1B示出的所述外延单元10。
当然，本领域技术人员能够理解的是，在本发明的所述倒装芯片的其他可能的示例中，若被提供的所述外延单元10具有自所述P型层14的所述外侧面141经由所述有源层13延伸至所述N型层12的所述N型层裸露部15，则在制造所述倒装芯片的过程中，不需要重新在所述外延单元10形成所述N型层裸露部15。
值得一提的是，所述外延单元10的多个所述N型层裸露部15的类型可以不同，例如在附图1B示出的所述倒装芯片的这个较佳示例中，所述外延单元10包括两种类型的所述N型层裸露部15，其中一种类型的所述N型层裸露部15 的截面呈圆形，其自所述P型层14经所述有源区13延伸至所述N型层12，其中另一种类型的所述N型层裸露部15具有一焊盘裸露部和自所述焊盘裸露部延伸的一扩展条裸露部，所述焊盘裸露部和所述扩展条裸露部均自所述P型层14经所述有源区13延伸至所述N型层12。
参考附图2A和图2B，在所述外延单元10的所述P型层14的所述外侧面141形成所述反射层20。优选地，所述反射层20是银反射层，以提高所述反射层20的反射率，从而保证所述发光二极管的亮度。具体地说，首先在所述外延单元10的所述P型层14确定需要形成所述反射层20的区域，然后在该区域形成所述反射层20，以使所述反射层20被设置在所述P型层14的所述外侧面141。优选地，当在所述外延单元10的所述P型层14确定需要形成所述反射层20的区域后，可以利用沉积的方式在该区域形成所述反射层20，以使所述反射层20被设置在所述P型层14的所述外侧面141。
更具体地说，可以使用负胶在所述外延单元10的所述P型层14光刻出需要沉积的反射层的图形，然后使用蒸镀或者溅射镀膜的方式在光刻出的反射层的图形沉积出所述反射层20，此时，所述反射层20形成在所述外延单元10的所述P型层14的所述外侧面141。例如，在本发明的所述倒装芯片的一个更具体的示例中，可以使用负胶在所述外延单元10的所述P型层14光刻出需要沉积的Mirror结构的图形，然后使用蒸镀或者溅射镀膜的方式在所述外延单元10的所述P型层14的所述外侧面141沉积出一Mirror层。也就是说，在本发明的所述倒装芯片的一个具体的示例中，形成在所述外延单元10的所述P型层14的所述外侧面141的所述反射层20可以是形成在所述外延单元10的所述P型层14的所述外侧面141的所述Mirror层。
优选地，所述反射层20采用银(Ag)和钛钨(TiW)的层叠结构，其中银(Ag)的厚度尺寸为100埃-5000埃(包括100埃和5000埃)，钛钨(TiW)的厚度尺寸为200埃-5000埃(包括200埃和5000埃)。
当使用负胶在所述外延单元10的所述P型层14光刻出需要沉积的反射层的图形，和使用蒸镀或者溅射镀膜工艺在光刻出的反射层的图形沉积出所述反射层20之后，可以对一倒装芯片半成品100进一步处理。例如，首先剥离掉多余的金属层，然后再去除所述倒装芯片半成品100的表面残留的光刻胶。在本发明的所述倒装芯片中，剥离掉所述倒装芯片半成品100的多余的金属层的方式不受限 制，例如可以采用蓝膜工艺剥离掉所述倒装芯片半成品100的表面残留的光刻胶。
参考附图3A和图3B，在所述外延单元10的所述P型层14的所述外侧面141形成所述防扩散层30，所述防扩散层30被电连接于所述P型层14，其中所述防扩散层30包覆所述反射层20，以防止所述反射层20出现迁移的不良现象。优选地，所述防扩散层30完全包覆所述反射层20。也就是说，所述防扩散层30的尺寸的大于所述反射层20的尺寸，以藉由所述防扩散层30阻止所述反射层20的任何一部分区域暴露，从而防止所述反射层20出现迁移的不良现象，以有利于保证所述倒装芯片的可靠性和稳定性。具体地说，首先在所述外延单元10的所述P型层14确定需要形成所述防扩散层20的区域，然后在该区域形成所述防扩散层30，并保证所述防扩散层30完全覆盖所述反射层20。优选地，当在所述外延单元10的所述P型层14确定需要形成所述防扩散层30的区域后，可以利用沉积的方式在该区域形成所述防扩散层30，并保证所述防扩散层30完全覆盖所述反射层20。
更具体地说，可以使用负胶在所述外延单元10的所述P型层14光刻出需要沉积的防扩散层的图形，然后使用蒸镀或者溅射镀膜的方式在光刻出的防扩散层的图形沉积出所述防扩散层30，此时，所述防扩散层30形成在所述外延单元10的所述P型层14的所述外侧面141，并且所述防扩散层30完全覆盖所述反射层20。例如，在本发明的所述倒装芯片的一个更具体的示例中，可以使用负胶在所述外延单元10的所述P型层14的所述外侧面141光刻出需要沉积的Barrier层的图形，然后使用蒸镀或者溅射镀膜的方式在所述外延单元10的所述P型层14的所述外侧面141沉积出完全覆盖所述反射层20的一Barrier层。也就是说，在本发明的所述倒装芯片的一个具体的示例中，形成在所述外延单元10的所述P型层14的所述外侧面141的用于完全覆盖所述反射层20的所述防扩散层30可以是形成在所述外延单元10的所述P型层14的所述外侧面141的用于完全覆盖所述反射层20的所述Barrier层。
优选地，所述防扩散层30是层叠结构，其中形成所述防扩散层30的材料选自：钛钨(TiW)、钛(Ti)、铂(Pt)、铝(Al)、镍(Ni)、金(Au)组成的材料组。具体地说，所述防扩散层30的材料可以选择钛钨(TiW)、钛(Ti)、铂(Pt)、铝(Al)、镍(Ni)、金(Au)中的一种材料，也可以选择钛钨(TiW)、 钛(Ti)、铂(Pt)、铝(Al)、镍(Ni)、金(Au)中的两种以上的材料。
当使用负胶在所述外延单元10的所述P型层14光刻出需要沉积的防扩散层的图形，和使用蒸镀或者溅射镀膜工艺在光刻出的防扩散层的图形沉积出所述防扩散层30之后，可以对所述倒装芯片半成品100进一步处理。例如，首先剥离掉多余的金属层，然后再去除所述倒装芯片半成品100的表面残留的光刻胶。在本发明的所述倒装芯片中，剥离掉所述倒装芯片半成品100的多余的金属层的方式不受限制，例如可以采用蓝膜工艺剥离掉所述倒装芯片半成品100的表面残留的光刻胶。
参考附图4A和图4B，在所述外延单元10的所述N型层12形成被保持在所述N型层裸露部15的内部的所述N电流扩展层40。也就是说，所述N电流扩展层40在所述N型层裸露部15的内部自所述N型层12向所述P型层14方向延伸，并且所述N电流扩展层40电连接于所述N型层12。优选地，所述N电流扩展层40的外侧面41低于所述P型层14的所述外侧面141。更优选地，所述N电流扩展层40的所述外侧面41低于所述有源层13和所述P型层14的接触面。值得一提的是，所述N电流扩展层40的材质在本发明的所述倒装芯片中不受限制，例如所述N电流扩展层40可以是但不限于N电流扩展金属层。
更具体地说，可以使用负胶在所述外延单元10的所述N型层12光刻出需要沉积的N电流扩展层的图形，然后使用蒸镀或者溅射镀膜的方式在光刻出的N电流扩展层的图形沉积出所述N电流扩展层40，其中所述N电流扩展层40的周壁与所述有源层13之间具有安全距离，且所述N电流扩展层40的周壁与所述P型层14之间安全距离，以避免所述N电流扩展层40接触所述有源层13和避免所述N电流扩展层40接触所述P型层14。例如，在本发明的所述倒装芯片的一个更具体的示例中，可以使用负胶在所述外延单元10的所述N型层12光刻出需要沉积的N电流扩展层的图形，然后使用蒸镀或者溅射镀膜的方式在所述N型层12沉积出被保持在所述N型层裸露部15的所述N电流扩展层40。优选地，所述N电流扩展层40的结构为铬(Cr)、铝(Al)、钛(Ti)铂(Pt)金(Au)、镍(Ni)电极结构。也就是说，形成所述N电流扩展层40的材料选自：铬(Cr)、铝(Al)、钛(Ti)铂(Pt)金(Au)、镍(Ni)组成的材料组。具体地说，所述N电流扩展层40的材料可以选择铬(Cr)、铝(Al)、钛(Ti)铂(Pt)金(Au)、镍(Ni)中的一种材料，也可以选择铬(Cr)、铝(Al)、 钛(Ti)铂(Pt)金(Au)、镍(Ni)中的两种以上的材料。
当使用负胶在所述外延单元10的所述N型层12光刻出需要沉积的N电流扩展层的图形，和使用蒸镀或者溅射镀膜工艺在光刻出的N电流扩展层的图形沉积出所述N电流扩展层40之后，可以对所述倒装芯片半成品100进一步处理。例如，首先剥离掉多余的金属层，然后再去除所述倒装芯片半成品100的表面残留的光刻胶。在本发明的所述倒装芯片中，剥离掉所述倒装芯片半成品100的多余的金属层的方式不受限制，例如可以采用蓝膜工艺剥离掉所述倒装芯片半成品100的表面残留的光刻胶。
参考附图5A和图5B，在所述倒装芯片半成品100的表面形成所述分布式布拉格反射单元(Distributed Bragg Reflector，DBR)50，其中所述分布式布拉格反射单元50一体地结合所述N型层12、所述有源层13、所述P型层14、所述防扩散层30和所述N电流扩展层40。也就是说，所述分布式布拉格反射单元50能够填充满所述N型层裸露部15。值得一提的是，在本发明的所述倒装芯片的其他可能的示例中，所述分布式布拉格反射单元50也可以仅一体地结合所述N型层12、所述有源层13、所述防扩散层30和所述N电流扩展层40。
值得一提的是，因为形成在所述P型层14的所述外侧面141的所述反射层20无法覆盖所述P型层14的所述外侧面141的整个区域，这使得所述P型层14的所述外侧面141的至少一部分是不能够反射所述有源层13产生的光线的。在本发明的所述倒装芯片中，所述P型层14的没有被所述反射层20覆盖的区域能够进一步被所述分布式布拉格反射单元50覆盖，以增加所述反射层20形成的反射面和所述分布式布拉格反射单元50形成的反射面的面积，这种方式能够提升所述倒装芯片的反射率，这对于大幅度地提升所述发光二极管的整体亮度是非常重要的。
所述分布式布拉格反射单元50具有至少一N型层通道51和至少一P型层通道52，其中所述N型层通道51对应于所述N电流扩展层40的至少一部分区域，所述P型层通道52对应于所述防扩散层30的至少一部分区域。在后续，形成在所述分布式布拉格反射单元50的外侧面53的所述N型电极60能够经由所述分布式布拉格反射单元50的所述N型层通道51被电连接于所述N电流扩展层40，相应地，形成在所述分布式布拉格反射单元50的所述外侧面53的所述P型电极70能够经由所述分布式布拉格反射单元50的所述P型层通道52被电连 接于所述防扩散层30。
在本发明的所述倒装芯片的一个具体的示例中，可以使用蒸镀方式在所述倒装芯片半成品100的表面形成所述分布式布拉格反射单元50，以使所述分布式布拉格反射单元50能够一体地结合所述N型层12、所述有源层13、所述P型层14、所述防扩散层30和所述N电流扩展层40。优选地，所述分布式布拉格反射单元50使用氧化硅、氧化钛、氟化镁、氧化铪、氧化铝、氮化铝的层叠结构，以提高所述分布式布拉格反射单元50的反射率，从而有利于提高所述发光二极管的整体亮度。具体地说，所述分布式布拉格反射单元50由至少两种折射率的膜层堆叠形成。所述分布式布拉格反射单元50的膜层的材料选自：氧化硅、氧化钛、氟化镁、氧化铪、氧化铝、氮化铝组成的材料组。另外，针对不同的波长可以设计出不同的反射层对，优选地，所述分布式布拉格反射单元50的反射层对在20对-50对(包括20对和50对)之间。
当在所述倒装芯片半成品100的表面形成一体地结合所述N型层12、所述有源层13、所述P型层14、所述防扩散层30和所述N电流扩展层40的所述分布式布拉格反射单元50之后，对所述分布式布拉格反射单元50进行光刻和蚀刻工艺，以形成所述分布式布拉格反射单元50的所述N型层通道51和所述P型层通道52，其中所述N型层通道51延伸至所述N电流扩展层40，以使所述N电流扩展层40的至少一部分区域暴露，相应地，所述P型层通道52延伸至所述防扩散层30，以使所述防扩散层30的至少一部分区域暴露。
具体地说，在本发明的所述倒装芯片的一个具体的示例中，首先使用正胶光刻胶对所述分布式布拉格反射单元50进行光刻，以使所述分布式布拉格反射单元50的需要被蚀刻的区域裸露。然后，利用ICP机台对所述分布式布拉格反射单元50进行蚀刻，以在所述分布式布拉格反射单元50形成所述N型层通道51和所述P型层通道52。
参考附图6A和图6B，在所述分布式布拉格反射单元50的所述外侧面53的不同区域分别形成所述N型电极60和所述P型电极70，其中所述N型电极60经由所述分布式布拉格反射单元50的所述N型层通道51延伸至和被电连接于所述N电流扩展层40，相应地，所述P型电极70经由所述分布式布拉格反射单元50的所述P型层通道52延伸至和被电连接于所述防扩散层30。
具体地说，在本发明的所述倒装芯片的一个具体的示例中，可以通过在所述 分布式布拉格反射单元50的所述外侧面53进行负胶光刻和剥离的方式形成所述N型电极60和所述P型电极70。更具体地说，可以使用负胶在所述分布式布拉格反射单元50的所述外侧面53光刻出需要沉积的电极的图形，然后使用蒸镀或者溅射镀膜的方式在光刻出的电极的图形沉积出所述N型电极60和所述P型电极70，其中所述N型电极60经由所述分布式布拉格反射单元50的所述N型层通道51延伸至和被电连接于所述N电流扩展层40，相应地，所述P型电极70经由所述分布式布拉格反射单元50的所述P型层通道52延伸至和被电连接于所述防扩散层30。当使用负胶在所述分布式布拉格反射单元50的所述外侧面53光刻出需要沉积的电极的图形，和使用蒸镀或者溅射镀膜的工艺在光刻出的电极的图形沉积出所述N型电极60和所述P型电极70之后，可以对所述倒装芯片半成品100进行进一步处理，以得到所述倒装芯片。例如，首先剥离掉多余的金属层，然后再去除所述倒装芯片半成品100的表面残留的光刻胶。在本发明的所述倒装芯片中，剥离掉所述倒装芯片半成品100的多余的金属层的方式不受限制，例如可以采用蓝膜工艺剥离掉所述倒装芯片半成品100的表面残留的光刻胶，以得到所述倒装芯片。
优选地，所述N型电极60和所述P型电极70的结构为铬(Cr)、铝(Al)、钛(Ti)、铂(Pt)、金(Au)、镍(Ni)、金锡(AuSn)电极结构。也就是说，所述N型电极60和所述P型电极70的电极结构的材料选自：铬(Cr)、铝(Al)、钛(Ti)、铂(Pt)、金(Au)、锡(Sn)、镍(Ni)、金锡(AuSn)组成的材料组。具体地说，所述N型电极60和所述P型电极70的电极结构的材料可以选择铬(Cr)、铝(Al)、钛(Ti)、铂(Pt)、金(Au)、锡(Sn)、镍(Ni)、金锡(AuSn)中的一种材料，也可以选择铬(Cr)、铝(Al)、钛(Ti)、铂(Pt)、金(Au)、锡(Sn)、镍(Ni)、金锡(AuSn)中的两种以上的材料。所述N型电极60的厚度尺寸和所述P型电极70的厚度尺寸范围为0μm-7μm(包括7μm)。
也就是说，附图6A和图6B示出了依本发明的一个较佳实施例的所述倒装芯片的具体结构，其中所述倒装芯片包括所述外延单元10、所述反射层20、所述防扩散层30、所述N电流扩展层40、所述分布式布拉格反射单元50、所述N型电极60以及所述P型电极70。所述外延单元10的所述衬底11、所述N型层12、所述有源层13以及所述P型层14被依次层叠地设置，所述外延单元10的 所述N型层裸露部15自所述P型层14的所述外侧面141经由所述有源层13延伸至所述N型层12，以使所述N型层12的至少一部分区域被暴露。所述反射层20形成在所述外延单元10的所述P型层14的所述外侧面141，所述防扩散层30形成在所述外延单元10的所述P型层14的所述外侧面141，并且所述防扩散层30完全覆盖所述反射层20。所述N电流扩展层40被保持在所述外延单元10的所述N型层裸露部15，并且所述N电流扩展层40被电连接于所述外延单元10的所述N型层12。所述分布式布拉格反射单元50一体地结合所述N型层12、所述有源层13、所述P型层14、所述防扩散层30和所述N电流扩展层40，并且所述分布式布拉格反射单元50的所述N型层通道51延伸至所述N电流扩展层40，以使所述N电流扩展层40的一部分区域被暴露，和所述分布式布拉格反射单元50的所述P型层通道52延伸至所述防扩散层30，以使所述防扩散层30的一部分区域被暴露。所述N型电极60形成在所述分布式布拉格反射单元50的所述外侧面53，并且所述N型电极60经由所述分布式布拉格反射单元50的所述N型层通道51延伸至和被电连接于所述N电流扩展层40。所述P型电极70形成在所述分布式布拉格反射单元50的所述外侧面53，并且所述P型电极70经由所述分布式布拉格反射单元50的所述P型层通道52延伸至和被电连接于所述防扩散层30。
当所述N型电极60和所述P型电极70被施加工作电压时，所述外延单元10的所述有源层13能够产生光线，并向四周辐射，其中所述有源层13产生的向所述外延单元10的所述衬底11方向辐射的光线能够直接经由所述衬底11向外界辐射，所述有源层13产生的向所述反射层20方向辐射的光线能够在被所述反射层20反射后经由所述衬底11向外界辐射，同时，所述有源层13产生的向所述分布式布拉格反射单元50方向辐射的光线能够在被所述分布式布拉格反射单元50反射后经由所述衬底11向外界辐射，通过这样的方式，所述倒装芯片的反射率能够被大幅度地提升，从而有利于进一步提升所述发光二极管的整体亮度，这是现有技术的倒装芯片意料之外的。
值得一提的是，在附图1A至图6B示出的所述倒装芯片的所述衬底11、所述N型层12、所述有源层13、所述P型层14、所述反射层20、所述防扩散层30、所述N电流扩展层40、所述分布式布拉格反射层50、所述N型电极60和所述P型电极70的厚度仅为示例，其并不表示所述衬底11、所述N型层12、 所述有源层13、所述P型层14、所述反射层20、所述防扩散层30、所述N电流扩展层40、所述分布式布拉格反射层50、所述N型电极60和所述P型电极70的真实厚度。并且，所述衬底11、所述N型层12、所述有源层13、所述P型层14、所述反射层20、所述防扩散层30、所述N电流扩展层40、所述分布式布拉格反射层50、所述N型电极60和所述P型电极70之间的真实比例也不像附图中示出的那样。另外，所述N型电极60和所述P型电极70的尺寸与所述倒装芯片的其他层的比例也不受限于附图1A至图6B示出的那样。
参考本发明的说明书附图之附图7A至图13B，依本发明的另一较佳实施例一发光二极管的倒装芯片及其制造方法和发光方法在接下来的描述中被揭露和被阐述，其中所述倒装芯片包括一外延单元10A、至少一反射层20A、至少一防扩散层30A、至少一N电流扩展层40A、至少一分布式布拉格反射单元50A、至少一N型电极60A以及至少一P型电极70A。
参考附图7A和图7B，在制造所述倒装芯片的过程中，首先提供所述外延单元10A，以供在后续，在所述外延单元10A上形成所述反射层20A。具体地说，所述外延单元10A包括一衬底11A、一N型层12A、一有源层13A以及一P型层14A，其中所述衬底11A、所述N型层12A、所述有源层13A以及所述P型层14A被依次层叠地设置，以使得所述N型层12A被保持在所述衬底11A和所述有源层13A之间，所述有源层13A被保持在所述N型层12A和所述P型层14A之间。也就是说，所述有源层13A隔离所述N型层12A和所述P型层14A之间，其中当所述N型层12A和所述P型层14A被施加工作电压时，所述有源层13A能够产生光线，并且所述有源层13A产生的光线能够经由所述衬底11A向外界辐射。
优选地，所述外延单元10A的所述衬底11A为透明衬底，以允许所述有源层13A产生的光线能够经由所述衬底11A向外界辐射。例如，所述衬底11A可以是但不限于蓝宝石衬底。优选地，所述外延单元10A的所述N型层12A可以是但不限于N型氮化镓层。优选地，所述外延单元10A的所述P型层14A可以是但不限于P型氮化镓层。
继续参考附图7A和图7B，所述外延单元10A具有至少一N型层裸露部15A，其中所述N型层裸露部15A自所述P型层14A的外侧面141A经由所述有源层13A延伸至所述N型层12A，以使得所述N型层12A的至少一部分区域被暴露。 也就是说，所述N型层12A和所述P型层14A在所述外延单元10A的同一侧均具有暴露面，以供在后续能够分别被连接于所述N型电极60A和所述P型电极70A。
优选地，所述N型层12A形成所述N型层裸露部15A的一部分，即，所述N型层12A在对应于所述N型层裸露部15A的区域的厚度尺寸小于所述N型层12A在对应于所述有源层13A的区域的厚度尺寸。也就是说，所述N型层裸露部15A自所述P型层14A的所述外侧面141A经由所述有源层13A延伸至所述N型层12A的中部。
值得一提的是，在所述外延单元10A上形成所述N型层裸露部15A的方式在本发明的所述倒装芯片中不受限制。例如，在本发明的所述倒装芯片的一个具体的示例中，可以通过蚀刻工艺在所述外延单元10A上形成所述N型层裸露部15A。具体地说，首先使用正胶光刻胶对所述外延单元10A进行光刻，以使所述外延单元10A的需要被蚀刻的区域裸露。在使用正胶光刻胶对所述外延单元10A进行光刻时，设定光刻胶厚度为3μm-5μm(包括3μm和5μm)。优选地，在使用正胶光刻胶对所述外延单元10A进行光刻后，可以对所述外延单元10A进行烘烤。然后，对所述外延单元10A的需要被蚀刻的区域进行干法蚀刻，例如，可以利用但不限于电感耦合等离子体机台((Inductive Coupled Plasma Emission Spectrometer，ICP)对所述外延单元10A的需要被蚀刻的区域进行干法蚀刻。在对所述外延单元10A进行干法蚀刻时使用到的气体可以是氯气(Cl 2)、三氯化硼(BCl 3)、氩气(Ar)。对所述外延单元10A进行干法蚀刻的蚀刻深度可以是0.9μm-2μm(包括0.9μm和2μm)，以得到自所述P型层14A的所述外侧面141A经由所述有源层13A延伸至所述N型层12A的所述N型层裸露部15A。在对所述外延单元10A完成蚀刻而在所述外延单元10A形成自所述P型层14A的所述外侧面141A经由所述有源层13A延伸至所述N型层12A的所述N型层裸露部15A之后，去除所述外延单元10A的表面的残余的光刻胶，以得到附图7A和图7B示出的所述外延单元10A。
当然，本领域技术人员能够理解的是，在本发明的所述倒装芯片的其他可能的示例中，若被提供的所述外延单元10A具有自所述P型层14A的所述外侧面141A经由所述有源层13A延伸至所述N型层12A的所述N型层裸露部15A，则在制造所述倒装芯片的过程中，不需要重新在所述外延单元10A形成所述N 型层裸露部15A。
参考附图8A和图8B，在所述外延单元10A的所述P型层14A的所述外侧面141A形成所述反射层20A。优选地，所述反射层20A是银反射层，以提高所述反射层20A的反射率，从而保证所述发光二极管的亮度。具体地说，首先在所述外延单元10A的所述P型层14A确定需要形成所述反射层20A的区域，然后在该区域形成所述反射层20A，以使所述反射层20A被设置在所述P型层14A的所述外侧面141A。优选地，当在所述外延单元10A的所述P型层14A确定需要形成所述反射层20A的区域后，可以利用沉积的方式在该区域形成所述反射层20A，以使所述反射层20A被设置在所述P型层14A的所述外侧面141A。
更具体地说，可以使用负胶在所述外延单元10A的所述P型层14A光刻出需要沉积的反射层的图形，然后使用蒸镀或者溅射镀膜的方式在光刻出的反射层的图形沉积出所述反射层20A，此时，所述反射层20A形成在所述外延单元10A的所述P型层14A的所述外侧面141A。例如，在本发明的所述倒装芯片的一个更具体的示例中，可以使用负胶在所述外延单元10A的所述P型层14A光刻出需要沉积的Mirror结构的图形，然后使用蒸镀或者溅射镀膜的方式在所述外延单元10A的所述P型层14A的外侧面沉积出一Mirror层。也就是说，在本发明的所述倒装芯片的一个具体的示例中，形成在所述外延单元10A的所述P型层14A的所述外侧面141A的所述反射层20A可以是形成在所述外延单元10A的所述P型层14A的所述外侧面141A的所述Mirror层。
优选地，所述反射层20A采用银(Ag)和钛钨(TiW)的层叠结构，其中银(Ag)的厚度尺寸为100埃-5000埃(包括100埃和5000埃)，钛钨(TiW)的厚度尺寸为200埃-5000埃(包括200埃和5000埃)。
当使用负胶在所述外延单元10A的所述P型层14A光刻出需要沉积的反射层的图形，和使用蒸镀或者溅射镀膜工艺在光刻出的反射层的图形沉积出所述反射层20A之后，可以对一倒装芯片半成品100A进一步处理。例如，首先剥离掉多余的金属层，然后再去除所述倒装芯片半成品100A的表面残留的光刻胶。在本发明的所述倒装芯片中，剥离掉所述倒装芯片半成品100A的多余的金属层的方式不受限制，例如可以采用蓝膜工艺剥离掉所述倒装芯片半成品100A的表面残留的光刻胶。
参考附图9A和图9B，在所述外延单元10A的所述P型层14A的所述外侧 面141A形成所述防扩散层30A，所述防扩散层30A被电连接于所述P型层14A，其中所述防扩散层30A包覆所述反射层20A，以防止所述反射层20A出现迁移的不良现象。也就是说，所述防扩散层30A的尺寸的大于所述反射层20A的尺寸，以藉由所述防扩散层30A阻止所述反射层20A的任何一部分区域暴露，从而防止所述反射层20A出现迁移的不良现象，以有利于保证所述倒装芯片的可靠性和稳定性。具体地说，首先在所述外延单元10A的所述P型层14A确定需要形成所述防扩散层30A的区域，然后在该区域形成所述防扩散层30A，并保证所述防扩散层30A完全覆盖所述反射层20A。优选地，当在所述外延单元10A的所述P型层14A确定需要形成所述防扩散层30A的区域后，可以利用沉积的方式在该区域形成所述防扩散层30A，并保证所述防扩散层30A完全覆盖所述反射层20A。
更具体地说，可以使用负胶在所述外延单元10A的所述P型层14A光刻出需要沉积的防扩散层的图形，然后使用蒸镀或者溅射镀膜的方式在光刻出的防扩散层的图形沉积出所述防扩散层30A，此时，所述防扩散层30A形成在所述外延单元10A的所述P型层14A的所述外侧面141A，并且所述防扩散层30A完全覆盖所述反射层20A。例如，在本发明的所述倒装芯片的一个更具体的示例中，可以使用负胶在所述外延单元10A的所述P型层14A的外侧面光刻出需要沉积的Barrier层的图形，然后使用蒸镀或者溅射镀膜的方式在所述外延单元10A的所述P型层14A的所述外侧面141A沉积出完全覆盖所述反射层20A的一Barrier层。也就是说，在本发明的所述倒装芯片的一个具体的示例中，形成在所述外延单元10A的所述P型层14A的所述外侧面141A的用于完全覆盖所述反射层20A的所述防扩散层30A可以是形成在所述外延单元10A的所述P型层14A的所述外侧面141A的用于完全覆盖所述反射层20A的所述Barrier层。
优选地，所述防扩散层30A是层叠结构，其中形成所述防扩散层30A的材料选自：钛钨(TiW)、钛(Ti)、铂(Pt)、铝(Al)、镍(Ni)、金(Au)组成的材料组。具体地说，所述防扩散层30A的材料可以选择钛钨(TiW)、钛(Ti)、铂(Pt)、铝(Al)、镍(Ni)、金(Au)中的一种材料，也可以选择钛钨(TiW)、钛(Ti)、铂(Pt)、铝(Al)、镍(Ni)、金(Au)中的两种以上的材料。
当使用负胶在所述外延单元10A的所述P型层14A光刻出需要沉积的防扩 散层的图形，和使用蒸镀或者溅射镀膜工艺在光刻出的防扩散层的图形沉积出所述防扩散层30A之后，可以对所述倒装芯片半成品100A进一步处理。例如，首先剥离掉多余的金属层，然后再去除所述倒装芯片半成品100A的表面残留的光刻胶。在本发明的所述倒装芯片中，剥离掉所述倒装芯片半成品100A的多余的金属层的方式不受限制，例如可以采用蓝膜工艺剥离掉所述倒装芯片半成品100A的表面残留的光刻胶。
参考附图10A和图10B，在所述倒装芯片半成品100A的表面形成所述分布式布拉格反射单元(Distributed Bragg Reflector，DBR)50A，其中所述分布式布拉格反射单元50A一体地结合所述N型层12A、所述有源层13A、所述P型层14A以及所述防扩散层30A。因为形成在所述P型层14A的所述外侧面141A的所述反射层20A无法覆盖所述P型层14A的外侧面的整个区域，这使得所述P型层14A的所述外侧面141A的至少一部分是不能反射所述有源层13A产生的光线的。在本发明的所述倒装芯片中，所述P型层14A的没有被所述反射层20A覆盖的区域能够进一步被所述分布式布拉格反射单元50A覆盖，以增加所述反射层20A形成的反射面和所述分布式布拉格反射单元50A形成的反射面的面积，这种方式能够提升所述倒装芯片的反射率，这对于大幅度地提升所述发光二极管的整体亮度是非常重要的。
所述分布式布拉格反射单元50A具有至少一N型层通道51A和至少一P型层通道52A，其中所述N型层通道51A对应于所述N型层12A的一部分区域，所述P型层通道52A对应于所述P型层14A的一部分区域。
在本发明的所述倒装芯片的一个具体的示例中，可以施工蒸镀方式在所述倒装芯片半成品100A的表面形成所述分布式布拉格反射单元50A，以使所述分布式布拉格反射单元50A能够一体地结合所述N型层12A、所述有源层13A、所述P型层14A以及所述防扩散层30A。优选地，所述分布式布拉格反射单元50A使用氧化硅、氧化钛、氟化镁、氧化铪、氧化铝、氮化铝的层叠结构，以提高所述分布式布拉格反射单元50A的反射率，从而有利于提高所述发光二极管的整体亮度。具体地说，所述分布式布拉格反射单元50A由至少两种折射率的膜层堆叠形成。所述分布式布拉格反射单元50A的膜层的材料选自：氧化硅、氧化钛、氟化镁、氧化铪、氧化铝、氮化铝组成的材料组。具体地说，所述分布式布拉格反射单元50A的材料可以选择氧化硅、氧化钛、氟化镁、氧化铪、氧化铝、 氮化铝中的一种材料，也可以选择氧化硅、氧化钛、氟化镁、氧化铪、氧化铝、氮化铝中的两种以上的材料。另外，针对不同的波长可以设计出不同的反射层对，优选地，所述分布式布拉格反射单元50A的反射层对在20对-50对(包括20对和50对)之间。
当在所述倒装芯片半成品100A的表面形成一体地结合所述N型层12A、所述有源层13A、所述P型层14A以及所述防扩散层30A的所述分布式布拉格反射单元50A之后，对所述分布式布拉格反射单元50A进行光刻和蚀刻工艺，以形成所述分布式布拉格反射单元50A的所述N型层通道51A和所述P型层通道52A，其中所述N型层通道51A延伸至所述外延单元10A的所述N型层12A，以使所述N型层12A的至少一部分区域被暴露，和所述P型层通道52A延伸至所述外延单元10A的所述P型层14A，以使所述P型层14A的至少一部分区域被暴露。
具体地说，在本发明的所述倒装芯片的一个具体的示例中，首先使用正胶光刻胶对所述分布式布拉格反射单元50A进行光刻，以使所述分布式布拉格反射单元50A的需要被蚀刻的区域暴露。然后，利用ICP机台对所述分布式布拉格反射单元50A进行蚀刻，以在所述分布式布拉格反射单元50A形成所述N型层通道51A和所述P型层通道52A。
参考附图11A和图11B，在所述分布式布拉格反射单元50A的外侧面53A分别形成相互独立的所述N电流扩展层40A和至少一P电流扩展层80A，其中所述N电流扩展层40A经由所述分布式布拉格反射单元50A的所述N型层通道51A延伸至和被电连接于所述外延单元10A的所述N型层12A，相应地，所述P电流扩展层80A经由所述分布式布拉格反射单元50A的所述P型层通道52A延伸至和被电连接于所述外延单元10A的所述P型层14A。
更具体地说，可以使用负胶在所述分布式布拉格反射单元50A的所述外侧面53A光刻出需要沉积的N电流扩展层的图形和P电流扩展层的图形，然后使用蒸镀或者溅射镀膜的方式在光刻出的N电流扩展层的图形和P电流扩展层的图形分别沉积出所述N电流扩展层40A和所述P电流扩展层80A，其中所述N电流扩展层40A和所述P电流扩展层80A之间具有安全距离。例如，在本发明的所述倒装芯片的一个更具体的示例中，可以使用负胶在所述分布式布拉格反射单元50A的所述外侧面53A光刻出需要沉积N电流扩展层的图形和P电流扩展 层的图形，然后使用蒸镀或者溅射镀膜的方式在N电流扩展层的图形沉积出所述N电流扩展层40A，并且所述N电流扩展层40A经由所述分布式布拉格反射单元50A的所述N型层通道51A延伸至和被电连接于所述外延单元10A的所述N型层12A，和在P电流扩展层的图形沉积出所述P电流扩展层80A，并且所述P电流扩展层80A经由所述分布式布拉格反射单元50A的所述P型层通道52A延伸至和被电连接于所述外延单元10A的所述P型层14A。优选地，所述N电流扩展层40A的结构和所述P电流扩展层80A的结构均为铬(Cr)、铝(Al)、钛(Ti)铂(Pt)金(Au)、镍(Ni)电极结构。也就是说，形成所述N电流扩展层40A和所述P电流扩展层80A的材料均选自：铬(Cr)、铝(Al)、钛(Ti)铂(Pt)金(Au)、镍(Ni)组成的材料组。具体地说，所述N电流扩展层40A和所述P电流扩展层80A的材料可以选择铬(Cr)、铝(Al)、钛(Ti)铂(Pt)金(Au)、镍(Ni)中的一种材料，也可以选择铬(Cr)、铝(Al)、钛(Ti)铂(Pt)金(Au)、镍(Ni)中的两种以上的材料。
当使用负胶在所述分布式布拉格反射单元50A的所述外侧面53A光刻出需要沉积的N电流扩展层的图形和P电流扩展层的通行，和使用蒸镀或者溅射镀膜工艺在光刻出的N电流扩展层和P电流扩展层分别沉积出所述N电流扩展层40A和所述P电流扩展层80A之后，可以对所述倒装芯片半成品100A进一步处理。例如，首先剥离掉多余的金属层，然后再去除所述倒装芯片半成品100A的表面残留的光刻胶。在本发明的所述倒装芯片中，剥离掉所述倒装芯片半成品100A的多余的金属层的方式不受限制，例如可以采用蓝膜工艺剥离掉所述倒装芯片半成品100A的表面残留的光刻胶。
参考附图12A和图12B，在所述倒装芯片半成品100A的外侧形成一绝缘层90A，其中所述绝缘层90A一体地结合所述分布式布拉格反射单元50A、所述N电流扩展层40A和所述P电流扩展层80A。优选地，所述绝缘层90A能够隔离所述N电流扩展层40A和所述P电流扩展层80A。所述绝缘层90A具有至少一第一通道91A和至少一第二通道92A，其中所述N电流扩展层40A的至少一部分区域对应于所述绝缘层90A的所述第一通道91A，以在后续允许所述N型电极60A经由所述绝缘层90A的所述第一通道91A延伸至和被电连接于所述N电流扩展层40A，相应地，所述P电流扩展层80A的至少一部分区域对应于所述绝缘层90A的所述第二通道92A，以在后续允许所述P型电极70A经由所述绝 缘层90A的所述第二通道92A延伸至和被电连接于所述P电流扩展层80A。
优选地，在本发明的所述倒装芯片的一个具体的示例中，可以使用等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)在所述倒装芯片半成品100A的外侧形成所述绝缘层90A，其中使用的气体可以是但不限于甲硅烷(SiH 4)、一氧化二氮(N 2O)、氮气(N 2)。优选地，所述绝缘层90A的厚度尺寸范围为5000埃-20000埃(包括5000埃和20000埃)，以保证所述倒装芯片的可靠性和稳定性。
值得一提的是，在所述绝缘层90A形成所述第一通道91A和所述第二通道92A的方式在本发明的所述倒装芯片中不受限制。例如，在本发明的所述倒装芯片的一个具体的示例中，可以通过蚀刻工艺在所述绝缘层90A上形成所述第一通道91A和所述第二通道92A。具体地说，首先使用正胶光刻胶对所述绝缘层90A进行光刻，以使所述绝缘层90A需要被蚀刻的区域裸露。然后，对所述绝缘层90A的需要被蚀刻的区域进行干法蚀刻，例如，可以利用但不限于ICP机台对所述绝缘层90A的需要被蚀刻的区域进行干法蚀刻，以在所述绝缘层90A形成所述第一通道91A和所述第二通道92A。所述绝缘层90A的材料选自：氧化硅、氮化硅、氮氧化硅、氧化铝、氮化铝组成的材料组。具体地说，所述绝缘层90A可以选择氧化硅、氮化硅、氮氧化硅、氧化铝、氮化铝中的一种材料，也可以选择氧化硅、氮化硅、氮氧化硅、氧化铝、氮化铝中的两种以上的材料。
参考附图13A和图13B，在所述绝缘层90A的外侧面93A的不同区域分别形成相互独立的所述N型电极60A和所述P型电极70A，其中所述N型电极60A经由所述绝缘层90A的所述第一通道91A延伸至和被电连接于所述N电流扩展层40A，相应地，所述P型电极70A经由所述绝缘层90A的所述第二通道92A延伸至和被电连接于所述P电流扩展层80A。
具体地说，在本发明的所述倒装芯片的一个具体的示例中，可以通过在所述绝缘层90A的所述外侧面93A进行负胶光刻和剥离的方式形成所述N型电极60A和所述P型电极70A。更具体地说，可以使用负胶在所述绝缘层90A的所述外侧面93A光刻出需要沉积的电极的图形，然后使用蒸镀或者溅射镀膜的方式在光刻出的电极的图形沉积出所述N型电极60A和所述P型电极70A，其中所述N型电极60A经由所述绝缘层90A的所述第一通道91A延伸至和被电连接于所述N电流扩展层40A，相应地，所述P型电极70A经由所述绝缘层90A的 所述第二通道92A延伸至和被电连接于所述P电流扩展层80A。当使用负胶在所述绝缘层90A的外侧面光刻出需要沉积的电极的图形，和使用蒸镀或者溅射镀膜的工艺在光刻出的电极的图形沉积出所述N型电极60A和所述P型电极70A之后，可以对所述倒装芯片半成品100A进行进一步处理，以得到所述倒装芯片。例如，首先剥离掉多余的金属层，然后再去除所述倒装芯片半成品100A的表面残留的光刻胶。在本发明的所述倒装芯片中，剥离掉所述倒装芯片半成品100A的多余的金属层的方式不受限制，例如可以采用蓝膜工艺剥离掉所述倒装芯片半成品100A的表面残留的光刻胶，以得到所述倒装芯片。
优选地，所述N型电极60A和所述P型电极70A的结构为铬(Cr)、铝(Al)、钛(Ti)、铂(Pt)、金(Au)、镍(Ni)、金锡(AuSn)电极结构。也就是说，所述N型电极60A和所述P型电极70A的电极结构的材料选自：铬(Cr)、铝(Al)、钛(Ti)、铂(Pt)、金(Au)、锡(Sn)、镍(Ni)、金锡(AuSn)组成的材料组。具体地说，所述N型电极60A和所述P型电极70A的电极结构的材料可以选择铬(Cr)、铝(Al)、钛(Ti)、铂(Pt)、金(Au)、锡(Sn)、镍(Ni)、金锡(AuSn)中的一种材料，也可以选择铬(Cr)、铝(Al)、钛(Ti)、铂(Pt)、金(Au)、锡(Sn)、镍(Ni)、金锡(AuSn)中的两种以上的材料。所述N型电极60A的厚度尺寸和所述P型电极70A的厚度尺寸范围为0μm-7μm(包括7μm)。
也就是说，附图13A和图13B示出了依本发明的一个较佳实施例的所述倒装芯片的具体结构，其中所述倒装芯片包括所述外延单元10A、所述反射层20A、所述防扩散层30A、所述N电流扩展层40A、所述P电流扩展层80A、所述分布式布拉格反射单元50A、所述N型电极60A以及所述P型电极70A。所述外延单元10A的所述衬底11A、所述N型层12A、所述有源层13A以及所述P型层14A被依次层叠地设置，所述外延单元10A的所述N型层裸露部15A自所述P型层14A的所述外侧面141A经由所述有源层13A延伸至所述N型层12A，以使所述N型层12A的至少一部分区域被暴露。所述反射层20A形成在所述外延单元10A的所述P型层14A的所述外侧面141A，所述防扩散层30A形成在所述外延单元10A的所述P型层14A的所述外侧面141A，并且所述防扩散层30A完全覆盖所述反射层20A。所述分布式布拉格反射单元50A一体地结合于所述N型层12A、所述有源层13A、所述P型层14A和所述防扩散层30A，并 且所述N型层12A的至少一部分区域对应于所述分布式布拉格反射单元50A的所述N型层通道51A，所述P型层14A的至少一部分区域对应于所述分布式布拉格反射单元50A的所述P型层通道52A。所述N电流扩展层40A形成于所述分布式布拉格反射单元50A，并且所述N电流扩展层40A经由所述分布式布拉格反射单元50A的所述N型层通道51A延伸至和被电连接于所述N型层12A。相应地，所述P电流扩展层80A形成于所述分布式布拉格反射单元50A，并且所述P电流扩展层80A经由所述分布式布拉格反射单元50A的所述P型层通道52A延伸至和被电连接于所述P型层14A。所述N电流扩展层40A和所述P电流扩展层80A具有安全距离。所述绝缘层90A一体地结合于所述分布式布拉格反射单元50A、所述N电流扩展层40A和所述P电流扩展层80A，其中所述N电流扩展层40A对应于所述绝缘层90A的所述第一通道91A，所述P电流扩展层80A对应于所述绝缘层90A的所述第二通道92A。所述绝缘层90A进一步隔离所述N电流扩展层40A和所述P电流扩展层80A。所述N型电极60A形成于所述绝缘层90A，并且所述N型电极60A经由所述绝缘层90A的所述第一通道91A延伸至和被电连接于所述N电流扩展层40A。所述P型电极70A形成于所述绝缘层90A，并且所述P型电极70A经由所述绝缘层90A的所述第二通道92A延伸至和被电连接于所述P电流扩展层80A。所述N型电极60A和所述P型电极70A相互独立。
当所述N型电极60A和所述P型电极70A被施加工作电压时，所述外延单元10A的所述有源层13A能够产生光线，并向四周辐射，其中所述有源层13A产生的向所述外延单元10A的所述衬底11A方向辐射的光线能够直接经由所述衬底11A向外界辐射，所述有源层13A产生的向所述反射层20A方向辐射的光线能够在被所述反射层20A反射后经由所述衬底11A向外界辐射，同时，所述有源层13A产生的向所述分布式布拉格反射单元50A方向辐射的光线能够在被所述分布式布拉格反射单元50A反射后经由所述衬底11A向外界辐射，通过这样的方式，所述倒装芯片的反射率能够被大幅度地提升，从而有利于进一步提升所述发光二极管的整体亮度，这是现有技术的倒装芯片意料之外的。
值得一提的是，在附图7A至图13B示出的所述倒装芯片的所述衬底11A、所述N型层12A、所述有源层13A、所述P型层14A、所述反射层20A、所述防扩散层30A、所述N电流扩展层40A、所述分布式布拉格反射层50A、所述N 型电极60A、所述P型电极70A、所述P电流扩展层80A以及和所述绝缘层90A的厚度仅为示例，其并不表示所述衬底11A、所述N型层12A、所述有源层13A、所述P型层14A、所述反射层20A、所述防扩散层30A、所述N电流扩展层40A、所述分布式布拉格反射层50A、所述N型电极60A、所述P型电极70A、所述P电流扩展层80A和所述绝缘层90A的真实厚度。并且，所述衬底11A、所述N型层12A、所述有源层13A、所述P型层14A、所述反射层20A、所述防扩散层30A、所述N电流扩展层40A、所述分布式布拉格反射层50A、所述N型电极60A、所述P型电极70A、所述P电流扩展层80A和所述绝缘层90A之间的真实比例也不像附图中示出的那样。另外，所述N型电极60A和所述P型电极70A的尺寸与所述倒装芯片的其他层的比例也不受限于附图7A至图13B示出的那样。
依本发明的另一个方面，本发明进一步提供一发光二极管的倒装芯片的制造方法，其中所述制造方法包括如下步骤：
(a)在一外延单元10的一P型层14的外侧面141形成至少一反射层20；
(b)藉由至少一分布式布拉格反射单元50覆盖所述P型层14的所述外侧面141的未被所述反射层覆盖的区域；以及
(c)电连接一P型电极70于所述P型层14，和电连接一N型电极60于所述外延单元10的一N型层12，以制得所述倒装芯片。
依本发明的另一个方面，本发明进一步提供一发光二极管的倒装芯片的发光方法，其中所述发光方法包括如下步骤：
(A)施加工作电压于所述倒装芯片的一N型电极60和一P型电极70，以使所述倒装芯片的一有源层13产生光线；
(B)允许所述有源层13产生的向所述倒装芯片的一衬底11方向辐射的光线在穿过所述衬底11后向所述倒装芯片的外界辐射；
(C)藉由至少一反射层20反射所述有源层13产生的向所述倒装芯片的一P型层14方向辐射的光线，以使被反射的光线在穿过所述衬底11后向所述倒装芯片的外界辐射；以及
(D)藉由至少一分布式布拉格反射单元50反射所述有源层13产生的向所述P型层14方向辐射的光线，以使被反射的光线在穿过所述衬底11后向所述倒装芯片的外界辐射。
本领域的技术人员可以理解的是，以上实施例仅为举例，其中不同实施例的特征可以相互组合，以得到根据本发明揭露的内容很容易想到但是在附图中没有明确指出的实施方式。
本领域的技术人员应理解，上述描述及附图中所示的本发明的实施例只作为举例而并不限制本发明。本发明的目的已经完整并有效地实现。本发明的功能及结构原理已在实施例中展示和说明，在没有背离所述原理下，本发明的实施方式可以有任何变形或修改。

Claims (37)

  1. 一发光二极管的倒装芯片，其特征在于，包括：
    至少一反射层；
    至少一N型电极；
    至少一P型电极；
    至少一分布式布拉格反射单元；以及
    一外延单元，其中所述外延单元包括一衬底、一N型层、一有源层以及一P型层，所述衬底、所述N型层、所述有源层和所述P型层被依次层叠地设置，并且所述外延单元具有至少一N型层裸露部，所述N型层裸露部自所述P型层的外侧面经由所述有源层延伸至所述N型层，其中所述反射层形成于所述P型层，所述分布式布拉格反射单元一体地结合于所述N型层、所述有源层、所述P型层以及所述反射层，其中所述N型电极被电连接于所述N型层，所述P型电极被电连接于所述P型层。
  2. 根据权利要求1所述的倒装芯片，进一步包括一防扩散层，其中所述防扩散层形成于所述P型层，并且所述防扩散层包覆所述反射层的至少一部分区域，其中所述分布式布拉格反射单元一体地结合于所述防扩散层。
  3. 根据权利要求2所述的倒装芯片，其中所述反射层是银反射层，所述防扩散层完全包覆所述反射层。
  4. 根据权利要求3所述的倒装芯片，其中所述防扩散层被电连接于所述P型层，所述P型电极以所述P型电极被电连接于所述防扩散层的方式被电连接于所述P型层。
  5. 根据权利要求4所述的倒装芯片，进一步包括至少一N电流扩展层，其中所述N电流扩展层以所述N电流扩展层被保持在所述外延单元的所述N型层裸露部的方式被电连接于所述N型层，其中所述N型电极以所述N型电极被电连接于所述N电流扩展层的方式被电连接于所述N型层，其中所述分布式布拉格反射单元一体地结合于所述N电流扩展层。
  6. 根据权利要求5所述的倒装芯片，其中所述分布式布拉格反射单元具有至少一N型层通道和至少一P型层通道，其中所述N电流扩展层对应于所述N型层通道，所述N型电极形成于所述分布式布拉格反射单元，并且所述N型电 极经由所述N型层通道延伸至所述N电流扩展层，其中所述防扩散层对应于所述P型层通道，所述P型电极形成于所述分布式布拉格反射单元，并且所述P型电极经由所述P型层通道延伸至所述防扩散层。
  7. 根据权利要求5所述的倒装芯片，其中所述N电流扩展层自所述N型层向所述P型层方向延伸。
  8. 根据权利要求1所述的倒装芯片，进一步包括至少一N电流扩展层和至少一P电流扩展层，其中所述分布式布拉格反射单元具有至少一N型层通道和至少一P型层通道，其中所述N型层对应于所述N型层通道，所述N电流扩展层形成于所述分布式布拉格反射单元，并且所述N电流扩展层经由所述N型层通道延伸至所述N型层，且所述N电流扩展层被电连接于所述N型层，所述N型电极以所述N型电极被电连接于所述N电流扩展层的方式被电连接于所述N型层，其中所述P型层对应于所述P型层通道，所述P电流扩展层形成于所述分布式布拉格反射单元，并且所述P电流扩展层经由所述P型层通道延伸至所述P型层，并且所述P电流扩展层被电连接于所述P型层，所述P型电极以所述P型电极被电连接于所述P电流扩展层的方式被电连接于所述P型层。
  9. 根据权利要求2至4中任一所述的倒装芯片，进一步包括至少一N电流扩展层和至少一P电流扩展层，其中所述分布式布拉格反射单元具有至少一N型层通道和至少一P型层通道，其中所述N型层对应于所述N型层通道，所述N电流扩展层形成于所述分布式布拉格反射单元，并且所述N电流扩展层经由所述N型层通道延伸至所述N型层，且所述N电流扩展层被电连接于所述N型层，所述N型电极以所述N型电极被电连接于所述N电流扩展层的方式被电连接于所述N型层，其中所述P型层对应于所述P型层通道，所述P电流扩展层形成于所述分布式布拉格反射单元，并且所述P电流扩展层经由所述P型层通道延伸至所述P型层，并且所述P电流扩展层被电连接于所述P型层，所述P型电极以所述P型电极被电连接于所述P电流扩展层的方式被电连接于所述P型层。
  10. 根据权利要求9所述的倒装芯片，进一步包括至少一绝缘层，所述绝缘层具有至少一第一通道和至少一第二通道，其中所述绝缘层形成于所述N电流扩展层和所述P电流扩展层，并且所述第一通道对应于所述N电流扩展层，和所述第二通道对应于所述P电流扩展层，其中所述N型电极经由所述绝缘层的 所述第一通道被电连接于所述N电流扩展层，所述P型电极经由所述绝缘层的所述第二通道被电连接于所述P电流扩展层。
  11. 根据权利要求10所述的倒装芯片，其中所述绝缘层结合于所述分布式布拉格反射单元，以藉由所述绝缘层隔离所述N电流扩展层和所述P电流扩展层。
  12. 根据权利要求10所述的倒装芯片，其中所述N型电极形成于所述绝缘层，并且所述N型电极经由所述绝缘层的所述第一通道延伸至所述N电流扩展层，其中所述P型电极形成于所述绝缘层，并且所述P型电极经由所述绝缘层的所述第二通道延伸至所述P电流扩展层。
  13. 根据权利要求1至12中任一所述的倒装芯片，其中所述分布式布拉格反射单元由至少两种折射率的膜层堆叠形成。
  14. 根据权利要求13所述的倒装芯片，其中所述分布式布拉格反射单元的膜层材料选自：氧化硅、氧化钛、氟化镁、氧化铪、氧化铝、氮化铝组成的材料组。
  15. 根据权利要求2至7、9至12中任一所述的倒装芯片，其中所述防扩散层的材料选自：钛钨、钛、铂、铝、镍、金组成的材料组。
  16. 根据权利要求5至12中任一所述的倒装芯片，其中所述N电流扩展层的材料选自：铬、铝、钛、铂、金、镍组成的材料组。
  17. 根据权利要求8至12中任一所述的倒装芯片，其中所述P电流扩展层的材料选自：铬、铝、钛、铂、金、镍组成的材料组。
  18. 根据权利要求1至12中任一所述的倒装芯片，其中所述N型电极和所述P型电极的电极材料选自：铬、铝、钛、铂、金、锡、镍、金锡组成的材料组。
  19. 根据权利要求1至12中任一所述的倒装芯片，其中所述N型层是N型氮化镓层，所述P型层是P型氮化镓层。
  20. 根据权利要求10至12中任一所述的倒装芯片，其中所述绝缘层的材料选自：氧化硅、氮化硅、氮氧化硅、氧化铝、氮化铝组成的材料组。
  21. 根据权利要求1至12中任一所述的倒装芯片，其中所述反射层的结构是银和钛钨的层叠结构。
  22. 根据权利要求21所述的倒装芯片，其中所述反射层的银层的厚度尺寸范围为：100埃-5000埃，其中所述反射层的钛钨层的厚度尺寸范围为：200埃-5000 埃。
  23. 根据权利要求1至22中任一所述的倒装芯片，其中所述分布式布拉格反射单元的厚度尺寸范围为：0μm-7μm。
  24. 一发光二极管的倒装芯片的制造方法，其特征在于，所述制造方法包括如下步骤：
    (a)在一外延单元的一P型层的外侧面形成至少一反射层；
    (b)藉由至少一分布式布拉格反射单元覆盖所述P型层的所述外侧面的未被所述反射层覆盖的区域；以及
    (c)电连接一P型电极于所述P型层，和电连接一N型电极于所述外延单元的一N型层，以制得所述倒装芯片。
  25. 根据权利要求24所述的制造方法，其中在所述步骤(b)之前，进一步包括步骤：形成一防扩散层于所述P型层的所述外侧面，其中所述防扩散层包覆所述反射层，并且所述防扩散层被电连接于所述P型层，从而在所述步骤(c)中，所述P型电极以所述P型电极被电连接于所述防扩散层的方式被电连接于所述P型层。
  26. 根据权利要求25所述的制造方法，其中在所述步骤(b)之前，进一步包括步骤：形成一N电流扩展层于所述N型层，其中所述N电流扩展层被电连接于所述N型层，从而在所述步骤(c)中，所述N型电极以所述N型电极被电连接于所述N电流扩展层的方式被电连接于所述N型层。
  27. 根据权利要求26所述的制造方法，其中在所述步骤(b)中，以所述分布式布拉格反射单元一体地结合于所述P型层、所述防扩散层和所述N电流扩展层的方式使所述分布式布拉格反射单元覆盖所述P型层的所述外侧面的未被所述反射层覆盖的区域，其中所述分布式布拉格反射单元具有对应于所述N电流扩展层的至少一N型层通道和对应于所述防扩散层的至少一P型层通道，所述N型电极经由所述N型层通道被电连接于所述N电流扩展层，所述P型电极经由所述P型层通道被电连接于所述防扩散层。
  28. 根据权利要求27所述的制造方法，其中在上述方法中，形成所述N型电极于所述分布式布拉格反射单元，以使所述N型电极经由所述N型层通道延伸至所述N电流扩展层，形成所述P型电极于所述分布式布拉格反射单元，以使所述P型电极经由所述P型层通道延伸至所述防扩散层。
  29. 根据权利要求25所述的制造方法，其中在所述步骤(b)中，以所述分布式布拉格反射单元一体地形成于所述P型层、所述防扩散层和所述N电流扩展层的方式使所述分布式布拉格反射单元覆盖所述P型层的所述外侧面的未被所述反射层覆盖的区域，其中所述分布式布拉格反射单元具有对应于所述N型层的至少一N型层通道和对应于所述P型层的至少一P型层通道，所述N型电极经由所述N型层通道被电连接于所述N型层，所述P型电极经由所述P型层通道被电连接于所述P型层。
  30. 根据权利要求29所述的制造方法，其中在上述方法中，进一步包括步骤：
    形成至少一N电流扩展层于所述分布式布拉格反射单元，并且所述N电流扩展层经由所述N型层通道延伸至所述N型层，且所述N电流扩展层被电连接于所述N型层，其中所述N型电极被电连接于所述N电流扩展层；和
    形成至少一P电流扩展层于所述分布式布拉格反射单元，并且所述P电流扩展层经由所述P型层通道延伸至所述P型层，并且所述P电流扩展层被电连接于所述P型层，其中所述P型电极被电连接于所述P电流扩展层。
  31. 根据权利要求30所述的制造方法，其中在上述方法中，进一步包括步骤，形成一绝缘层于所述N电流扩展层、所述P电流扩展层和所述分布式布拉格反射单元，其中所述绝缘层具有对应于所述N电流扩展层的至少一第一通道和对应于所述P电流扩展层的至少一第二通道，所述N型电极经由所述第一通道被电连接于所述N电流扩展层，所述P型电极经由所述第二通道被电连接于所述P电流扩展层。
  32. 根据权利要求31所述的制造方法，其中在上述方法中，形成所述N型电极于所述绝缘层，以使所述N型电极经由所述第一通道延伸至所述N电流扩展层，形成所述P型电极于所述绝缘层，以使所述P型电极经由所述第二通道延伸至所述P电流扩展层。
  33. 一发光二极管的倒装芯片的发光方法，其特征在于，所述发光方法包括如下步骤：
    (A)施加工作电压于所述倒装芯片的一N型电极和一P型电极，以使所述倒装芯片的一有源层产生光线；
    (B)允许所述有源层产生的向所述倒装芯片的一衬底方向辐射的光线在穿 过所述衬底后向所述倒装芯片的外界辐射；
    (C)藉由至少一反射层反射所述有源层产生的向所述倒装芯片的一P型层方向辐射的光线，以使被反射的光线在穿过所述衬底后向所述倒装芯片的外界辐射；以及
    (D)藉由至少一分布式布拉格反射单元反射所述有源层产生的向所述P型层方向辐射的光线，以使被反射的光线在穿过所述衬底后向所述倒装芯片的外界辐射。
  34. 根据权利要求33所述的发光方法，其中所述反射层覆盖所述P型层的外侧面的一部分区域，所述分布式布拉格反射单元覆盖所述P型层的外侧面的另一部分区域，从而在所述步骤(C)和所述步骤(D)中，所述反射层和所述分布式布拉格反射单元均能够反射所述有源层产生的向所述P型层方向辐射的光线。
  35. 根据权利要求34所述的发光方法，其中所述分布式布拉格反射单元由至少两种折射率的膜层堆叠形成。
  36. 根据权利要求34所述的发光方法，其中所述分布式布拉格反射单元的膜层材料选自：氧化硅、氧化钛、氟化镁、氧化铪、氧化铝、氮化铝组成的材料组。
  37. 根据权利要求34所述的发光方法，其中所述分布式布拉格反射单元的厚度尺寸范围为：0μm-7μm。
PCT/CN2018/097778 2018-04-26 2018-07-31 发光二极管的倒装芯片及其制造方法和发光方法 WO2019205328A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/626,517 US11621380B2 (en) 2018-04-26 2018-07-31 Flip-chip of light emitting diode and manufacturing method and illuminating method thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201820604683.5 2018-04-26
CN201820604683.5U CN208797027U (zh) 2018-04-26 2018-04-26 发光二极管的倒装芯片
CN201810382603.0 2018-04-26
CN201810382603.0A CN110416380A (zh) 2018-04-26 2018-04-26 发光二极管的倒装芯片及其制造方法和发光方法

Publications (1)

Publication Number Publication Date
WO2019205328A1 true WO2019205328A1 (zh) 2019-10-31

Family

ID=68293724

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/097778 WO2019205328A1 (zh) 2018-04-26 2018-07-31 发光二极管的倒装芯片及其制造方法和发光方法

Country Status (2)

Country Link
US (1) US11621380B2 (zh)
WO (1) WO2019205328A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102565148B1 (ko) * 2018-06-27 2023-08-18 서울바이오시스 주식회사 플립칩형 발광 다이오드 칩 및 그것을 포함하는 발광 장치
CN112951954B (zh) * 2021-01-28 2023-03-24 湘能华磊光电股份有限公司 一种发光二极管芯片及其制作工艺

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103828073A (zh) * 2011-09-16 2014-05-28 首尔伟傲世有限公司 发光二极管及制造该发光二极管的方法
CN104681704A (zh) * 2015-01-30 2015-06-03 大连德豪光电科技有限公司 倒装led芯片及其制备方法
CN105609612A (zh) * 2012-05-14 2016-05-25 新世纪光电股份有限公司 半导体发光元件及覆晶式封装元件

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103828073A (zh) * 2011-09-16 2014-05-28 首尔伟傲世有限公司 发光二极管及制造该发光二极管的方法
CN105609612A (zh) * 2012-05-14 2016-05-25 新世纪光电股份有限公司 半导体发光元件及覆晶式封装元件
CN104681704A (zh) * 2015-01-30 2015-06-03 大连德豪光电科技有限公司 倒装led芯片及其制备方法

Also Published As

Publication number Publication date
US11621380B2 (en) 2023-04-04
US20200251632A1 (en) 2020-08-06

Similar Documents

Publication Publication Date Title
US11942568B2 (en) Light-emitting diode device and method for manufacturing the same
US7812421B2 (en) Light emitting devices with an electrically active top reflector contact
CN104471727B (zh) 半导体发光器件
TW201807840A (zh) 微型發光二極體及其製造方法
CN111446336A (zh) 发光二极管
WO2014122709A1 (ja) 半導体装置およびその製造方法
KR20160046538A (ko) 발광 소자 및 그 제조 방법
US20080217634A1 (en) Vertical light-emitting diode structure with omni-directional reflector
US11637223B2 (en) Light emitting diode device
US20230387354A1 (en) Optoelectronic semiconductor chip
WO2017219818A1 (zh) 发光二极管及其制作方法
WO2019205328A1 (zh) 发光二极管的倒装芯片及其制造方法和发光方法
TW202036939A (zh) 發光二極體及其製造方法
KR20220128967A (ko) 발광 다이오드
US20220140203A1 (en) Flip-chip light-emitting diode
JP2012529170A (ja) 発光半導体装置及び製造方法
US10396248B2 (en) Semiconductor light emitting diode
CN102082216A (zh) 一种发光二极管芯片及其制造方法
KR101371545B1 (ko) 반도체 발광소자
US20220069170A1 (en) Light-emitting device and method for manufacturing the same
CN113782658B (zh) 发光半导体及其制备方法
TWI455377B (zh) 發光二極體結構及其製作方法
CN113555482A (zh) 发光元件及其制造方法
CN112510133A (zh) 发光二极管芯片、发光二极管及发光二极管芯片制备方法
CN219716889U (zh) 一种倒装mini LED芯片

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18916641

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18916641

Country of ref document: EP

Kind code of ref document: A1