WO2019201316A1 - Procédé et dispositif de codage et de décodage de données, système olt, onu et pon - Google Patents

Procédé et dispositif de codage et de décodage de données, système olt, onu et pon Download PDF

Info

Publication number
WO2019201316A1
WO2019201316A1 PCT/CN2019/083308 CN2019083308W WO2019201316A1 WO 2019201316 A1 WO2019201316 A1 WO 2019201316A1 CN 2019083308 W CN2019083308 W CN 2019083308W WO 2019201316 A1 WO2019201316 A1 WO 2019201316A1
Authority
WO
WIPO (PCT)
Prior art keywords
payload
length
fec
codeword structure
data blocks
Prior art date
Application number
PCT/CN2019/083308
Other languages
English (en)
Chinese (zh)
Inventor
高波
景磊
聂世玮
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2019201316A1 publication Critical patent/WO2019201316A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H04B10/516—Details of coding or modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used

Definitions

  • the present application relates to the field of optical communications, and more particularly to a data encoding and decoding method, a data encoding and decoding apparatus, an optical line terminal, an optical network unit, and a PON system in a PON system.
  • Passive Optical Network (PON) technology is a point-to-multipoint fiber access technology.
  • the PON system may include an Optical Line Terminal (OLT), an Optical Distribution Network (ODN), and at least one Optical Network Unit (ONU).
  • OLT is connected to the ODN, and the ODN is connected to multiple ONUs.
  • EPON is a technology that uses passive optical transmission.
  • FEC Forward error correction
  • FEC means that the signal is processed in a certain way before being transmitted, and at the receiving end, it is decoded according to the corresponding algorithm to achieve the purpose of finding the wrong code and correcting the error.
  • the basic working principle of the FEC in the EPON system is to add an FEC check part to the information data transmitted by the transmitting end, and the check parts and the verified information data are related to each other by a certain rule (constrained).
  • the receiving end checks the relationship between the information data and the check part according to the established rules. Once an error occurs in the transmission, the relationship is destroyed, and the receiving end automatically finds and corrects the wrong code word.
  • the length of the uplink burst information data sent by the ONU to the OLT is variable.
  • the length of the information data is too short, it is insufficient to generate a complete codeword.
  • the prior art is not very good. Support for this situation.
  • the present application provides a data encoding and decoding method, a data encoding and decoding apparatus, a precoding indicating method and apparatus, an optical line terminal, an optical network unit, and a PON system in a PON system, which are intended to be more capable of Good support for the transmission of uplink data of too short length.
  • the first aspect provides a data encoding method in a PON system.
  • the executing entity may be an ONU in the PON system.
  • the ONU sends uplink burst data to the OLT, and the ONU first encodes the burst data.
  • the physical coding sublayer is executed, and different codeword structures can be generated according to the number of received first data blocks.
  • One of the codeword structures is a shortening code, and the method includes: receiving, at the physical coding sublayer, S first data blocks, each first data block having a length of M bits; M*S being less than a forward error correction coding
  • the FEC payload length of the FEC pattern can be used to generate a shortening code.
  • the shortening code can be applied to the case of inputting various numbers of first data blocks, and the rate of input and output can be kept constant, and the implementation is simple, and can be applied to shortening codes of various lengths.
  • each third data block is generated by data transcoding of t*M bits, t>1, and each third data block has a length of N bits
  • the method includes: at the physical coding sublayer Receiving Q3 first data blocks, M*Q3 ⁇ FEC payload length, and Q3 ⁇ Q1; expanding the Q3 first data blocks in the physical coding sublayer, so that the total length of the expanded data is equal to Q1*M; Transcoding the extended data to generate Q2 third data blocks; performing FEC encoding on the Q2 third data blocks according to the FEC pattern to generate a third check portion; and generating a second codeword structure in the physical coding sublayer,
  • the second codeword structure includes a third payload and a third non-payload portion, the third payload includes Q2 third data blocks, the length of the third payload is equal to the FEC payload length, and the third non-payload portion includes the The third check portion and the third sync flag, the length of the third non-payload portion being an integer multiple of
  • the extended manner may be adopted, so that the data length satisfies the condition for generating the non-shortened code, thereby generating the second code word structure. Therefore, the coding mode can be further applied to all cases (that is, regardless of the number of first data blocks, an applicable coding mode can be found in the above three coding modes), thereby ensuring that the FEC pattern can not only
  • the shortening codes applicable to the above various lengths can also be applied to non-shortening codes at the same time, and the coding flexibility is improved. The combination of the above three coding modes can effectively ensure the efficiency of coding and maximize the bandwidth efficiency.
  • the synchronization flag (including the first synchronization flag, the second synchronization flag, and the third synchronization identifier) may be located at a payload (including the first payload, the second payload, and the third payload) and a check portion (including the foregoing Between a check part, a second check part and a third check part, it is advantageous to identify the code word as a shortened code or a non-shortened code in the process of synchronizing the code words by the OLT, and can further realize fast synchronization.
  • At least two of the first synchronization flag, the second synchronization flag, and the third synchronization flag have the same length. Therefore, when the shortening code and the non-shortening code are identified, a similar synchronization mechanism can be adopted, which is more convenient for synchronization, and is advantageous for achieving fast synchronization.
  • the three sync IDs can be the same length.
  • At least two of the first synchronization flag, the second synchronization flag, and the third synchronization identifier have the same value. Therefore, when the shortening code and the non-shortening code are identified, the same synchronization mechanism can be adopted, which is more convenient for synchronization, and is more advantageous for achieving fast synchronization.
  • the values of the three synchronization identifiers can be the same.
  • the lengths of at least two of the first check portion, the second check portion, and the third check portion may be the same, so that when the shortening code and the non-shortening code are identified, the same synchronization mechanism can be adopted, which is more convenient for synchronization, and more Conducive to fast synchronization.
  • the lengths of the three check sections can be the same.
  • the length of the first payload is equal to the sum of the lengths of the S first data blocks, that is, the first payload is composed only of S first data blocks;
  • the length of the second payload is equal to the sum of the lengths of the Q2 second data blocks That is, the second payload consists only of Q2 second data blocks.
  • the length of the third payload is equal to the sum of the lengths of the Q2 third data blocks, that is, the third payload is composed only of Q2 third data blocks.
  • the length of the first non-payload portion is greater than or equal to the sum of the lengths of the first synchronization flag and the first check portion, and the remaining bits in the first non-payload portion except the first synchronization flag and the first check portion Can be used for other indication purposes;
  • the length of the second non-payload portion is greater than or equal to the sum of the lengths of the second synchronization flag and the second verification portion, and the second non-payload portion except the second synchronization flag and the second parity
  • the remaining bits can be used for other indication purposes.
  • the length of the third non-payload portion is greater than or equal to the sum of the lengths of the third sync flag and the third check portion, and the remaining bits in the third non-payload portion except the third sync flag and the third check portion Can be used for other indication purposes.
  • At least two of the first non-payload portion, the second non-payload portion, and the third non-payload portion are of equal length to facilitate fast synchronization.
  • the three non-payload portions are all the same length.
  • M is equal to 66 or 65, N is equal to 129 or 257; or, M is equal to 129, and N is equal to 257.
  • the FEC pattern is any one of LDPC (19789, 16962), LDPC (20046, 16962), LDPC (20303, 16962), and LDPC (20560, 16962).
  • a second aspect provides a data decoding method in a PON system.
  • the execution entity may be an OLT in a PON system, and the ONU sends uplink burst data to the OLT, and is decoded by the OLT.
  • the decoding method is performed by a physical coding sublayer.
  • a forward error correction coding FEC pattern corresponds to the FEC payload length, the FEC payload length is an integer multiple of M, and the length of the first payload is less than the FEC payload length; Identifying, by the physical coding sublayer, the first codeword structure according to the first synchronization flag; extracting the first payload and the first parity portion in the physical coding sublayer; and selecting, according to the FEC pattern and the first verification part, the physical coding sublayer Forward error correction decoding is performed on the first payload.
  • the shortening code can be applied to the case of inputting various numbers of first data blocks, all of which can ensure the input and output rates are constant, and the implementation is simple, and can be applied to shortening codes of various lengths.
  • the method further includes: receiving, at the physical coding sublayer, a second codeword structure, where the second codeword structure includes a second payload and a second non-payload portion, and the second non-net
  • the load portion includes a second check portion and a second synchronization flag
  • the second payload includes a plurality of second data blocks, each of the second data blocks has a length of N bits, and N>M, and the length of the second payload is equal to FEC a payload length
  • the second non-payload portion is an integer multiple of M
  • the second codeword structure is identified according to the second synchronization flag at the physical coding sublayer
  • the second payload and the second parity portion are extracted at the physical coding sublayer
  • the FEC payload length is also an integer multiple of M, thereby ensuring that the FEC pattern can be applied not only to the above
  • receiving the first codeword structure includes: receiving a code stream in the physical coding sublayer, where the code stream includes a burst delimiter and a first codeword structure, or The code stream includes a burst delimiter, a first codeword structure and a second codeword structure; identifying the first codeword structure according to the first synchronization flag comprises: after the burst delimiter or after the second check portion, each Interval M bits, identify whether there is a first synchronization flag at the current interval position, and count the current number of times of identification or the total number of bits of the current interval; after each recognition of the presence of the first synchronization flag, if the current statistics are recognized The product of M is less than the FEC payload length, or if the current total number of bits is less than the FEC payload length, it is determined that the currently identified codeword is the first codeword structure. With this synchronization mechanism, the OLT side can identify shortening codes
  • the P-bit is separated to identify whether there is a terminator, wherein the difference between the first non-payload length and the length of the first synchronization flag is P bits; if there is a terminator, it is determined that the currently recognized codeword is The first code word structure.
  • receiving the second codeword structure includes: receiving a code stream in the physical coding sublayer, the code stream includes a burst delimiter and a second codeword structure, or the code stream includes a burst delimiter, a first codeword structure and a second codeword structure; identifying the second codeword structure according to the second synchronization flag comprises: after identifying the burst delimiter or the second check portion, each interval of M bits, at the current interval The location identifies whether there is a second synchronization flag at a time, and counts the current number of times of identification or the total number of bits of the current interval; after each second synchronization flag is recognized, if the product of the current statistical recognition number and M is equal to the FEC payload length, Or if the total number of bits currently counted is equal to the FEC payload length, it is determined that the currently identified codeword is the second codeword structure.
  • the OLT side can further identify the non-shortened code.
  • the current statistical recognition number or the total number of current statistics is cleared to zero, thereby facilitating the OLT to continue the new round of recognition; the currently identified second synchronization flag
  • the first codeword structure or the second codeword structure is further identified; wherein the difference between the first non-payload length and the length of the first synchronization flag is P bits.
  • a third aspect provides a data encoding apparatus in a PON system, where the apparatus may be applied to an ONU to send uplink special transmission data to an OLT.
  • the apparatus may include: a receiving module, an FEC encoding module, a generating module, and may further include Code module.
  • An extension module can also be included.
  • a receiving module configured to receive S first data blocks, each first data block has a length of M bits, and M*S is smaller than a FEC payload length of a forward error correction code FEC pattern;
  • a shortening code can be generated.
  • the FEC encoding module performs FEC encoding on the first data blocks according to the FEC pattern to generate a first check portion, and the FEC payload length is an integer multiple of M; then the generating module generates a first codeword structure, where the first codeword structure includes a first payload and a first non-payload portion, the first payload includes S first data blocks, the length of the first payload is less than the FEC payload length; and the first non-payload portion includes the first check portion and the first A synchronization flag, the length of the first payload and the first non-payload portion are both integer multiples of M.
  • the shortening code can be applied to the case of inputting various numbers of first data blocks, and the rate of input and output can be kept constant, and the implementation is simple, and can be applied to shortening codes of various lengths.
  • a non-short code can also be called a full code, or a full code.
  • the non-shortening code can be divided into two cases.
  • the receiving module is further configured to receive Q1 first data blocks, M*Q1>FEC payload length; and the transcoding module transcodes the Q1 first data blocks.
  • FEC encoding module FEC encoding the second data block according to the FEC pattern to generate a second check portion; the generating module generates a second code word structure, the second code
  • the word structure includes a second payload and a second non-payload portion, the second payload includes Q2 second data blocks, the length of the second payload is equal to the FEC payload length, and the second non-payload portion includes the second parity
  • the partial and second synchronization flags, the length of the second non-payload portion is an integer multiple of M.
  • the FEC payload length is also an integer multiple of M. It can be applied to the case of inputting any number of first data blocks, no matter what the number of first data blocks input, can find a suitable coding mode correspondingly, thereby ensuring that the FEC pattern can be applied not only to the above
  • the shortening codes of various lengths can also be applied to non-shortened codes at the same time, which improves the flexibility of coding.
  • the receiving module is further configured to receive Q3 first data blocks, M*Q3 ⁇ FEC payload length, and Q3 ⁇ Q1; and an expansion module, configured to expand Q3 first data blocks. Processing, so that the total length of the extended data is equal to Q1*M; the transcoding module is further configured to transcode the extended data to generate Q2 third data blocks; the forward error correction coding code module is further used according to the FEC code Performing FEC encoding on the Q2 third data blocks to generate a third check portion; the generating module is further configured to generate a second codeword structure, where the second codeword structure includes a third payload and a third non-payload portion, and a third The payload includes Q2 third data blocks, the length of the third payload is equal to the FEC payload length; the third non-payload portion includes the third check portion and the third synchronization flag, and the length of the third non-payload portion is M Integer multiple.
  • the extended manner may be adopted, so that the data length satisfies the condition for generating the non-shortened code, thereby generating the second code word structure. Therefore, the coding mode can be further applied to all cases (that is, regardless of the number of the first data blocks, one can find a suitable coding mode among the above three coding modes), and the coding flexibility is improved. The combination of the above three coding modes can effectively ensure the efficiency of coding and maximize the bandwidth efficiency.
  • a fourth aspect provides a data decoding apparatus in a PON system.
  • the apparatus includes: a receiving module, configured to receive a first codeword structure, where the first codeword structure includes a first payload And a first non-payload portion, the first non-payload portion includes a first check portion and a first synchronization flag, the first payload includes at least one first data block, each first data block having a length of M bits
  • the lengths of the first payload and the first non-payload portion are all integer multiples of M.
  • a forward error correction coding FEC pattern corresponds to an FEC payload length, and the FEC payload length is an integer multiple of M.
  • the length of the first payload is smaller than the length of the FEC payload;
  • the synchronization module is configured to identify the first codeword structure according to the first synchronization flag;
  • the extraction module is configured to extract the first payload and the first verification portion;
  • the erroneous coding and decoding module is configured to perform forward error correction decoding on the first payload according to the FEC pattern and the first check portion.
  • an ONU may include a processing module, which may be a MAC (Media Access Control) chip, or a processor, or a DSP (digital signal processor).
  • the processing module receives S first data blocks in a physical coding sublayer, each first data block has a length of M bits, and M*S is smaller than a FEC payload length of a forward error correction coding FEC pattern; FEC net The length of the load is an integer multiple of M; the first coding part is generated by performing FEC coding on the S first data blocks according to the FEC pattern at the physical coding sublayer; and the first codeword structure is generated in the physical coding sublayer, the first codeword
  • the structure includes a first payload and a first non-payload portion, the first payload includes S first data blocks, the length of the first payload is less than the FEC payload length; and the first non-payload portion includes the first check portion And the first synchronization flag, the lengths of the first payload and the first non-
  • the sixth aspect provides an OLT, where the OLT can include a processing module, which can be a MAC (Media Access Control) chip, or a processor, or a DSP (digital signal processor). Wait.
  • the processing module receives a first codeword structure at a physical coding sublayer, the first codeword structure includes a first payload and a first non-payload portion, and the first non-payload portion includes a first parity portion and a first synchronization flag
  • the first payload includes at least one first data block, each first data block has a length of M bits, and the lengths of the first payload and the first non-payload portion are integer multiples of M, a forward direction
  • the error correction coding FEC pattern is correspondingly provided with an FEC payload length, the FEC payload length is an integer multiple of M, the length of the first payload is smaller than the FEC payload length, and the first code is identified according to the first synchronization flag at the physical coding sublayer.
  • the shortening code can be applied to the case of inputting various numbers of first data blocks, all of which can ensure the input and output rates are constant, and the implementation is simple, and can be applied to shortening codes of various lengths.
  • protection themes between the above aspects are different, but the specific implementation details may be referred to each other. Some protection topics do not specifically describe the implementation details, and other various topics may be referred to.
  • an ONU comprising the apparatus of the third aspect above.
  • an OLT comprising the apparatus of the above fourth aspect.
  • a codeword structure is provided, the codeword structure being the first codeword structure described above.
  • a codeword structure is provided, the codeword structure being the second codeword structure described above.
  • a codeword structure is provided, the codeword structure being the third codeword structure described above.
  • the details of the synchronization flag, the specific details of the data block, the specific details of the FEC pattern, and the specific details of the code word structure may be referred to other aspects, and are not described herein.
  • a MAC chip comprising the apparatus of the third or fourth aspect described above.
  • a PON system comprising the optical line terminal of the fifth aspect and the optical network unit of the sixth aspect.
  • a computer readable storage medium storing computer software instructions for use in the apparatus of the third or fourth aspect, or an ONU for storing the fifth aspect of the above
  • Computer software instructions, or computer software instructions for storing the OLT of the sixth aspect described above when executed on a computer, cause the computer to perform the methods of the above aspects.
  • FIG. 1 is a schematic structural diagram of a PON system according to an embodiment of the present application.
  • FIG. 2 is an exemplary flowchart of a data encoding and decoding method for a shortened code according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of shortening code generation according to an embodiment of the present application.
  • FIG. 4 is an exemplary flowchart of a data encoding and decoding method for a non-shortened code according to an embodiment of the present application
  • FIG. 5(a) is a schematic diagram of data block transcoding according to an embodiment of the present application.
  • FIG. 5(b) is another schematic diagram of data block transcoding according to an embodiment of the present application.
  • FIG. 5(c) is still another schematic diagram of data block transcoding according to an embodiment of the present application.
  • FIG. 5(d) is still another schematic diagram of data block transcoding according to an embodiment of the present application.
  • FIG. 5(e) is still another schematic diagram of data block transcoding according to an embodiment of the present application.
  • FIG. 5(f) is still another schematic diagram of data block transcoding according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of generating a non-short code according to an embodiment of the present application.
  • FIG. 7 is another exemplary flowchart of a data encoding and decoding method for a non-shortened code according to an embodiment of the present application.
  • FIG. 8 is another schematic diagram of generating a non-short code according to an embodiment of the present application.
  • FIG. 9 is an exemplary flowchart of a synchronization mechanism of an OLT according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of hardware of an ONU according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of hardware of an OLT according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of an exemplary functional module of a data encoding apparatus according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of an exemplary functional block of a data decoding apparatus according to an embodiment of the present application.
  • EPON Ethernet Passive Optical Networks
  • 10G EPON single wave 25G EPON, 2x25G EPON, single wave 50G EPON, 2x50G EPON.
  • 100G EPON and so on It can also be used in various Gigabit Passive Optical Networks (GPON).
  • GPON Gigabit Passive Optical Networks
  • the PON system 100 includes at least one OLT 110, at least one ODN 120, and a plurality of ONUs 130.
  • the OLT 110 provides a network side interface for the PON system 100
  • the ONU 130 provides a user side interface for the PON system 100 to be connected to the ODN 120.
  • the ONU 130 directly provides the user port function, it is called an Optical Network Terminal (ONT).
  • ONT Optical Network Terminal
  • the ONU 130 mentioned below generally refers to an ONT that can directly provide a user port function and an ONU that provides a user side interface.
  • the ODN 120 is a network of optical fibers and passive optical splitting devices for connecting OLT 110 devices and ONUs 130 devices for distributing or multiplexing data signals between the OLT 110 and the ONUs 130.
  • the direction from the OLT 110 to the ONU 130 is defined as the downstream direction, and the direction from the ONU 130 to the OLT 110 is defined as the upstream direction.
  • the OLT 110 broadcasts the downlink data to the multiple ONUs 130 managed by the OLT 110 by using a Time Division Multiplexing (TDM) method.
  • TDM Time Division Multiplexing
  • Each ONU 130 only receives data carrying its own identity;
  • the ONUs 130 communicate with the OLT 110 in a Time Division Multiple Access (TDMA) manner, and each ONU 130 transmits uplink data according to the time domain resources allocated by the OLT 110.
  • TDMA Time Division Multiple Access
  • the downlink optical signal sent by the OLT 110 is a continuous optical signal
  • the upstream optical signal sent by the ONU 130 is a burst optical signal.
  • the OLT 110 is typically located at a Central Office (CO), and can centrally manage at least one ONU 130 and transfer data between the ONU 130 and an upper layer network.
  • the OLT 110 can serve as a medium between the ONU 130 and an upper layer network such as the Internet, a Public Switched Telephone Network (PSTN), and forward data received from the upper layer network to the ONU 130, and The data received from the ONU 130 is forwarded to the upper layer network.
  • CO Central Office
  • PSTN Public Switched Telephone Network
  • the OLT 110 may vary depending on the particular type of the PON system 100, for example, in one embodiment, the OLT 110 may include a transmitter and a receiver for transmitting a downlink continuous optical signal to the ONU 130, the receiver for receiving an uplink burst optical signal from the ONU 130, wherein the downlink optical signal and the uplink optical signal can be transmitted through the ODN 120.
  • the OLT 110 may include a transmitter and a receiver for transmitting a downlink continuous optical signal to the ONU 130, the receiver for receiving an uplink burst optical signal from the ONU 130, wherein the downlink optical signal and the uplink optical signal can be transmitted through the ODN 120.
  • embodiments of the present application are not limited thereto.
  • the ONU 130 can be distributed in a user-side location (such as a customer premises).
  • the ONU 130 can be a network device for communicating with the OLT 110 and the user, in particular, the ONU 130 can act as a medium between the OLT 110 and the user, for example, the ONU 130 can receive data from the OLT 110. Forwarded to the user and forwarded data received from the user to the OLT 110.
  • the ODN 120 can be a data distribution network that can include fiber optics, optocouplers, beamsplitters, or other devices.
  • the fiber, optocoupler, splitter, or other device may be a passive optical device, in particular, the fiber, optocoupler, optical splitter, or other device may be at OLT 110 and ONU 130 Devices that do not require power supply when distributing data signals.
  • the optical splitter can be connected to the OLT 110 through a trunk optical fiber and connected to the plurality of ONUs 130 through a plurality of branch optical fibers, thereby implementing between the OLT 110 and the ONU 130. Point-to-multipoint connection.
  • the ODN 120 may also include one or more processing devices, such as optical amplifiers or relay devices.
  • the ODN 120 may be specifically extended from the OLT 110 to the plurality of ONUs 130, but may be configured as any other point-to-multipoint structure. The embodiment of the present application is not limited thereto.
  • the technical solution of the embodiment of the present application described below may be that the ONU 130 performs FEC encoding to generate a codeword structure, and sends the codeword structure to the OLT 110, and the OLT 110 decodes the codeword structure.
  • the OLT and the ONU may include a processing module, which may be a MAC (Media Access Control) chip, or a processor, or a DSP (digital signal processor).
  • a processing module which may be a MAC (Media Access Control) chip, or a processor, or a DSP (digital signal processor).
  • the operation at the Physical Coding Sublayer (PCS) is performed by the processing module.
  • PCS Physical Coding Sublayer
  • the following is an example of an operation of performing a physical coding sublayer by a MAC chip.
  • the codeword structure sent by the ONU to the OLT can be divided into a non-short code and a shortening code.
  • the FEC code type used by the ONU and the OLT is provided with the FEC codeword length and the FEC payload length, indicating that the length of the check portion is equal to the FEC codeword length minus the FEC payload in the codeword structure encoded by the FEC pattern. length.
  • the FEC pattern may be a Low Density Parity Check Code (LDPC), for example, may be LDPC (19789, 16962), LDPC (20046, 16962), LDPC (20303, 16962), LDPC (20560, In any of 16962), the FEC pattern is not limited to the ones listed above, nor is it limited to the LDPC pattern. It can be understood that the FEC pattern can also adopt other expressions, and can indicate the FEC codeword length and the FEC payload length.
  • LDPC Low Density Parity Check Code
  • the FEC pattern adopted by the ONU and the OLT is LDPC (20560, 16962).
  • the FEC pattern indicates that the FEC payload length is 16962, and the FEC codeword length is 20560, indicating that the length is less than or equal to 16962 bits.
  • the codeword structure is called a non-short code. If the payload length in the codeword structure is less than the FEC payload length (16962 bits), and the check portion length in the codeword structure is the difference between the FEC codeword length and the FEC payload length (3598 bits), the codeword structure The total length is less than the FEC codeword length of 20560 bits, and the codeword structure is called a shortening code.
  • the physical coding sublayer receives the input data block (the length may be 66 bits or 65 bits), taking the received data block length as 66 bits as an example.
  • the input data block refers to the data content that needs to be transmitted.
  • a data block of length 66 bits may be transcoded first. For example, every 2 data blocks of length 66 bits may be transcoded into a data length of 129 bits. Block, or, every 4 data blocks of length 66 bits can be transcoded into a data block of length 257 bits, and then the transcoded data block is FEC-encoded to generate a codeword structure.
  • the FEC pattern is LDPC (20560, 16962), and the length of the transcoded data block is 257 bits.
  • the multiplication sign is represented by "*".
  • the number of 66-bit data blocks sent by the ONU to the OLT may be exactly equal to 264, or exactly equal to an integer multiple of 264.
  • transcoding processing is performed first, and then FEC encoding generates a codeword structure, ONU.
  • the codeword structure sent to the OLT is a non-short code.
  • the number of 66-bit data blocks sent by the ONU to the OLT may also be less than or equal to 256.
  • the total length of the 66-bit data block is less than 16962, and the transcoding process may not be performed at this time.
  • the bit data block is FEC encoded to generate one shortening code.
  • the ONU can send a shortening code to the OLT; or the total number of 66-bit data blocks sent by the ONU to the OLT is greater than 264, but the total number is divided by 264. The remainder is less than or equal to 256.
  • the ONU sends at least one non-short code and one shortening code to the OLT.
  • 264 66-bit data blocks can be transcoded.
  • a non-short code is generated, and the remaining 100 66b data blocks are not transcoded, and FEC encoding is performed to generate a shortening code, and the ONU can send a non-short code and a shortening code to the OLT.
  • the number of 66-bit data blocks sent by the ONU to the OLT may also be equal to 257.
  • the total length of the 66-bit data block is equal to 16962.
  • the transcoding process is performed first, and then the transcoding is performed. After the data block is extended, the total length of the extended data is equal to 16962, and then FEC encoding is performed to generate a non-shortened code, and the ONU can send a non-shortened code to the OLT; another implementation manner is that no transcoding is performed.
  • the FCS encoding of the 66b data block directly generates a non-shortened code, and the payload of the non-shortened code is the above 257 66-bit data blocks, and the ONU can send a non-shortened code to the OLT.
  • the total number of 66-bit data blocks sent by the ONU to the OLT is greater than 264, but the total number divided by the remainder of 264 is equal to 257. For example, if the total number is 521, then 264 66-bit bits may be used.
  • the data block is transcoded, and the non-shortened code is generated after FEC encoding.
  • the remaining 257 66-bit data blocks are transcoded, then extended, and then FEC encoded to generate a non-shortened code.
  • the ONU can send 2 to the OLT.
  • the number of 66-bit data blocks sent by the ONU to the OLT may also be greater than 257 and less than 264.
  • the total number of 66-bit data blocks sent by the ONU to the OLT is greater than 264, but the total number is divided by 264.
  • the specific details are the same as above, and will not be described here.
  • the shortening code includes one encoding mode
  • the non-shortening code is specifically divided into two encoding modes.
  • the three encoding modes will be specifically described below with reference to the accompanying drawings.
  • the first codeword structure refers to a shortening code.
  • the following embodiments refer to the non-shortened codes in the two coding modes as the second codeword structure and the third codeword structure, respectively.
  • a data encoding and decoding method is provided, including steps S200 to S206, and specific implementation manners of each step are as follows:
  • the ONU receives S first data blocks in the physical coding sublayer, where S is an integer.
  • S is an integer.
  • Each first data block has a length of M bits.
  • the total length of the S first data blocks is less than the FEC payload length, and the FEC payload length is an integer multiple of M.
  • the first data block can be a 64B/66B or 64B/65B data block.
  • the data block of 64B/66B means that the total length of the data block is 66 bits, which contains 64 bits of data, and there are 2 bits of indication information for indicating whether the 64-bit data in the data block is data information or control information.
  • the 2-bit indication information may be located at the head or the tail of the data block.
  • the data block of 64B/65B means that the total length of the data block is 65 bits, which contains 64 bits of data, and there is 1 bit of indication information for indicating whether 64-bit data in the data block is data information or Control information.
  • the 1-bit indication information may be located at the head or the tail of the data block.
  • the length of the first data block may also be other lengths, which is not limited herein.
  • the ONU performs FEC encoding on the first data blocks according to the FEC pattern at the physical coding sublayer to generate a first check portion.
  • the total length of the S first data blocks is smaller than the FEC payload length, and the S first data blocks are not sufficient to constitute a non-short code, and the shortening code may be configured.
  • the S first data blocks may not be transcoded, and the S first data blocks may be directly FEC encoded, that is, the S first data blocks may be directly transmitted to the FEC encoder.
  • the FEC payload length is an integer multiple of M.
  • the ONU generates a first codeword structure in the physical coding sublayer, where the first codeword structure includes a first payload and a first non-payload portion.
  • the first payload includes S first data blocks, and the length of the first payload is smaller than the FEC payload length, wherein the first payload may include only S first data blocks, or the first payload may further include S The first data block and other parts of the use (such as the precoding enable indication part, etc.).
  • the first non-payload portion includes a first check portion and a first sync flag, and the first non-payload portion is an integer multiple of M.
  • the first non-payload portion may include only the first check portion and the first synchronization flag, or the first non-payload portion may further include the first check portion and the first synchronization flag, and portions for other purposes ( Such as precoding enable indication part, etc.).
  • FIG. 3 it is a schematic diagram of shortening code generation in an embodiment of the present application.
  • the FEC pattern Take the FEC pattern as LDPC (20560, 16962) as an example.
  • the synchronization flag is used, or the remaining 32b can be partially used as a synchronization flag, and the rest is used for other purposes (such as a precoding enable indication, etc.).
  • 56 or more numbers of 66b placeholder blocks may be added.
  • the remaining bits may be used as synchronization flags or other purposes.
  • the OLT receives the first codeword structure in a physical coding sublayer.
  • the OLT identifies, in the physical coding sublayer, the first codeword structure according to the first synchronization flag.
  • the OLT may pre-store the synchronization sequence, traverse the pre-stored synchronization sequence in the received codeword structure until the synchronization flag in the codeword structure matches the pre-stored synchronization sequence, and the identification is completed.
  • the forward error correction decoding here corresponds to the foregoing forward error correction coding, and the same expression can be used, for example, the forward error correction decoding method is LDPC (19789, 16962), LDPC (20046, 16962), LDPC (20303, 16962), LDPC (20560, 16962). Taking LDPC (20560, 16962) as an example, the OLT uses the 3598-bit check data field to perform forward error correction decoding on the payload. For specific details, reference may be made to the foregoing description of the forward error correction coding, and details are not described herein again.
  • the first codeword structure is a shortening code
  • the first payload in the shortened code includes S first data blocks, which is an integer multiple of M
  • the first non-payload portion is also an integer multiple of M. Therefore, the shortening code can be applied to the case of inputting various numbers of first data blocks, and the number of added placeholder blocks can be constant, and the rate of input and output can be kept constant, and the implementation is simple, and can be applied to various types. Shortening code for length.
  • the first coding and decoding mode of the non-shortened code is taken as an example.
  • the method further includes steps S300 to S307.
  • the specific implementation manner of each step is as follows:
  • the ONU receives Q1 first data blocks in the physical coding sublayer, and the total length of the Q1 first data blocks is greater than the FEC payload length;
  • the ONU transcodes the Q1 first data blocks in the physical coding sublayer to generate Q2 second data blocks, and Q1>Q2, each second data block has a length of N bits, and N>M;
  • the ONU performs FEC encoding on the Q2 second data blocks according to the FEC pattern at the physical coding sublayer to generate a second check portion.
  • the ONU generates a second codeword structure in the physical coding sublayer.
  • the second codeword structure includes a second payload and a second non-payload portion, where the second payload includes Q2 second data blocks, and the second payload
  • the length is equal to the FEC payload length; the second non-payload portion includes the second check portion and the second synchronization flag, and the second non-payload portion is an integer multiple of M.
  • 64B/66B data block transcoded into 128B/129B data blocks As shown in Fig. 5(a) to Fig. 5(d), every two 64B/66B data blocks are transcoded into one 128B/129B data block.
  • the data blocks of 64B/66B are divided into two types, one is a data block carrying data information, and the other is a data block carrying control information.
  • the 2-bit indication information in the data block is “01”, indicating that 64 bits of the data block are data information; the 2-bit indication information in the data block is “10”. ", indicating that 64 bits of the data block are control information.
  • Fig. 5(a) shows that two blocks of 64B/66B carrying data information are transcoded into one 128B/129B data block.
  • the two-bit indication information of the two 64B/66B data blocks can be separately removed, and the 1-bit indication information is added to the 128-bit data type carried by the transcoded data block (including two types of data information and control information). ).
  • DB1 (64) and DB2 (64) respectively represent 64-bit data information in two data blocks.
  • FIG. 5(b) shows that two blocks of 64B/66B carrying control information are transcoded into one 128B/129B data block.
  • the 64B/66B data block carrying the control information includes 4 bits of S1(4), and 4 bits of S1(4) in one of the data blocks can be deleted, and 2 bits of 2 64B/66B data blocks are reserved. Indicate the information and add another 1 bit.
  • the arrangement rule of each information in the transcoded 129-bit data block can be set according to actual needs to achieve interworking. Taking FIG. 5(b) as an example, an additional 1 bit is placed in the header of the data block, and then 2 bits of information information of 2 64B/66B data blocks are respectively, and then 4 bits of S1(4) are removed.
  • the control information in the data block of 64B/66B is then the control information in the 64B/66B data block of S1(4) which does not remove 4 bits. It can be understood that other ways can also be arranged.
  • FIG. 5(c) shows that one 64B/66B data block carrying control information and one 64B/66B data block carrying data information are transcoded into one 128B/129B data block.
  • the 64B/66B data block carrying the control information includes 4 bits of S1(4), and the 4-bit S1(4) in the data block can be deleted, and the 2-bit indication of the two 64B/66B data blocks is reserved. Information, and add another 1 bit.
  • the arrangement rule of each information in the transcoded 129-bit data block can be set according to actual needs to achieve interworking. Taking FIG.
  • an additional 1 bit is placed in the header of the data block, followed by 2-bit indication information carrying the control information and the 64B/66B data block carrying the data information, and then removing the 4 bits.
  • the control information in the 64B/66B data block of S1(4) is then the data information in the 64B/66B data block carrying the data information. It can be understood that other ways can also be arranged.
  • FIG. 5(d) shows that one 64B/66B data block carrying data information and one 64B/66B data block carrying control information are transcoded into one 128B/129B data block.
  • the additional 1 bit is placed in the data block header, and then is the 2-bit indication information carrying the data information and the 64B/66B data block carrying the control information, and then carrying the data information.
  • the data information in the 64B/66B data block is then removed for control information in the 64-bit/BB block of the 4-bit S1(4). It can be understood that other ways can also be arranged.
  • Figure 5(e) shows that two blocks of 64B/65B carrying data information are transcoded into one 128B/129B data block.
  • the 1-bit indication information of the two 64B/65B data blocks can be separately removed, and the 1-bit indication information is added to the 128-bit data type carried by the transcoded data block (including two types of data information and control information). ).
  • DB1 (64) and DB2 (64) respectively represent 64-bit data information in two data blocks.
  • Figure 5(f) shows that four blocks of 64B/65B carrying data information are transcoded into one 256B/257B data block.
  • the 1-bit indication information of the four 64B/65B data blocks can be separately removed, and the 1-bit indication information is added to convert the 256-bit data type carried by the transcoded data block (including two types of data information and control information). ).
  • DB1 (64), DB2 (64), DB3 (64), and DB4 (64) respectively represent 64-bit data information among four data blocks.
  • every 4 64B/66B data blocks are transcoded into one 256B/257B data block.
  • the specific transcoding principle is similar to the above, and can be effectively retained.
  • the data information and the control information are removed from the indication information or S1(4), and one or more bits may be additionally added.
  • the transcoded data block does not lose valid data, and the total number of bits is 256B.
  • FIG. 6 is a schematic diagram of non-short code generation in an embodiment of the present application.
  • the FEC pattern as LDPC (20560, 16962) as an example.
  • the first data block is a data block of length 66b
  • the second data block length after transcoding is 257b as an example.
  • the codeword structure includes the payload of 16962b, the second checksum of 3598b, the remaining 32b can all be used as the synchronization flag, or the remaining 32b can be partially used as the synchronization flag, and the rest is used. For other purposes (such as precoding enable instructions, etc.).
  • 49 or more numbers of 66b placeholder blocks may be added.
  • the remaining bits may be used as synchronization flags or other purposes. For other FEC patterns, the principle is the same as above, and will not be described here.
  • the OLT receives the second codeword structure in the physical coding sublayer.
  • the OLT identifies the second codeword structure according to the second synchronization flag at the physical coding sublayer.
  • the OLT may pre-store the synchronization sequence, traverse the pre-stored synchronization sequence in the received codeword structure until the synchronization flag in the codeword structure matches the pre-stored synchronization sequence, and the identification is completed.
  • the second codeword structure is a non-shortened code
  • the FEC payload length is also an integer multiple of M, thereby ensuring that the FEC pattern can be applied not only to the shortening code but also to the non-shortened code. Increased coding flexibility.
  • the coding mode of the non-shortened code may also be adopted, as shown in FIG.
  • the method of encoding and decoding, the method further includes steps S400 to S408, and the specific implementation manner of each step is as follows:
  • the ONU receives Q3 first data blocks in the physical coding sublayer, and Q3 ⁇ Q1, and the total length of the Q3 first data blocks is greater than or equal to the FEC payload length;
  • the ONU performs the extension processing on the Q3 first data blocks in the physical coding sublayer, so that the total length of the expanded data is equal to Q1*M;
  • the FEC pattern Take the FEC pattern as LDPC (20560, 16962) as an example.
  • the first data block is an example of a data block of length 66b.
  • Q3*66 ⁇ 16962, that is, Q3 ⁇ 257, Q1 is equal to 264, and Q3 ⁇ 264.
  • the extended data length is (Q1-Q3)*M.
  • the ONU transcodes the extended data in the physical coding sublayer to generate Q2 third data blocks, each third data block has a length of N bits, and N>M;
  • the ONU performs FEC encoding on the Q2 third data blocks according to the FEC pattern at the physical coding sublayer to generate a fourth check portion.
  • the ONU generates a third codeword structure in the physical coding sublayer, where the third codeword structure includes a third payload and a third non-payload portion, and the third payload includes Q2 third data blocks, and the third payload
  • the length is equal to the FEC payload length; the third non-payload portion includes the third check portion and the third synchronization flag, and the third non-payload portion is an integer multiple of M.
  • FIG. 8 is a schematic diagram of non-short code generation in another embodiment of the present application.
  • the FEC pattern as LDPC (20560, 16962) as an example.
  • the first data block is a data block of length 66b
  • the length of the third data block is 257b as an example.
  • Q3 is equal to 260 as an example.
  • the data of the 17424b is transcoded, which is the same as above, and will not be described here.
  • 66 third data blocks are obtained.
  • the codeword structure includes the payload of 16962b, the third checksum of 3598b, the remaining 32b can all be used as the synchronization flag, or the remaining 32b can be partially used as the synchronization flag, and the rest is used. For other purposes (such as precoding enable instructions, etc.). In addition, 49 or more number of 66b placeholder blocks may be added. In addition to the 16962b payload and the 3598b third check portion in the codeword structure, the remaining bits may be used as synchronization flags or other purposes. For other FEC patterns, the principle is the same as above, and will not be described here.
  • the OLT receives the third codeword structure in the physical coding sublayer.
  • the OLT identifies, in the physical coding sublayer, a third codeword structure according to the third synchronization flag.
  • the OLT may pre-store the synchronization sequence, traverse the pre-stored synchronization sequence in the received codeword structure until the synchronization flag in the codeword structure matches the pre-stored synchronization sequence, and the identification is completed.
  • the extended manner may be adopted, so that the data length satisfies the condition for generating the non-shortened code, thereby generating
  • the third codeword structure described above makes the coding mode further applicable to all cases (that is, regardless of the number of first data blocks, an applicable coding mode can be found among the above three coding modes), and the coding is improved. Flexibility.
  • the third payload includes Q3 first data blocks.
  • the two encoding and decoding methods of the non-shortened code can be implemented as separate embodiments, or can be implemented by combining with the shortening codes.
  • the synchronization flag (including the first synchronization flag, the second synchronization flag, and/or the third synchronization flag described above) may be followed by a payload (including the first payload, the second payload, and/or the third payload) Or located between the payload and the check portion (including the first check portion, the second check portion, and/or the third check portion), or in the code word structure (including the first code word structure, the second The header of the codeword structure and/or the third codeword structure, or at the end of the codeword structure.
  • the sync flag can also be called AM (async mark) or FEC delimiter.
  • the following embodiment is described by taking the synchronization flag between the payload and the check portion as an example, which can further achieve fast synchronization.
  • At least two of the first synchronization flag, the second synchronization flag, and the third synchronization flag have the same length.
  • the lengths of the first synchronization flag, the second synchronization flag, and the third synchronization flag are all the same. It is easier to synchronize and facilitates fast synchronization. It can be understood that, in other embodiments, the lengths of at least two of the first synchronization flag, the second synchronization flag, and the third synchronization flag may also be different.
  • At least two of the first synchronization flag, the second synchronization flag, and the third synchronization flag have the same value.
  • the values of the first synchronization flag, the second synchronization flag, and the third synchronization flag are the same. More convenient to synchronize, which is conducive to fast synchronization. It can be understood that, in other embodiments, the values of at least two of the first synchronization flag, the second synchronization flag, and the third synchronization flag may also be different.
  • the values of the first synchronization flag, the second synchronization flag, and the third synchronization flag are different from each other, so that it is convenient to distinguish which one of the above-mentioned codeword structures is currently identified when synchronizing.
  • the length of the first payload is equal to the sum of the lengths of the S first data blocks, that is, the first payload is composed only of S first data blocks, and the length of the second payload is equal to Q2 second.
  • the sum of the lengths of the data blocks, that is, the second payload is composed of only Q2 second data blocks.
  • the length of the third payload is equal to the sum of the lengths of the Q2 third data blocks, that is, the third payload is composed only of Q2 third data blocks.
  • the length of the first payload may also be greater than the length of the S first data blocks, for example, may be (S+1)*M, and an extra 66b data block may be used for other indication purposes. .
  • the length of the first non-payload portion is greater than or equal to the sum of the lengths of the first synchronization flag and the first check portion, and the first non-payload portion except the first synchronization flag and the first check portion
  • the remaining bits may be used for other indication purposes
  • the length of the second non-payload portion is greater than or equal to the sum of the lengths of the second synchronization flag and the second parity portion, and the second non-payload portion is in addition to the second synchronization.
  • the remaining bits may be used for other indication purposes; the length of the third non-payload portion is greater than or equal to the sum of the lengths of the third sync flag and the third check portion, and the third non-net In addition to the third sync flag and the third check portion, the remaining bits can be used for other indication purposes.
  • the length of the first non-payload portion is equal to the length of the second non-payload portion to facilitate fast synchronization. In an embodiment, the lengths of the first non-payload portion, the second non-payload portion, and the third non-payload portion are all equal, thereby facilitating fast synchronization.
  • the ONU For each uplink burst, the ONU sends a code stream, and the code stream includes an uplink burst structure.
  • the header of the uplink burst structure includes a burst delimeter, the tail includes a terminator, and the terminator can also be called It is an end of burst (EOB), or a TP (terminating pattern).
  • the uplink burst structure may include only one first codeword structure, or may include at least one second codeword structure and one first codeword structure, or may also include one third codeword structure, or It may also include at least one second codeword structure and one third codeword structure.
  • various codeword structures in the above burst structure include an example of a payload, a synchronization flag, and a check portion, and the synchronization flag is located between the payload and the check portion as an example description.
  • the synchronization flag is exemplified by 32 bits.
  • the payload length of the non-shortened code is 16962b, and the length of the verification part is 3598b.
  • the synchronization flags of the above three codeword structures are the same.
  • the shortening code is identified according to the synchronization flag, and the process of recognition can also be understood as a synchronization process.
  • the synchronization mechanism of the OLT is as shown in FIG. 9:
  • the OLT receives a code stream in a physical coding sublayer, where the code stream includes a burst delimiter and a first codeword structure, or the code stream includes a burst delimiter, a first codeword structure, and a second codeword structure.
  • S203 includes: S501. After the burst delimiter or after the second check portion, the OLT identifies the presence or absence of the first synchronization flag at the current interval position every M bits, and counts the current number of times of identification or the current interval. Total number of bits;
  • S204 includes: S502, after the OLT identifies that the first synchronization flag exists, if the product of the current statistical recognition number and M is less than the FEC payload length, or if the current total number of bits is less than the FEC payload length, then S503 is performed. ;
  • the number of data blocks of 66b size is counted from 0, and each time it is counted, it is judged whether the first 32 bits of the current interval position are The sync flag, if not, continues to count the 66b data block at the current interval. For example, from 0b to 65b, a 66b data block is counted, the statistical count is 1; the current interval is 66b, and then it is identified whether the 66b to 97b is a synchronization flag, and if not, the statistics are continued from 66b to 131b.
  • the data block of 66b the statistical number is 2; the current interval is the 132b, and then it is identified whether the 132b to 163b is the synchronization flag, if not, the statistics continue from 132b; if the 132b to 163b are the synchronization flag, The statistics end, the number of statistics is 2, obviously, 2*66 ⁇ 16962, therefore, the currently identified codeword is the first codeword structure, that is, the shortening code.
  • the scheme for counting the total number of bits in the current interval is similar to the above, and will not be described here. It can be understood that the total number of bits of the current interval of statistics is equal to the product of the current number of statistics and M.
  • step S502 specifically includes:
  • the terminator is understood to be that the interval position is a position after the synchronization flag, wherein a difference between the first non-payload length and the length of the first synchronization flag is P bits; and the first codeword structure includes only the first payload
  • the first synchronization flag and the first check portion the length of the first check portion is P bits, that is, 3598 bits.
  • the currently identified codeword is the first codeword structure. If there is a terminator, it is determined that the currently identified codeword is the first codeword structure. If there is no terminator, return the position before the P-bit interval, continue to execute M bits per interval, identify whether there is a first synchronization flag at the current interval, and count the current number of times or count the total number of bits in the current interval. .
  • the 132b to 163b are the synchronization flags, it is judged whether the bit starting with 3762b is the end after the interval of 3598 bits from the 164b, that is, from 164b to 3761b (ie, the first check portion). If the length of the terminator is 30 bits, it is judged whether or not 3762b to 3791b is a terminator. If it is a terminator, it is determined that the currently identified codeword is the first codeword structure. If it is not the terminator, then the 132b to 163b are not the synchronization flag.
  • the data block of the 66b is continuously counted from the 132b to the 197b, and the number of statistics is increased by 1, that is, the current number of statistics is refreshed to 3; The interval is 198b and the identification continues.
  • the code stream includes a burst delimiter and a second codeword structure, or the code stream includes a burst delimiter, a first codeword structure, and a second codeword structure;
  • the OLT After identifying the burst delimiter or the second check portion, the OLT identifies whether there is a second synchronization flag at the current interval position every M bits, and counts the current number of times of identification or counts the total number of bits of the current interval;
  • the method further includes: S504, after the OLT identifies the second synchronization flag, if the product of the current statistical identification number and M is equal to the FEC payload length, or if the current total number of bits is equal to the FEC payload length, then determining The currently identified codeword is a second codeword structure.
  • the current interval position is 16963b, and it is judged whether the 16963b to 16994b is a synchronization flag.
  • the product of the current recognition number and 66 is 16962b, which is equal to the FEC payload length, and the currently identified
  • the codeword is a second codeword structure, and the current number of statistics or the total number of bits of the current statistics can be cleared.
  • 3598 bits are spaced apart, that is, the 16995b to 20592b are the second check portion. A new round of identification continues from 20593b.
  • the third codeword structure is also a non-shortened code, and the specific identification process is the same as the second codeword structure, and details are not described herein again.
  • the synchronization flag of the third codeword structure can be different from the synchronization flag of the second codeword structure, thereby facilitating the separation of the third codeword structure from the second codeword structure.
  • the method further includes: S505, after determining that the currently identified codeword is the second codeword structure or the first codeword structure or the third codeword structure, the OLT clears the current statistical identification number or the total number of bits of the current statistics. ;
  • the first codeword structure or the second codeword structure is continuously identified; wherein the difference between the first non-payload length and the length of the first synchronization flag is P bits .
  • the application also provides an ONU 130.
  • the ONU includes a processor 610, a memory 620, a medium access control (MAC) chip 630, a transceiver 640, and a wavelength division multiplexer 650.
  • MAC medium access control
  • the processor 610 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit ASIC, or at least one integrated circuit for executing related programs to implement the technology provided by the embodiments of the present application. Program.
  • CPU central processing unit
  • ASIC application-specific integrated circuit
  • the memory 620 may be a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM).
  • Memory 620 can store operating systems and other applications.
  • the program code for implementing the technical solution provided by the embodiment of the present application is saved in the memory 620 and executed by the processor 610.
  • the processor 610 can include a memory 620 internally. In another embodiment, processor 610 and memory 620 are two separate structures.
  • processor 610 and MAC chip 630 may be two separate structures.
  • a MAC chip 630 can be included in the processor 610.
  • the MAC chip 630 may include a physical coding sublayer and a MAC Control sublayer.
  • Transceiver 640 can include a light emitter and/or a light receiver.
  • the light emitter can be used to transmit an optical signal and the optical receiver can be used to receive an optical signal.
  • the light emitter can be realized by a light emitting device such as a gas laser, a solid laser, a liquid laser, a semiconductor laser, a direct modulation laser, or the like.
  • the light receiver can be implemented by a photodetector such as a photodetector or a photodiode such as an avalanche diode.
  • the transceiver 640 can also include a digital to analog converter and an analog to digital converter.
  • the wavelength division multiplexer 650 is coupled to the transceiver 640, which acts as a multiplexer when the network device transmits an optical signal. When the network device receives the optical signal, the wavelength division multiplexer acts as a demultiplexer.
  • a wavelength division multiplexer can also be referred to as an optical coupler.
  • the MAC chip 630 or the processor 610 can perform the steps of physically coding the sublayers.
  • the MAC chip 630 of the ONU is configured to perform steps S200, S201, S202, S300, S301, S302, S303, S400, S401, S402, S403 and S404.
  • the application also provides an OLT 110.
  • the OLT includes a processor 710, a memory 720, a medium access control (MAC) chip 730, a transceiver 740, and a wavelength division multiplexer 750.
  • MAC medium access control
  • the processor 710 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit ASIC, or at least one integrated circuit for executing related programs to implement the technology provided by the embodiments of the present application. Program.
  • CPU central processing unit
  • ASIC application-specific integrated circuit
  • the memory 720 may be a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM).
  • the memory 720 can store an operating system and other applications.
  • the program code for implementing the technical solution provided by the embodiment of the present application is saved in the memory 720 and executed by the processor 710.
  • the processor 710 can include a memory 720 internally. In another embodiment, processor 710 and memory 720 are two separate structures.
  • processor 710 and MAC chip 730 can be two separate structures.
  • a MAC chip 730 can be included in the processor 710.
  • the MAC chip 730 may include a physical coding sublayer and a MAC control sublayer.
  • Transceiver 740 can include a light emitter and/or a light receiver.
  • the light emitter can be used to transmit an optical signal and the optical receiver can be used to receive an optical signal.
  • the light emitter can be realized by a light emitting device such as a gas laser, a solid laser, a liquid laser, a semiconductor laser, a direct modulation laser, or the like.
  • the light receiver can be implemented by a photodetector such as a photodetector or a photodiode such as an avalanche diode.
  • the transceiver 740 can also include a digital to analog converter and an analog to digital converter.
  • the wavelength division multiplexer 750 is coupled to the transceiver 740, which acts as a multiplexer when the network device transmits an optical signal.
  • the wavelength division multiplexer acts as a demultiplexer.
  • a wavelength division multiplexer can also be referred to as an optical coupler.
  • the MAC chip 730 or the processor 710 can perform the steps of physically coding the sublayers.
  • the MAC chip 730 of the OLT is configured to perform steps S203, S204, S205, S206, S304, S305, S306, S307, S405, S406, S407, S408, and steps S500, S501, S502, S503. , S504 and S505.
  • the present application also provides a data encoding apparatus in a PON system, which may be integrated in the above-described embodiment ONU, for example, may be integrated in the MAC chip of the ONU, integrated in the processor, or integrated in the DSP chip.
  • the apparatus includes: a receiving module 810, a forward error correction coding module 820, and a generating module 830.
  • the receiving module 810 is configured to perform steps S200, S300, and S400.
  • the forward error correction encoding module 820 is configured to perform steps S140, S201, S302, and S403, and the generating module 830 is configured to perform steps S202 and S303. , S404.
  • the device further includes a transcoding module 840, and the transcoding module 840 is configured to perform steps S301, S402.
  • the device further includes an expansion module 850, and the expansion module 850 is configured to perform step S401.
  • the present application further provides a data decoding apparatus in a PON system, which may be integrated in the OLT of the above embodiment, for example, may be integrated in the MAC chip of the OLT, integrated in the processor, or integrated in the DSP chip.
  • the apparatus includes: a receiving module 910, a synchronization module 920, an extraction module 930, and a forward error correction decoding module 940.
  • the receiving module 910 is configured to perform steps S203, S304, S405, and S500
  • the synchronization module 920 is configured to perform steps S204, S305, S406, S501, S502, S503, S504, and S505, and the extraction module 930 is used.
  • the forward error correction decoding module 940 is configured to perform steps S206, S307, and S408.
  • the present application further provides an optical line terminal comprising the data encoding apparatus of any of the above embodiments, or the optical line terminal comprising the data decoding apparatus of any of the above embodiments.
  • the application further provides an optical network unit comprising the data encoding device of any of the above embodiments, or the optical network unit comprising the data decoding device of any of the above embodiments.
  • the present application also provides a PON system including the optical line terminal and the optical network unit described above.
  • a computer program product includes one or more computer instructions.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, computer instructions can be wired from a website site, computer, server or data center (eg Coax, fiber, digital subscriber line (DSL) or wireless (eg, infrared, wireless, microwave, etc.) is transmitted to another website, computer, server, or data center.
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media.
  • Useful media can be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media (eg, Solid State Disk (SSD)).

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

La présente invention concerne un procédé et un dispositif de codage et de décodage de données dans un système PON, le procédé consistant : lorsque la longueur totale d'un premier bloc de données reçu est inférieure à la longueur de charge utile FEC d'un motif FEC, à effectuer un codage FEC sur le premier bloc de données reçu pour générer un code raccourci, la longueur de charge utile du code raccourci étant inférieure à la longueur de charge utile FEC du motif FEC, la longueur de chaque premier bloc de données étant M bits, et la longueur de charge utile FEC et la longueur de la partie non utile du code raccourci sont des multiples entiers de M ; lorsque la longueur totale est supérieure ou égale à la longueur de charge utile FEC, à étendre le premier bloc de données reçu en premier, puis à le transcoder pour générer une pluralité de troisièmes blocs de données, le troisième bloc de données ayant une longueur de N bits, et N > M ; puis à effectuer un codage FEC sur le troisième bloc de données pour générer un code non raccourci. Le procédé de codage décrit peut être applicable à un cas d'entrée de divers nombres des premiers blocs de données et peut assurer que les débits d'entrée et de sortie ne changent pas. La mise en œuvre est simple, et le procédé peut être appliqué à des codes non raccourcis et des codes raccourcis de différentes longueurs.
PCT/CN2019/083308 2018-04-19 2019-04-18 Procédé et dispositif de codage et de décodage de données, système olt, onu et pon WO2019201316A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810355101.9A CN110391871B (zh) 2018-04-19 2018-04-19 数据编译码方法和装置、olt、onu和pon系统
CN201810355101.9 2018-04-19

Publications (1)

Publication Number Publication Date
WO2019201316A1 true WO2019201316A1 (fr) 2019-10-24

Family

ID=68239385

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/083308 WO2019201316A1 (fr) 2018-04-19 2019-04-18 Procédé et dispositif de codage et de décodage de données, système olt, onu et pon

Country Status (2)

Country Link
CN (1) CN110391871B (fr)
WO (1) WO2019201316A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114765528A (zh) * 2021-01-15 2022-07-19 烽火通信科技股份有限公司 帧同步方法、装置、设备及可读存储介质

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117439702A (zh) * 2022-07-15 2024-01-23 中兴通讯股份有限公司 数据传输方法及装置、电子设备、计算机可读介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009067899A1 (fr) * 2007-11-12 2009-06-04 Huawei Technologies Co., Ltd. Procédé et dispositif de codage de données et de décodage de données
WO2012000434A1 (fr) * 2010-06-29 2012-01-05 Huawei Technologies Co., Ltd. Procédé d'envoi et de réception de données avec une correction d'erreurs sans voie de retour et élément et système associés
WO2014183299A1 (fr) * 2013-05-17 2014-11-20 华为技术有限公司 Procédé de traitement de données et dispositif associé de codage et de décodage fec
WO2016127820A1 (fr) * 2015-02-15 2016-08-18 中兴通讯股份有限公司 Procédé de codage de données et appareil

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6141788A (en) * 1998-03-13 2000-10-31 Lucent Technologies Inc. Method and apparatus for forward error correction in packet networks
CN101166273A (zh) * 2006-10-16 2008-04-23 华为技术有限公司 实现视频数据传送的方法、装置及系统
US8171370B2 (en) * 2006-11-14 2012-05-01 Futurewei Technologies, Inc. Method and apparatus for applying forward error correction in 66b systems
CN101345745B (zh) * 2007-07-09 2012-01-04 华为技术有限公司 数据成帧方法及其设备
CN101374035B (zh) * 2008-09-19 2012-09-05 中兴通讯股份有限公司 吉比特无源光网络中的解码方法和系统以及成帧方法
CN102439874B (zh) * 2009-10-30 2015-03-25 华为技术有限公司 光在网络中发送下行帧的方法及相关装置
CN102158770B (zh) * 2010-02-12 2016-08-03 中兴通讯股份有限公司 一种无源光网络中上行带宽分配的方法和系统
CN102195738B (zh) * 2010-03-02 2015-06-10 中兴通讯股份有限公司 用于吉比特无源光网络系统下行帧同步的处理方法及装置
WO2014040247A1 (fr) * 2012-09-12 2014-03-20 华为技术有限公司 Procédé pour adapter des mots de code de correction d'erreurs sans voie de retour (fec) à un bloc de ressource physique, procédé pour synchroniser des mots de code fec, et système correspondant
US20150046775A1 (en) * 2013-08-07 2015-02-12 Broadcom Corporation Encoding and Decoding Schemes to Achieve Standard Compliant Mean Time to False Packet Acceptance

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009067899A1 (fr) * 2007-11-12 2009-06-04 Huawei Technologies Co., Ltd. Procédé et dispositif de codage de données et de décodage de données
WO2012000434A1 (fr) * 2010-06-29 2012-01-05 Huawei Technologies Co., Ltd. Procédé d'envoi et de réception de données avec une correction d'erreurs sans voie de retour et élément et système associés
WO2014183299A1 (fr) * 2013-05-17 2014-11-20 华为技术有限公司 Procédé de traitement de données et dispositif associé de codage et de décodage fec
WO2016127820A1 (fr) * 2015-02-15 2016-08-18 中兴通讯股份有限公司 Procédé de codage de données et appareil

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114765528A (zh) * 2021-01-15 2022-07-19 烽火通信科技股份有限公司 帧同步方法、装置、设备及可读存储介质
CN114765528B (zh) * 2021-01-15 2023-09-26 烽火通信科技股份有限公司 帧同步方法、装置、设备及可读存储介质

Also Published As

Publication number Publication date
CN110391871B (zh) 2021-11-19
CN110391871A (zh) 2019-10-29

Similar Documents

Publication Publication Date Title
CN107113288B (zh) 在66位码中添加操作、管理与维护(oam)信息
US8122325B2 (en) Forward error correction for 64b66b coded systems
EP2499770B1 (fr) Motif de synchronisation de trame aval protégé par une protection contre les erreurs d'en-tête dans un réseau optique passif de dix gigabits
JP7152488B2 (ja) データ符号化方法および装置、データ復号方法および装置、ｏｌｔ、ｏｎｕ、ならびにｐｏｎシステム
US8270832B2 (en) Method and apparatus for synchronization in a passive optical network
US10855397B2 (en) Downstream data frame transmission method and device
WO2016183830A1 (fr) Procédé, dispositif et système de verrouillage de trame de réseau optique passif
CN101523787A (zh) 用于在66b系统中应用前向纠错的方法和装置
CN107925422A (zh) 无源光网络（pon）中的自适应前向纠错（fec）
WO2019201316A1 (fr) Procédé et dispositif de codage et de décodage de données, système olt, onu et pon
WO2010048854A1 (fr) Procédé, dispositif et système de codage de données et de décodage de données
WO2011050529A1 (fr) Procédé de transmission de trames de liaison descendante dans un réseau optique et appareil correspondant
WO2020147023A1 (fr) Procédé et appareil de conversion de signaux par salves en signaux continus
US8259734B2 (en) Method and device for sending upstream transfer frame in passive optical network
WO2017113349A1 (fr) Procédé et appareil d'analyse syntaxique de données et de transmission de données
US20080267634A1 (en) 9b10b Code for Passive Optical Networks

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19787891

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19787891

Country of ref document: EP

Kind code of ref document: A1