WO2019200878A1 - 一种cpld日志记录方法 - Google Patents

一种cpld日志记录方法 Download PDF

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Publication number
WO2019200878A1
WO2019200878A1 PCT/CN2018/112005 CN2018112005W WO2019200878A1 WO 2019200878 A1 WO2019200878 A1 WO 2019200878A1 CN 2018112005 W CN2018112005 W CN 2018112005W WO 2019200878 A1 WO2019200878 A1 WO 2019200878A1
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signal
recorded
cpld
determining
storage
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PCT/CN2018/112005
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English (en)
French (fr)
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陈占良
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郑州云海信息技术有限公司
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Publication of WO2019200878A1 publication Critical patent/WO2019200878A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system

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  • the present invention relates to the field of information recording technologies, and in particular, to a CPLD log recording method.
  • the Complex Programmable Logic Device plays an important role in the logic design of the entire motherboard. For example, complete the timing control of the switch, realize the control of the fan speed, realize the control of the signal signal such as error reporting, realize the low pin count bus (LPC) bus protocol analysis and perform the basic input output system (Basic Input Output System, BIOS) code lighting and other functions.
  • LPC low pin count bus
  • BIOS basic input output system
  • the key information is often recorded in the flash module by using the log recording method for the analysis of the later problem.
  • the design of the CPLD belongs to the hardware design, and rarely uses the method of recording the log.
  • the value of the CPLD internal register will be transmitted to the basic management controller (Basic Manager Controller, BMC) through the bus for log record analysis, and the log is realized by software inside the BMC. recording.
  • BMC Basic Manager Controller
  • the interaction between the CPLD and the BMC is implemented by means of a bus, and the process of recording the internal registers of the CPLD through the software of the BMC is complicated, and the cooperation between the CPLD and the BMC is required to realize the log recording, and in the CPLD and the BMC.
  • abnormal interference can also cause data errors, affect the recording of register data, and reduce the efficiency of bug analysis.
  • a CPLD log recording method is provided to solve the problem of large data recording error and low efficiency of bug analysis in the prior art.
  • a CPLD logging method includes:
  • the signal to be recorded is written to the storage area.
  • the determining the to-be-recorded signal according to the type of the bug specifically includes:
  • a suspicious signal is selected from the associated signal as a signal to be recorded according to a cause of a possible bug.
  • the determining the storage area specifically includes:
  • a storage area is determined according to the occupied space and the remaining storage space.
  • the instantiating the RAM specifically includes:
  • the collecting the signal to be recorded specifically includes:
  • the signal to be recorded is sampled according to the clock pulse.
  • the determining the sampling time precision specifically includes:
  • the writing the signal to be recorded to the storage area specifically includes:
  • the collected signal to be recorded is written into a corresponding storage address according to the address signal;
  • the address signal is incremented according to an instantiation result
  • the signal acquisition is stopped, if otherwise, the acquired signal to be recorded is written to the corresponding storage address when the write enable signal is valid.
  • the result of the increment is a storage initial position.
  • the determining whether the current signal state is abnormal comprises: determining whether the currently saved signal is a normal value.
  • the method further comprises: reading the saved signal from the storage area for bug analysis.
  • the type of the bug that needs to record the signal is first determined in the present invention, and then the relevant signals involved in the reproduction process are determined according to the bug, and then the suspicious signal that may cause the bug is determined from the relevant signal according to experience and performed.
  • Recording obtaining RAM information from the CPLD during recording, determining a storage area for storing the suspicious signal according to the storage condition of the RAM, and storing the collected suspicious signal because the collected suspicious signal comes from the internal register of the CPLD, and the RAM for storage It is also the internal structure of the CPLD. Therefore, the acquisition and storage of the internal data of the CPLD is realized, which ensures the correctness of the data. When the stored signal is abnormal, the signal acquisition and storage will be stopped immediately. Therefore, the register before the bug can be generated. The data is saved for analysis of the causes of bugs, improving the efficiency of bug analysis.
  • FIG. 1 is a schematic flowchart of a CPLD log recording method according to an embodiment of the present disclosure
  • FIG. 2 is a schematic flowchart of a method for determining a signal to be recorded according to an embodiment of the present invention
  • FIG. 3 is a schematic flowchart of a method for determining a storage area according to an embodiment of the present disclosure
  • FIG. 4 is a schematic flowchart of a RAM instantiation method according to an embodiment of the present invention.
  • FIG. 5 is a schematic flowchart diagram of a signal sampling method according to an embodiment of the present invention.
  • FIG. 6 is a schematic flowchart diagram of a sampling time precision determining method according to an embodiment of the present invention.
  • FIG. 7 is a schematic flowchart diagram of a method for writing a signal to be recorded into a RAM according to an embodiment of the present invention.
  • FIG. 8 is a schematic flowchart diagram of another CPLD log recording method according to an embodiment of the present invention.
  • FIG. 1 is a schematic flowchart of a CPLD log recording method according to an embodiment of the present invention.
  • a CPLD log recording method provided by an embodiment of the present invention includes:
  • S10 Obtain a bug type, and determine a signal to be recorded according to the type of the bug.
  • S20 Obtain CPLD internal random access memory (RAM) information, and determine a storage area.
  • RAM internal random access memory
  • S40 Collect the signal to be recorded.
  • S50 Write the to-be-recorded signal into the storage area.
  • FIG. 2 is a schematic flowchart of a method for determining a signal to be recorded according to an embodiment of the present invention. As shown in FIG. 2, determining a signal to be recorded according to the type of the bug in step S10 specifically includes:
  • S12 Select a suspicious signal from the correlation signal as a signal to be recorded according to a cause of a bug.
  • the suspicious signal causing the bug is used as a signal to be recorded. These suspicious signals come from the internal registers of the CPLD, but the number of internal registers of the CPLD is large, and these suspicious signals may also come from a plurality of different registers.
  • the embodiment of the present invention collects suspiciously.
  • the signal acquisition operation is performed on all the registers inside the CPLD.
  • the register that does not send the suspicious signal although there is an acquisition operation process, since there is no signal output that can be set, there is no acquisition result and no recording is required.
  • FIG. 3 is a schematic flowchart of a method for determining a storage area according to an embodiment of the present invention. As shown in FIG. 3, determining a storage area in step S20 specifically includes:
  • S21 Determine a storage space of the RAM, and calculate a remaining storage space.
  • S22 Determine, according to the number of the signals to be recorded, the occupied space of the to-be-recorded signal that is collected each time.
  • S23 Determine a storage area according to the occupied space and the remaining storage space.
  • the RAM used in the present invention is the internal RAM of the CPLD, and the value of the internal register of the CPLD can be directly saved. Since the data is only accessed inside the CPLD, the access efficiency is high, and the storage information error is not easy to occur. However, the RAM in the CPLD needs to store other information, and it cannot be used to save the signal to be recorded. Therefore, we first need to obtain the RAM information, calculate the remaining storage space, and then according to the signal that needs to be collected each time. The number calculates how much storage space will be used each time it is stored, and then determines the area for storage in conjunction with the remaining storage space of the RAM.
  • the embodiment of the present invention is implemented by using the RAM inside the CPLD.
  • it is required to perform functional design through the IP core inside the CPLD (that is, determine the storage area of the RAM, the space occupied by each storage, and the specific storage address in the storage area.
  • the RAM needs to be instantiated.
  • FIG. 4 it is a schematic flowchart of the RAM instantiation method according to an embodiment of the present invention, as shown in FIG. 4, in step S30.
  • the instantiation of the RAM specifically includes:
  • S31 Determine a data width and a storage depth according to the to-be-recorded signal.
  • S32 Perform storage parameter setting according to the data width and the storage depth.
  • S34 Define a write channel and a read channel of the RAM, and set related parameters.
  • step S30 the storage area in the RAM is initially determined, but we need to instantiate the RAM before the area can be used as an area dedicated to storing the register signal, and no other data is stored, thereby affecting the data. Effectiveness.
  • the data width is the length of one signal data. In this embodiment, it is set to 1bit
  • the storage depth is determined according to the length of the signal data (that is, the data width) and the number of signals collected at one time. When the number of collected signals is 10, the stored depth should be only 10 bits to ensure that all 10 signals are guaranteed. Save it, when the RAM has more memory, we can set the storage depth to be larger, but ensure that the set storage depth should be an integer multiple of the storage space, so that each collected data can be saved in a continuous In the address.
  • the storage initial position that is, the location where the first collected data is stored.
  • the storage depth is an integer multiple of the storage space
  • the next acquired signal will exist in the next address.
  • the address offset remains the same, so we can define the address offset as the size of the space occupied by the storage, for example The number of signals collected at one time is 10, the size of each signal is 1 bit, and the last storage area is 0000H, then the storage address of the newly acquired signal is 0000H+10bit, of which 10bit is the address offset, which needs to be explained. Yes, this is merely an exemplary illustration of the present invention and does not represent the actual storage address during its normal operation.
  • the register data stored in the embodiment of the present invention needs to be read for bug analysis after the occurrence of the bug.
  • the write channel and the read channel are respectively defined, and the write operation and the read operation can be realized. At the same time.
  • FIG. 5 is a schematic flowchart of a signal sampling method according to an embodiment of the present invention. As shown in FIG. 5, collecting the to-be-recorded signal in step S40 specifically includes:
  • S43 Sampling the signal to be recorded according to the clock pulse.
  • the signal is collected with the clock pulse as the trigger condition.
  • the clock pulse arrives, the signal is collected once.
  • the width of the clock pulse the frequency of the signal acquisition can be effectively controlled, and the acquisition can be avoided too fast or too slow.
  • FIG. 6 a schematic flowchart of a sampling time precision determining method provided by an embodiment of the present invention is shown in FIG. 6 , and determining sampling time precision specifically includes:
  • S411 Acquire a pulse frequency of a signal to be recorded.
  • S412 Determine a sampling frequency according to the pulse frequency and Nyquist sampling law.
  • the sampling frequency is at least 2fm, but it can also be set to 5fm or 10fm according to the actual situation.
  • the specific sampling frequency is set by the user, and will not be described here.
  • FIG. 7 is a schematic flowchart of a method for writing a signal to be recorded into a RAM according to an embodiment of the present invention. As shown in FIG. 7 , the step of writing the to-be-recorded signal into the storage area in step S50 includes:
  • S52 Determine a trigger condition, and set a write enable signal according to the trigger condition.
  • the signal acquisition is stopped, if otherwise, the acquired signal to be recorded is written to the corresponding storage address when the write enable signal is valid.
  • the increment result is a storage initial position. For example, if the defined storage area is 0000H-1000H, the storage address of the next signal is adjusted after the signal is stored to 1000H. Go back to 0000H and overwrite the signal data originally stored in 0000H.
  • the determining whether the current signal state is abnormal specifically includes: determining whether the currently saved signal is a normal value. Assume that the signal transmission of a signal in one cycle is 1, 2, 3, 4, 5 in sequence, but if the actual data collected becomes other values, such as 1, 1, 1, 3, 2, the signal can be determined. Abnormal, this anomaly may be the cause of the bug. Therefore, when the signal is abnormal, the abnormal signal acts as an interrupt signal, interrupting the clock pulse, stopping the signal acquisition, and preventing the data before the signal abnormality from being overwritten due to continued acquisition.
  • the address signal when the signal is abnormal, the acquisition signal is interrupted, if the system is not down, the address signal also stores the address to be saved by the next signal, and can continue to be stored from the address saved by the address signal when the signal is restarted. It is also possible to start the storage from the initial position, but if the system is down, the data in the RAM is cleared at this time, and can only be re-executed to re-storage from the initial position.
  • FIG. 8 is a schematic flowchart of another CPLD log recording method according to an embodiment of the present invention. As shown in FIG. 8 , the embodiment of the present invention further includes: reading a saved signal from the storage area for use in a bug. analysis.
  • the user can read the stored register data from the RAM for analysis of the bug, and the manner in which the read is performed is not limited.
  • the type of the bug that needs to record the signal is first determined, and then the relevant signal involved in the reproduction process is determined according to the bug, and then the suspicious signal that may cause the bug is determined from the relevant signal according to experience and recorded, and the record is from the CPLD.
  • the RAM information is obtained, and the storage area for storing the suspicious signal is determined according to the storage condition of the RAM, and the collected suspicious signal is stored, because the collected suspicious signal comes from the internal register of the CPLD, and the RAM for storage is also the internal structure of the CPLD. Therefore, the real-time acquisition and storage of the internal data of the CPLD is realized, and the correctness of the data is ensured.
  • the stored signal is abnormal, the collection and storage of the signal will be stopped immediately. Therefore, the data of the register before the generation of the bug can be saved, which is convenient. Analysis of the cause of the bug improves the efficiency of bug analysis.

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Abstract

本发明实施例公开了一种CPLD日志记录方法，包括：获取bug类型，根据所述bug类型确定待记录信号；获取CPLD内部RAM信息，确定存储区域；对所述RAM进行例化；对所述待记录信号进行采集；将所述待记录信号写入所述存储区域。本发明实施例实现了CPLD内部数据的实时采集存储，保证了数据的正确性，当存储的信号异常时将立即停止对信号的采集和存储，可以将bug产生前的寄存器的数据进行保存，便于bug产生原因的分析，提高了bug问题分析的效率。

Description

一种CPLD日志记录方法
本发明要求于2018年04月18日提交中国专利局、申请号为201810347448.9、申请名称为“一种CPLD日志记录方法”的中国专利申请的优先权，其全部内容通过引用结合在本发明中。
技术领域
本发明涉及信息记录技术领域，具体涉及一种CPLD日志记录方法。
背景技术
服务器的主板设计中，复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)在整个主板的逻辑设计中起着重要的作用。比如，完成开关机的时序控制，实现风扇转速的控制，实现报错等点灯信号的控制，实现低脚位数(Low pin count Bus，LPC)总线协议解析进行基本输入输出系统(Basic Input Output System，BIOS)code点灯等功能。在整个主板的设计及后续生产过程中，伴随着各种bug问题，对于复现时间不确定的问题进行分析时，需要将CPLD内部寄存器的值进行记录，用于bug问题的分析。
现有技术中，在软件设计时，经常使用日志记录的方式将关键信息记录在flash模块中，用于后期问题的分析，然而CPLD的设计属于硬件设计，很少会用到记录日志的方式进行问题分析，在一些应用设计时，会将CPLD内部寄存器的值通过总线的方式传到基本管理控制器(Basic Manager Controller，BMC)进行日志的记录分析，并在BMC内部通过软件的方式实现日志的记录。
然而，通过总线的方式实现CPLD与BMC之间的交互，并通过BMC内部的软件实现CPLD内部寄存器的日志记录的过程实现复杂，需要CPLD和BMC协同合作才能实现日志的记录，而且在CPLD和BMC通信过程中，异常的干扰也会导致数据出错，影响寄存器数据的记录，降低了bug问题分析的效率。
发明内容
本发明实施例中提供了一种CPLD日志记录方法，以解决现有技术中的数据记录误差大及bug问题分析效率低的问题。
为了解决上述技术问题，本发明实施例公开了如下技术方案：
一种CPLD日志记录方法，包括：
获取bug类型，根据所述bug类型确定待记录信号；
获取CPLD内部RAM信息，确定存储区域；
对所述RAM进行例化；
对所述待记录信号进行采集；
将所述待记录信号写入所述存储区域。
优选地，所述根据所述bug类型确定待记录信号具体包括：
根据bug复现过程确定关联信号；
根据可能产生bug的原因，从所述关联信号中选取可疑信号作为待记录信号。
优选地，所述确定存储区域具体包括；
确定所述RAM的存储空间，并计算剩余存储空间；
根据所述待记录信号的个数确定每次采集的所述待记录信号的占用空间；
根据所述占用空间和剩余存储空间确定存储区域。
优选地，所述对所述RAM进行例化具体包括：
根据所述待记录信号确定数据宽度和存储深度；
根据所述数据宽度和存储深度进行存储参数设置；
定义存储初始位置及每次记录的地址偏移量；
定义所述RAM的写通道和读通道，并设置相关参数。
优选地，所述对所述待记录信号进行采集具体包括：
确定采样时间精度；
根据所述采样时间精度设置时钟脉冲；
根据所述时钟脉冲对待记录信号进行采样。
优选地，所述确定采样时间精度具体包括：
获取待记录信号的脉冲频率；
根据所述脉冲频率以及奈奎斯特采样定律确定采样频率；
将所述采样频率取倒数即为采样时间精度。
优选地，所述将所述待记录信号写入所述存储区域具体包括：
根据例化结果确定地址信号；
确定触发条件，根据所述触发条件设置写使能信号；
当所述写使能信号有效时将采集到的待记录信号根据所述地址信号写入对应的存储地址；
所述地址信号根据例化结果递增；
判断当前信号状态是否异常；
如果是则停止信号采集，如果否则在写使能信号有效时将采集到的待记录信号写入对应的存储地址。
优选地，当所述地址信号为所述存储区域最大值时，其递增结果为存储初始位置。
优选地，所述判断当前信号状态是否异常具体包括：判断当前保存的信号是否为正常值。
优选地，所述方法还包括：从所述存储区域内读取保存的信号，用于bug分析。
由以上技术方案可见，本发明中首先确定需要记录信号的bug类型，然后根据bug在复现过程确定会涉及到的相关信号，再根据经验从相关信号中确定出可能造成bug的可疑信号并进行记录，记录时从CPLD中获取RAM信息，根据RAM的存储情况确定用于存放可疑信号的存储区域，将采集到的可疑信号进行存储，因为采集的可疑信号来自CPLD的内部寄存器，存储用的RAM也是CPLD的内部结构，因此，实现了CPLD内部数据的时候采集存储，保证了数据的正确性，当存储的信号异常时将立即停止对信号的采集和存储，因此，可以将bug产生前的寄存器的数据进行保存，便于bug产生原因的分析，提高了bug问题分析的效率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本发明实施例提供的一种CPLD日志记录方法的流程示意图；
图2为本发明实施例提供的待记录信号确定方法的流程示意图；
图3为本发明实施例提供的存储区域确定方法的流程示意图；
图4为本发明实施例提供的RAM例化方法的流程示意图；
图5为本发明实施例提供的信号采样方法的流程示意图；
图6本发明实施例提供的采样时间精度确定方法的流程示意图；
图7为本发明实施例提供的将待记录信号写入RAM的方法的流程示意图；
图8为本发明实施例提供的另一种CPLD日志记录方法的流程示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明中的技术方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
参见图1，为本发明实施例提供的一种CPLD日志记录方法的流程示意图，如图1所示，本发明实施例提供的CPLD日志记录方法，包括：
S10：获取bug类型，根据所述bug类型确定待记录信号。
S20：获取CPLD内部随机存取存储器(random access memory，RAM)信息，确定存储区域。
S30：对所述RAM进行例化。
S40：对所述待记录信号进行采集。
S50：将所述待记录信号写入所述存储区域。
现对各步骤进行详细描述，获取的bug类型为用户想要分析解决的bug，CPLD获取用户设置的bug类型后，根据bug类型确定需要记录的信号，其中，每次设置的bug类型可以有多个，具体的，参见图2，为本发明实施例提供的待记录信号确定方法的流程示意图，如图2所示，步骤S10中根据所述bug类型确定待记录信号具体包括：
S11：根据bug复现过程确定关联信号。
S12：根据可能产生bug的原因，从所述关联信号中选取可疑信号作为待记录信号。
当bug发生时，需要通过复现发现bug产生的原因，但是在复现的过程中涉及到的相关信号众多，其中有些信号根据经验可以判断出与bug的产生没有关系，但是对于某些信号，我们在复现过程中不能确定是否影响bug的产生，也无法确定是其中的某些信号单独作用导致的bug还是综合作用导致的bug，因此，我们需要从复现的过程中，初步判断出可能导致此次bug的可疑信号作为待记录信号，这些可疑信号来自CPLD的内部寄存器， 但CPLD内部寄存器的数量众多，这些可疑信号也可能来自多个不同的寄存器，因此，本发明实施例在采集可疑信号的时候会对CPLD内部的全部寄存器进行信号采集操作，对于不发送可疑信号的寄存器，虽然有采集操作过程，但是因为没有设定的可以信号输出，因此没有采集结果，也不需要进行记录。
参见图3，为本发明实施例提供的存储区域确定方法的流程示意图，如图3所示，步骤S20中确定存储区域具体包括；
S21：确定所述RAM的存储空间，并计算剩余存储空间。
S22：根据所述待记录信号的个数确定每次采集的所述待记录信号的占用空间。
S23：根据所述占用空间和剩余存储空间确定存储区域。
本发明所采用RAM为CPLD的内部RAM，可以将CPLD内部寄存器的数值直接进行保存，因为数据只在CPLD内部存取，因此存取效率高，且不易出现存储信息错误的情况。但是CPLD内的RAM还需要进行其他信息的存储，不能全部用来保存待记录信号，因此，我们在使用时首先需要获取RAM的信息，计算其中的剩余存储空间，然后根据每次需要采集的信号个数计算出每次存储时将会占用多少存储空间，然后结合RAM的剩余存储空间确定出用于存储的区域。
本发明实施例是通过CPLD内部的RAM实现的，为了实现本发明，需要通过CPLD内部的IP核进行功能设计(即确定RAM的存储区域，每次存储占用的空间，以及存储区域内具体存储地址的偏移量)，在进行功能设计之前需要对RAM进行例化处理，具体的，参见图4，为本发明实施例提供的RAM例化方法的流程示意图，如图4所示，步骤S30中对所述RAM进行例化具体包括：
S31：根据所述待记录信号确定数据宽度和存储深度。
S32：根据所述数据宽度和存储深度进行存储参数设置。
S33：定义存储初始位置及每次记录的地址偏移量。
S34：定义所述RAM的写通道和读通道，并设置相关参数。
在步骤S30中，初步确定了RAM中的存储区域，但是我们需要对RAM进行例化之后才可以将该区域作为专用于存储寄存器信号的区域，而不会再有其他数据存入，从而影响数据的有效性。在对RAM进行例化时，我们需要根据待记录信号每次采集的大小，以及采集的个数确定数据宽度和存储深度，其中，数据宽度即为一个信号数据的长度，本实施例中设置为1bit，存储深度根据信号数据的长度(即数据宽度)及一次采集的信号个数决定，当采集信号的个数为10个时，存储的深度只少应为10bit才能保证将这个10个信号全部保存下来，当RAM的剩余内存较多时，我们可以将存储深度设置的较大，但要保证设置的存储深度应为一次存储占用空间的整数倍，从而保证每次采集的数据可以保存在连续的地址之中。
数据长度和存储深度确定之后只是确定了需要多大的存储空间，但是我们需要将选用的存取区域固定下来，因此就需要定义存储初始位置，即第一次采集到的数据所存放的位置，当我们定义的存储深度为一次存储占用空间的整数倍时，下一次采集到的信号将会存在下一个地址中，此时我们需要定义地址偏移量，用来指示信号的存储位置，其中，由于采集的信号数量以及每个信号的长度在该bug没有解决前是不变的，因此，地址偏移量也 保持不变，从而我们可以定义地址偏移量为一次存储所占用空间的大小，例如，一次采集信号的数量为10个，每个信号的大小为1bit，上次的存储区域为0000H，则新采集信号的存储地址为0000H+10bit，其中10bit即为地址偏移量，需要说明的是，这仅为本发明的一示例性说明，不能代表其正常运行时的实际存储地址。
本发明实施例中存储的寄存器数据在bug发生后需要进行读取供bug问题的分析，为了保证可以同时进行写操作和读操作，分别定义了写通道和读通道，可以实现写操作和读操作的同时进行。
参见图5，为本发明实施例提供的信号采样方法的流程示意图，如图5所示，在步骤S40中对所述待记录信号进行采集具体包括：
S41：确定采样时间精度。
S42：根据所述采样时间精度设置时钟脉冲。
S43：根据所述时钟脉冲对待记录信号进行采样。
信号的采集以时钟脉冲作为触发条件，当时钟脉冲到来时就采集一次信号，这样，通过控制时钟脉冲的宽度可以有效的控制信号采集的频率，可以避免过快或过慢采集。
参见图6，本发明实施例提供的采样时间精度确定方法的流程示意图，如图6所示，确定采样时间精度具体包括：
S411：获取待记录信号的脉冲频率。
S412：根据所述脉冲频率以及奈奎斯特采样定律确定采样频率。
S413：将所述采样频率取倒数即为采样时间精度。
根据奈奎斯特采样定律，当被采集信号的频率为fm时，采样频率至少为2fm，但是根据实际情况也可以设置为5fm或10fm，具体采样频率由用户自行设置，在此不做赘述。
参见图7，为本发明实施例提供的将待记录信号写入RAM的方法的流程示意图，如图7所示，步骤S50中将所述待记录信号写入所述存储区域具体包括：
S51：根据所述例化结果确定地址信号。
S52：确定触发条件，根据所述触发条件设置写使能信号。
S53：当所述写使能信号有效时将采集到的待记录信号根据所述地址信号写入对应的存储地址。
S54：所述地址信号根据所述例化结果递增。
S55：判断当前信号状态是否异常。
如果是则停止信号采集，如果否则在写使能信号有效时将采集到的待记录信号写入对应的存储地址。
其中，当所述地址信号为所述存储区域最大值时，其递增结果为存储初始位置，例如，定义的存储区域为0000H-1000H，则当信号存储至1000H之后，下一信号的存储地址调回0000H，并覆盖0000H中原来存储的信号数据。
所述判断当前信号状态是否异常具体包括：判断当前保存的信号是否为正常值。假设，某信号在一个周期内的信号传输依次为1、2、3、4、5，但如果采集到的实际数据变为了其他数值，例如1、1、1、3、2，则可以确定信号异常，此异常可能是导致bug的原因，因此，当信号异常时该异常信号作为中断信号，令时钟脉冲中断，停止信号采集，防止因 为继续采集而使信号异常前的数据被覆盖。需要说明的是，当信号异常使采集信号中断后，如果系统没有宕机，则地址信号还保存有下一信号要保存的地址，当重新开始采集信号之后可以从此时地址信号保存的地址继续存储也可以从初始位置开始存储，但如果系统发生了宕机，则此时RAM中的数据被清除，只能重新进行例化从初始位置重新进行存储。
参见图8，为本发明实施例提供的另一种CPLD日志记录方法的流程示意图，如图8所示，本发明实施例还包括：从所述存储区域内读取保存的信号，用于bug分析。
用户可以从RAM中将存储的寄存器数据进行读取用于bug的分析，具体采用何种方式进行读取本发明不做限制。
本发明中首先确定需要记录信号的bug类型，然后根据bug在复现过程确定会涉及到的相关信号，再根据经验从相关信号中确定出可能造成bug的可疑信号并进行记录，记录时从CPLD中获取RAM信息，根据RAM的存储情况确定用于存放可疑信号的存储区域，将采集到的可疑信号进行存储，因为采集的可疑信号来自CPLD的内部寄存器，存储用的RAM也是CPLD的内部结构，因此，实现了CPLD内部数据的实时采集存储，保证了数据的正确性，当存储的信号异常时将立即停止对信号的采集和存储，因此，可以将bug产生前的寄存器的数据进行保存，便于bug产生原因的分析，提高了bug问题分析的效率。
以上所述仅是本发明的具体实施方式，使本领域技术人员能够理解或实现本发明。对这些实施例的多种修改对本领域的技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种CPLD日志记录方法，其特征在于，包括：
    获取bug类型，根据所述bug类型确定待记录信号；
    获取CPLD内部RAM信息，确定存储区域；
    对所述RAM进行例化；
    对所述待记录信号进行采集；
    将所述待记录信号写入所述存储区域。
  2. 根据权利要求1所述的CPLD日志记录方法，其特征在于，所述根据所述bug类型确定待记录信号具体包括：
    根据bug复现过程确定关联信号；
    根据可能产生bug的原因，从所述关联信号中选取可疑信号作为待记录信号。
  3. 根据权利要求1所述的CPLD日志记录方法，其特征在于，所述确定存储区域具体包括；
    确定所述RAM的存储空间，并计算剩余存储空间；
    根据所述待记录信号的个数确定每次采集的所述待记录信号的占用空间；
    根据所述占用空间和剩余存储空间确定存储区域。
  4. 根据权利要求1所述的CPLD日志记录方法，其特征在于，所述对所述RAM进行例化具体包括：
    根据所述待记录信号确定数据宽度和存储深度；
    根据所述数据宽度和存储深度进行存储参数设置；
    定义存储初始位置及每次记录的地址偏移量；
    定义所述RAM的写通道和读通道，并设置相关参数。
  5. 根据权利要求1所述的CPLD日志记录方法，其特征在于，所述对所述待记录信号进行采集具体包括：
    确定采样时间精度；
    根据所述采样时间精度设置时钟脉冲；
    根据所述时钟脉冲对待记录信号进行采样。
  6. 根据权利要求5所述的CPLD日志记录方法，其特征在于，所述确定采样时间精度具体包括：
    获取待记录信号的脉冲频率；
    根据所述脉冲频率以及奈奎斯特采样定律确定采样频率；
    将所述采样频率取倒数即为采样时间精度。
  7. 根据权利要求1所述的CPLD日志记录方法，其特征在于，所述将所述待记录信号写入所述存储区域具体包括：
    根据例化结果确定地址信号；
    确定触发条件，根据所述触发条件设置写使能信号；
    当所述写使能信号有效时将采集到的待记录信号根据所述地址信号写入对应的存储地 址；
    所述地址信号根据例化结果递增；
    判断当前信号状态是否异常；
    如果是则停止信号采集，如果否则在写使能信号有效时将采集到的待记录信号写入对应的存储地址。
  8. 根据权利要求7所述的CPLD日志记录方法，其特征在于，当所述地址信号为所述存储区域最大值时，其递增结果为存储初始位置。
  9. 根据权利要求7所述的CPLD日志记录方法，其特征在于，所述判断当前信号状态是否异常具体包括：判断当前保存的信号是否为正常值。
  10. 根据权利要求1-9任一所述的CPLD日志记录方法，其特征在于，所述方法还包括：从所述存储区域内读取保存的信号，用于bug分析。
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