WO2019188178A1 - Système multi-cœur - Google Patents

Système multi-cœur Download PDF

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Publication number
WO2019188178A1
WO2019188178A1 PCT/JP2019/009630 JP2019009630W WO2019188178A1 WO 2019188178 A1 WO2019188178 A1 WO 2019188178A1 JP 2019009630 W JP2019009630 W JP 2019009630W WO 2019188178 A1 WO2019188178 A1 WO 2019188178A1
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WO
WIPO (PCT)
Prior art keywords
processing
core
cpu
execution
task
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PCT/JP2019/009630
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English (en)
Japanese (ja)
Inventor
智明 片野
Original Assignee
株式会社デンソー
株式会社エヌエスアイテクス
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Application filed by 株式会社デンソー, 株式会社エヌエスアイテクス filed Critical 株式会社デンソー
Publication of WO2019188178A1 publication Critical patent/WO2019188178A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Definitions

  • This disclosure relates to a multi-core system.
  • Patent Document 1 Although the cost of only the corresponding task can be estimated, it is difficult to make a determination reflecting the overhead of the OS and multi-task processing. It is also conceivable to formulate rules for the scheduler to schedule in advance. However, while the development man-hours for formulating execution rules increase, allocation can only be made within the scope of the established rules. Further, since a compiler and scheduler for interpreting the rules are required, the system becomes complicated and the implementation cost increases.
  • This disclosure is intended to provide a multi-core system that can suppress an increase in mounting cost to a minimum and can perform task optimal allocation among a plurality of cores.
  • the present disclosure is a multi-core system, and includes a plurality of cores having a function of notifying the execution status of task processing, and a scheduler that receives processing status information related to the execution status of processing from the plurality of cores.
  • the execution status of each core can be dynamically grasped.
  • processing overhead due to scheduling can be reduced.
  • FIG. 1 is a diagram illustrating a system configuration of a multi-core system according to the present embodiment.
  • FIG. 2 is a diagram illustrating functional components of the multi-core system according to the present embodiment.
  • FIG. 3 is a diagram for explaining processing of the multi-core system according to the present embodiment.
  • FIG. 4 is a diagram for explaining processing of the multi-core system according to the present embodiment.
  • FIG. 5 is a diagram for explaining processing of the multi-core system according to the present embodiment.
  • FIG. 6 is a diagram for explaining processing of the multi-core system according to the present embodiment.
  • FIG. 7 is a diagram for explaining processing of the multi-core system according to the present embodiment.
  • the multi-core system includes software 2 and hardware 4.
  • the software 2 includes an OS 21, a task 22 executed by the OS, a paratask 23 executed by the OS, and a paratask 24 outside the OS jurisdiction.
  • the OS 21 is an operating system for driving the CPU0_41 and the CPU1_42 included in the hardware 4.
  • the paratask 23 and the paratask 24 are equivalent in processing content.
  • the hardware 4 includes a CPU 0_41, a CPU 1_42, an accelerator DFP (Data Flow Processor) 43, a scheduler 44, a DMA (Direct Memory Access) 45, an interconnect 46, and a memory 47.
  • DFP Data Flow Processor
  • DMA Direct Memory Access
  • CPU0_41 and CPU1_42 are processor units under the jurisdiction of the OS 21, and the operation is controlled by the OS 21.
  • the CPU 0_41 has a PMU (Performance Unit) 411.
  • the PMU 411 is a part that holds processing state information of the CPU 0_41.
  • the PMU 411 is a part that notifies the scheduler 44 of the processing state information of the CPU 0_41.
  • the processing status information of the CPU 0_41 includes information such as the number of execution cycles, the number of execution instructions, the number of processes in the conditional branch, the cache hit rate, and the processing rate of the branch destination in the conditional branch instruction.
  • CPU1_42 has PMU421.
  • the PMU 421 has the same function as the PMU 411.
  • the DFP 43 is an accelerator, and is positioned as an individual master provided to cope with a heavy calculation load on the CPU0_41 and the CPU1_42.
  • the DFP 10 is configured to support interrupts generated by the scheduler 44.
  • the interconnect 46 is a part responsible for exchanging information between the DMA 45 and the memory 47.
  • the memory 47 is provided with a data area 471 and a data area 472.
  • the data area 471 is an area for holding data on the CPU0_41 and CPU1_42 sides.
  • the data area 472 is an area for holding data on the DFP 43 side.
  • the DMA 45 is a part for copying data between memories 47.
  • the DMA 45 performs data copying as necessary between a data area 471 that is an area for holding data on the CPU 0_41 and CPU 1_42 sides and a data area 472 that is for holding data on the DFP 43 side.
  • the DMA 45 copies the data used for the process from the data area 471 to the data area 472. Since the processing result of the DFP 43 is stored in the data area 472, the DMA 45 copies the processing result data from the data area 472 to the data area 471.
  • the CPU 0_41 includes a PMU 411 and a register 412.
  • the PMU 411 acquires a processing state from an arithmetic unit such as an ALU, Decode, and Fetch provided in the CPU 0_41 and a cache, and holds processing state information.
  • the PMU 411 transmits processing state information to the scheduler 44.
  • the register 412 is a part that holds execution core notification information transmitted from the scheduler 44.
  • the CPU 1_42 has a PMU 421 and a register 422.
  • the PMU 421 acquires a processing state from an arithmetic unit such as ALU, Decode, and Fetch provided in the CPU 1_42 and a cache, and holds processing state information.
  • the PMU 421 transmits processing state information to the scheduler 44.
  • the register 422 is a part that holds execution core notification information transmitted from the scheduler 44.
  • the DFP 43 has a PMU 431 and a register 432.
  • the PMU 431 acquires a processing state from an arithmetic unit such as ALU, Decode, and Fetch provided in the DFP 43 and a cache, and holds processing state information.
  • the PMU 431 transmits processing state information to the scheduler 44.
  • the register 432 is a part that holds execution core notification information transmitted from the scheduler 44.
  • the scheduler 44 includes a processing state reception unit 441, an execution core determination unit 442, an execution core confirmation reception unit 443, and an execution core notification unit 444 as functional components.
  • the processing state receiving unit 441 is a part that receives processing state information transmitted from the PMU 411, the PMU 421, and the PMU 431.
  • the processing state reception unit 441 outputs the received processing state information of the CPU0_41, CPU1_42, and DFP43 to the execution core determination unit 442.
  • the execution core confirmation receiving unit 443 is a part that receives execution core confirmation information transmitted from the CPU0_41 and the CPU1_42.
  • the execution core confirmation information is information for confirming whether or not the execution can be performed as it is when performing task processing using the CPU 1_41 and the CPU 1_42.
  • the execution core confirmation receiving unit 443 outputs the execution core confirmation information to the execution core determination unit 442.
  • the execution core determination unit 442 is a part that determines the core for task processing in consideration of the processing status information of the CPU0_41, the CPU1_42, and the DFP43, triggered by the input of execution core confirmation information. For example, when execution core confirmation information is input from the CPU 0_41, if the entire processing speed is faster when the CPU 0_41 executes the processing as it is even if the processing state information is taken into consideration, the CPU 0_41 is determined as the task processing core. On the other hand, when the execution core confirmation information is input from the CPU 0_41 and the processing state information is taken into consideration and the overall processing speed is faster when the CPU 1_42 or the DFP 43 executes, the CPU 1_42 or the DFP 43 is determined as the task processing core. The execution core determination unit 442 outputs the determined result to the execution core notification unit 444.
  • the execution core notification unit 444 is a part that transmits execution core notification information to a core that processes a task based on the determination result of the execution core determination unit 442.
  • FIG. 3 is a flowchart for explaining processing of the entire system in the present embodiment with reference to FIG.
  • the OS confirms the execution core.
  • execution core confirmation information is transmitted to the CPU0_41 and the CPU1_42.
  • execution core notification information is transmitted.
  • step S002 it is determined whether or not the task is executed by the CPU 0_41 or the CPU 1_42 which is the main CPU.
  • the process proceeds to step S003. If the task is not executed by the CPU 0_41 or the CPU 1_42 which is the main CPU, the process proceeds to step S004.
  • step S003 the task is executed by the CPU 0_41 or the CPU 1_42 which is the main CPU.
  • step S004 preparation for task processing in the DFP 43, which is another core, is executed. Specifically, the DMA 45 copies necessary data from the data area 471 to the data area 472.
  • step S005 the task is executed by the DFP 43.
  • step S005 an end process is executed. Specifically, the DMA 45 copies data as a processing result from the data area 472 to the data area 471.
  • step S051 any of CPU0_41, CPU1_42, and DFP43 executes task processing.
  • step S052 following step S051, the core that executed the task updates the PMU value (processing state information).
  • step S053 following step S052 any one of the PMU 411, the PMU 421, and the PMU 431 transmits the updated value to the scheduler 44.
  • step S101 a PMU value that is processing state information transmitted by the PMU 411, the PMU 421, and the PMU 431 is received.
  • step S102 the execution core determination unit 442 converts the PMU value, which is processing state information, into a value for comparing execution states.
  • step S103 the processing states of all cores are compared.
  • step S104 the execution core determination unit 442 determines a core to execute the next task process.
  • step S151 the execution core confirmation receiving unit 443 receives the execution core confirmation information.
  • step S152 the execution core determination unit 442 determines whether the task is executed by the CPU 0_41 or the CPU 1_42 which is the main CPU. If the task is executed by the CPU 0_41 or the CPU 1_42 which is the main CPU, the process proceeds to step S153. If the task is not executed by the CPU 0_41 or the CPU 1_42 which is the main CPU, the process proceeds to step S154.
  • step S153 the execution core notification unit 444 transmits execution core notification information to the CPU 0_41 or the CPU 1_42 which is the main CPU.
  • step S154 the execution core notification unit 444 transmits execution core notification information to the DFP 43.
  • step S155 following step S154 an instruction to receive data necessary for task execution in the DFP 43 is output to the DMA 45.
  • step S156 following step S155, the DMA 45 is activated and executes necessary data copying.
  • step S157 following step S156, the operation of the DMA 45 is completed.
  • step S158 following step S157, the DFP 43, which is another core, is activated.
  • step S201 the scheduler 44 receives a task processing end notification from the DFP 43, which is another core.
  • step S202 the DMA 45 is activated in order to return the task processing result to the CPU0_41 and CPU1_42 which are the main CPUs.
  • the DMA 45 copies the processing result data from the data area 472 to the data area 471.
  • step S203 the operation of the DMA 45 is completed.
  • step S204 the scheduler 44 transmits a task end notification to the CPU0_41 and CPU1_42 which are the main CPUs.
  • step S205 it is determined whether there is a next execution task. If there is a next execution task, the process ends. If there is no next execution task, the termination process of DFP 43 which is another core is executed.
  • the present embodiment is a multi-core system that performs processing from CPU0_41, CPU1_42, and DFP43 as a plurality of cores having a function of notifying the execution status of task processing, and CPU0_41, CPU1_42, and DFP43 that are a plurality of cores.
  • a scheduler 44 for receiving processing state information relating to the execution status of
  • the scheduler 44 When the scheduler 44 receives the processing state information, the execution state of each core such as the CPU 0_41, the CPU 1_42, and the DFP 43 can be dynamically grasped. By notifying the processing execution state from the core side and managing the notified execution state by a scheduler independent of the core, processing overhead due to scheduling can be reduced. Since no special compiler or pre-rule formulation is required, cost reduction can be achieved with a simple implementation configuration.
  • the scheduler 44 assigns task processing to each of the plurality of cores CPU0_41, CPU1_42, and DFP43 based on the processing state information.
  • tasks can be assigned to the core with the lightest processing load.
  • the plurality of cores are configured by at least two or more types of CPUs CPU0_41, CPU1_42, and DFP43.
  • the scheduler 44 receives an inquiry as to whether or not task processing can be executed from at least a part of the plurality of cores, and executes tasks from the plurality of cores based on the processing state information corresponding to the reception timing. Determine the core that performs the processing.
  • Processing can be accurately assigned after judging the current processing status of each heterogeneous core. Performance improvement and power consumption reduction can be realized.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)

Abstract

L'invention concerne un système multi-cœur comprenant : une pluralité de cœurs (41, 42, 43) ayant une fonction d'émission d'une notification d'un état d'exécution d'un processus de tâche ; et un programmateur (44) pour recevoir, en provenance de la pluralité de cœurs (41, 42, 43), des informations d'état de processus concernant l'état d'exécution de processus.
PCT/JP2019/009630 2018-03-30 2019-03-11 Système multi-cœur WO2019188178A1 (fr)

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JP2018-068432 2018-03-30
JP2018068432A JP2019179415A (ja) 2018-03-30 2018-03-30 マルチコアシステム

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008084009A (ja) * 2006-09-27 2008-04-10 Toshiba Corp マルチプロセッサシステム
JP2015035028A (ja) * 2013-08-07 2015-02-19 株式会社東芝 情報処理方法、情報処理装置及びプログラム

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007037006A1 (fr) * 2005-09-29 2007-04-05 Fujitsu Limited Processeur multiconducteur
WO2012120655A1 (fr) * 2011-03-08 2012-09-13 富士通株式会社 Procédé et système de planification
JP2014067248A (ja) * 2012-09-26 2014-04-17 Renesas Electronics Corp プロセッサ、割り込み処理方法及び割り込み制御装置
JP6214142B2 (ja) * 2012-10-09 2017-10-18 キヤノン株式会社 情報処理装置、情報処理方法およびプログラム
JP2018022345A (ja) * 2016-08-03 2018-02-08 東芝メモリ株式会社 情報処理システム

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008084009A (ja) * 2006-09-27 2008-04-10 Toshiba Corp マルチプロセッサシステム
JP2015035028A (ja) * 2013-08-07 2015-02-19 株式会社東芝 情報処理方法、情報処理装置及びプログラム

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