WO2019186838A1

WO2019186838A1 - Solid-state imaging element, solid-state imaging device, solid-state imaging system, and method for driving solid-state imaging element

Info

Publication number: WO2019186838A1
Application number: PCT/JP2018/013007
Authority: WO
Inventors: 悠吾能勢; 基範石井; 信三香山; 春日　繁孝
Original assignee: パナソニックＩｐマネジメント株式会社
Priority date: 2018-03-28
Filing date: 2018-03-28
Publication date: 2019-10-03
Also published as: JPWO2019186838A1; JP7033739B2

Abstract

According to the present invention, a light receiving unit (200) is configured to be switchable to a light exposing state and a light shielding state, and generates charges according to light received in the light exposing state. A charge storage unit (300) stores charges. A first charge transmitting unit (400) transmits charges from the light receiving unit (200) to the charge storage unit (300). An output unit (500) outputs signals according to charges stored in the charge storage unit (300). A charge storage capacitor (600) stores charges. A second charge transmitting unit (700) transmits charges between the charge storage unit (300) and one end of the charge storage capacitor (600).

Description

Solid-state imaging device, solid-state imaging device, solid-state imaging system, and driving method of solid-state imaging device

The technology disclosed here relates to solid-state imaging technology.

Conventionally, a solid-state imaging device capable of performing photon counting in addition to imaging of a subject has been developed. By using such photon counting, for example, it is possible to perform a distance measurement method of TOF (Time Of Flight) method.

Patent Document 1 discloses a solid-state imaging device in which a plurality of pixels having a first pixel group including an infrared transmission filter are two-dimensionally arranged. Each pixel of the first pixel group includes a light receiving circuit, a counter circuit, a comparison circuit, and a memory circuit. The light receiving circuit has a light receiving element that performs photoelectric conversion for converting received light into an electric signal, sets a photoelectric time for photoelectric conversion in the light receiving element by an exposure signal, and detects incident light that reaches a pixel within the photoelectric time. A light reception signal corresponding to the presence or absence is output. The counter circuit counts the number of arrivals of incident light as a count value based on the light reception signal input from the light reception circuit. The comparison circuit sets a value corresponding to the count value as a threshold value, and turns on the comparison signal when the count value is larger than the threshold value. The storage circuit receives the comparison signal and a time signal that changes with time, and stores the time signal as a distance signal when the comparison signal is in an ON state.

Further, as shown in FIG. 10A of Patent Document 1, an amplification transistor is connected to the memory circuit, and a selection transistor is connected to the amplification transistor. Further, a luminance image amplification transistor is connected to the light receiving circuit, and a luminance image selection transistor is connected to the luminance image amplification transistor. The solid-state imaging device obtains a distance image by obtaining a distance signal based on the received light signal via the counter circuit, the comparison circuit, and the storage circuit, and passes through the luminance image amplification transistor and the luminance image selection transistor. A luminance image of the object is obtained by obtaining a light reception signal.

International Publication No. 2017/098725 Pamphlet

However, in the solid-state imaging device disclosed in Patent Document 1, since two output units each including an amplification transistor and a selection transistor are provided, it is difficult to reduce the circuit scale of the solid-state imaging device.

The technology disclosed herein relates to a solid-state imaging device, and the solid-state imaging device is configured to be switchable between an exposure state and a light-shielding state, and a light-receiving unit that generates charges according to light received in the exposure state; A charge storage unit for storing charge, a first charge transfer unit for transferring the charge from the light receiving unit to the charge storage unit, an output unit for outputting a signal corresponding to the charge stored in the charge storage unit, A charge storage capacitor that stores the charge; and a second charge transfer unit that transfers the charge bidirectionally between the charge storage unit and one end of the charge storage capacitor.

The technology disclosed herein relates to a method for driving a solid-state imaging device, and the solid-state imaging device is configured to be switchable between an exposure state and a light-shielding state, and generates a charge corresponding to light received in the exposure state. A light receiving unit; a charge storage unit for storing the charge; a first charge transfer unit for transferring the charge from the light receiving unit to the charge storage unit; and a signal corresponding to the charge stored in the charge storage unit. A charge storage capacitor that stores the charge, and a second charge transfer unit that transfers the charge bidirectionally between the charge storage unit and one end of the charge storage capacitor. In this solid-state imaging device driving method, the charge generated by the light receiving unit is transferred to the charge storage unit by the first charge transfer unit, and the charge stored in the charge storage unit is transferred to the second charge transfer unit. A first step of driving the solid-state imaging device so that a transfer operation transferred to the charge storage capacitor by a unit is performed a predetermined number of times, and after the first step, A second step of driving the solid-state imaging device so that charges are transferred to the charge storage unit by the second charge transfer unit and a signal corresponding to the charge stored in the charge storage unit is output by the output unit; And.

According to the technology disclosed herein, the charge stored in the charge storage capacitor is transferred to the charge storage unit by the second charge transfer unit, and a signal corresponding to the charge stored in the charge storage unit is output from the output unit. Thus, a signal corresponding to the charge stored in the charge storage capacitor can be output. As a result, it is not necessary to separately provide a configuration (a configuration different from the output unit) for outputting a signal corresponding to the charge stored in the charge storage capacitor, so that the circuit scale of the solid-state imaging device can be reduced. .

It is a block diagram which illustrates the composition of a solid imaging system. It is a circuit diagram which illustrates the composition of a solid-state image sensor. It is a conceptual diagram for demonstrating the principle of distance measurement. It is a flowchart which illustrates distance detection control. It is a timing chart which illustrates distance detection control. It is a flowchart which illustrates imaging control. It is a circuit diagram which illustrates the composition of the modification of a solid-state image sensing device.

Hereinafter, embodiments will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Solid-state imaging system)
FIG. 1 illustrates a configuration of a solid-state imaging system 10 according to the embodiment. The solid-state imaging system 10 is configured to perform imaging of an object scene and distance measurement using photon counting. Specifically, the solid-state imaging device 20, the light source 30, and the control unit 40 are provided. The solid-state imaging device 20 includes a pixel region 21 and a drive processing unit 22.

[Pixel area]
The pixel region 21 includes P × Q (P and Q are integers of 2 or more) solid-state imaging devices 100 and Q vertical signal lines 110. The P × Q solid-state imaging devices 100 are arranged in a matrix of P rows and Q columns. The Q vertical signal lines 110 correspond to the Q solid-state image sensor rows of the P × Q solid-state image sensors 100, respectively.

[Solid-state image sensor]
FIG. 2 illustrates the configuration of the solid-state imaging device 100. The solid-state imaging device 100 includes a light receiving unit 200, a charge storage unit 300, a first charge transfer unit 400, an output unit 500, a charge storage capacitor 600, a second charge transfer unit 700, and a first reset unit 800. The second reset unit 900 is provided.

<Light receiving section>
The light receiving unit 200 is configured to be switchable between an exposure state and a light shielding state. The light receiving unit 200 is configured to generate a charge corresponding to the light received in the exposure state. Note that the light receiving unit 200 does not generate charges in a light-shielded state. In this example, the light receiving unit 200 is switched between an exposure state and a light shielding state in response to the exposure signal EXP.

Specifically, in this example, the light receiving unit 200 includes a photoelectric conversion element 201. The light receiving unit 200 is configured to expose the photoelectric conversion element 201 in the exposure state and shield the photoelectric conversion element 201 in the light shielding state. For example, the light receiving unit 200 is provided with an exposure mechanism (not shown) that exposes and shields the photoelectric conversion element.

In this example, the photoelectric conversion element 201 is composed of an avalanche photodiode. However, the present invention is not limited to this, and the photoelectric conversion element 201 may be configured by other types of photodiodes.

<Charge storage unit>
The charge storage unit 300 is configured to store charges. In this example, the charge storage unit 300 includes a floating diffusion unit 301.

<First charge transfer unit>
The first charge transfer unit 400 is configured to transfer charges from the light receiving unit 200 to the charge storage unit 300. In this example, the first charge transfer unit 400 transfers charges from the light receiving unit 200 to the charge storage unit 300 in response to the transfer control signal TRN. Specifically, in this example, the first charge transfer unit 400 includes a transfer transistor 401.

The transfer transistor 401 is connected between the photoelectric conversion element 201 of the light receiving unit 200 and the floating diffusion unit 301 of the charge storage unit 300. The gate of the transfer transistor 401 is connected to the transfer control node 402 to which the transfer control signal TRN is applied. The transfer transistor 401 is switched between an on state and an off state in response to the transfer control signal TRN.

<Output section>
The output unit 500 is configured to output a signal corresponding to the charge accumulated in the charge accumulation unit 300. In this example, the output unit 500 outputs a signal corresponding to the charge accumulated in the charge accumulation unit 300 in response to the selection control signal SEL. Specifically, in this example, the output unit 500 includes an amplification transistor 501 and a selection transistor 502.

The amplification transistor 501 and the selection transistor 502 are connected in series between the power supply node 503 to which the power supply voltage VDD is applied and the vertical signal line 110. The gate of the amplification transistor 501 is connected to the floating diffusion unit 301 of the charge storage unit 300. The gate of the selection transistor 502 is connected to a selection control node 504 to which a selection control signal SEL is applied. The selection transistor 502 is switched between an on state and an off state in response to the selection control signal SEL.

<Charge storage capacitor>
The charge storage capacitor 600 is configured to store charges.

<Second charge transfer unit>
The second charge transfer unit 700 is configured to transfer charges bidirectionally between the charge storage unit 300 and one end of the charge storage capacitor 600. In this example, the second charge transfer unit 700 transfers charges from the charge storage unit 300 to one end of the charge storage capacitor 600 (or from one end of the charge storage capacitor 600 to the charge storage unit 300) in response to the switching control signal SWT. To do. Specifically, in this example, the second charge transfer unit 700 includes a switching transistor 701, a rectifying element 702, and a potential control node 703.

The switching transistor 701 and the rectifying element 702 are connected in series between the floating diffusion portion 301 of the charge storage unit 300 and one end of the charge storage capacitor 600. The gate of the switching transistor 701 is connected to a switching control node 704 to which a switching control signal SWT is applied. The switching transistor 701 is switched between an on state and an off state in response to the switching control signal SWT.

The potential control node 703 is connected to the other end of the charge storage capacitor 600. In the potential control node 703, the potential of one end of the charge storage capacitor 600 (hereinafter referred to as “memory potential VCNT”) when transferring charge from the charge storage capacitor 600 to the charge storage unit 300 is the potential of the charge storage unit 300 (this In the example, the potential control signal EIV is applied so as to be higher than the potential of the floating diffusion portion 301 (hereinafter referred to as “intermediate potential VFD”).

In this example, the rectifying element 702 is constituted by a rectifying transistor 710. The rectifying transistor 710 is diode-connected. Specifically, the gate of the rectifying transistor 710 is connected to the drain or source of the rectifying transistor 710.

In this example, a rectifying element 702 and a switching transistor 701 are sequentially arranged from the floating diffusion portion 301 of the charge storage portion 300 toward one end of the charge storage capacitor 600. Note that the arrangement of the switching transistor 701 and the rectifying element 702 may be reversed. That is, the switching transistor 701 and the rectifying element 702 may be sequentially arranged from the floating diffusion part 301 of the charge storage part 300 toward one end of the charge storage capacitor 600.

<First reset section>
The first reset unit 800 is configured to reset the intermediate potential VFD (the potential of the charge storage unit 300, in this example, the potential of the floating diffusion unit 301). In this example, the first reset unit 800 resets the intermediate potential VFD in response to the first reset control signal RS1. Specifically, in this example, the first reset unit 800 includes a first reset transistor 801.

The first reset transistor 801 is connected between the first reset voltage node 802 to which the first reset voltage VRS1 for resetting the intermediate potential VFD is applied and the floating diffusion unit 301 of the charge storage unit 300. The gate of the first reset transistor 801 is connected to the first reset control node 803 to which the first reset control signal RS1 is applied. The first reset transistor 801 is switched between an on state and an off state in response to the first reset control signal RS1.

<Second reset section>
The second reset unit 900 is configured to reset the storage potential VCNT (the potential at one end of the charge storage capacitor 600). In this example, the second reset unit 900 resets the storage potential VCNT in response to the second reset control signal RS2. Specifically, in this example, the second reset unit 900 includes a second reset transistor 901.

The second reset transistor 901 is connected between the second reset voltage node 902 to which the second reset voltage VRS2 for resetting the storage potential VCNT is applied and one end of the charge storage capacitor 600. The gate of the second reset transistor 901 is connected to the second reset control node 903 to which the second reset control signal RS2 is applied. The second reset transistor 901 is switched between an on state and an off state in response to the second reset control signal RS2.

(Drive processing section)
Returning to FIG. 1, the drive processing unit 22 is configured to drive P × Q solid-state imaging devices 100. In this example, the drive processing unit 22 uses the exposure signal EXP, the transfer control signal TRN, the selection control signal SEL, the switching control signal SWT, the first reset control signal RS1, and the second reset control signal RS2 as P × Q solids. By supplying each of the image pickup devices 100, P × Q solid-state image pickup devices 100 are driven.

In this example, the drive processing unit 22 is configured to perform a photon counting operation and an imaging operation in response to control by the control unit 40.

In the photon counting operation, the drive processing unit 22 transfers the charge generated by the light receiving unit 200 to the charge storage unit 300 by the first charge transfer unit 400 and the charge stored in the charge storage unit 300 to the second charge transfer unit. After the transfer operation transferred to the charge storage capacitor 600 by 700 is performed a predetermined number of times, the charge stored in the charge storage capacitor 600 is transferred to the charge storage unit 300 by the second charge transfer unit 700 and charged. The solid-state imaging device 100 is driven so that the output unit 500 outputs a signal corresponding to the charge accumulated in the accumulation unit 300.

In the imaging operation, the drive processing unit 22 outputs a signal corresponding to the charge stored in the charge storage unit 300 by transferring the charge generated by the light receiving unit 200 to the charge storage unit 300 by the first charge transfer unit 400. The solid-state imaging device 100 is driven so as to be output by 500.

Specifically, in this example, the drive processing unit 22 includes a pixel drive circuit 25, a vertical shift register 26, a correlated double sampling circuit 27, a horizontal shift register 28, and an output circuit 29.

<Pixel drive circuit>
In response to the control by the control unit 40, the pixel driving circuit 25 sends the exposure signal EXP, the transfer control signal TRN, the switching control signal SWT, the first reset control signal RS1, and the second reset control signal RS2 to P × Q solids. The image pickup device 100 is configured to be supplied to each.

<Vertical shift register>
The vertical shift register 26 is configured to supply a selection control signal SEL to each of the P × Q solid-state imaging devices 100 in response to control by the control unit 40. The vertical shift register 26 sequentially selects P solid-state image sensor rows of the P × Q solid-state image sensors 100. In this example, the vertical shift register 26 is supplied to Q solid-state image sensors 100 included in a selected solid-state image sensor row among the P solid-state image sensor rows of the P × Q solid-state image sensors 100. The signal level of the selection control signal SEL is changed from the low level to the high level.

In the solid-state imaging device 100 selected by the vertical shift register 26, a signal corresponding to the charge stored in the charge storage unit 300 is output by the output unit 500 to the vertical signal line 110 (the vertical signal line 110 corresponding to the solid-state imaging device 100). Is output. That is, when one of the P solid-state image sensor rows of the P × Q solid-state image sensor 100 is selected by the vertical shift register 26, the Q solid-state image sensors 100 included in the solid-state image sensor row. Q signals are respectively output from the output unit 500 to the Q vertical signal lines 110.

In this example, two vertical shift registers 26 are provided. Then, the selection of the solid-state imaging element row by one of the two vertical shift registers 26 and the selection of the solid-state imaging element row by the other vertical shift register 26 are alternately performed.

<Correlated double sampling circuit>
The correlated double sampling circuit 27 is configured to perform correlated double sampling processing on each of the Q signals respectively output to the Q vertical signal lines 110. Specifically, the correlated double sampling circuit 27 samples a signal level in a later-described signal period and a signal level in a later-described reset period among signals output to the vertical signal line 110, and a difference between these signal levels. Output a signal according to. In this way, by performing the correlated double sampling process, the offset component is removed from the Q signals.

In this example, two correlated double sampling circuits 27 are provided. Then, Q signals respectively output to the Q vertical signal lines 110 from the solid-state imaging element row selected by one vertical shift register 26 out of the two vertical shift registers 26 are one correlated double sampling circuit 27. Q signals respectively output to the Q vertical signal lines 110 from the solid-state imaging element row selected by the other vertical shift register 26 are supplied to the other correlated double sampling circuit 27.

<Horizontal shift register>
The horizontal shift register 28 is configured to sequentially transfer the Q signals processed in the correlated double sampling circuit 27. In this example, two horizontal shift registers 28 are provided, and Q signals processed in one correlated double sampling circuit 27 out of two correlated double sampling circuits 27 are transmitted by one horizontal shift register 28. The Q signals sequentially transferred and processed in the other correlated double sampling circuit 27 are sequentially transferred by the other horizontal shift register 28.

<Output circuit>
The output circuit 29 is configured to amplify the signal transferred by the horizontal shift register 28 with a predetermined amplification gain and output the amplified signal. In this example, two output circuits 29 are provided, and a signal is transferred from one horizontal shift register 28 to one output circuit 29 of the two horizontal shift registers 28, and the other horizontal shift register 28 to the other horizontal shift register 28. A signal is transferred to the output circuit 29.

〔light source〕
The light source 30 is configured to irradiate the signal light L1. In this example, the light source 30 emits signal light L1 (pulse light) having a predetermined pulse width A. For example, the light source 30 is configured to irradiate light to the entire part where three-dimensional information (distance information) is to be acquired by diffusing light as necessary. In addition, the light source 30 is comprised by LED, for example.

(Control part)
The control unit 40 is configured to control the operation of the solid-state imaging device 20 and the operation of the light source 30. For example, the control unit 40 includes an arithmetic processing unit such as a CPU and a storage unit such as a memory that stores a program or information for operating the arithmetic processing unit.

In this example, the control unit 40 includes a drive control unit 41 and an information output unit 42. That is, the drive control unit 41 and the information output unit 42 constitute a part of the function of the control unit 40.

<Drive control unit>
The drive control unit 41 is configured to control the operation of the drive processing unit 22 of the solid-state imaging device 20 and the operation of the light source 30. In this example, the drive control unit 41 is configured to perform distance detection control and imaging control.

In the distance detection control, the drive control unit 41 controls the operation of the drive processing unit 22 so that the photon counting operation is performed by the drive processing unit 22 in each of a plurality of distance detection periods respectively corresponding to a plurality of distance sections. . Further, in the distance detection control, the drive control unit 41, in the transfer operation of the photon counting operation in each of the plurality of distance detection periods, delay time corresponding to the distance detection period from the time when the signal light L1 is emitted from the light source 30. After the TD has elapsed, the light receiving unit 200 enters an exposure state, and the charge generated by the light receiving unit 200 is transferred to the charge storage unit 300 by the first charge transfer unit 400, and the charge stored in the charge storage unit 300 is transferred to the second charge. The operation of the drive processing unit 22 and the operation of the light source 30 are controlled so as to be transferred to the charge storage capacitor 600 by the transfer unit 700.

In the imaging control, the drive control unit 41 controls the drive processing unit 22 such that the drive processing unit 22 performs an imaging operation.

<Information output section>
The information output unit 42 outputs information (distance information) related to the distance to the object based on the signal output from the output unit 500 in the photon counting operation of the pixel drive circuit 25 in each of the plurality of distance detection periods. It is configured. In this example, the information output unit 42 outputs three-dimensional information (distance image) composed of P × Q distance values each indicating a value corresponding to the distance to the object.

[Distance measurement using photon counting]
Next, the principle of distance measurement using photon counting will be described with reference to FIG. In this example, photon counting is used as a distance measuring method of TOF (Time Of Flight) method.

First, the TOF method of distance measurement will be described. The distance measurement method of the TOF method is a method in which light is emitted from the time when light is irradiated toward an object from a light source (in this example, the light source 30) provided in the vicinity of the distance measuring device (in this example, the solid-state imaging device 20). It is a distance measuring method for measuring the time from the time when the object is reflected by the object and returning to the distance measuring device, and for determining the distance from the distance measuring device to the object based on the time.

As shown in FIG. 3, in this solid-state imaging system 10, there are N distances R (for example, distances that can be measured by the solid-state imaging system 10) from the solid-state imaging device 20, which is a distance measurement range, to an arbitrary point. Divided into distance sections. Specifically, the distance section of the first field is set to a section from zero to R / N, the second distance section is set to a section from R / N to 2R / N, and the third The th distance section is set to a section from 2R / N to 3R / N, and the N th distance section is set to a section from R (N−1) / N to R. Here, when an object is present in the Kth (K is an integer greater than or equal to 1 and less than or equal to N) distance section among the N distance sections, reflection is performed from the time when the signal light L1 is emitted from the light source 30. The time T until the time when the light L2 reaches the solid-state imaging device 20 is expressed by the following equation, where the speed of light is “V”.

That is, by setting the time T (delay time TD) from the time when the signal light L1 is emitted from the light source 30 to the time when the light receiving unit 200 is brought into the exposure state from the light shielding state, the light reception in the exposure state is set. It becomes possible for the part 200 to receive the reflected light L2.

Based on such a principle, in the solid-state imaging system 10, the delay time TD in each of the N distance sections is set as follows.

That is, when the light receiving unit 200 is changed from the light shielding state to the exposure state at the time when the delay time TD corresponding to the Kth distance section has elapsed from the time when the signal light L1 is emitted from the light source 30, the light reception in the exposure state is performed. If the unit 200 can receive the reflected light L2, it can be said that the object exists in the Kth distance section. Further, when the light receiving unit 200 in the exposure state receives the reflected light L2, the light receiving unit 200 generates a charge corresponding to the reflected light L2. Then, the charge generated by the light receiving unit 200 is transferred to the charge storage capacitor 600 via the first charge transfer unit 400 and the second charge transfer unit 700 and stored therein, thereby being stored in the charge storage capacitor 600. It is possible to determine whether or not an object exists in the Kth distance section based on the amount of electric charge.

[Operation of drive controller: Distance detection control]
Next, distance detection control by the drive control unit 41 will be described with reference to FIGS. 4 and 5. In this example, distance detection control (steps ST102 to ST111) is performed in each of the N distance detection periods corresponding to the N distance intervals shown in FIG. In the distance detection control, the drive processing unit 22 performs a photon counting operation in N distance detection periods respectively corresponding to N distance sections. The light source 30 emits M (M is an integer of 1 or more) signal light L1 in each of the N distance detection periods. That is, the signal light L1 is irradiated M times in each of the N distance detection periods. FIG. 5 illustrates a case where the light source 30 emits two signal lights L1 in the Kth distance detection period among the N distance detection periods (when M = 2).

<Step ST101>
First, the drive control unit 41 selects the first distance section from among the N distance sections as a target for distance detection control. Thereby, the first distance detection period corresponding to the first distance section is started. Hereinafter, the distance section selected as the target of distance detection control is referred to as “Kth distance section (K is an integer not less than 1 and not more than N)”.

<Step ST102>
When a distance detection period corresponding to the Kth distance section (hereinafter referred to as “Kth distance detection period”) is started, the drive processing unit 22 receives light in response to control by the drive control unit 41. P × Q solid-state imaging devices 100 are reset so that the potential of the unit 200 (in this example, the potential of the photoelectric conversion element 201, hereinafter referred to as “input potential VPD”), the intermediate potential VFD, and the storage potential VCNT are reset. Drive.

As shown at time t1 in FIG. 5, the pixel drive circuit 25 of the drive processing unit 22 sets the signal levels of the transfer control signal TRN, the first reset control signal RS1, the switching control signal SWT, and the second reset control signal RS2 to a low level. To high level. As a result, the transfer transistor 401, the switching transistor 701, the first reset transistor 801, and the second reset transistor 901 are turned on, the intermediate potential VFD is reset by the first reset voltage VRS1, and the storage potential VCNT from the second reset voltage VRS2. Is reset. In addition, since the transfer transistor 401 is in the on state, the input potential VPD is reset together with the reset of the intermediate potential VFD. Then, when the reset of the input potential VPD, the intermediate potential VFD, and the storage potential VCNT is completed (for example, a predetermined reset time elapses), the pixel drive circuit 25 receives the transfer control signal TRN and the first reset control signal RS1. The signal levels of the switching control signal SWT and the second reset control signal RS2 are changed from the high level to the low level. As a result, the transfer transistor 401, the switching transistor 701, the first reset transistor 801, and the second reset transistor 901 are turned off.

<Step ST103>
Next, the drive control unit 41 selects the first signal light L1 among the M signal lights L1 to be irradiated in the Kth distance detection period as an irradiation process target. Hereinafter, the signal light L1 selected as the target of the irradiation process is referred to as “Jth signal light (J is an integer not less than 1 and not more than M)”.

<Step ST104>
Next, the light source 30 emits the J-th signal light L <b> 1 in response to control by the drive control unit 41. In this example, the pulse width of the signal light L1 is set to the pulse width A.

As shown at time t2 in FIG. 5, the light source 30 has an irradiation time corresponding to the pulse width A from the time when irradiation of the J-th signal light L1 (first signal light L1 at time t2) is started. Then, the irradiation with the J-th signal light L1 ends.

<Step ST105>
Next, in response to the control by the drive control unit 41, the drive processing unit 22 receives the Jth signal light L1 from the light source 30 and starts the Kth distance detection period (that is, the Kth distance). When the delay time TD corresponding to (section) elapses, P × Q solid-state imaging devices 100 are driven so that the light receiving unit 200 is in an exposure state for a predetermined exposure time. In this example, the exposure time corresponding to the J-th signal light L1 is set to a time corresponding to the pulse width (pulse width A in this example) of the J-th signal light L1. Also, the delay time TD corresponding to the Kth distance detection period is set as the following equation.

As shown at time t3 in FIG. 5, the pixel drive circuit 25 of the drive processing unit 22 is delayed from the time when the J-th signal light L1 (first signal light L1 at time t3) is emitted from the light source 30. When the time TD elapses, the signal level of the exposure signal EXP is changed from the low level to the high level. As a result, the light receiving unit 200 is in an exposure state, charges corresponding to the light received by the light receiving unit 200 are generated, and the input potential VPD changes according to the amount of the generated charges. In the example of FIG. 5, the first reflected light L2 corresponding to the first signal light L1 reaches the light receiving unit 200 at time t3. That is, the first signal light L1 irradiated at time t1 is reflected by the object (the object existing in the Kth distance section) and reaches the light receiving unit 200 as the first reflected light L2. Yes. Then, when the exposure time (time corresponding to the pulse width A) elapses from the time when the signal level of the exposure signal EXP is changed from the low level to the high level, the pixel driving circuit 25 changes the signal level of the exposure signal EXP from the high level to the low level. To level. Thereby, the light-receiving part 200 will be in a light-shielding state.

<Step ST106>
Next, in response to the control by the drive control unit 41, the drive processing unit 22 transfers the charge generated by the light receiving unit 200 to the charge storage unit 300 by the first charge transfer unit 400, and then the charge storage unit 300. The P × Q solid-state imaging devices 100 are driven so that the charge accumulated in the second charge transfer unit 700 is transferred to the charge storage capacitor 600.

As shown at time t4 in FIG. 5, the pixel drive circuit 25 of the drive processing unit 22 changes the signal level of the transfer control signal TRN from the low level to the high level. As a result, the transfer transistor 401 is turned on, charges are transferred from the light receiving unit 200 to the charge storage unit 300 via the transfer transistor 401 in the on state, and the intermediate potential VFD changes according to the amount of the transferred charges. To do. Then, when the transfer of charges from the light receiving unit 200 to the charge storage unit 300 is completed (for example, a predetermined transfer time elapses), the pixel driving circuit 25 changes the signal level of the transfer control signal TRN from the high level to the low level. To level. As a result, the transfer transistor 401 is turned off.

Next, as shown at time t5 in FIG. 5, the pixel drive circuit 25 of the drive processing unit 22 changes the signal level of the switching control signal SWT from the low level to the high level. As a result, the switching transistor 701 is turned on, and charge is transferred from the charge storage unit 300 to the charge storage capacitor 600 via the switching transistor 701 in the on state, and the storage potential VCNT is changed according to the amount of the transferred charge. Change. The amount of charge transferred from the charge storage unit 300 to the charge storage capacitor 600 is an amount corresponding to the capacitance ratio between the charge storage unit 300 and the charge storage capacitor 600. Then, when the transfer from the charge storage unit 300 to the charge storage capacitor 600 is completed (for example, a predetermined transfer time elapses), the pixel drive circuit 25 changes the signal level of the switching control signal SWT from the high level to the low level. To. As a result, the switching transistor 701 is turned off.

<Step ST107>
Next, the drive control unit 41 determines whether or not all of the M signal lights L1 to be irradiated in the Kth distance detection period have been selected as an irradiation process target (that is, M times of signal light L1 irradiation are performed). Whether or not it is completed). If all of the M signal lights L1 to be irradiated in the Kth distance detection period have not been selected as targets for irradiation processing, the process proceeds to step ST108, and if not, the process proceeds to step ST110.

<Step ST108>
When all of the M signal lights L1 to be irradiated in the Kth distance detection period are not selected as the target of the irradiation process, the drive control unit 41 performs M irradiation to be performed in the Kth distance detection period. The signal light next to the J-th signal light L1 (J + 1-th signal light L1) is selected as the next irradiation process target.

<Step ST109>
Next, in response to control by the drive control unit 41, the drive processing unit 22 drives the P × Q solid-state imaging elements 100 so that the input potential VPD and the intermediate potential VFD are reset. Then, the process proceeds to step ST104.

As shown at time t6 in FIG. 5, the pixel drive circuit 25 of the drive processing unit 22 changes the signal levels of the transfer control signal TRN and the first reset control signal RS1 from low level to high level. As a result, the transfer transistor 401 and the first reset transistor 801 are turned on, and the intermediate potential VFD is reset by the first reset voltage VRS1. In addition, since the transfer transistor 401 is in the on state, the input potential VPD is reset together with the reset of the intermediate potential VFD. Then, when the reset of the input potential VPD and the intermediate potential VFD is completed (for example, a predetermined reset time has elapsed), the pixel drive circuit 25 increases the signal levels of the transfer control signal TRN and the first reset control signal RS1. From level to low level. As a result, the transfer transistor 401 and the first reset transistor 801 are turned on.

Next, as shown at times t7 to t10 in FIG. 5, the same processing (steps ST104 to ST106) as at times t2 to t5 in FIG. 5 is performed. The storage potential VCNT changes according to the number (number of times) of the reflected light L2 received by the light receiving unit 200 in the exposed state. That is, as the number of reflected lights L2 received by the light receiving unit 200 in the exposure state increases, the amount of charge transferred to the charge storage capacitor 600 increases, and as a result, the storage potential VCNT decreases.

<Step ST110>
On the other hand, when all of the M signal lights L1 to be irradiated in the Kth distance detection period in step ST107 are selected as targets for irradiation processing (that is, irradiation of M times of signal light L1 is completed). ), In response to the control by the drive control unit 41, the drive processing unit 22 resets the intermediate potential VFD, and then the charge stored in the charge storage capacitor 600 is transferred to the charge storage unit 300 by the second charge transfer unit 700. P × Q solid-state imaging devices 100 are driven so as to be transferred to.

As shown at time t11 in FIG. 5, the pixel drive circuit 25 of the drive processing unit 22 changes the signal level of the first reset control signal RS1 from low level to high level. As a result, the first reset transistor 801 is turned on, and the intermediate potential VFD is reset by the first reset voltage VRS1. Then, when the reset of the intermediate potential VFD is completed (for example, a predetermined reset time elapses), the pixel drive circuit 25 changes the signal level of the first reset control signal RS1 from the high level to the low level. As a result, the first reset transistor 801 is turned off.

Next, as shown at time t12 in FIG. 5, the pixel drive circuit 25 of the drive processing unit 22 changes the signal level of the potential control signal EIV from the low level to the high level. Note that the high level of the potential control signal EIV is set to a potential higher than the intermediate potential VFD after reset. As a result, the storage potential VCNT becomes higher than the intermediate potential VFD.

Next, as shown at time t13 in FIG. 5, the pixel drive circuit 25 of the drive processing unit 22 changes the signal level of the switching control signal SWT from the low level to the high level. As a result, the switching transistor 701 is turned on, and charge is transferred from one end of the charge storage capacitor 600 to the charge storage unit 300 via the switching transistor 701 in the on state, and an intermediate potential is set according to the amount of the transferred charge. VFD changes. The amount of charge transferred from the charge storage capacitor 600 to the charge storage unit 300 is an amount corresponding to the capacitance ratio between the charge storage unit 300 and the charge storage capacitor 600. Then, when the transfer of charges from the charge storage capacitor 600 to the charge storage unit 300 is completed (for example, a predetermined transfer time elapses), the pixel drive circuit 25 receives the potential control signal EIV and the switching control signal SWT. Change the level from high to low.

<Step ST111>
Next, in response to the control by the drive control unit 41, the drive processing unit 22 outputs P × Q solids so that a signal corresponding to the charge accumulated in the charge accumulation unit 300 is output by the output unit 500. The image sensor 100 is driven every P solid-state image sensor rows. As a result, a signal corresponding to the charge stored in each charge storage unit 300 of the P × Q solid-state imaging devices 100 is controlled via the correlated double sampling circuit 27, the horizontal shift register 28, and the output circuit 29. Is supplied to the information output unit 42 of the unit 40. That is, the information output unit 42 is supplied with information (count image) composed of P × Q signal values each indicating a count value. The count value is a value corresponding to the amount of charge accumulated in the charge storage capacitor 600. In this example, the count value is a value corresponding to the number of reflected lights L2 received by the light receiving unit 200 in the exposure state. . In this example, the count value increases as the amount of charge stored in the charge storage capacitor 600 increases (the number of reflected light L2 received by the light receiving unit 200 in the exposure state increases).

As shown at time t14 in FIG. 5, the vertical shift register 26 of the drive processing unit 22 changes the signal level of the selection control signal SEL from the low level to the high level. As a result, the selection transistor 502 is turned on, and a signal corresponding to the charge accumulated in the charge accumulation unit 300 is output from the amplification transistor 501 to the vertical signal line 110 via the selection transistor 502 in the on state.

Next, as shown at time t15 in FIG. 5, the pixel drive circuit 25 of the drive processing unit 22 changes the signal level of the first reset control signal RS1 from low level to high level. As a result, the first reset transistor 801 is turned on, and the intermediate potential VFD is reset by the first reset voltage VRS1. As a result, the signal level of the signal output from the amplification transistor 501 to the vertical signal line 110 via the on-state selection transistor 502 becomes a signal level corresponding to the reset intermediate potential VFD.

Then, when the reset of the intermediate potential VFD is completed (for example, a predetermined reset time elapses), the pixel drive circuit 25 of the drive processing unit 22 changes the signal level of the first reset control signal RS1 from the high level to the low level. To. As a result, the first reset transistor 801 is turned off. Further, when the output of the signal from the output unit 500 to the vertical signal line 110 is completed (for example, when a predetermined output time elapses), the vertical shift register 26 changes the signal level of the selection control signal SEL from the high level to the low level. To level. As a result, the selection transistor 502 is turned off.

In the example of FIG. 5, the period from time t14 to time t15 is a signal period, and the period from time t15 to the time when the signal level of the selection control signal SEL changes from a high level to a low level is a reset period. The correlated double sampling circuit 27 samples the signal level in the signal period and the signal level in the reset period among the signals output from the output unit 500 to the vertical signal line 110. The signal processed by the correlated double sampling circuit 27 is supplied to the information output unit 42 of the control unit 40 via the horizontal shift register 28 and the output circuit 29.

<Step ST112>
Next, the drive control unit 41 determines whether or not all of the N distance sections have been selected as distance detection control targets (that is, whether or not N distance detection processes respectively corresponding to the N distance sections have been completed). )). If all of the N distance sections have not been selected as targets for distance detection control, the process proceeds to step ST113, and if all of the N distance sections have been selected as targets for distance detection control, processing is performed. Exit.

<Step ST113>
Next, the drive control unit 41 selects the next distance section (K + 1th distance section) after the Kth distance section among the N distance sections as the next distance detection control target. Next, the process proceeds to step ST102.

[Operation of information output unit: Output of distance information]
Next, the operation by the information output unit 42 will be described. When N distance detection processes corresponding to the N distance sections are completed, the information output unit 42 outputs N count images (P × Q each indicating a count value) corresponding to the N distance sections. (Information consisting of the signal value). And the information output part 42 produces | generates a distance image (three-dimensional information comprised by the PxQ distance value each showing the value according to the distance to a target object) based on these N count images. Generate and output the distance image.

For example, the information output unit 42 performs a comparison process on each of the N count images. In the comparison process for the K-th count image, the information output unit 42 sets the K-th count value for each of the P × Q signal values (count values) constituting the K-th count image. It is determined whether or not the threshold value is equal to or greater than a threshold value determined for the Kth distance section corresponding to the image. The threshold value determined for each of the N distance intervals is set to, for example, a signal value (count value) acquired when an object exists in the distance interval.

And the information output part 42 produces | generates a distance image based on the result of the comparison process with respect to each of N count images. For example, the information output unit 42 in the X-th row (X is an integer not less than 1 and not more than P) in the Y-th column among the P × Q signal values (count values) constituting the K-th count image. When the signal value (Y is an integer greater than or equal to 1 and less than or equal to Q) is greater than or equal to a threshold value determined for the Kth count image, the Xth of the P × Q distance values constituting the distance image In the row, the distance value in the Yth row is set to a value corresponding to the Kth distance section.

Note that the information output unit 42 may be configured to adjust a threshold value determined for each of the N distance intervals according to the background light.

[Operation of drive control unit: imaging control]
Next, imaging control by the drive control unit 41 will be described with reference to FIG. In the imaging control, the drive processing unit 22 performs an imaging operation in response to control by the drive control unit 41.

<Step ST201>
First, in response to control by the drive control unit 41, the drive processing unit 22 drives the P × Q solid-state imaging elements 100 so that the input potential VPD and the intermediate potential VFD are reset.

<Step ST202>
Next, in response to the control by the drive control unit 41, the drive processing unit 22 drives the P × Q solid-state imaging devices 100 so that the light receiving unit 200 is in an exposure state for a predetermined exposure time. . As a result, the light receiving unit 200 is in an exposure state, charges corresponding to the light received by the light receiving unit 200 are generated, and the input potential VPD changes according to the amount of the generated charges.

<Step ST203>
Next, the drive processing unit 22 responds to the control by the drive control unit 41 so that the charge generated by the light receiving unit 200 is transferred to the charge storage unit 300 by the first charge transfer unit 400. The solid-state imaging device 100 is driven. Thus, charges are transferred from the light receiving unit 200 to the charge storage unit 300 via the first charge transfer unit 400, and the intermediate potential VFD changes according to the amount of transferred charges.

<Step ST204>
Next, in response to the control by the drive control unit 41, the drive processing unit 22 outputs P × Q solids so that a signal corresponding to the charge accumulated in the charge accumulation unit 300 is output by the output unit 500. The image sensor 100 is driven every P solid-state image sensor rows. As a result, a signal corresponding to the charge stored in each charge storage unit 300 of the P × Q solid-state imaging devices 100 is controlled via the correlated double sampling circuit 27, the horizontal shift register 28, and the output circuit 29. Supplied to the unit 40. That is, the control unit 40 is supplied with information (luminance image) composed of P × Q signal values each indicating a value corresponding to the luminance.

[Effects of the embodiment]
As described above, the charge stored in the charge storage capacitor 600 is transferred to the charge storage unit 300 by the second charge transfer unit 700, and a signal corresponding to the charge stored in the charge storage unit 300 is output by the output unit 500. Thus, a signal corresponding to the charge accumulated in the charge storage capacitor 600 can be output. This eliminates the need to separately provide a configuration (a configuration different from the output unit 500) for outputting a signal corresponding to the charge stored in the charge storage capacitor 600, thereby reducing the circuit scale of the solid-state imaging device 100. be able to.

Further, it is not necessary to separately provide a configuration (a configuration different from the output unit 500) for outputting a signal corresponding to the charge stored in the charge storage capacitor 600, and accordingly, the light receiving area of the light receiving unit 200 is expanded accordingly. can do. Thereby, since the sensitivity of the light receiving unit 200 can be improved, the distance that can be measured by the solid-state imaging system 10 can be increased.

In the transistor forming process for forming a transistor (for example, the switching transistor 701 or the like) included in the solid-state imaging device 100 by configuring the rectifying element 702 of the second charge transfer unit 700 with a diode-connected rectifying transistor 710. A rectifying element 702 can be formed. Thereby, formation of the rectifying element 702 can be facilitated.

(Modification of solid-state image sensor)
As shown in FIG. 6, in the solid-state imaging device 100, the light receiving unit 200 may include a plurality of photoelectric conversion elements 201. The plurality of photoelectric conversion elements 201 are configured to generate charges corresponding to the light received by each of the plurality of photoelectric conversion elements 201. And the light-receiving part 200 may be comprised so that the some photoelectric conversion element 201 may be exposed in an exposure state. The first charge transfer unit 400 may include a plurality of transfer transistors 401. The plurality of transfer transistors 401 are connected between the plurality of photoelectric conversion elements 201 and the floating diffusion unit 301 of the charge storage unit 300, respectively. The gates of the plurality of transfer transistors 401 are connected to a transfer control node 402 to which a transfer control signal TRN is applied.

As described above, by providing a plurality of photoelectric conversion elements 201 in the light receiving unit 200, the light receiving area of the light receiving unit 200 can be expanded. Thereby, the sensitivity of the light receiving unit 200 can be improved.

(Other embodiments)
In the above description, the case where there is a reset period after the signal period in the signal output from the output unit 500 to the vertical signal line 110 in step ST111 is described as an example, but the signal is output from the output unit 500 to the vertical signal line 110. There may be a signal period after the reset period in the signal. Specifically, in step ST <b> 111, the drive processing unit 22 resets the intermediate potential VFD (the potential of the charge storage unit 300) and outputs a signal (reset level signal) corresponding to the charge stored in the charge storage unit 300. After being output to the vertical signal line 110 by the output unit 500, the signal level of the signal output from the output unit 500 by transferring the charge stored in the charge storage capacitor 600 by the second charge transfer unit 700 to the charge storage unit 300. The solid-state imaging device 100 may be driven so that changes.

In the above description, the N distance sections may be set to the same section length, or may be set to different section lengths.

Further, the above embodiments may be combined as appropriate. The above embodiments are essentially preferable examples, and are not intended to limit the scope of the present invention, its application, or its use.

As described above, the technology disclosed herein is useful for a solid-state imaging device, a solid-state imaging device, a solid-state imaging system, and a driving method of the solid-state imaging device.

DESCRIPTION OF SYMBOLS 10 Solid-state imaging system 20 Solid-state imaging device 21 Pixel area 22 Drive processing part 25 Pixel drive circuit 26 Vertical shift register 27 Correlated double sampling circuit 28 Horizontal shift register 29 Output circuit 30 Light source 40 Control part 41 Drive control part 42 Information output part 100 Solid-state imaging device 200 Light receiving unit 201 Photoelectric conversion element 300 Charge storage unit 301 Floating diffusion unit 400 First charge transfer unit 401 Transfer transistor 500 Output unit 501 Amplification transistor 502 Selection transistor 600 Charge storage capacitor 700 Second charge transfer unit 701 Switching transistor 702 Rectifier element 710 Rectifier transistor 800 First reset unit 801 First reset transistor 900 2 reset unit 901 second reset transistor

Claims

A light receiving portion configured to be switchable between an exposure state and a light shielding state, and generating a charge according to light received in the exposure state;
A charge storage section for storing the charge;
A first charge transfer unit that transfers the charge from the light receiving unit to the charge storage unit;
An output unit that outputs a signal corresponding to the charge accumulated in the charge accumulation unit;
A charge storage capacitor for storing the charge;
A solid-state imaging device, comprising: a second charge transfer unit that transfers the charge bidirectionally between the charge storage unit and one end of the charge storage capacitor.
In claim 1,
The second charge transfer unit includes:
A switching transistor and a rectifying element connected in series between the charge storage unit and one end of the charge storage capacitor;
A potential control node connected to the other end of the charge storage capacitor;
The rectifying element is configured such that a direction from one end of the charge storage capacitor toward the charge storage unit is a forward direction.
A potential control signal is applied to the potential control node so that the potential of one end of the charge storage capacitor is higher than the potential of the charge storage unit when the charge is transferred from the charge storage capacitor to the charge storage unit. A solid-state imaging device.
In claim 2,
The solid-state imaging device, wherein the rectifying element is constituted by a diode-connected rectifying transistor.
In any one of claims 1 to 3,
The light receiving unit includes a photoelectric conversion element that generates an electric charge according to received light, and is configured to expose the photoelectric conversion element in the exposure state.
The first charge transfer unit includes a transfer transistor connected between the photoelectric conversion element and the charge storage unit.
In any one of claims 1 to 3,
The light receiving unit includes a plurality of photoelectric conversion elements that generate charges corresponding to light received by each, and is configured to expose the plurality of photoelectric conversion elements in the exposure state;
The first charge transfer unit includes a plurality of transfer transistors respectively connected between the plurality of photoelectric conversion elements and the charge storage unit.
A solid-state imaging device according to any one of claims 1 to 5,
A drive processing unit for driving the solid-state imaging device,
The drive processing unit transfers the charge generated by the light receiving unit to the charge storage unit by the first charge transfer unit and stores the charge stored in the charge storage unit by the second charge transfer unit. After the transfer operation transferred to the capacitor is performed a predetermined number of times, the charge stored in the charge storage capacitor is transferred to the charge storage unit by the second charge transfer unit and stored in the charge storage unit A solid-state imaging device that performs a photon counting operation for driving the solid-state imaging device so that a signal corresponding to the generated charge is output by the output unit.
In claim 6,
In the drive processing unit, the charge generated by the light receiving unit is transferred to the charge storage unit by the first charge transfer unit, and a signal corresponding to the charge stored in the charge storage unit is output by the output unit. As described above, a solid-state imaging device that performs an imaging operation for driving the solid-state imaging device.
A solid-state imaging device according to claim 6 or 7,
A light source that emits signal light;
A solid-state imaging system comprising: a control unit that controls the operation of the solid-state imaging device and the operation of the light source.
In claim 8,
The controller is
The drive processing unit performs the photon counting operation in each of a plurality of distance detection periods respectively corresponding to a plurality of distance sections. In the transfer operation of the photon counting operation in each of the plurality of distance detection periods, from the light source, The light receiving unit is exposed after a delay time corresponding to the distance detection period has elapsed from the time when the signal light is irradiated, and the charge generated by the light receiving unit is transferred to the charge storage unit by the first charge transfer unit. Distance detection control for controlling the operation of the drive processing unit and the operation of the light source so that the charge stored in the charge storage unit is transferred to the charge storage capacitor by the second charge transfer unit. A drive control unit to perform,
An information output unit that outputs information on the distance to the object based on a signal output by the output unit in the photon counting operation of the drive processing unit in each of the plurality of distance detection periods. Solid-state imaging system featuring
The light receiving unit is configured to be switchable between an exposure state and a light shielding state, and generates a charge according to light received in the exposure state, a charge storage unit that stores the charge, and the light receiving unit to the charge storage unit. A first charge transfer unit configured to transfer the charge; an output unit configured to output a signal corresponding to the charge stored in the charge storage unit; a charge storage capacitor configured to store the charge; the charge storage unit; and the charge storage unit. A solid-state imaging device driving method comprising: a second charge transfer unit that transfers the charge bidirectionally to and from one end of a capacitor,
The transfer generated by the light receiving unit is transferred to the charge storage unit by the first charge transfer unit, and the charge stored in the charge storage unit is transferred to the charge storage capacitor by the second charge transfer unit. A first step of driving the solid-state imaging device so that the operation is performed a predetermined number of times;
After the first step, the charge stored in the charge storage capacitor is transferred to the charge storage unit by the second charge transfer unit, and a signal corresponding to the charge stored in the charge storage unit is output by the output unit. And a second step of driving the solid-state imaging device so as to output the solid-state imaging device.