WO2019184971A1 - Procédé de communication de rapport d'état de tampon de liaison latérale et dispositif terminal - Google Patents

Procédé de communication de rapport d'état de tampon de liaison latérale et dispositif terminal Download PDF

Info

Publication number
WO2019184971A1
WO2019184971A1 PCT/CN2019/080078 CN2019080078W WO2019184971A1 WO 2019184971 A1 WO2019184971 A1 WO 2019184971A1 CN 2019080078 W CN2019080078 W CN 2019080078W WO 2019184971 A1 WO2019184971 A1 WO 2019184971A1
Authority
WO
WIPO (PCT)
Prior art keywords
logical channel
channel group
destination address
domain
bitmap
Prior art date
Application number
PCT/CN2019/080078
Other languages
English (en)
Chinese (zh)
Inventor
周建萍
杨晓东
郑倩
马景智
Original Assignee
维沃移动通信有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 维沃移动通信有限公司 filed Critical 维沃移动通信有限公司
Publication of WO2019184971A1 publication Critical patent/WO2019184971A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
    • H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H04W28/0278—Traffic management, e.g. flow control or congestion control using buffer status reports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H04W28/06—Optimizing the usage of the radio link, e.g. header compression, information sizing, discarding information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H04W28/06—Optimizing the usage of the radio link, e.g. header compression, information sizing, discarding information
    • H04W28/065—Optimizing the usage of the radio link, e.g. header compression, information sizing, discarding information using assembly or disassembly of packets

Definitions

  • the present disclosure relates to the field of communications, and in particular, to a reporting method and a terminal device for reporting a secondary link cache status.
  • Sidelink BSR Sidelink Buffer Status Report
  • the format of the LTE Sidelink BSR is in the order of the Logical Channel Group Identity (LCG ID). When there are not enough resources to report the resource requirements, one or more destination indexes may be reported for the same LCG ID. Pass the amount of data. For the fast-growing Vehicle to Everything (V2X) services and use cases, the service priority division needs to be more detailed.
  • the number of logical channel groups (LCGs) of the LTE Sidelink BSR is only 4 sets, which cannot meet the current requirements.
  • LTE Sidelink's Buffer Size field occupies 6 bits, and the total index is 64 types, and there are few types, while the enhanced vehicle networking (enhanced V2X, eV2X) service type requires a larger amount of data, if LTE 64 is still used.
  • the index, eV2X indicates that the Buffer Size span of each level is large, and the base station cannot accurately confirm the demand of the Sidelink UE for resources, which will cause a certain amount of resource waste in the resource scheduling process.
  • the current agreement has not yet defined the Sidelink BSR format of New Radio (NR).
  • An object of the embodiments of the present disclosure is to provide a method for transmitting a secondary link buffer status report, and a terminal device, which can more flexibly indicate a Buffer of valid data that can be used for transmission of all logical channels in a logical channel group based on a short-range service destination address. Size.
  • an embodiment of the present disclosure provides a method for transmitting a secondary link buffer status report, where the method includes: sending a secondary link cache status report, where the secondary link cache status report includes: a destination address field, a logical channel Group domain and cache size domain, or include logical channel group domain and cache size domain,
  • the destination address field and at least one of the logical channel group domains are represented based on a bitmap.
  • an embodiment of the present disclosure provides a terminal device, where the terminal device includes: a sending module, and a secondary link buffer status report, where the secondary link cache status report includes: a destination address domain, a logical channel group domain, and Cache size domain, or include logical channel group domain and cache size domain,
  • the destination address field and at least one of the logical channel group domains are represented based on a bitmap.
  • an embodiment of the present disclosure provides a terminal device, including a processor, a memory, and a program stored on the memory and executable on the processor, where the program is used by the processor. The steps of the method as described in the first aspect are implemented when executed.
  • an embodiment of the present disclosure provides a computer readable storage medium storing a program on a computer readable storage medium, the program being executed by a processor to implement the steps of the method as described in the first aspect.
  • bitmap-based per destination index and/or the Perlink BSR format of the per LCG ID it is possible to more flexibly indicate that all logical channels in a logical channel group based on the short-range service destination address are available for transmission. Buffer Size of valid data.
  • FIG. 1 is a flow chart of a method for transmitting a Sidelink BSR according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a MAC CE of a Sidelink BSR according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a MAC CE of a Sidelink BSR of another embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a subheader of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a subheader of a MAC CE of a Sidelink BSR according to another embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a terminal device according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a terminal device according to another embodiment of the present disclosure.
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • LTE-A Long Term Evolution advanced
  • New Air Interface New Radio, NR
  • a user equipment which may also be called a mobile terminal, a mobile user equipment, or the like, may be connected to a radio access network (for example, a radio access network (RAN)) and one or The plurality of core networks communicate, and the user equipment can be a terminal device, such as a mobile phone (or "cellular" phone) and a computer with a terminal device, for example, can be portable, pocket-sized, handheld, built-in or on-board Mobile devices that exchange language and/or data with a wireless access network.
  • a radio access network for example, a radio access network (RAN)
  • RAN radio access network
  • the base station may be a Base Transceiver Station (BTS) in GSM or CDMA, or may be a base station (NodeB) in WCDMA, or may be an evolved base station (eNB or e-NodeB) in LTE and
  • BTS Base Transceiver Station
  • NodeB base station
  • eNB evolved base station
  • gNB 5G base station
  • the LCG (logical channel group) of the Sidelink BSR is divided into four groups.
  • the field of one logical channel group index occupies 2 bits, and the LCG (logical channel group) corresponding to the reported (cache area) is specified.
  • the Destination Index is configurable in length, with a maximum of 16 groups, and a destination address index field occupies 4 bits, corresponding to the destination group destination L2ID of the communication.
  • the Buffer Size is arranged in the order in which the logical channel group contains the sub-link logical channel priorities decreasing.
  • the Buffer Size field is 6 bits long and specifies all Media Access Control (MAC) MAC protocol data units (Protocol Data Units) within the Transmission Time Interval (TTI) of the Sendlink UE.
  • MAC Media Access Control
  • TTI Transmission Time Interval
  • the LCG corresponding to the short-range service destination address includes the remaining Radio Link Control (RLC) layer and the Packet Data Convergence Protocol (PDCP) layer of all logical channels. The sum of valid data available for transmission.
  • RLC Radio Link Control
  • PDCP Packet Data Convergence Protocol
  • FIG. 1 is a flowchart of a method for transmitting a Sidelink Buffer Status Report (Sidelink BSR) according to an embodiment of the present disclosure.
  • the method of Figure 1 is performed by a secondary link terminal device.
  • the method can include:
  • the sub-link cache status report includes a destination address field, a logical channel group domain, and a cache size domain, or includes a logical channel group domain and a cache size domain, where the destination address domain and the logical channel group domain are at least One is based on a bitmap.
  • the role of the Sidelink BSR is that the Sidelink UE transmits the amount of data to be transmitted of all logical channels in a logical channel group based on the ProSe Destination to the base station.
  • the destination address field is a field field carrying the destination address information of the secondary link terminal device, or the destination address field is the destination address information of the secondary link terminal device.
  • the logical channel group domain is a field field carrying logical channel group information of the secondary link terminal device, or the logical channel group domain is logical channel group information of the secondary link terminal device;
  • the buffer size field is a field field of the to-be-sent data amount information of the logical channel group carrying the sub-link terminal device, or the buffer size field is the to-be-sent data amount of the logical channel group of the sub-link terminal device.
  • bitmap-based Per destination index and/or the Perlink BSR format of the per LCG ID it is possible to more flexibly indicate that all logical channels in a logical channel group based on the ProSe Destination are to be sent. Buffer Size of valid data that can be used for transmission.
  • the Sidelink BSR includes: a destination address domain, a logical channel group domain, and a cache size domain, where
  • the destination address field is an index of at least one destination address reported by the secondary link terminal device, and the at least one destination address is a data transferable destination address of the secondary link terminal device;
  • the logical channel group domain is at least one logical channel group bitmap, the at least one logical channel group bitmap is in one-to-one correspondence with the at least one destination address, and one logical channel group bitmap is used to indicate whether all logical channel groups in the corresponding destination address are available. Pass data
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in all logical channel group bitmaps of the logical channel group domain, wherein if the at least one to wait
  • the first amount of data to be sent in the data volume corresponds to the first bit in the first logical channel group bitmap corresponding to the index of the first destination address, and the first amount of data to be sent indicates that the secondary link terminal device is a sum of the amount of data to be transmitted of all the logical channels of the first logical channel group of the first destination address, where the first logical channel group is a logical channel group corresponding to the first bit.
  • the destination address index is used to indicate that the secondary link terminal device has a data transferable destination address.
  • each destination address index corresponds to a logical channel group bitmap in the logical channel group domain, and the logical channel group bitmap indicates whether all logical channel groups corresponding to the destination address have transmittable data. For example, when a logical channel group corresponding to a destination address is eight, the logical channel group bitmap indicates whether the logical channel group LCG0-LCG7 corresponding to the destination address has transmittable data.
  • the Sidelink BSR includes: a destination address domain, a logical channel group domain, and a cache size domain, and the destination address domain is continuous, and the logical channel group domain is continuous, and the cache size domain is continuous. It is continuous.
  • one destination address index occupies 4 bits
  • one destination address corresponds to 8 logical channel groups (LCG0-LCG7)
  • a corresponding amount of pending data on one logical channel group is in a buffer size domain. It occupies 8 bits.
  • the destination address field is continuous
  • the logical channel group domain is continuous
  • the buffer size domain is continuous
  • the number of destination address indexes is an odd number, which may be set to 2*N-1.
  • the length of the logical channel group field is 2*N-1 bytes
  • the length of the buffer size field is m.
  • the first 4 bits of the first byte of the destination address field are reserved bits.
  • the reserved bits may also be located in the last 4 bits of the last byte of the destination address field.
  • the first 4 bits or the last 4 bits of the reserved bit are located in any other byte of the destination address field.
  • FIG. 3 is a schematic diagram of a MAC CE of a Sidelink BSR according to an embodiment of the present disclosure.
  • the destination address field is continuous
  • the logical channel group domain is continuous
  • the buffer size domain is continuous
  • the number of destination address indexes is even, which may be set to 2*N.
  • the destination address is The length of the domain is N bytes
  • the length of the logical channel group domain is 2*N bytes
  • the length of the buffer size domain is m bytes, where m is the bit in all logical channel group bitmaps of the logical channel group domain.
  • the total number of bits is set to 1.
  • the destination address field is continuous, the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, and the cache size domain is discontinuous, the cache The size field includes at least one buffer size sub-domain, and the logical channel group sub-domain is a logical channel group bitmap corresponding to a destination address, and the buffer size sub-domain is one of the to-be-sent data amounts, and the at least one logical channel group
  • Each of the logical channel group subfields in the domain is followed by x buffer size subfields, where x is the total number of bits set to 1 in a logical channel group bitmap of the following logical channel group subfield.
  • the value of x can be zero.
  • the value of x may be 0-8.
  • one destination address index occupies 4 bits
  • one destination address corresponds to 8 logical channel groups (LCG0-LCG7)
  • the corresponding amount of pending data on one logical channel group occupies 8 bits in the buffer size domain.
  • the number of destination address indexes is an odd number, it may be set to 2*N-1.
  • the length of the destination address field is N bytes, and the length of the logical channel group domain is 2*.
  • N-1 bytes the length of the buffer size field is m bytes, where m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain.
  • the first 4 bits of the first byte of the destination address field are reserved bits, or the last 4 bits of the last byte of the destination address field are reserved bits. Of course, it is not excluded that the first 4 bits or the last 4 bits of the reserved bit are located in any other byte of the destination address field.
  • the number of destination address indexes is an even number, it may be set to 2*N.
  • the length of the destination address field is N bytes, and the length of the logical channel group domain is 2*N.
  • the length of the buffer size field is m bytes, where m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain.
  • the destination address field is discontinuous, the destination address field includes at least one destination address sub-domain, the logical channel group domain is discontinuous, and the logical channel group domain includes at least one logical channel group
  • the cache size field is not continuous.
  • the cache size field includes at least one cache size sub-domain.
  • the destination address sub-domain is a destination address index
  • the logical channel group sub-domain is a logical channel group bitmap corresponding to a destination address.
  • a buffer size sub-domain is the amount of data to be sent, each logical channel group sub-domain in the at least one logical channel group sub-domain is followed by x cache size sub-fields, and x is a logical channel group to be followed.
  • the value of x can be zero.
  • the value of x may be 0-8.
  • one destination address index occupies 4 bits
  • one destination address corresponds to 8 logical channel groups (LCG0-LCG7)
  • the corresponding amount of pending data on one logical channel group occupies 8 bits in the buffer size domain.
  • the length of the destination address field is N bytes
  • the length of the logical channel group field is N bytes
  • the length of the buffer size field is m bytes
  • m is the logic.
  • the number of bits in all logical channel group bitmaps of the channel group domain is set to 1, wherein each byte in the destination address field includes 4 reserved bits.
  • the length of the destination address index of the Sidelink BSR may not be 4 bits, and the logical channel group corresponding to one destination address may not be eight, and the number of bits occupied by one data to be sent may not be eight.
  • Those skilled in the art can derive the length of each domain of the Sidelink BSR in the foregoing scenario based on actual conditions.
  • the MAC CE of the Sidelink BSR includes information of the entire Sidelink BSR; if the secondary link If the uplink resource of the terminal device is insufficient to upload the size of the entire Sidelink BSR, the MAC CE of the Sidelink BSR includes the information of the Sidelink BSR after the truncation process.
  • the Sidelink BSR includes: a destination address domain, a logical channel group domain, and a cache size domain, where
  • the destination address field is a destination address bitmap reported by the terminal device carrying the secondary link, and the destination address bitmap is used to indicate whether the destination address of the secondary link terminal device has data to be transmitted;
  • the logical channel group domain is at least one logical channel group bitmap, and the at least one logical channel group bitmap is in one-to-one correspondence with the destination address of the destination address bitmap bit set to 1, and one logical channel group bitmap is used to indicate the corresponding destination address. Whether all logical channel groups have data to transmit;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in a logical channel group bitmap of the logical channel group domain, wherein if the at least one to wait
  • the first amount of data to be sent in the data volume corresponds to the second bit of the first logical channel group bitmap corresponding to the first bit of the destination address bitmap, and the first amount of data to be sent represents the secondary link terminal device.
  • the first destination address is a destination address indicated by a first bit of the destination address bitmap
  • the first logical channel group is The logical channel group indicated by the second bit of the first logical channel group bitmap.
  • each bit set to 1 in the destination address bitmap corresponds to one logical channel group bitmap
  • the logical channel group bitmap indicates all logical channel groups corresponding to the destination address corresponding to the bit set to 1. Is there any data available? For example, when the first destination address is set to 1 in the destination address bitmap, and the first destination address corresponds to the first logical channel group bitmap, and a destination address corresponds to 8 logical channel groups, Then, the first logical channel group bitmap indicates whether the logical channel group LCG0-LCG7 corresponding to the first destination address has transmittable data.
  • the logical channel group domain is contiguous and the cache size domain is contiguous.
  • the total number of destination addresses is 16 and one destination address corresponds to 8 logical channel groups (LCG0-LCG7), and the corresponding amount of data to be sent on one logical channel group occupies 8 bits in the buffer size domain. Based on this, the length of each domain of the Sidelink BSR in several different scenarios will be described below.
  • FIG. 4 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • the destination address domain is continuous
  • the logical channel group domain is continuous
  • the buffer size domain is continuous, and it is assumed that 2 bytes can be used to indicate whether the destination address of the secondary link terminal device has data transferable, and data is transmittable therein.
  • the number of destination addresses is N
  • the total number of bits in the logical channel group bitmap of the logical channel group domain is set to 1.
  • the length of the destination address field is 2 bytes
  • the length of the logical channel group field is N bytes
  • N is the total number of bits in the destination address bitmap of the destination address field being set to 1
  • the buffer size domain The length is m bytes, and m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain.
  • the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the cache size domain is discontinuous, and the cache size domain includes at least one cache size
  • a logical channel group sub-domain of the logical channel group is a logical channel group bitmap corresponding to a destination address, and the buffer size sub-domain is a data volume to be sent, and each of the logical channel groups in the at least one logical channel group sub-domain
  • the subfield is followed by x buffer size subfields, where x is the total number of bits set to 1 in a logical channel group bitmap of the following logical channel group subfield.
  • the value of x can be zero.
  • the value of x may be 0-8.
  • the length of the destination address field is 2 bytes
  • the length of the logical channel group field is N bytes
  • N is the total number of bits in the destination address bitmap of the destination address field being set to 1
  • the length of the buffer size field For m bytes, m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain.
  • the total number of destination addresses may not be 16 4
  • the logical channel group corresponding to one destination address may not be 8
  • the number of bits occupied by one pending data volume may not be 8.
  • the MAC CE of the Sidelink BSR includes information of the entire Sidelink BSR; if the secondary link If the uplink resource of the terminal device is insufficient to upload the size of the entire Sidelink BSR, the MAC CE of the Sidelink BSR includes the information of the Sidelink BSR after the truncation process.
  • the Sidelink BSR includes a logical channel group domain and a cache size domain, where
  • the logical channel group domain is a logical channel group bitmap corresponding to the size of v2x-DestinationInfoList destination addresses of the secondary link terminal device, and one logical channel group bitmap is used to indicate whether all logical channel groups of the corresponding destination address have data transferable. ;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in all logical channel group bitmaps of the logical channel group domain, wherein if the at least one to wait
  • the first amount of data to be sent in the amount of data to be transmitted corresponds to the first bit of the first logical channel group bitmap
  • the first logical channel group bitmap corresponds to the first destination address
  • the first amount of data to be sent represents the pair.
  • v2x-DestinationInfoList may be specified by a protocol or configured by a Radio Resource Control (RRC).
  • RRC Radio Resource Control
  • the protocol may specify that the destination addresses of the indices 1, 3, 5, 7 are used among the 16 destination addresses; for example, the first six destination addresses of the 16 destination addresses may be configured by RRC signaling, and so on.
  • the logical channel group domain occupies the same number of bytes as the parameter size of v2x-DestinationInfoList; the buffer size field has a length of m bytes, and m is all logic of the logical channel group domain.
  • the logical channel group domain is contiguous and the cache size domain is contiguous.
  • FIG. 5 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • the logical channel group domain is continuous and the buffer size domain is continuous.
  • the logical channel group domain includes size of v2x-DestinationInfoList consecutive logical channel group bitmaps, each logical channel group bitmap corresponds to one destination address, and each logical channel group bitmap occupies 1 byte.
  • the length of the buffer size field is m bytes, and m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain.
  • the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the cache size domain is discontinuous, and the cache size domain includes at least one cache size
  • a logical channel group sub-domain of the logical channel group is a logical channel group bitmap corresponding to a destination address, and the buffer size sub-domain is a data volume to be sent, and each of the logical channel groups in the at least one logical channel group sub-domain
  • the subfield is followed by x buffer size subfields, where x is the total number of bits set to 1 in a logical channel group bitmap of the following logical channel group subfield.
  • the value of x can be zero.
  • the value of x may be 0-8.
  • the logical channel group corresponding to one destination address may not be eight, and the number of bits occupied by one data to be sent may not be eight.
  • Those skilled in the art can derive the length of each domain of the Sidelink BSR in the foregoing scenario based on actual conditions.
  • the MAC CE of the Sidelink BSR includes information of the entire Sidelink BSR; if the secondary link If the uplink resource of the terminal device is insufficient to upload the size of the entire Sidelink BSR, the MAC CE of the Sidelink BSR includes the information of the Sidelink BSR after the truncation process.
  • the Sidelink BSR includes: a logical channel group domain, a destination address domain, and a cache size domain, where
  • the logical channel group domain is a logical channel group bitmap, and the one logical channel group bitmap is used to indicate whether the secondary link terminal device has data to be transmitted in all logical channel groups;
  • the destination address field is at least one destination address bitmap, and the at least one destination address bitmap is in one-to-one correspondence with a logical channel group in which the bit in the logical channel group bitmap is set to 1, and a destination address bitmap is used to indicate the secondary link terminal. Whether all destination addresses of the device have data to be transmitted on the logical channel group corresponding to the destination address bitmap;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in the at least one destination address bitmap, wherein if the at least one amount of data to be sent is in the
  • the first amount of data to be sent corresponds to the second bit of the first destination address bitmap corresponding to the first bit of the logical channel group address bitmap, and the first amount of data to be sent indicates that the secondary link terminal device is in the first purpose.
  • the total number of logical channel groups is eight, the total number of destination addresses is 16, and the corresponding amount of data to be sent on one logical channel group occupies 8 bits in the buffer size domain.
  • the logical channel group domain length is 1 byte; a destination address bitmap occupies 2 bytes, the destination address field length is 2*N bytes, and N is set to 1 in the logical channel group bitmap.
  • the total number of bits; the size of the buffer size field is m bytes, and m is the total number of bits set to 1 in all destination address bitmaps in the destination address field.
  • the destination address fields are contiguous and the cache size fields are contiguous.
  • FIG. 6 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • the destination address field is contiguous and the cache size field is contiguous.
  • the logical channel group includes one logical channel group bitmap, that is, a bitmap of eight logical channel groups of LCG0-LCG7, and the number of logical channel groups in which data can be transmitted is N, and the destination address domain
  • the total number of bits in the middle destination address bitmap is set to 1 and is m.
  • the logical channel group field has a length of 1 byte
  • a destination address bitmap occupies 2 bytes
  • the destination address field has a length of 2*N bytes
  • the cache size field has a length of m bytes, m. The total number of bits set to 1 in all destination address bitmaps in the destination address field.
  • the destination address domain is discontinuous, the destination address domain includes at least one destination address subdomain, the cache size domain is discontinuous, and the cache size domain includes at least one cache size subdomain,
  • the destination address sub-domain is a destination address bitmap corresponding to a logical channel group, and the buffer size sub-domain is a pending data volume, and each of the destination address sub-domains in the at least one destination address sub-domain is followed by the x caches.
  • the value of x can be zero.
  • the value of x can be 0-16.
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink resource of the secondary link terminal device is insufficient.
  • the Sidelink BSR's MAC CE contains the information of the Sidelink BSR after truncation.
  • the Sidelink BSR includes: a logical channel group domain, a destination address domain, and a cache size domain, where
  • the logical channel group domain is an index of at least one logically transferable logical channel group of the secondary link terminal device
  • the destination address field is at least one destination address bitmap, the at least one destination address bitmap is in one-to-one correspondence with the at least one logically channelizable logical channel group, and a destination address bitmap is used to indicate all destination addresses of the secondary link terminal device. Whether data is transmittable on the logical channel group corresponding to the destination address bitmap;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in the at least one destination address bitmap, wherein if the at least one amount of data to be sent is in the
  • the first amount of data to be sent corresponds to the second bit of the first destination address bitmap corresponding to the first logical channel group, and the first amount of data to be sent indicates the first of the first destination address of the secondary link terminal device.
  • the logical channel group index occupies 3 bits, and the total number of destination addresses is 16.
  • the corresponding amount of data to be sent on one logical channel group occupies 8 bits in the buffer size domain. Based on this, the length of each domain of the Sidelink BSR in several different scenarios will be described below.
  • the logical channel group domain is contiguous
  • the destination address domain is contiguous
  • the cache size domain is contiguous
  • FIG. 7 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • the logical channel group domain is contiguous
  • the destination address domain is contiguous
  • the cache size domain is contiguous.
  • the logical channel group domain includes an index of at least one logical channel group.
  • the length of the destination address field is 2*N bytes
  • the length of the buffer size field is m bytes
  • m is the total number of bits set to 1 in all destination address bitmaps in the destination address domain.
  • the length of the logical channel group domain is related to the number of bits occupied by one logical channel group index and the number N of indexes of the at least one logical channel group, specifically Ceiling (N*L/8), where L represents a logic The number of occupied bits of the channel group index, Ceiling (y) represents the smallest integer not less than y.
  • the logical channel group domain is continuous, the destination address domain is discontinuous, the destination address domain includes at least one destination address subdomain, and the cache size domain is discontinuous, and the cache size domain is And including at least one cache size sub-domain, where the destination address sub-domain is a destination address bitmap corresponding to a logical channel group, and one of the cache size sub-domains is a quantity of the to-be-sent data, and the at least one destination address sub-domain each of the destinations
  • the address subfield is followed by x cache size subfields, where x is the total number of bits in the destination address bitmap of the followed destination address subfield set to one.
  • the value of x can be zero.
  • the value of x can be 0-16.
  • the length of the destination address field is 2*N bytes
  • the length of the buffer size field is m bytes
  • m is the total number of bits set to 1 in all destination address bitmaps in the destination address domain.
  • the length of the logical channel group domain is related to the number of bits occupied by one logical channel group index and the number N of indexes of the at least one logical channel group, specifically Ceiling (N*L/8), where L represents a logic The number of occupied bits of the channel group index, Ceiling (y) represents the smallest integer not less than y.
  • the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the destination address domain is discontinuous, and the destination address domain includes at least one destination address sub
  • the domain of the cache size is not continuous.
  • the cache size field includes at least one cache size sub-domain.
  • the logical channel group sub-domain is a logical channel group index, and the destination address sub-domain is a destination address bitmap corresponding to a logical channel group.
  • One of the cache size sub-domains is a quantity of the to-be-sent data, and each destination address sub-domain in the at least one destination address sub-domain is followed by x cache size sub-domains, and x is a destination of the following destination address sub-domain. The total number of bits in the address bitmap that are set to 1.
  • the value of x can be zero.
  • the value of x can be 0-16.
  • the length of the logical channel group domain is N bytes, and one destination address bitmap occupies 2 bytes.
  • the length of the address field is 2*N bytes, the length of the buffer size field is m bytes, and m is the total number of bits in the destination address bitmap of the destination address field being set to 1.
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink of the secondary link terminal device If the resource is insufficient to upload the size of the entire Sidelink BSR, the MAC CE of the Sidelink BSR includes the information of the Sidelink BSR that has been truncated.
  • the sub-header of the MAC CE of the Sidelink BSR may include an R domain, an F domain, an LCID domain, and an L domain, where
  • the length of the L field is 8 bits, and when the F field is 1, the length of the L field is 16 bits.
  • the LCID field is used to indicate that the MAC CE type following the subheader is a Sidelink BSR
  • the L field is used to indicate the byte length of the MAC CE of the Sidelink BSR.
  • the F-domain is set to "0", and the sub-header of the MAC CE of the Sidelink BSR is as shown in FIG. 8.
  • the sub-head of the MAC CE of the Sidelink BSR is as shown in FIG. 8.
  • the Buffer Size of valid data available for transmission can be more flexibly indicated by the bitmap-based per-point index and/or Per LCG ID's Sidelink BSR format for fast-growing V2X services.
  • the V2X service priority can be more clearly divided, the Buffer Size is expanded from 6 bits to 8 bits, and the corresponding index total class is increased from 64 to 256. This provides the network with a more granular and accurate Buffer Size information of the Sidelink UE.
  • the terminal device provided by the embodiment of the present disclosure can implement the processes implemented by the terminal device in the various embodiments of FIG. 1 and support the Sidelink BSR format provided in FIG. 2-7, and the MAC CE of the Sidelink BSR provided in FIG. 8 and FIG.
  • the subheader format, to avoid repetition, will not be described here.
  • the secondary link terminal device can report the cached data size on the corresponding destination address and the logical channel group to the base station.
  • the network device such as a base station, can receive the Sidelink BSR accordingly, and receive the cache data size sent by the secondary link terminal device on the destination address and logical channel group indicated by the Sidelink BSR.
  • FIG. 10 is a block diagram of a terminal device of another embodiment of the present disclosure.
  • the terminal device 1000 shown in FIG. 10 includes at least one processor 1001, a memory 1002, at least one network interface 1004, and a user interface 1003.
  • the various components in terminal device 1000 are coupled together by bus system 1005.
  • bus system 1005 is used to implement connection communication between these components.
  • the bus system 1005 includes a power bus, a control bus, and a status signal bus in addition to the data bus.
  • various buses are labeled as bus system 1005 in FIG.
  • the user interface 1003 may include a display, a keyboard, a pointing device (eg, a mouse, a trackball), a touch panel, or a touch screen.
  • a pointing device eg, a mouse, a trackball
  • a touch panel e.g., a touch screen.
  • the memory 1002 in the embodiments of the present disclosure may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (Erasable PROM, EPROM), or an electric Erase programmable read only memory (EEPROM) or flash memory.
  • the volatile memory can be a Random Access Memory (RAM) that acts as an external cache.
  • RAM Random Access Memory
  • many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (Synchronous DRAM).
  • SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • DDRSDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • ESDRAM Enhanced Synchronous Dynamic Random Access Memory
  • SDRAM Synchronous Connection Dynamic Random Access Memory
  • DRRAM direct memory bus random access memory
  • the memory 1002 stores elements, executable modules or data structures, or a subset thereof, or their extended set: an operating system 10021 and an application 10022.
  • the operating system 10021 includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks.
  • the application 10022 includes various applications, such as a media player (Media Player), a browser, and the like, for implementing various application services.
  • a program implementing the method of the embodiments of the present disclosure may be included in the application 10022.
  • the terminal device 1000 further includes: a computer program stored in the memory 1002 and executable on the processor 1001.
  • a computer program stored in the memory 1002 and executable on the processor 1001.
  • the sub-link cache status report includes a destination address field, a logical channel group domain, and a cache size domain, or includes a logical channel group domain and a cache size domain, where the destination address domain and the logical channel group domain are at least One is based on a bitmap.
  • the method disclosed in the above embodiments of the present disclosure may be applied to the processor 1001 or implemented by the processor 1001.
  • the processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 1001 or an instruction in a form of software.
  • the processor 1001 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like. Programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in connection with the embodiments of the present disclosure may be directly implemented by the hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software modules can be located in a conventional computer readable storage medium of the art, such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the computer readable storage medium is located in the memory 1002, and the processor 1001 reads the information in the memory 1002 and performs the steps of the above method in combination with its hardware.
  • the computer readable storage medium stores a computer program, and when the computer program is executed by the processor 1001, the steps of the method embodiment shown in FIG. 1 are implemented.
  • the embodiments described in the embodiments of the present disclosure may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof.
  • the processing unit can be implemented in one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processing (DSP), Digital Signal Processing Equipment (DSP Device, DSPD), programmable Programmable Logic Device (PLD), Field-Programmable Gate Array (FPGA), general purpose processor, controller, microcontroller, microprocessor, other for performing the functions described in this disclosure In an electronic unit or a combination thereof.
  • ASICs Application Specific Integrated Circuits
  • DSP Digital Signal Processing
  • DSP Device Digital Signal Processing Equipment
  • PLD programmable Programmable Logic Device
  • FPGA Field-Programmable Gate Array
  • the techniques described in the embodiments of the present disclosure may be implemented by modules (eg, procedures, functions, etc.) that perform the functions described in the embodiments of the present disclosure.
  • the software code can be stored in memory and executed by the processor.
  • the memory can be implemented in the processor or external to the processor.
  • the terminal device 1000 can implement various processes implemented by the terminal device in the foregoing embodiment. To avoid repetition, details are not described herein again.
  • the embodiment of the present disclosure further provides a computer readable storage medium, where the computer program is stored on a computer program, and when the computer program is executed by the processor, the processes of the foregoing method embodiment of FIG. 1 are implemented, and the same technology can be achieved. The effect, to avoid repetition, will not be repeated here.
  • the computer readable storage medium such as a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
  • the terminal device 1100 may include a transmitting module 1110. among them,
  • the sending module 1110 sends a secondary link buffer status report.
  • the sub-link cache status report includes a destination address field, a logical channel group domain, and a cache size domain, or includes a logical channel group domain and a cache size domain, where the destination address domain and the logical channel group domain are at least One is based on a bitmap.
  • the Sidelink BSR includes: a destination address domain, a logical channel group domain, and a cache size domain, where
  • the destination address field is an index of at least one destination address reported by the secondary link terminal device, and the at least one destination address is a data transferable destination address of the secondary link terminal device;
  • the logical channel group domain is at least one logical channel group bitmap, the at least one logical channel group bitmap is in one-to-one correspondence with the at least one destination address, and one logical channel group bitmap is used to indicate whether all logical channel groups in the corresponding destination address are available. Pass data
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in all logical channel group bitmaps of the logical channel group domain, wherein if the at least one to wait
  • the first amount of data to be sent in the data volume corresponds to the first bit in the first logical channel group bitmap corresponding to the index of the first destination address, and the first amount of data to be sent indicates that the secondary link terminal device is a sum of the amount of data to be transmitted of all the logical channels of the first logical channel group of the first destination address, where the first logical channel group is a logical channel group corresponding to the first bit.
  • the destination address field is continuous
  • the logical channel group domain is continuous
  • the cache size domain is continuous
  • the destination address field is contiguous, the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the cache size domain is discontinuous, and the cache size domain includes at least one cache size subdomain, and one
  • the logical channel group sub-domain is a logical channel group bitmap corresponding to a destination address
  • the buffer size sub-domain is the amount of the to-be-issued data
  • the at least one logical channel group sub-domain is followed by each of the logical channel group sub-domains. Following x cache size subfields, where x is the total number of bits set to 1 in a logical channel group bitmap of the following logical channel group subfield; or
  • the destination address field is discontinuous, the destination address field includes at least one destination address sub-domain, the logical channel group domain is discontinuous, and the logical channel group domain includes at least one logical channel group sub-domain, the cache size domain is discontinuous, the cache The size field includes at least one cache size sub-domain, the destination address sub-domain is a destination address index, and one of the logical channel group sub-domains is a logical channel group bitmap corresponding to a destination address, and one of the cache size sub-domains is one Sending data volume, each logical channel group subfield in the at least one logical channel group subfield is followed by x cache size subfields, and x is a logical channel group subfield of the following logical channel group subfield is set to The total number of bits of 1;
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink resource of the secondary link terminal device is insufficient to upload the entire
  • the size of the Sidelink BSR includes the information of the Sidelink BSR that has been truncated in the MAC CE of the Sidelink BSR.
  • the length of the index of the destination address is 4 bits, and the number of logical channels corresponding to the destination address is 8, and the amount of data to be sent occupies 8 bits in the buffer size domain, where
  • the length of the destination address field is N bytes
  • the length of the logical channel group field is 2*N- 1 byte
  • the length of the buffer size field is m bytes
  • m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain, wherein the first word of the destination address field
  • the first 4 bits of the section are reserved bits, or the last 4 bits of the last byte of the destination address field are reserved bits; or
  • the length of the destination address field is N bytes
  • the length of the logical channel group field is 2*N bytes.
  • the length of the buffer size field is m bytes, and m is the total number of bits in all logical channel group bitmaps of the logical channel group domain being set to 1; or
  • the cache The size of the size field is m bytes, where m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain, wherein each byte in the destination address field includes 4 reserved bits.
  • the Sidelink BSR includes: a destination address domain, a logical channel group domain, and a cache size domain, where
  • the destination address field is a destination address bitmap reported by the terminal device carrying the secondary link, and the destination address bitmap is used to indicate whether the destination address of the secondary link terminal device has data to be transmitted;
  • the logical channel group domain is at least one logical channel group bitmap, and the at least one logical channel group bitmap is in one-to-one correspondence with the destination address of the destination address bitmap bit set to 1, and one logical channel group bitmap is used to indicate the corresponding destination address. Whether all logical channel groups have data to transmit;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in a logical channel group bitmap of the logical channel group domain, wherein if the at least one to wait
  • the first amount of data to be sent in the data volume corresponds to the second bit of the first logical channel group bitmap corresponding to the first bit of the destination address bitmap, and the first amount of data to be sent represents the secondary link terminal device.
  • the first destination address is a destination address indicated by a first bit of the destination address bitmap
  • the first logical channel group is The logical channel group indicated by the second bit of the first logical channel group bitmap.
  • the logical channel group domain is continuous, and the buffer size domain is continuous;
  • the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the cache size domain is discontinuous, the cache size domain includes at least one cache size subdomain, and one logical channel group subdomain is one a logical channel group bitmap corresponding to the destination address, where the buffer size sub-domain is the amount of data to be sent, and each of the logical channel group sub-domains in the at least one logical channel group sub-domain is followed by the x cache size sub-domains.
  • x is the total number of bits set to 1 in a logical channel group bitmap of the followed logical channel group subfield;
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink resource of the secondary link terminal device is insufficient to upload the entire
  • the size of the Sidelink BSR includes the information of the Sidelink BSR that has been truncated in the MAC CE of the Sidelink BSR.
  • the length of the index of the destination address is 4 bits, and the number of logical channels corresponding to the destination address is 8, and the amount of data to be sent occupies 8 bits in the buffer size domain, where
  • the destination address field has a length of 2 bytes.
  • the length of the logical channel group field is N bytes, and N is the total number of bits in the destination address bitmap set to 1.
  • the length of the buffer size field is m bytes, and m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain.
  • the Sidelink BSR includes a logical channel group domain and a cache size domain.
  • the logical channel group domain is a logical channel group bitmap corresponding to the size of v2x-DestinationInfoList destination addresses of the secondary link terminal device, and one logical channel group bitmap is used to indicate whether all logical channel groups of the corresponding destination address have data transferable. ;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in all logical channel group bitmaps of the logical channel group domain, wherein if the at least one to wait
  • the first amount of data to be sent in the amount of data to be transmitted corresponds to the first bit of the first logical channel group bitmap
  • the first logical channel group bitmap corresponds to the first destination address
  • the first amount of data to be sent represents the pair.
  • the logical channel group domain is continuous, and the buffer size domain is continuous;
  • the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the cache size domain is discontinuous, the cache size domain includes at least one cache size subdomain, and one logical channel group subdomain is one a logical channel group bitmap corresponding to the destination address, where the buffer size sub-domain is the amount of data to be sent, and each of the logical channel group sub-domains in the at least one logical channel group sub-domain is followed by the x cache size sub-domains.
  • x is the total number of bits set to 1 in a logical channel group bitmap of the followed logical channel group subfield;
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink resource of the secondary link terminal device is insufficient to upload the entire
  • the size of the Sidelink BSR includes the information of the Sidelink BSR that has been truncated in the MAC CE of the Sidelink BSR.
  • a logical channel group corresponding to the destination address is eight, and one amount of the to-be-sent data occupies 8 bits in the buffer size domain, where
  • the number of bytes occupied by the logical channel group domain is the same as the size of v2x-DestinationInfoList parameter;
  • the length of the buffer size field is m bytes, and m is the total number of logical channel groups in which the bits in all logical channel group bitmaps of the logical channel group domain are set to 1.
  • the parameter size of v2x-DestinationInfoList is configured by the radio resource control RRC, or is specified by the protocol.
  • the Sidelink BSR includes: a logical channel group domain, a destination address domain, and a cache size domain, where
  • the logical channel group domain is a logical channel group bitmap, and the one logical channel group bitmap is used to indicate whether the secondary link terminal device has data to be transmitted in all logical channel groups;
  • the destination address field is at least one destination address bitmap, and the at least one destination address bitmap is in one-to-one correspondence with a logical channel group in which the bit in the logical channel group bitmap is set to 1, and a destination address bitmap is used to indicate the secondary link terminal. Whether all destination addresses of the device have data to be transmitted on the logical channel group corresponding to the destination address bitmap;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in the at least one destination address bitmap, wherein if the at least one amount of data to be sent is in the
  • the first amount of data to be sent corresponds to the second bit of the first destination address bitmap corresponding to the first bit of the logical channel group address bitmap, and the first amount of data to be sent indicates that the secondary link terminal device is in the first purpose.
  • the destination address field is contiguous and the cache size domain is contiguous;
  • the destination address field is discontinuous, the destination address field includes at least one destination address sub-domain, and the cache size domain is discontinuous, and the cache size domain includes at least one cache size sub-domain, where the destination address sub-domain corresponds to a logical channel group.
  • a destination address bitmap wherein the buffer size sub-domain is an amount of the to-be-sent data, and each of the destination address sub-domains in the at least one destination address sub-domain is followed by x cache size sub-domains, where x is the followed destination address.
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink resource of the secondary link terminal device is insufficient to upload the entire
  • the size of the Sidelink BSR includes the information of the Sidelink BSR that has been truncated in the MAC CE of the Sidelink BSR.
  • the total number of logical channel groups is eight, and the total number of destination addresses is 16, and one amount of data to be sent occupies 8 bits in the buffer size domain, where
  • the logical channel group domain has a length of 1 byte
  • the one destination address bitmap occupies 2 bytes
  • the destination address field is 2*N bytes in length, and N is the total number of bits set to 1 in the logical channel group bitmap;
  • the buffer size field has a length of m bytes, and m is the total number of bits set to 1 in all destination address bitmaps of the destination address field.
  • the Sidelink BSR includes: a logical channel group domain, a destination address domain, and a cache size domain, where
  • the logical channel group domain is an index of at least one logically transferable logical channel group of the secondary link terminal device
  • the destination address field is at least one destination address bitmap, the at least one destination address bitmap is in one-to-one correspondence with the at least one logically channelizable logical channel group, and a destination address bitmap is used to indicate all destination addresses of the secondary link terminal device. Whether data is transmittable on the logical channel group corresponding to the destination address bitmap;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in the at least one destination address bitmap, wherein if the at least one amount of data to be sent is in the
  • the first amount of data to be sent corresponds to the second bit of the first destination address bitmap corresponding to the first logical channel group, and the first amount of data to be sent indicates the first of the first destination address of the secondary link terminal device.
  • the logical channel group domain is continuous, the destination address domain is continuous, and the cache size domain is continuous;
  • the logical channel group domain is contiguous, the destination address domain is discontinuous, the destination address domain includes at least one destination address subdomain, the cache size domain is discontinuous, and the cache size domain includes at least one cache size subdomain, the destination address
  • the sub-domain is a destination address bitmap corresponding to a logical channel group, and the buffer size sub-domain is a data volume to be sent, and each of the destination address sub-domains in the at least one destination address sub-domain is followed by x cache sizes. Domain, where x is the total number of bits in the destination address bitmap of the followed destination address subfield set to 1; or
  • the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the destination address domain is discontinuous, the destination address domain includes at least one destination address subdomain, and the cache size domain is discontinuous, the cache The size field includes at least one cache size subdomain.
  • the logical channel group sub-domain is a logical channel group index
  • the destination address sub-domain is a destination address bitmap corresponding to a logical channel group
  • the buffer size sub-domain is a pending data volume
  • the at least one destination address sub-domain Each destination address subfield is followed by x cache size subfields, where x is the total number of bits in the destination address bitmap of the followed destination address subfield set to 1;
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink resource of the secondary link terminal device is insufficient to upload the entire
  • the size of the Sidelink BSR includes the information of the Sidelink BSR that has been truncated in the MAC CE of the Sidelink BSR.
  • the total number of destination addresses is 16, and the amount of data to be sent occupies 8 bits in the buffer size domain, where
  • the length of the logical channel group domain is related to the number N of indexes of the at least one logical channel group, and the length of the destination address domain is 2*N bytes, and the one destination address bitmap is occupied. 2 bytes, the length of the buffer size field is m bytes, and m is the total number of bits set to 1 in all destination address bitmaps of the destination address field; or
  • the logical channel group domain When the logical channel group domain is discontinuous, and the number of indexes of the at least one logical channel group is N, the logical channel group domain has a length of N bytes, and the destination address domain has a length of 2*N.
  • the length of the buffer size field is m bytes, and m is the total number of bits set to 1 in all destination address bitmaps of the destination address field.
  • the sub-header of the MAC CE of the Sidelink BSR includes an R domain, an F domain, an LCID domain, and an L domain, where
  • the length of the L field is 8 bits, and when the F field is 1, the length of the L field is 16 bits.
  • the LCID field is used to indicate that the MAC CE type following the subheader is a Sidelink BSR
  • the L field is used to indicate the byte length of the MAC CE of the Sidelink BSR.
  • the terminal device 1100 can implement various processes implemented by the terminal device in the foregoing embodiment. To avoid repetition, details are not described herein again.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

La présente invention concerne un procédé de transmission d'un rapport d'état de tampon de liaison latérale et un dispositif terminal de liaison latérale. Le procédé consiste à envoyer un rapport d'état de tampon de liaison latérale. Le rapport d'état de tampon de liaison latérale comprend un champ d'adresse de destination, un champ de groupe de canaux logiques et un champ de taille de tampon, ou comprend un champ de groupe de canaux logiques et un champ de taille de tampon, le champ d'adresse de destination et/ou le champ de groupe de canaux logiques étant représentés sous la forme d'une table de bits.
PCT/CN2019/080078 2018-03-29 2019-03-28 Procédé de communication de rapport d'état de tampon de liaison latérale et dispositif terminal WO2019184971A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810273355.6 2018-03-29
CN201810273355.6A CN110324858B (zh) 2018-03-29 2018-03-29 副链路缓存状态报告的上报方法和终端设备

Publications (1)

Publication Number Publication Date
WO2019184971A1 true WO2019184971A1 (fr) 2019-10-03

Family

ID=68058569

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/080078 WO2019184971A1 (fr) 2018-03-29 2019-03-28 Procédé de communication de rapport d'état de tampon de liaison latérale et dispositif terminal

Country Status (2)

Country Link
CN (1) CN110324858B (fr)
WO (1) WO2019184971A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011159102A2 (fr) * 2010-06-18 2011-12-22 엘지전자 주식회사 Procédé dans lequel un terminal transmet un rapport d'état de tampon dans un système de communication sans fil, et appareil pour le procédé
CN106454687A (zh) * 2015-07-21 2017-02-22 电信科学技术研究院 一种分配资源的方法和设备
WO2017049728A1 (fr) * 2015-09-25 2017-03-30 宇龙计算机通信科技(深圳)有限公司 Procédé et dispositif de génération de rapport d'état de mémoire tampon de liaison latérale
CN107347215A (zh) * 2016-05-06 2017-11-14 普天信息技术有限公司 在v2x网络中资源的分配方法及终端
CN107360591A (zh) * 2017-06-15 2017-11-17 电信科学技术研究院 一种上报缓存状态报告的方法和设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011159102A2 (fr) * 2010-06-18 2011-12-22 엘지전자 주식회사 Procédé dans lequel un terminal transmet un rapport d'état de tampon dans un système de communication sans fil, et appareil pour le procédé
CN106454687A (zh) * 2015-07-21 2017-02-22 电信科学技术研究院 一种分配资源的方法和设备
WO2017049728A1 (fr) * 2015-09-25 2017-03-30 宇龙计算机通信科技(深圳)有限公司 Procédé et dispositif de génération de rapport d'état de mémoire tampon de liaison latérale
CN107347215A (zh) * 2016-05-06 2017-11-14 普天信息技术有限公司 在v2x网络中资源的分配方法及终端
CN107360591A (zh) * 2017-06-15 2017-11-17 电信科学技术研究院 一种上报缓存状态报告的方法和设备

Also Published As

Publication number Publication date
CN110324858A (zh) 2019-10-11
CN110324858B (zh) 2020-08-25

Similar Documents

Publication Publication Date Title
JP7018513B6 (ja) Ｈａｒｑ－ａｃｋフィードバック時間の特定方法と指示方法、端末機器及びネットワーク機器
EP3737173B1 (fr) Procédé pour envoyer des données et dispositif de communication
US10231267B2 (en) Access control method and apparatus based on service level
ES2372357T3 (es) Procedimiento y aparato para gestionar el reporte de información de programación.
CN107113200B (zh) 缓存状态报告的处理方法、装置以及通信系统
WO2019192471A1 (fr) Procédé de transmission, dispositif terminal et dispositif de réseau destiné à un rapport de csi
CN111263457B (zh) 一种副链路缓存状态报告发送、接收方法和设备
US20210258980A1 (en) Sidelink logical channel and resource configurations
US20190230682A1 (en) Data transmission method, apparatus, and system
WO2018059360A1 (fr) Procédé et dispositif de traitement de rapport d'état de tampon
US8964616B2 (en) System and method for scheduling cell broadcast message
CN114391235A (zh) 执行用于非优先的上行链路授权的混合自动重复请求进程的方法及相关设备
CN110139388B (zh) 缓冲区状态的上报、数据调度方法、终端及网络侧设备
CN110661603A (zh) Pucch的传输方法、终端设备和网络设备
CN111107583B (zh) sidelink重传请求BSR发送方法和终端设备
WO2020088520A1 (fr) Procédé de transmission de liaison montante et dispositif terminal
WO2019184971A1 (fr) Procédé de communication de rapport d'état de tampon de liaison latérale et dispositif terminal
WO2022028386A1 (fr) Procédé et appareil de détermination de type de qualité, procédé et appareil d'envoi de valeur de qualité, dispositif, et support de stockage
JP2021518707A (ja) 無線通信方法、ユーザ装置及びネットワーク装置
WO2017113993A1 (fr) Procédé et dispositif destinés au réglage de la planification de ressource
WO2021004374A1 (fr) Procédé de transmission de données, procédé de réception de données et dispositif
WO2021160158A1 (fr) Procédé de transmission et dispositif de réseau
WO2018090317A1 (fr) Procédé de planification de ressources, et dispositif et système pertinents
WO2021134596A1 (fr) Procédé et appareil de communication de liaison latérale
CN102843772B (zh) 调度信息上报的方法及装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19774608

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19774608

Country of ref document: EP

Kind code of ref document: A1