WO2019176810A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2019176810A1
WO2019176810A1 PCT/JP2019/009485 JP2019009485W WO2019176810A1 WO 2019176810 A1 WO2019176810 A1 WO 2019176810A1 JP 2019009485 W JP2019009485 W JP 2019009485W WO 2019176810 A1 WO2019176810 A1 WO 2019176810A1
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Prior art keywords
region
cathode
axis direction
cathode region
width
Prior art date
Application number
PCT/JP2019/009485
Other languages
French (fr)
Japanese (ja)
Inventor
内藤　達也
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to DE112019000096.9T priority Critical patent/DE112019000096T5/en
Priority to CN201980004216.6A priority patent/CN111066149B/en
Priority to JP2020506487A priority patent/JP6954449B2/en
Priority to CN202410080118.3A priority patent/CN117936538A/en
Publication of WO2019176810A1 publication Critical patent/WO2019176810A1/en
Priority to US16/799,719 priority patent/US11476249B2/en
Priority to US17/961,546 priority patent/US20230029909A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
    • H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0761—Vertical bipolar transistor in combination with diodes only
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
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    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
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    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material

Definitions

  • the present invention relates to a semiconductor device.
  • Patent Document 1 International Publication WO2016 / 129041
  • a semiconductor device in a first aspect of the present invention, includes a semiconductor substrate, a transistor portion provided on the semiconductor substrate, and a diode portion provided on the semiconductor substrate and arranged with the transistor portion along a predetermined arrangement direction.
  • the diode portion is in contact with a first conductivity type drift region provided on the semiconductor substrate, a second conductivity type base region provided above the drift region, and above the drift region, and a lower surface of the semiconductor substrate.
  • a plurality of second conductivity type floating regions arranged at least partially overlapping the first cathode region.
  • the first cathode region may protrude in the arrangement direction from the floating region in a top view of the semiconductor substrate.
  • the first cathode region and the second cathode region may be alternately arranged in the extending direction orthogonal to the arrangement direction in a top view of the semiconductor substrate.
  • a plurality of floating regions may be provided in the extending direction so as to overlap both the first cathode region and the second cathode region in a top view of the semiconductor substrate.
  • the floating region may protrude in the extending direction from the first cathode region in a top view of the semiconductor substrate.
  • the first cathode region may protrude in the extending direction perpendicular to the arrangement direction than the floating region.
  • the first cathode region and the second cathode region may be alternately arranged in the arrangement direction in a top view of the semiconductor substrate.
  • a plurality of floating regions may be provided in the arrangement direction so as to overlap both the first cathode region and the second cathode region in a top view of the semiconductor substrate.
  • the floating region may protrude in the arrangement direction from the first cathode region in a top view of the semiconductor substrate.
  • a semiconductor device in a second aspect of the present invention, includes a semiconductor substrate, a first conductivity type drift region provided on the semiconductor substrate, and a second conductivity type base region provided in contact with the upper surface of the semiconductor substrate and above the drift region.
  • the semiconductor device is in contact with the lower surface of the semiconductor substrate and is provided below the drift region, the first conductivity type first cathode region, is in contact with the lower surface of the semiconductor substrate and is provided below the drift region, and the first cathode
  • a second-conductivity-type second cathode region provided between the regions and a lower surface of the semiconductor substrate, provided below the drift region, and provided so as to sandwich the first and second cathode regions.
  • a third cathode region of the second conductivity type in a semiconductor substrate, a first conductivity type drift region provided on the semiconductor substrate, and a second conductivity type base region provided in contact with the upper surface of the semiconductor substrate and above the drift region.
  • the semiconductor device is in contact with the lower surface of the semiconductor substrate and is
  • the width of the third cathode region along the arrangement direction of the first cathode region and the second cathode region is larger than the width of the second cathode region along the arrangement direction.
  • the width of the second cathode region along the direction in which the third cathode region sandwiches the first cathode region and the second cathode region is larger than the width of the second cathode region along the arrangement direction.
  • the semiconductor device may include a plurality of second cathode regions and a plurality of third cathode regions. The plurality of second cathode regions and the plurality of third cathode regions may be in contact with each other in a top view of the semiconductor substrate.
  • a semiconductor device in a third aspect of the present invention, includes a semiconductor substrate and one or more diode portions provided on the semiconductor substrate.
  • the diode portion includes a first conductivity type drift region provided on the semiconductor substrate and a second conductivity type base region provided in contact with the upper surface of the semiconductor substrate and above the drift region.
  • the semiconductor device is in contact with the lower surface of the semiconductor substrate and is provided below the drift region and separated from each other, the first cathode region of the first conductivity type and the second cathode region having a conductivity type different from that of the first cathode region.
  • a plurality of second conductivity type floating regions which are provided separately from each other for each first cathode region and are arranged at least partially overlapping the first cathode region.
  • FIG. 3 is an enlarged view of a region C1 in FIG. 2b. It is a figure which shows an example of the aa 'cross section in FIG. 2b. It is a figure which shows an example of the bb 'cross section in FIG. 2b. It is another enlarged view of the area
  • FIG. 3b is an enlarged view of region B2 in FIG. 3a.
  • FIG. 3b is an enlarged view of a region C2 in FIG.
  • FIG. 3b It is a figure which shows an example of the cc 'cross section in FIG. 3b. It is a figure which shows an example of the dd 'cross section in FIG. 3b. It is another enlarged view of the area
  • FIG. 5b is a diagram showing an example of a gg ′ cross section in FIG. 5b. It is a figure which shows an example of the hh 'cross section in FIG. 5b. It is another enlarged view of the area
  • FIG. 6b is an enlarged view of region B5 in FIG. 6a.
  • FIG. 6b is an enlarged view of region C5 in FIG. 6b. It is a figure which shows an example of the ii 'cross section in FIG. 6b. It is a figure which shows an example of the j 'cross section in FIG. 6b. It is another enlarged view of the area
  • FIG. 7b is an enlarged view of a region C6 in FIG. 7b.
  • FIG. 8 is a diagram showing an example of a kk ′ cross section in FIG. 7b. It is a figure which shows an example of the mm 'cross section in FIG. 7b. It is another enlarged view of the area
  • FIG. 9b is an enlarged view of region C8 in FIG. 9b.
  • FIG. 9B is a diagram showing an example of a qq ′ cross section in FIG. 9B.
  • FIG. 9B is a diagram showing an example of an rr ′ cross section in FIG. 9B.
  • FIG. 10b is an enlarged view of region B9 in FIG. 10a.
  • FIG. 10b is a diagram showing an example of an ss ′ cross section in FIG. 10b.
  • FIG. 10B is a diagram showing an example of a tt ′ cross section in FIG. 10B. It is another enlarged view of the area
  • FIG. 12 is an enlarged view of a region C10 in FIG. 11b. It is a figure which shows an example of the uu 'cross section in FIG. 11b.
  • FIG. 12 is a diagram showing an example of a vv ′ cross section in FIG. 11b. It is a figure which shows another example of the upper surface of the semiconductor device 200 which concerns on this embodiment.
  • FIG. 12B is a diagram showing an example of a cross section aa-aa ′ in FIG. 12b.
  • FIG. 12B is a diagram showing an example of a bb-bb ′ cross section in FIG. 12b.
  • FIG. 14a It is a figure which shows another example of the upper surface of the semiconductor device 200 which concerns on this embodiment. It is the enlarged view of the area
  • FIG. 16a It is a figure which shows an example of the upper surface of the semiconductor device 200 which concerns on this embodiment. It is an enlarged view of the area
  • FIG. 17a It is a figure which shows another example of the upper surface of the semiconductor device 200 which concerns on this embodiment. It is the enlarged view of the area
  • one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as “upper” and the other side is referred to as “lower”.
  • the upper surface is referred to as the upper surface and the other surface is referred to as the lower surface.
  • the directions of “up” and “down” are not limited to the direction of gravity or the direction of attachment to a substrate or the like when the semiconductor device is mounted.
  • a plane parallel to the upper surface of the semiconductor substrate is defined as an XY plane, and a depth direction of the semiconductor substrate is defined as a Z axis.
  • the first conductivity type is an N type and the second conductivity type is a P type.
  • the first conductivity type may be a P type and the second conductivity type may be an N type.
  • the conductivity types of the substrates, layers, regions, etc. in the respective embodiments have opposite polarities.
  • the doping concentration refers to the concentration of impurities that have become donors or acceptors.
  • the concentration difference between the donor and the acceptor may be referred to as a doping concentration.
  • the peak value may be used as the doping concentration in the doping region.
  • the doping concentration in the doped region is substantially uniform, the average doping concentration in the doping region may be used as the doping concentration.
  • FIG. 1 a is a diagram showing an example of the upper surface of the semiconductor device 100 according to the present embodiment.
  • the semiconductor device 100 of this example is a semiconductor chip including a transistor unit 70 and a diode unit 80.
  • the transistor unit 70 includes a transistor such as an IGBT.
  • the diode unit 80 includes a diode such as an FWD (Free Wheel Diode) provided adjacent to the transistor unit 70 on the upper surface of the semiconductor substrate 10.
  • FWD Free Wheel Diode
  • the semiconductor substrate 10 is provided with an active portion 72.
  • the active portion 72 is a region where a main current flows between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in an on state. That is, the current flows in the depth direction in the semiconductor substrate 10 from the upper surface to the lower surface or from the lower surface to the upper surface of the semiconductor substrate 10.
  • the transistor unit 70 and the diode unit 80 are referred to as an element unit or an element region, respectively.
  • the region where the element portion is provided may be the active portion 72.
  • the active portion 72 includes a region sandwiched between the element portions and provided with the gate metal layer 50.
  • the active portion 72 may be a region where the emitter electrode is provided in a top view of the semiconductor substrate 10 and a region sandwiched between the emitter electrodes.
  • an emitter electrode is provided above the transistor unit 70 and the diode unit 80.
  • a region between the active portion 72 and the outer peripheral edge 76 of the semiconductor substrate 10 is defined as an outer peripheral region 74.
  • the outer peripheral region 74 is provided so as to surround the active portion 72 when the semiconductor substrate 10 is viewed from above.
  • one or more metal pads for connecting the semiconductor device 100 and an external device with a wire or the like may be arranged.
  • the semiconductor device 100 may have an edge termination structure portion surrounding the active portion 72 in the outer peripheral region 74.
  • the edge termination structure part alleviates electric field concentration on the upper surface side of the semiconductor substrate 10.
  • the edge termination structure portion may have, for example, a guard ring, a field plate, a RESURF, and a combination of these.
  • the active unit 72 may be provided with a plurality of transistor units 70 and diode units 80.
  • the transistor unit 70 and the diode unit 80 may be alternately and periodically arranged in the XY plane.
  • FIG. 1a shows an example in which three transistor portions 70 are provided in the X axis direction and seven in the Y axis direction, and three diode portions 80 are provided in the X axis direction and six in the Y axis direction.
  • a gate metal layer 50 may be provided between the transistor portions 70 facing each other in the X-axis direction.
  • Each diode portion 80 is provided with a first conductivity type cathode region 81 on the lower surface of the semiconductor substrate 10.
  • the cathode region 81 may be provided in a range not in contact with the outer peripheral region 74 as shown in FIG.
  • the gate metal layer 50 may be provided so as to surround the active portion 72 when the semiconductor substrate 10 is viewed from above. Gate metal layer 50 is electrically connected to gate pad 55 provided in outer peripheral region 74. The gate metal layer 50 may be provided along the outer peripheral edge 76 of the semiconductor substrate 10. The gate pad 55 may be disposed between the outer peripheral end 76 of the semiconductor substrate 10 and the active portion 72 in the X-axis direction. A gate metal layer 50 may be provided extending in the Y-axis direction between the gate pad 55 and the outer peripheral end 76.
  • the temperature sensing unit 90 is provided above the active unit 72.
  • the temperature sensing part 90 may be provided in the center of the active part 72 when the semiconductor substrate 10 is viewed from above.
  • the temperature sensing unit 90 detects the temperature of the active unit 72.
  • the temperature sensing unit 90 may be a pn junction type temperature sensing diode formed of single crystal or polycrystalline silicon.
  • the temperature sense wiring 92 is provided above the active portion 72 when the semiconductor substrate 10 is viewed from above.
  • the temperature sense wiring 92 is connected to the temperature sense unit 90.
  • the temperature sensing wiring 92 extends in a predetermined direction (X-axis direction in this example) up to the outer peripheral region 74 and is connected to a temperature measurement pad 94 provided in the outer peripheral region 74.
  • the current flowing from the temperature measurement pad 94 flows to the temperature sense wiring 92 and the temperature sense unit 90.
  • the temperature sensing unit 90 is a pn junction type temperature sensing diode
  • at least two temperature sensing wirings 92 and temperature measuring pads 94 are provided, one of which is electrically connected to the anode terminal of the pn junction type temperature sensing diode.
  • the other is electrically connected to the cathode of the pn junction type temperature sensing diode.
  • the detection unit 96 is provided as a spare for the temperature sensing unit 90.
  • a current sensing portion 59 In the outer peripheral region 74, a current sensing portion 59, a current sensing pad 58, and a Kelvin pad 53 are provided.
  • the current sense unit 59 detects a current flowing through the gate pad 55.
  • the current sense pad 58 is a pad for measuring the current flowing through the current sense unit 59.
  • the Kelvin pad 53 is connected to an emitter electrode provided above the active portion 72 in a top view of the semiconductor substrate 10.
  • FIG. 1b is an enlarged view of region D in FIG. 1a.
  • the semiconductor device 100 of this example is provided inside the semiconductor substrate 10 and exposed on the upper surface of the semiconductor substrate 10.
  • the gate trench portion 40, the dummy trench portion 30, the P + type well region 11, and the N + type emitter region. 12 includes a P ⁇ type base region 14 and a P + type contact region 15.
  • the gate trench portion 40 or the dummy trench portion 30 may be simply referred to as a trench portion.
  • the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.
  • an interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 50 and the upper surface of the semiconductor substrate 10, it is omitted in FIG.
  • a contact hole 56, a contact hole 49, and a contact hole 54 are provided through the interlayer insulating film.
  • Gate metal layer 50 contacts gate runner 48 through contact hole 49.
  • the emitter electrode 52 is in contact with the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through the contact hole 54.
  • the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through the contact hole 56.
  • a connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided.
  • An insulating film such as an oxide film is provided between the connection portion 25 and the upper surface of the semiconductor substrate 10.
  • the gate runner 48 is formed of polysilicon doped with impurities.
  • the gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate 10. Gate runner 48 is not connected to the dummy conductive portion in dummy trench portion 30.
  • the gate runner 48 of this example is formed from below the contact hole 49 to the tip 41 of the gate trench 40.
  • An insulating film such as an oxide film is provided between the gate runner 48 and the upper surface of the semiconductor substrate 10. At the distal end portion 41 of the gate trench portion 40, the gate conductive portion is exposed on the upper surface of the semiconductor substrate 10. A contact hole for connecting the gate conductive portion and the gate runner 48 is provided in the insulating film above the gate conductive portion.
  • FIG. 1b there is a portion where the emitter electrode 52 and the gate runner 48 overlap in plan view, but the emitter electrode 52 and the gate runner 48 are electrically insulated from each other with an insulating film (not shown) interposed therebetween.
  • the emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal.
  • each electrode is formed of aluminum or an aluminum-silicon alloy.
  • Each electrode may have a barrier metal formed of titanium, a titanium compound, or the like below a region formed of aluminum or the like, and may have a plug formed of tungsten or the like in the contact hole.
  • the one or more gate trench portions 40 and the one or more dummy trench portions 30 are arranged on the upper surface of the semiconductor substrate 10 at predetermined intervals along a predetermined arrangement direction (Y-axis direction in this example). In the transistor portion 70 of this example, one or more gate trench portions 40 and one or more dummy trench portions 30 are alternately provided along the arrangement direction.
  • the gate trench portion 40 in this example includes two straight portions 39 extending linearly along a longitudinal direction (X-axis direction in this example) perpendicular to the arrangement direction, and a tip portion 41 connecting the two straight portions 39. May be included. It is preferable that at least a part of the tip portion 41 is provided in a curved shape on the upper surface of the semiconductor substrate 10.
  • the end portions 41 which are straight ends along the longitudinal direction, are connected to each other by the tip portion 41, so that electric field concentration at the end portions of the straight portions 39 can be reduced. it can.
  • each straight line portion 39 of the gate trench portion 40 is treated as one gate trench portion 40.
  • the at least one dummy trench portion 30 is provided between the respective straight portions 39 of the gate trench portion 40. Similar to the gate trench portion 40, these dummy trench portions 30 may have a straight portion 29 and a tip portion 31. In another example, the dummy trench part 30 has the straight part 29 and does not have to have the tip part 31. In the example illustrated in FIG. 1B, in the transistor portion 70, the two straight portions 29 of the dummy trench portion 30 are disposed between the two straight portions 39 of the gate trench portion 40.
  • a plurality of dummy trench portions 30 are arranged along the X-axis direction on the upper surface of the semiconductor substrate 10.
  • the shape of the dummy trench portion 30 in the diode portion 80 on the XY plane may be the same as that of the dummy trench portion 30 provided in the transistor portion 70.
  • the front end portion 31 and the straight portion 29 of the dummy trench portion 30 may have the same shape as the front end portion 41 and the straight portion 39 of the gate trench portion 40.
  • the dummy trench part 30 provided in the diode part 80 and the linear dummy trench part 30 provided in the transistor part 70 may have the same length in the Y-axis direction.
  • the emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15.
  • the well region 11 and the end of the contact hole 54 in the longitudinal direction on the side where the gate metal layer 50 is provided are separated from each other in the XY plane.
  • the diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. Partial regions on the gate metal layer 50 side of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11. The bottom part in the Z-axis direction of the tip part 41 of the gate trench part 40 and the bottom part in the Z-axis direction of the tip part 31 of the dummy trench part 30 may be covered with the well region 11.
  • Each of the transistor portion 70 and the diode portion 80 is provided with one or more mesa portions 60 sandwiched between the trench portions.
  • the mesa portion 60 is a region on the upper surface side of the deepest bottom portion of the trench portion in the region of the semiconductor substrate 10 sandwiched between the trench portions.
  • the base region 14 is provided in the mesa portion 60 sandwiched between the trench portions.
  • the base region 14 is a second conductivity type (P ⁇ type) having a doping concentration lower than that of the well region 11.
  • a contact region 15 of the second conductivity type having a higher doping concentration than the base region 14 is provided on the upper surface of the base region 14 of the mesa portion 60.
  • the contact region 15 in this example is P + type.
  • the well region 11 may be provided away from the contact region 15 disposed at the end of the contact region 15 in the Y-axis direction in the direction of the gate metal layer 50.
  • the base region 14 is exposed between the well region 11 and the contact region 15.
  • the first conductivity type emitter region 12 having a higher doping concentration than the drift region provided in the semiconductor substrate 10 is selectively provided on the upper surface of the mesa unit 60-1.
  • the emitter region 12 of this example is N + type.
  • a portion in contact with the gate trench portion 40 functions as a channel portion.
  • an electron inversion layer is formed in a portion adjacent to the gate trench portion 40 in the base region 14 provided between the emitter region 12 and the drift region in the Z-axis direction.
  • a channel is formed.
  • base regions 14-e are disposed at both ends of each mesa 60 in the Y-axis direction.
  • the region adjacent to the base region 14-e on the center side of the mesa portion 60 is the contact region 15. Further, the region that is in contact with the base region 14-e on the opposite side to the contact region 15 is the well region 11.
  • the contact regions 15 and the emitter regions 12 are alternately arranged along the Y-axis direction in the region sandwiched between the base regions 14-e at both ends in the Y-axis direction. .
  • Each of the contact region 15 and the emitter region 12 is provided from one adjacent trench portion to the other trench portion.
  • one or more mesa portions 60-2 provided at the boundary with the diode portion 80 have a contact region 15 having a larger area than the contact region 15 of the mesa portion 60-1. Is provided.
  • the emitter region 12 may not be provided in the mesa unit 60-2.
  • the contact region 15 is provided in the entire region sandwiched between the base regions 14-e.
  • each mesa portion 60-1 of the transistor portion 70 of this example the contact hole 54 is provided above each of the contact region 15 and the emitter region 12.
  • the contact hole 54 in the mesa portion 60-2 is provided above the contact region 15.
  • the contact hole 54 is not provided in a region corresponding to the base region 14-e and the well region 11.
  • the contact hole 54 in each mesa unit 60 of the transistor unit 70 may have the same length in the Y-axis direction.
  • a cathode region 81 is provided in a region in contact with the lower surface of the semiconductor substrate 10.
  • the cathode region 81 may include an N + type first cathode region, a P + type second cathode region, and a P + third cathode region.
  • region 81 is provided is shown with the broken line.
  • a P + type collector region may be provided in a region where the cathode region 81 is not provided in a region in contact with the lower surface of the semiconductor substrate 10.
  • the transistor portion 70 is a region in which a mesa portion 60 provided with the contact region 15 and the emitter region 12 and a trench portion adjacent to the mesa portion 60 are provided in a region overlapping with the collector region in the Z-axis direction. It's okay. However, a contact region 15 may be provided in place of the emitter region 12 in the mesa unit 60-2 at the boundary with the diode unit 80.
  • the base region 14 is disposed on the upper surface of the mesa unit 60-3 of the diode unit 80.
  • the contact region 15 may be provided in a region adjacent to the base region 14-e.
  • a contact hole 54 terminates above the contact region 15.
  • the diode unit 80 includes five mesa units 60-3 and seven dummy trench units 30 sandwiching the mesa unit 60-3.
  • the number of dummy trench portions 30 is not limited to this. More mesa portions 60-3 and dummy trench portions 30 may be provided in the diode portion 80.
  • FIG. 2a is an enlarged view of region A in FIG. 1a.
  • the transistor unit 70 is provided adjacent to the diode unit 80 on both the Y axis direction positive side and the Y axis direction negative side of the diode unit 80.
  • the width WI is the width of the transistor unit 70 in the Y-axis direction.
  • the width WF is the width of the diode portion 80 in the Y-axis direction.
  • the width Wh is arranged on the X axis direction negative side with respect to the transistor unit 70 and the diode part 80 from the end of the well region 11 arranged on the X axis direction positive side with respect to the transistor part 70 and the diode part 80. This is the width of the portion up to the end of the well region 11.
  • the base region 14 is provided on the upper surface side of the semiconductor substrate 10 and the well region 11 is not provided.
  • Width WI may be larger than width WF.
  • the width WI may be not less than 2 times and not more than 5 times the width WF.
  • the width WI may be 1200 ⁇ m or more and 2000 ⁇ m or less.
  • the width WI is 1500 ⁇ m as an example.
  • the width WF may be 400 ⁇ m or more and 600 ⁇ m or less.
  • the width WF is 500 ⁇ m as an example.
  • the end S of the P + type well region 11 is provided on the positive side in the X-axis direction of the diode unit 80 and the transistor unit 70. Further, an end S ′ of the P + type well region 11 is provided on the negative side in the X-axis direction of the diode portion 80 and the transistor portion 70.
  • the well region 11 is provided outside the region where the transistor portions 70 and the diode portions 80 are alternately arranged. In other words, the well region 11 is not provided in the transistor portion 70 and the diode portion 80 from the end portion S.
  • the width Wh from the end S of the well region 11 on the X axis direction positive side to the end S ′ of the well region 11 on the X axis direction negative side may be larger than the width WI.
  • the width Wh may be not less than 1.5 times and not more than 3 times the width WI.
  • the width Wh may be not less than 3000 ⁇ m and not more than 3600 ⁇ m.
  • the width Wh may be 3100 ⁇ m as an example.
  • the cathode region 81 includes a first cathode region 82 and a second cathode region 83 as shown in FIG.
  • a plurality of first cathode regions 82 and second cathode regions 83 extending in the X-axis direction are provided separately from each other.
  • the first cathode regions 82 and the second cathode regions 83 are alternately arranged in the Y-axis direction when the semiconductor substrate 10 is viewed from above.
  • the first cathode region 82 is the first conductivity type.
  • the first cathode region 82 of this example is an N + type as an example.
  • the second cathode region 83 has a conductivity type different from that of the first cathode region 82.
  • the second cathode region 83 of this example is a P + type as an example.
  • configurations other than the first cathode region 82 and the second cathode region 83 and the floating region 17 provided in the diode unit 80 and the transistor unit 70, that is, configurations of the gate trench unit 40, the dummy trench unit 30, and the like. Is omitted.
  • the first cathode region 82 provided on the most positive side in the Y-axis direction in the diode part 80 may be in contact with the adjacent transistor part 70 on the positive side in the Y-axis direction of the diode part 80 when the semiconductor substrate 10 is viewed from above.
  • the first cathode region 82 provided on the most negative side in the Y-axis direction in the diode unit 80 may be in contact with the adjacent transistor unit 70 on the negative side in the Y-axis direction of the diode unit 80 in a top view of the semiconductor substrate 10.
  • a second conductivity type collector region 22 is provided in a region in contact with the lower surface of the semiconductor substrate 10 between the end of the first cathode region 82 on the positive side in the X-axis direction and the end S. Good.
  • the collector region 22 may be provided in a region in contact with the lower surface of the semiconductor substrate 10 between the end on the negative side in the X-axis direction of the first cathode region 82 and the end S ′.
  • the collector region 22 of this example is a P + type as an example.
  • the positional relationship between the cathode region 81 including the first cathode region 82 and the second cathode region 83 and the configuration other than the first cathode region 82 and the second cathode region 83 is the positional relationship in the top view shown in FIG. Good.
  • the configurations other than the first cathode region 82 and the second cathode region 83 are, for example, the contact hole 54, the dummy trench portion 30, and the contact region 15 provided at the end of the contact hole 54 in the X-axis direction.
  • the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82 and the second cathode region 83 in the top view of the semiconductor substrate 10 may be 60% or more and 90% or less. .
  • the ratio of the area of the second cathode region 83 to the total area may be 10% or more and 40% or less.
  • the ratio of the area of the first cathode region 82 and the area of the second cathode region 83 to the total area is 80% and 20%, respectively.
  • the semiconductor device 100 of this example has a plurality of floating regions 17 provided separately for each first cathode region 82.
  • the floating region 17 is of the second conductivity type.
  • the floating region 17 of this example is a P + type as an example.
  • the floating region 17 is disposed so as to at least partially overlap the first cathode region 82 when the semiconductor substrate 10 is viewed from above.
  • FIG. 2 a shows an example in which the entire floating region 17 is arranged so as to overlap the first cathode region 82 in a top view of the semiconductor substrate 10. That is, in FIG. 2 a, the first cathode region 82 protrudes in the arrangement direction (Y-axis direction) from the floating region 17 in a top view of the semiconductor substrate 10. Further, the first cathode region 82 protrudes in the extending direction (X-axis direction) perpendicular to the arrangement direction from the floating region 17 in a top view of the semiconductor substrate 10.
  • the floating region 17 is arranged so as not to overlap the transistor portion 70 when the semiconductor substrate 10 is viewed from above.
  • the floating region 17 is arranged so as not to contact the boundary between the diode portion 80 and the transistor portion 70.
  • FIG. 2b is an enlarged view of region B1 in FIG. 2a.
  • FIG. 2B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 2A to the end S ′ of the well region 11 on the X axis direction negative side.
  • the floating region 17 extending in the X-axis direction is arranged in the Y-axis direction as an example inside the first cathode region 82 in the XY plane. Are provided.
  • the width Wwc in the X-axis direction in a top view from the end S of the well region 11 on the X-axis direction positive side to the end on the X-axis direction positive side of the first cathode region 82 may be smaller than the width WF of the diode portion 80. .
  • the width Wwc may be not less than 0.25 times and not more than 0.75 times the width WF.
  • the width Wwc may be 150 ⁇ m or more and 300 ⁇ m or less.
  • the width Wwc is 250 ⁇ m as an example.
  • the end T on the positive side in the X-axis direction of the contact hole 54 is provided with a width Wwca away from the end S on the positive side in the X-axis direction of the well region 11 on the negative side in the X-axis direction, as shown in FIG. Further, the end portion T ′ on the negative side in the X-axis direction of the contact hole 54 is provided to be separated from the end portion S ′ on the negative side in the X-axis direction of the well region 11 on the positive side in the X-axis direction by a width Wwca.
  • the contact hole 54 may be provided continuously from the end T to the end T ′ in the X-axis direction.
  • one contact hole 54 is shown, but actually, as is clear from the top view shown in FIG. 1b, the position of the end T in the X-axis direction and the end T ' A plurality of contact holes 54 having the same position in the X-axis direction are provided in the Y-axis direction.
  • the width Wwca from the end S on the positive side in the X-axis direction of the well region 11 to the end T on the positive side in the X-axis direction of the plurality of contact holes 54 provided in the diode portion 80 is the first width from the end T.
  • the width may be smaller than the width Wwcb in the X-axis direction in a top view up to the end on the positive side in the X-axis direction of the cathode region 82.
  • the width Wwca may be not less than 0.1 times and not more than 0.9 times the width Wwcb.
  • the width Wwca may be 20 ⁇ m or more and 110 ⁇ m or less.
  • the width Wwcb may be 120 ⁇ m or more and 180 ⁇ m or less.
  • the width Wwca is 100 ⁇ m as an example.
  • the width Wwcb is 150 ⁇ m as an example.
  • the sum of the width Wwca and the width Wwcb is the width Wwc.
  • the width from the end S ′ on the negative side in the X-axis direction of the well region 11 to the end T ′ on the negative side in the X-axis direction of the plurality of contact holes 54 provided in the diode portion 80 is also equal to the width Wwca. It's okay.
  • the width in the X-axis direction in the top view of the semiconductor substrate 10 from the end T ′ to the end on the negative side in the X-axis direction of the first cathode region 82 may be equal to the width Wwcb.
  • the width in the X-axis direction in a top view from the end S ′ of the well region 11 on the negative side in the X-axis direction to the end on the negative side in the X-axis direction of the first cathode region 82 may be equal to the width Wwc.
  • the width Wcv1 in the X-axis direction of the first cathode region 82 may be smaller than the width Wh.
  • the width Wcv1 is equal to a value obtained by subtracting twice the width Wwc from the width Wh.
  • the width Wcv1 may be 90% or more and 96% or less of the width Wh.
  • the width Wcv1 may be 2700 ⁇ m or more and 3450 ⁇ m or less.
  • the width Wcv1 is 2850 ⁇ m as an example.
  • the width Wch1 in the Y-axis direction of the first cathode region 82 may be 5% to 40% of the width WF.
  • the width Wch1 may be 20 ⁇ m or more and 240 ⁇ m or less.
  • the floating region 17 is provided inside the first cathode region 82 in the XY plane, as shown in FIG. 2b.
  • the floating region 17 is not connected to the emitter electrode 52.
  • the width Wfl11 of the floating region 17 in the Y-axis direction may be 89% or more and 95% or less of the width Wch1.
  • the width Wfl21 of the floating region 17 in the X-axis direction may be 89% or more and 95% or less of the width Wcv1.
  • the area of the floating region 17 occupying the area of the first cathode region 82 in the top view of the semiconductor substrate 10 may be 80% or more and 90% or less.
  • the ratio of the area of the floating region 17 to the area may be 64% or more and 72% or less.
  • the width Wcf1 up to the end of may be 3% or more and 6% or less of the width Wch1.
  • the width Wcf1 may not be zero.
  • the width Wcf1 may be 2 ⁇ m or more and 6 ⁇ m or less.
  • the width Wcf1 is 5 ⁇ m as an example.
  • the Y-axis of the floating region 17 provided on the most negative side in the Y-axis direction from the boundary between the diode unit 80 and the transistor unit 70 adjacent to the diode unit 80 on the negative side in the Y-axis direction.
  • the width to the end on the negative direction side may also be equal to the width Wcf1.
  • the width Wcf2 from the X-axis direction positive end of the first cathode region 82 to the X-axis direction positive end of the floating region 17 is 3% or more and 6% or less of the width Wcv1. It may be.
  • the width Wcf2 may be zero. Further, the width Wcf2 may be equal to or different from the width Wcf1.
  • the width Wcf2 may be 2 ⁇ m or more and 6 ⁇ m or less.
  • the width Wcf2 is 5 ⁇ m as an example.
  • the width from the Y-axis direction negative side end of the first cathode region 82 to the Y-axis direction negative side end of the Y-axis direction negative side floating region 17 is also equal to the width Wcf2.
  • the width Wcnt in the Y-axis direction of the contact hole 54 may be smaller than Wcf1 and width Wcf2.
  • the width Wcnt may be not less than 0.3 ⁇ m and not more than 0.7 ⁇ m.
  • the width Wcnt is 0.5 ⁇ m as an example.
  • FIG. 2c is an enlarged view of region C1 in FIG. 2b.
  • three first cathode regions 82 are provided in the Y-axis direction as an example.
  • a second cathode region 83 is provided between adjacent first cathode regions 82 in the Y-axis direction.
  • the width Wnf1 is the floating region 17 arranged so as to overlap the first cathode region 82 from the Y-axis direction negative end of the first cathode region 82 in the most positive first cathode region 82 in the Y-axis direction. Is the width in the Y-axis direction to the end on the negative side in the Y-axis direction.
  • the width Wnf1 is a floating in the first cathode region 82 that is the most negative side in the Y-axis direction, overlapping the first cathode region 82 from the Y-axis direction positive end of the first cathode region 82. This is the width in the Y-axis direction up to the end on the Y-axis direction positive side of the region 17.
  • the width in the Y-axis direction up to the positive end of the floating region 17 disposed so as to overlap the first cathode region 82 may be equal to the width Wnf1.
  • the width in the Y-axis direction from the end on the negative side in the Y-axis direction of the first cathode region 82 to the end on the negative side of the floating region 17 arranged so as to overlap the first cathode region 82 is also equal to the width Wnf1. Good.
  • Width Wnf1 may be equal to width Wcf1, but may be different.
  • the width Wnf1 may be zero.
  • the first conductive type first cathode regions 82 and the second conductive type second cathode regions 83 are alternately provided in the Y-axis direction in the diode portion 80.
  • a plurality of second conductivity type floating regions 17 are provided separately from each other for each first cathode region 82, and are disposed so as to overlap the first cathode region 82 in a top view of the semiconductor substrate 10. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be suppressed.
  • FIG. 2d is a diagram showing an example of a cross section aa ′ in FIG. 2b.
  • the semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in the section aa ′.
  • the emitter electrode 52 is provided on the upper surface 21 of the semiconductor substrate 10 and the upper surface of the interlayer insulating film 38.
  • the collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10.
  • the emitter electrode 52 and the collector electrode 24 are formed of a conductive material such as metal.
  • the interlayer insulating film 38 may be silicate glass such as PSG or BPSG.
  • the interlayer insulating film 38 may be an oxide film or a nitride film.
  • the semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or a gallium oxide substrate.
  • the semiconductor substrate 10 in this example is a silicon substrate.
  • the semiconductor substrate 10 includes a first conductivity type drift region 18.
  • the drift region 18 in this example is N-type.
  • the drift region 18 may be a region remaining in the semiconductor substrate 10 without being provided with another doping region.
  • the upper surface 21 of the semiconductor substrate 10 is provided with one or more gate trench portions 40 and one or more dummy trench portions 30. Each trench portion is provided from the upper surface 21 through the base region 14 to reach the drift region 18.
  • the dummy trench portion 30 includes a dummy trench provided on the upper surface 21, and a dummy insulating film 32 and a dummy conductive portion 34 provided in the dummy trench.
  • the upper end of the dummy trench may be at the same position as the upper surface 21 in the Z-axis direction.
  • the dummy insulating film 32 is provided so as to cover the inner wall of the dummy trench.
  • the dummy insulating film 32 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the dummy trench.
  • the dummy conductive portion 34 is provided inside the dummy insulating film 32 inside the dummy trench. That is, the dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.
  • the dummy conductive portion 34 is formed of a conductive material such as polysilicon.
  • the dummy conductive portion 44 includes a region facing the base region 14 with the dummy insulating film 32 interposed therebetween.
  • the dummy trench portion 30 in the cross section is covered with the interlayer insulating film 38 on the upper surface 21.
  • a gate trench part 40 is provided in the Y-axis direction positive side and negative side transistor part 70 with respect to the aa ′ cross section.
  • the gate trench portion 40 may have the same structure as the dummy trench portion 30 in the YZ section.
  • the gate trench portion 40 includes a gate trench provided on the upper surface 21 side, and a gate insulating film and a gate conductive portion provided in the gate trench. When a predetermined voltage is applied to the gate conductive portion, a channel formed by an electron inversion layer is formed on the surface layer of the base region 14 in contact with the gate trench.
  • the gate conductive part may be formed of the same material as the dummy conductive part 34.
  • the dummy conductive portion 34 and the gate conductive portion are formed of a conductive material such as polysilicon.
  • the bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a curved surface (curved shape in cross section) convex downward.
  • one or more high-concentration regions 19 of the first conductivity type may be provided above the drift region 18 in contact with the dummy trench portion 30.
  • the high concentration region 19 is, for example, an N + type.
  • the high concentration region 19 may be provided in the mesa unit 60-3, but may not be provided.
  • the high concentration region 19 may be in contact with the dummy trench portion 30, but may not be in contact with it.
  • the high concentration regions 19-1 and 19-2 are arranged side by side in the Z-axis direction. In the Z-axis direction, a drift region 18 may be provided between the high concentration region 19-1 and the high concentration region 19-2.
  • the second conductivity type base region 14 is provided above the high concentration region 19 in contact with the upper surface 21 and in contact with the dummy trench portion 30.
  • the base region 14 in this example is a P-type as an example.
  • the hole concentration is reduced by the charge neutrality condition as compared with the drift region 18. That is, the high concentration region 19 suppresses the injection of holes from the base region 14 to the drift region 18. Thereby, the injection efficiency of minority carriers from the base region 14 to the drift region 18 is significantly reduced. As the number of high-concentration regions 19 increases, the minority carrier injection efficiency can be reduced. Thereby, the reverse recovery characteristic of the diode part 80, especially the recovery current can be greatly reduced.
  • the base region 14 of the second conductivity type is provided above the drift region 18 in contact with the dummy trench portion 30.
  • a second conductivity type contact region 15 is provided in contact with the upper surface 21 and in contact with the dummy trench portion 30.
  • the base region of this example is a P + type as an example.
  • the contact region 15 may be in contact with the dummy trench portion 30, but may not be in contact.
  • a buffer region 20 of the first conductivity type may be provided below the drift region 18.
  • the buffer area 20 is an N + type as an example.
  • the doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18.
  • the buffer region 20 is a field stop that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the P + type collector region 22, the N + type first cathode region 82, and the P + type second cathode region 83. It may function as a layer.
  • a P + type collector region 22 exposed on the lower surface 23 is provided below the buffer region 20.
  • an N + type first cathode region 82 and a P + type second cathode region 83 exposed on the lower surface 23 are provided below the buffer region 20.
  • a first cathode region 82 is provided in a region adjacent to the transistor unit 70.
  • the diode portion 80 is a region that overlaps the first cathode region 82 and the second cathode region 83 in the direction perpendicular to the lower surface 23.
  • the transistor unit 70 is a region in which predetermined unit configurations including the emitter region 12 and the contact region 15 are regularly arranged in a region overlapping the collector region 22 in a direction perpendicular to the lower surface 23.
  • the floating region 17 is provided above the first cathode region 82 in the diode portion 80.
  • three floating regions 17 are provided in the Y-axis direction in the section aa ′.
  • the floating region 17 may be provided in contact with the first cathode region 82.
  • the boundary position P1 is a boundary position on the Y axis direction positive side among the two boundary positions.
  • the boundary position P1 ′ is a boundary position on the Y axis direction negative side among the two boundary positions.
  • the boundary positions P1 and P1 ′ are boundary positions in a cross section parallel to the aa ′ cross section.
  • the aa ′ cross section is a plane perpendicular to the lower surface 23 and parallel to the arrangement direction of the dummy trench portions 30.
  • the end position P2 is an end position closest to the boundary position P1 of the floating region 17 provided on the most positive side in the Y-axis direction in a plane parallel to the lower surface 23.
  • the end position P2 ′ is the end position closest to the boundary position P1 ′ of the floating region 17 provided on the most negative side in the Y-axis direction in a plane parallel to the lower surface 23.
  • a plurality of floating regions 17 may be provided in the Y-axis direction from the end position P2 to the end position P2 ′.
  • three floating regions 17 are provided in the Y-axis direction from the end position P2 to the end position P2 ′.
  • the width Wcf1 is a distance in the Y-axis direction from the boundary position P1 to the end position P2.
  • the width Wcf1 is a distance in the Y-axis direction from the boundary position P1 ′ to the end position P2 ′.
  • the width Wd is the width of the floating region 17 in the Z-axis direction.
  • the width Wd may be smaller than the width Wcf1.
  • the width Wd may be not less than 0.05 times and not more than 0.5 times the width Wcf1.
  • the width Wd may be not less than 0.3 ⁇ m and not more than 1 ⁇ m.
  • the width Wd is 0.5 ⁇ m as an example.
  • the floating is arranged so as to overlap the first cathode region 82 from the Y-axis direction positive end of the first cathode region 82.
  • the width in the Y-axis direction to the positive end of the region 17 may be equal to the width Wnf1.
  • the width in the Y-axis direction from the end on the negative side in the Y-axis direction of the first cathode region 82 to the end on the negative side of the floating region 17 arranged so as to overlap the first cathode region 82 is also equal to the width Wnf1. Good.
  • the width Wfl11 of the floating region 17 in the Y-axis direction may be 89% or more and 95% or less of the width Wch1.
  • the width Wnf1 may be equal to the width Wcf1, but may be different.
  • the width Wnf1 may be zero.
  • FIG. 2e is a diagram showing an example of a bb ′ cross section in FIG. 2b.
  • the bb ′ cross section is the XZ plane passing through the b ′′ -b ′ ′′ line in FIG. 2d.
  • the floating region 17 is provided above the first cathode region 82 in the diode unit 80.
  • the boundary position P5 is a boundary position on the negative side in the X-axis direction among the two boundary positions.
  • the boundary position P5 ′ is a boundary position on the positive side in the X-axis direction among the two boundary positions.
  • the boundary positions P5 and P5 ′ are boundary positions in a cross section parallel to the bb ′ cross section.
  • the bb ′ cross section is a surface perpendicular to the lower surface 23 and parallel to the extending direction of the dummy trench portion 30.
  • the end position P6 is closest to the boundary position P5 of the floating region 17 arranged on the most negative side in the X-axis direction among the plurality of floating regions 17 arranged in the X-axis direction in a plane parallel to the lower surface 23.
  • the end position P6 ′ is a boundary position of the floating region 17 arranged on the most positive side in the X-axis direction among the plurality of floating regions 17 arranged in the Y-axis direction in a plane parallel to the lower surface 23. This is the end position closest to P5 ′.
  • the floating region 17 is continuously provided in the X-axis direction from the end position P6 to the end position P6 ′.
  • the width Wfl21 is the width of the floating region 17 in the X-axis direction.
  • the width Wcf2 is a distance in the X-axis direction from the boundary position P5 to the end position P6.
  • the width Wcf2 is a distance in the X-axis direction from the boundary position P5 ′ to the end position P6 ′.
  • the width Wcv1 is a distance in the X-axis direction from the boundary position P5 to the boundary position P5 ′.
  • the width Wfl21 may be 89% or more and 95% or less of the width Wcv1.
  • the floating region 17 is provided above the first cathode region 82 in the diode unit 80, the surge voltage during reverse recovery of the diode unit 80 can be suppressed.
  • a lifetime killer region can be locally provided by irradiating He or the like on the upper surface 21 side and the lower surface 23 side of the diode portion 80 to suppress carrier injection, but the formation of the lifetime killer region is costly. high.
  • the surge voltage at the time of reverse recovery of the diode part 80 becomes large, the diode part 80 cannot be speeded up.
  • the collector region 22 on the X axis direction positive side in FIG. 2E may extend to the outer peripheral region 74 on the X axis direction positive side in FIG. 1A.
  • the collector region 22 may be connected to the collector region 22 provided on the lower surface 23 of the transistor portion 70.
  • the collector region 22 provided on the negative side in the X-axis direction may extend to the outer peripheral region 74 on the negative side in the X-axis direction in FIG. .
  • a first conductivity type termination region having a doping concentration lower than that of the first cathode region 82 may be provided on the lower surface 23 instead of the collector region 22.
  • the doping concentration of the termination region may be 1/10 or less of the doping concentration of the first cathode region 82.
  • FIG. 3a is another enlarged view of region A in FIG. 1a.
  • the semiconductor device 100 of this example is different from the semiconductor device 100 shown in FIG. 2A in that some of the floating regions 17 have a first cathode region 82 and a second cathode in the top view of the semiconductor substrate 10.
  • the semiconductor device 100 is different from the semiconductor device 100 shown in FIG. That is, in the semiconductor device 100 of this example, some floating regions 17 among the plurality of floating regions 17 are in the X-axis direction between the first cathode region 82 and the second cathode region 83 when the semiconductor substrate 10 is viewed from above. It overlaps with the boundary and is provided from the first cathode region 82 to the second cathode region 83 in the Y-axis direction.
  • FIG. 3b is an enlarged view of region B2 in FIG. 3a.
  • FIG. 3B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 3A to the end S ′ of the well region 11 on the X axis direction negative side.
  • the contact hole 54 shown in FIGS. 2b and 2c is omitted.
  • the semiconductor device 100 of this example is provided with nine floating regions 17 extending in the X-axis direction and arranged in the Y-axis direction as an example in the diode unit 80.
  • three first cathode regions 82 and two second cathode regions 83 are provided as an example, so that the first cathode region 82 and the second cathode region 83 are arranged in the X-axis direction.
  • the area of the floating region 17 occupying the area of the first cathode region 82 in the top view of the semiconductor substrate 10 may be 80% or more and 90% or less.
  • the ratio of the area of the floating region 17 to the area may be 64% or more and 72% or less.
  • the width Wcf1 and the width Wcf2 may be the same as the width Wcf1 and the width Wcf2 in the example illustrated in FIG.
  • the width Wcf1 may not be zero.
  • the width Wcf2 may be zero.
  • the width Wfl21 of the floating region 17 in the X-axis direction may be the same as the width Wfl21 in the example illustrated in FIG.
  • the width Wfl12 of the floating region 17 in the Y-axis direction may be smaller than the width Wfl11 in the example illustrated in FIG.
  • FIG. 3c is an enlarged view of region C2 in FIG. 3b.
  • nine first cathode regions 82 are provided in the Y-axis direction as an example.
  • a second cathode region 83 is provided between adjacent first cathode regions 82 in the Y-axis direction.
  • four floating regions 17 out of nine floating regions 17 are provided so as to overlap with the boundary in the X-axis direction between the first cathode region 82 and the second cathode region 83.
  • five floating regions 17 are provided inside the first cathode region 82 in a top view of the semiconductor substrate 10.
  • the width Wfn1 is such that the floating region 17 provided on the negative side in the Y-axis direction of the floating region 17 provided to overlap the boundary between the first cathode region 82 and the second cathode region 83 adjacent to the first cathode region 82 on the negative side in the Y-axis direction. It is the width in the Y-axis direction from the end to the boundary.
  • the width Wfn1 is the positive value in the Y-axis direction of the floating region 17 provided to overlap the boundary between the first cathode region 82 and the second cathode region 83 adjacent to the first cathode region 82 on the Y-axis direction positive side. This is the width in the Y-axis direction from the side end to the boundary.
  • the width Wff11 is an interval in the Y-axis direction between the floating region 17 and the floating region 17 adjacent to the floating region 17. All of the plurality of floating regions 17 may be arranged in the Y-axis direction at intervals of the width Wff11. However, if there is the floating region 17 that overlaps the boundary between the first cathode region 82 and the second cathode region 83, the width Wff11 There may be floating regions 17 arranged at different intervals.
  • Width Wfn1 is smaller than width Wfl12.
  • the width Wfn1 may be equal to or different from the width Wcf1.
  • FIG. 3d is a diagram showing an example of a cross section along the line cc ′ in FIG. 3b.
  • the semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in the section cc ′.
  • the emitter electrode 52 is provided on the upper surface 21 of the semiconductor substrate 10 and the upper surface of the interlayer insulating film 38.
  • the collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10.
  • the floating region 17 is provided above the first cathode region 82 in the diode portion 80.
  • nine floating regions 17 are provided in the Y-axis direction in the section cc ′.
  • the floating region 17 may be provided in contact with the first cathode region 82.
  • some floating regions 17 are provided above the boundary between the first cathode region 82 and the second cathode region 83.
  • the floating region 17 provided above the boundary is provided in contact with both the first cathode region 82 and the second cathode region 83.
  • four floating regions 17 out of the nine floating regions 17 are provided in contact with both the first cathode region 82 and the second cathode region 83 above the boundary.
  • the diode unit 80 is more reverse than the semiconductor device 100 shown in FIG. The surge voltage at the time of recovery can be further suppressed.
  • FIG. 3e is a diagram showing an example of a dd ′ cross section in FIG. 3b.
  • the dd ′ cross section is an XZ plane passing through a d ′′ -d ′ ′′ line in FIG. 3D.
  • the configuration of the section dd ′ in the semiconductor device 100 of this example is the same as the configuration of the section bb ′ in the semiconductor device 100 shown in FIG. 2e.
  • FIG. 4a is another enlarged view of region A in FIG. 1a.
  • the semiconductor device 100 of this example is different from the semiconductor device 100 shown in FIG. 2A in that the first cathode regions 82 and the second cathode regions 83 are alternately arranged in the X-axis direction when the semiconductor substrate 10 is viewed from above. Different from the semiconductor device 100 shown in FIG.
  • the first cathode region 82 and the second cathode region 83 are provided in contact with the transistor unit 70 on both the Y axis direction positive side and the negative side.
  • the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82 and the second cathode region 83 in the top view of the semiconductor substrate 10 may be 60% or more and 90% or less.
  • the ratio of the area of the second cathode region 83 to the total area may be 10% or more and 40% or less.
  • the area of the first cathode region 82 and the area of the second cathode region 83 occupying the total area are 80% and 20%, respectively.
  • the semiconductor device 100 of this example has a plurality of floating regions 17 provided separately for each first cathode region 82.
  • the first cathode region 82 protrudes in the arrangement direction from the floating region 17 in a top view of the semiconductor substrate 10.
  • both sides of the first cathode region 82 protrude in the arrangement direction from the floating region 17 in a top view of the semiconductor substrate 10 in the arrangement direction. That is, the first cathode region 82 has portions that are not covered by the floating region 17 on both sides of the floating region 17 in the Y-axis direction.
  • one side of the first cathode region 82 may protrude from the floating region 17 in the arrangement direction when the semiconductor substrate 10 is viewed from above.
  • the first cathode region 82 protrudes in the extending direction from the floating region 17.
  • both sides of the first cathode region 82 project in the extending direction from the floating region 17 in a top view of the semiconductor substrate 10 in the extending direction. That is, the first cathode region 82 has portions that are not covered by the floating region 17 on both sides of the floating region 17 in the X-axis direction. Note that, in the extending direction, one side of the first cathode region 82 may protrude from the floating region 17 in the extending direction in a top view of the semiconductor substrate 10.
  • the entire floating region 17 is disposed so as to overlap the first cathode region 82 in a top view of the semiconductor substrate 10. That is, the floating region 17 is provided inside the first cathode region 82 when the semiconductor substrate 10 is viewed from above.
  • the floating region 17 is arranged so as not to overlap the transistor portion 70 when the semiconductor substrate 10 is viewed from above.
  • the floating region 17 is arranged so as not to contact the boundary between the diode portion 80 and the transistor portion 70.
  • FIG. 4b is an enlarged view of region B3 in FIG. 4a.
  • FIG. 4B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 4A to the end S ′ of the well region 11 on the X axis direction negative side.
  • ten floating regions 17 are provided as an example inside the first cathode region 82 in the XY plane.
  • the width Wcf1 and the width Wcf2 may be the same as the width Wcf1 and the width Wcf2 in the example illustrated in FIG.
  • the width Wcf1 may not be zero.
  • the width Wcf2 may be zero.
  • the width Wnf2 is determined from the boundary between the first cathode region 82 and the second cathode region 83 adjacent to the first cathode region 82 on the negative side in the X-axis direction. Is the width in the X-axis direction up to the end on the negative side in the X-axis direction of the floating region 17 provided to overlap.
  • the width Wnf2 is a floating provided to overlap the first cathode region 82 from the boundary between the first cathode region 82 and the second cathode region 83 adjacent to the first cathode region 82 on the X axis direction positive side. This is the width in the X-axis direction up to the end on the X-axis direction positive side of the region 17.
  • the width Wnf2 may be the same as the width Wcf2, but may be different.
  • the width Wch2 is the width of the first cathode region 82 and the second cathode region 83 in the Y-axis direction.
  • the width Wch is equal to the width WF.
  • the width Wcv2 is the width of the first cathode region 82 in the X-axis direction.
  • the width Wfl13 is the width of the floating region 17 in the Y-axis direction.
  • the width Wfl22 is the width of the floating region 17 in the X-axis direction.
  • the width Wfl13 of the floating region 17 in the Y-axis direction may be 89% or more and 95% or less of the width Wch2.
  • the width Wfl22 of the floating region 17 in the X-axis direction may be 89% or more and 95% or less of the width Wcv2.
  • the area of the floating region 17 occupying the area of the first cathode region 82 in the top view of the semiconductor substrate 10 may be 80% or more and 90% or less.
  • the ratio of the area of the floating region 17 to the area may be 64% or more and 72% or less.
  • FIG. 4c is a diagram showing an example of a cross section taken along line ee ′ in FIG. 4b.
  • the semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in the ee ′ cross section.
  • the emitter electrode 52 is provided on the upper surface 21 of the semiconductor substrate 10 and the upper surface of the interlayer insulating film 38.
  • the collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10.
  • the floating region 17 is provided above the first cathode region 82 in the diode portion 80.
  • the floating region 17 is continuously provided from the end position P2 to the end position P2 ′ in the ee ′ cross section.
  • the floating region 17 may be provided in contact with the first cathode region 82.
  • FIG. 4d is a diagram showing an example of the ff ′ cross section in FIG. 4b.
  • the ff ′ cross section is an XZ plane passing through the f ′′ -f ′ ′′ line in FIG. 4C.
  • 10 floating regions 17 are provided in the X-axis direction in the ff ′ cross section.
  • the floating region 17 may be in contact with the first cathode region 82.
  • the width Wnf2 may be the same as the width Wcf2, but may be different.
  • the width Wfl22 of the floating region 17 in the X-axis direction may be 89% or more and 95% or less of the width Wcv2.
  • the floating region 17 since the floating region 17 is provided above the first cathode region 82 in the diode unit 80, the surge voltage (overshoot voltage) during reverse recovery of the diode unit 80 can be suppressed. it can.
  • FIG. 5a is another enlarged view of region A in FIG. 1a.
  • some floating regions 17 among the plurality of floating regions 17 are the first cathode region 82 and the second cathode region in the top view of the semiconductor substrate 10.
  • the semiconductor device 100 differs from the semiconductor device 100 shown in FIG. That is, in the semiconductor device 100 of this example, some floating regions 17 among the plurality of floating regions 17 are in the Y-axis direction between the first cathode region 82 and the second cathode region 83 when the semiconductor substrate 10 is viewed from above. It overlaps with the boundary and is provided from the first cathode region 82 to the second cathode region 83 in the X-axis direction.
  • FIG. 5b is an enlarged view of region B4 in FIG. 5a.
  • FIG. 5b shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 5a to the end S ′ of the well region 11 on the X axis direction negative side.
  • the semiconductor device 100 of this example is provided with 30 floating regions 17 as an example in the diode unit 80.
  • the semiconductor device 100 of this example is provided with ten first cathode regions 82 and nine second cathode regions 83, and therefore, in the Y-axis direction between the first cathode region 82 and the second cathode region 83.
  • the first cathode region 82 provided on the most positive side in the X-axis direction is adjacent to the collector region 22 provided on the X-axis direction positive side of the first cathode region 82.
  • One floating region 17 is provided so as to overlap with a boundary parallel to the Y-axis direction between the first cathode region 82 and the collector region 22.
  • the first cathode region 82 provided on the most negative side in the X-axis direction is adjacent to the collector region 22 provided on the X-axis direction negative side of the first cathode region 82.
  • Another one floating region 17 is provided so as to overlap with a boundary parallel to the Y-axis direction between the first cathode region 82 and the collector region 22.
  • the remaining 10 floating regions 17 are provided inside the first cathode region 82 in a top view of the semiconductor substrate 10.
  • the area of the floating region 17 occupying the area of the first cathode region 82 in the top view of the semiconductor substrate 10 may be 80% or more and 90% or less.
  • the ratio of the area of the floating region 17 to the area may be 64% or more and 72% or less.
  • the width Wcf1 may be the same as the width Wcf1 in the example illustrated in FIG.
  • the width Wcf1 may not be zero.
  • the width Wfl13 of the floating region 17 in the Y-axis direction may be the same as the width Wfl13 in the example illustrated in FIG.
  • the width Wfl23 in the X-axis direction of the floating region 17 may be smaller than the width Wfl22 in the example illustrated in FIG.
  • the width Wfc2 is the first cathode region 82 provided on the most positive side in the X-axis direction from the end on the positive side in the X-axis direction of the floating region 17 provided on the most positive side in the X-axis direction. And the width in the X-axis direction to the boundary parallel to the Y-axis direction between the collector region 22 provided on the positive side in the X-axis direction.
  • the width Wfc2 is equal to the first cathode region 82 provided on the most negative side in the X-axis direction from the end on the negative side in the X-axis direction of the floating region 17 provided on the most negative side in the X-axis direction.
  • FIG. 5c is an enlarged view of region C4 in FIG. 5b.
  • the first cathode region 82 and the second cathode region 83 are provided from the boundary on the Y axis direction positive side to the negative side boundary of the transistor unit 70.
  • the floating region 17 provided on the most negative side in the X-axis direction is provided so as to overlap the first cathode region 82 and the second cathode region 83 when the semiconductor substrate 10 is viewed from above.
  • FIG. 5c is an enlarged view of region C4 in FIG. 5b.
  • the floating region 17 provided on the most positive side in the X-axis direction is provided so as to overlap the first cathode region 82 and the collector region 22 in a top view of the semiconductor substrate 10.
  • the width Wfn2 is determined from the boundary between the first cathode region 82 and the second cathode region 83 adjacent to the first cathode region 82 on the negative side in the X-axis direction. Is the width in the X-axis direction up to the end on the negative side in the X-axis direction of the floating region 17 provided to overlap.
  • the width Wfn2 is outside the region C4, but from the boundary between the first cathode region 82 and the second cathode region 83 adjacent to the first cathode region 82 on the positive side in the X-axis direction, This is the width in the X-axis direction to the end on the positive side in the X-axis direction of the floating region 17 provided so as to overlap the region 82.
  • the width Wff21 is an interval in the X-axis direction between the floating region 17 and the floating region 17 adjacent to the floating region 17. All of the plurality of floating regions 17 may be arranged in the X-axis direction at intervals of the width Wff21. However, if there is the floating region 17 that overlaps the boundary between the first cathode region 82 and the second cathode region 83, the width Wff21 There may be floating regions 17 arranged at different intervals.
  • Width Wfn2 is smaller than width Wfl23.
  • the width Wfn2 may be equal to the width Wfc2, but may be different.
  • FIG. 5d is a diagram showing an example of a gg ′ cross section in FIG. 5b.
  • the configuration of the dd ′ section in the semiconductor device 100 of this example is the same as the configuration of the ee ′ section in the semiconductor device 100 shown in FIG. 4c.
  • FIG. 5e is a diagram showing an example of the hh ′ cross section in FIG. 5b.
  • the hh ′ cross section is the XZ plane passing through the h ′′ -h ′ ′′ line in FIG. 5D.
  • the floating region 17 is provided above the first cathode region 82 in the diode unit 80.
  • the floating region 17 may be provided in contact with the first cathode region 82.
  • the end position P6 ′′ on the X axis direction negative side of the first cathode region 82 on the most negative side in the X axis direction is provided on the X axis direction negative side with respect to the boundary position P5.
  • the end position P6 ′ ′′ on the X axis direction positive side of the first cathode region 82 on the most positive side in the X axis direction is provided on the X axis direction positive side with respect to the boundary position P5 ′.
  • the width Wfc2 is a width in the X-axis direction from the boundary position P5 to the end position P6 ′′.
  • the width Wfc2 is a width in the X-axis direction from the boundary position P5 ′ to the end position P6 ′ ′′.
  • some floating regions 17 are provided above the boundary between the first cathode region 82 and the second cathode region 83.
  • the floating region 17 provided above the boundary is provided in contact with both the first cathode region 82 and the second cathode region 83.
  • the floating regions 17 provided on the most negative side and the most positive side in the X-axis direction are provided above the boundary position P5 and the boundary position P5 ′, respectively.
  • the floating region 17 provided above the boundary position P5 is provided in contact with both the first cathode region 82 on the most negative side in the X-axis direction and the collector region 22 on the negative side in the X-axis direction.
  • the floating region 17 provided above the boundary position P5 ′ is provided in contact with both the first cathode region 82 on the most positive side in the X-axis direction and the collector region 22 on the positive side in the X-axis direction.
  • the second conductivity type second cathode region 83 and the second conductivity type floating region 17 are provided in contact with each other. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be further suppressed than the semiconductor device 100 shown in FIG.
  • FIG. 6a is another enlarged view of region A in FIG. 1a.
  • the first cathode regions 82 are separated from each other and provided in a lattice shape when the semiconductor substrate 10 is viewed from above.
  • the lattice shape means that the first cathode regions 82 are periodically arranged in both the X-axis direction and the Y-axis direction.
  • FIG. 6a shows an example in which ten first cathode regions 82 are provided in the X-axis direction and three in the Y-axis direction.
  • a second cathode region 83 is provided between two first cathode regions 82 adjacent to each other in the Y-axis direction when the semiconductor substrate 10 is viewed from above.
  • a third cathode region 84 is provided between two first cathode regions 82 adjacent in the X-axis direction.
  • a third cathode region 84 is also provided between two second cathode regions 83 adjacent in the X-axis direction when the semiconductor substrate 10 is viewed from above.
  • the semiconductor device 100 of this example has a plurality of floating regions 17 provided separately for each first cathode region 82.
  • the first cathode region 82 protrudes in the arrangement direction from the floating region 17 in a top view of the semiconductor substrate 10.
  • both sides of the first cathode region 82 protrude in the arrangement direction from the floating region 17 in a top view of the semiconductor substrate 10 in the arrangement direction. That is, the first cathode region 82 has portions that are not covered by the floating region 17 on both sides of the floating region 17 in the Y-axis direction.
  • the first cathode region 82 protrudes in the extending direction from the floating region 17.
  • both sides of the first cathode region 82 project in the extending direction from the floating region 17 in a top view of the semiconductor substrate 10 in the extending direction. That is, the first cathode region 82 has portions that are not covered by the floating region 17 on both sides of the floating region 17 in the X-axis direction.
  • the entire floating region 17 is disposed so as to overlap the first cathode region 82 in a top view of the semiconductor substrate 10. That is, the floating region 17 is provided inside the first cathode region 82 provided in a lattice shape when the semiconductor substrate 10 is viewed from above.
  • the floating region 17 is arranged so as not to overlap the transistor portion 70 when the semiconductor substrate 10 is viewed from above.
  • the floating region 17 is arranged so as not to contact the boundary between the diode portion 80 and the transistor portion 70.
  • FIG. 6b is an enlarged view of region B5 in FIG. 6a.
  • 6B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 6A to the end S ′ of the well region 11 on the X axis direction negative side.
  • the floating region 17 is provided inside the first cathode region 82 in the XY plane.
  • the width Wcf1 and the width Wcf2 may be the same as the width Wcf1 and the width Wcf2 in the example illustrated in FIG.
  • the width Wcf1 may not be zero.
  • the width Wcf2 may be zero.
  • the width Wfl11 may be the same as the width Wfl11 in the example illustrated in FIG.
  • the width Wfl22 may be the same as the width Wfl22 in the example shown in FIG. 4b.
  • the width Wch1 may be the same as the width Wch1 in the example illustrated in FIG.
  • the width Wcv2 may be the same as the width Wcv2 in the example shown in FIG. 4b.
  • the width Wfl11 of the floating region 17 in the Y-axis direction may be 89% or more and 95% or less of the width Wch1.
  • the width Wfl22 of the floating region 17 in the X-axis direction may be 89% or more and 95% or less of the width Wcv2.
  • the area of the floating region 17 occupying the area of the first cathode region 82 in the top view of the semiconductor substrate 10 may be 80% or more and 90% or less.
  • the ratio of the area of the floating region 17 to the area may be 64% or more and 72% or less.
  • FIG. 6c is an enlarged view of region C5 in FIG. 6b.
  • the semiconductor device 100 of this example includes the second cathode in a direction (X-axis direction) parallel to the boundary between the first cathode region 82 and the second cathode region 83 when the semiconductor substrate 10 is viewed from above.
  • a third cathode region 84 provided in contact with the second cathode region 83 is provided at the end portion U ⁇ b> 1 on the X axis direction negative side of the region 83.
  • the third cathode region 84 may be provided in contact with each of the two ends U1 of the second cathode region 83.
  • the semiconductor device 100 of this example includes three first cathode regions 82 in the Y-axis direction as an example.
  • the floating region 17 is provided inside the XY plane of each first cathode region 82.
  • the width Wnf2 is the width in the X-axis direction from the end on the negative side in the X-axis direction of the first cathode region 82 to the end on the negative side in the X-axis direction of the floating region 17 arranged to overlap the first cathode region 82 It is. Further, the width Wnf2 is outside the region C5, but in the first cathode region 82 excluding the most negative and positive first cathode regions 82 in the X-axis direction, the first cathode region 82 is positive in the X-axis direction. This is the width in the X-axis direction from the end on the side to the end on the positive side in the X-axis direction of the floating region 17 disposed so as to overlap the first cathode region 82.
  • Width Wnf2 may be equal to width Wcf2, but may be different.
  • the width Wnf2 may be zero.
  • FIG. 6d is a diagram showing an example of the ii ′ cross section in FIG. 6b.
  • the configuration of the semiconductor device 100 of this example along the ii ′ cross section is the same as the configuration of the semiconductor device 100 shown in FIG.
  • FIG. 6e is a diagram showing an example of a section ij ′ in FIG. 6b.
  • the jj ′ cross section is the XZ plane passing through the j ′′ -j ′ ′′ line in FIG. 6d.
  • the configuration of the jj ′ section in the semiconductor device 100 of this example is that a third cathode region 84 is provided in place of the second cathode region 83 in the ff ′ section in the semiconductor device 100 shown in FIG. Different from the semiconductor device 100 shown in FIG.
  • the semiconductor device 100 of the present example includes the floating region 17 for each first cathode region 82 provided separately in a grid pattern. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be suppressed.
  • FIG. 7a is another enlarged view of region A in FIG. 1a.
  • the floating region 17 projects in the extending direction from the first cathode region 82 in a top view of the semiconductor substrate 10.
  • both sides of the floating region 17 protrude in the extending direction from the first cathode region 82 in the extending direction. That is, the floating region 17 is provided so as to overlap the entire first cathode region 82 in the X-axis direction. Note that either one of the positive side and the negative side in the X-axis direction of the floating region 17 may protrude in the extending direction from the first cathode region 82.
  • the end on the positive side in the X-axis direction of the floating region 17 is X more than the end on the positive side in the X-axis direction of the first cathode region 82.
  • the end on the negative side in the X-axis direction of the floating region 17 is provided on the negative side in the X-axis direction with respect to the end on the negative side in the X-axis direction of the first cathode region 82.
  • the floating regions 17 may be provided in a lattice shape.
  • the semiconductor device 100 shown in FIG. 7A shows an example in which ten floating regions 17 are provided in the X-axis direction and three in the Y-axis direction.
  • the number of floating regions 17 in the X-axis direction may match the number of first cathode regions 82 in the X-axis direction.
  • the floating region 17 provided to overlap the first cathode region 82 includes the floating region 17 provided to overlap the other first cathode region 82 adjacent to the first cathode region 82 in either the positive or negative direction of the X-axis direction. , May be separated from each other in the X-axis direction, but may be integrated.
  • FIG. 7b is an enlarged view of region B6 in FIG. 7a.
  • FIG. 7B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 7A to the end S ′ of the well region 11 on the X axis direction negative side.
  • the floating region 17 is provided in the diode portion 80 so as to overlap the entire first cathode region 82 in the X-axis direction.
  • the width Wcf1 may be the same as the width Wcf1 in the example illustrated in FIG.
  • the width Wcf1 may not be zero.
  • the width Wfl14 of the floating region 17 in the Y-axis direction may be larger, smaller, or equal to the width Wfl11 in the semiconductor device 100 of FIG.
  • the width Wfl24 of the floating region 17 in the X-axis direction may be larger than the width Wfl22 in the semiconductor device 100 of FIG. 4b.
  • a region of the floating region 17 that does not overlap with the first cathode region 82 in a top view of the semiconductor substrate 10 may overlap with the second cathode region 83.
  • An end on the positive side in the X-axis direction of the floating region 17 provided so as to overlap with the first cathode region 82 provided on the most positive side in the X-axis direction is the X-axis of the first cathode region 82 in a top view of the semiconductor substrate 10. It may overlap with a part of the collector region 22 provided on the positive direction side.
  • An end on the negative side in the X-axis direction of the floating region 17 provided so as to overlap with the first cathode region 82 provided on the most negative side in the X-axis direction is the X-axis of the first cathode region 82 in a top view of the semiconductor substrate 10. It may overlap with a part of the collector region 22 provided on the negative direction side.
  • the width Wfc ⁇ b> 2 is the width of the first cathode region 82 from the end on the positive side in the X-axis direction of the floating region 17 provided so as to overlap with the first cathode region 82 on the most positive side in the X-axis direction. This is the width in the X-axis direction up to the end on the positive side in the X-axis direction.
  • the width Wfc2 extends from the end on the negative side in the X axis direction of the floating region 17 provided so as to overlap with the first negative cathode region 82 on the most negative side in the X axis direction to the negative side in the X axis direction of the first cathode region 82. This is the width in the X-axis direction to the end.
  • the width Wfc2 may be equal to or different from the width Wch2 in the semiconductor device 100 shown in FIG. 4b.
  • the area of the floating region 17 occupying the area of the first cathode region 82 in the top view of the semiconductor substrate 10 may be 80% or more and 90% or less.
  • the ratio of the area of the floating region 17 to the area may be 64% or more and 72% or less.
  • FIG. 7c is an enlarged view of region C6 in FIG. 7b.
  • the floating region 17 is provided so as to overlap the entire first cathode region 82 in the X-axis direction when the semiconductor substrate 10 is viewed from above.
  • the semiconductor device 100 of this example includes three first cathode regions 82 in the Y-axis direction. Further, the width Wfl24 is larger than the width Wcv2.
  • the width Wfn2 is negative in the X-axis direction of the floating region 17 provided to overlap the first cathode region 82 from the end on the negative side in the X-axis direction of the first cathode region 82 in the region C6 when the semiconductor substrate 10 is viewed from above. It is the width in the X-axis direction to the end on the side.
  • the width Wfn2 may be equal to the width Wfc2, but may be different.
  • FIG. 7d is a diagram showing an example of a kk ′ cross section in FIG. 7b.
  • the first cathode region 82 is continuously provided in the Y-axis direction from the end portion P1 to the end portion P1 ′ in the kk ′ cross section.
  • the floating region 17 is provided above the first cathode region 82.
  • the floating region 17 may be provided in contact with the first cathode region 82.
  • the width Wfl14 may be larger, smaller, or equal to the width Wfl11 in the example shown in FIG. 2d.
  • FIG. 7e is a diagram showing an example of a mm ′ cross section in FIG. 7b.
  • the mm ′ cross section is the XZ plane passing through the m ′′ -m ′ ′′ line in FIG. 7d.
  • the first cathode regions 82 and the second cathode regions 83 are alternately provided in the X-axis direction in the mm ′ cross section.
  • the floating region 17 is provided above the first cathode region 82.
  • the floating region 17 provided above the first cathode region 82 is also provided above a part of the second cathode region 83 adjacent to the first cathode region 82 in the X-axis direction. For this reason, the width Wfl24 is larger than the width Wcv2.
  • the floating region 17 provided on the most positive side in the X-axis direction may be provided above a part of the collector region 22 provided on the positive side in the X-axis direction.
  • the floating region 17 provided on the most negative side in the X-axis direction may also be provided above a part of the collector region 22 on the X-axis direction negative side.
  • the floating region 17 may be provided in contact with the first cathode region 82.
  • the floating region 17 may be provided in contact with the second cathode region 83.
  • the floating region 17 may be provided in contact with the collector region 22.
  • the floating region 17 is provided so as to overlap the entire first cathode region 82 in the X-axis direction.
  • the floating region 17 is provided so as to overlap the second cathode region 83 at both ends in the X-axis direction of the first cathode region 82. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be further suppressed than the semiconductor device 100 shown in FIG. 6a.
  • FIG. 8a is another enlarged view of region A in FIG. 1a.
  • a plurality of first cathode regions 82 separated from each other in a top view of the semiconductor substrate 10 are provided extending in the X-axis direction, like the semiconductor device 100 illustrated in FIG.
  • a second cathode region 83 is provided between the first cathode regions 82 adjacent to each other in the Y axis direction when the semiconductor substrate 10 is viewed from above.
  • the first cathode region 82 provided on the most positive side in the Y-axis direction may be in contact with the transistor unit adjacent to the positive side of the diode unit 80 in the Y-axis direction.
  • the first cathode region 82 provided on the most negative side in the Y-axis direction may be in contact with the transistor portion adjacent on the Y-axis direction negative side of the diode portion 80.
  • the floating regions 17 may be provided in a lattice shape.
  • the semiconductor device 100 shown in FIG. 8A shows an example in which 20 floating regions 17 are provided in the X axis direction and 3 in the Y axis direction.
  • the number of floating regions 17 in the Y-axis direction may match the number of first cathode regions 82 in the Y-axis direction.
  • the floating region 17 protrudes in the arrangement direction from the first cathode region 82 in a top view of the semiconductor substrate 10.
  • the central floating region 17 has both sides of the floating region 17 projecting beyond the first cathode region 82 in the arrangement direction. That is, the floating region 17 is provided so as to overlap the entire first cathode region 82 in the arrangement direction.
  • the Y region in the Y axis direction of the floating region 17 on the positive side in the Y axis direction protrudes beyond the first cathode region 82 in the Y direction in the arrangement direction. That is, the Y-axis direction negative end of the floating region 17 is provided on the Y-axis direction negative side of the first cathode region 82 on the Y-axis negative side.
  • the floating region 17 on the negative side in the Y-axis direction protrudes beyond the first cathode region 82 in the Y-axis direction positive side of the floating region 17 in the arrangement direction. . That is, the end on the Y axis direction positive side of the floating region 17 is provided closer to the Y axis direction positive side than the end portion of the first cathode region 82 on the Y axis direction positive side. Note that the floating region 17 is not provided so as to overlap the transistor portion 70.
  • FIG. 8b is an enlarged view of region B7 in FIG. 8a.
  • FIG. 8B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 8A to the end S ′ of the well region 11 on the X axis direction negative side.
  • the floating region 17 provided to overlap the first cathode region 82 that does not contact the transistor unit 70 among the plurality of first cathode regions 82 in the diode unit 80 includes: The first cathode region 82 is provided so as to overlap the entire Y-axis direction.
  • the width Wcf1 and the width Wcf2 may be the same as the width Wcf1 and the width Wcf2 in the example illustrated in FIG.
  • the width Wcf1 may not be zero.
  • the width Wcf2 may be zero.
  • the width Wfl15 in the Y-axis direction of the floating region 17 provided on the most positive side and the negative side in the Y-axis direction may be larger or smaller than the width Wfl11 in the semiconductor device 100 in FIG. Or may be equal.
  • the width Wfl16 in the Y-axis direction of the floating region 17 provided at the center in the Y-axis direction may be larger, smaller, or equal to the width Wfl11 in the semiconductor device 100 of FIG. Further, the width Wfl16 may be larger than the width Wfl5.
  • the width Wfl25 of the floating region 17 in the X-axis direction may be larger, smaller, or equal to the width Wfl22 in the example of FIG.
  • the width Wfl22 may be larger, smaller, or equal to the width Wfl15.
  • Width Wfl22 may be larger than width Wfl16, may be smaller, or may be equal.
  • FIG. 8c is an enlarged view of region C7 in FIG. 8b.
  • the semiconductor device 100 of this example includes the floating region 17 provided to overlap the first cathode region 82 provided at the center in the Y-axis direction when the semiconductor substrate 10 is viewed from the top among the plurality of floating regions 17. Is provided so as to overlap the entire first cathode region 82 in the Y-axis direction.
  • the width Wfn1 is the Y axis from the end on the Y axis direction positive side of the first cathode region 82 to the end on the Y axis direction positive side of the floating region 17 provided to overlap with the end.
  • the width Wfn1 is a width in the Y-axis direction from the end on the Y-axis direction negative side of the first cathode region 82 to the end on the Y-axis direction negative side of the floating region 17 provided so as to overlap with the end.
  • the width Wfn1 may be equal to the width Wfn1 in the example of FIG.
  • the width Wfn1 may be equal to the width Wcf1.
  • FIG. 8d is a diagram showing an example of the nn ′ cross section in FIG. 8b.
  • the first cathode regions 82 and the second cathode regions 83 are alternately provided in the Y-axis direction in the nn ′ cross section.
  • the floating region 17 is provided above the first cathode region 82.
  • the floating region 17 provided above the first cathode region 82 is also provided above a part of the second cathode region 83 adjacent to the first cathode region 82 in the Y-axis direction. For this reason, the width Wfl16 is larger than the width Wch1.
  • the floating region 17 may be provided in contact with the first cathode region 82.
  • the floating region 17 may be provided in contact with the second cathode region 83.
  • the floating region 17 provided in the center in the Y-axis direction is provided so as to overlap the entire first cathode region 82 in the Y-axis direction.
  • the floating region 17 is provided so as to overlap the second cathode region 83 at both ends in the Y-axis direction of the first cathode region 82. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be further suppressed than the semiconductor device 100 shown in FIG. 6a.
  • FIG. 8e is a diagram showing an example of a pp ′ section in FIG. 8b.
  • the pp ′ cross section is an XZ plane passing through the p ′′ -p ′ ′′ line in FIG.
  • the first cathode region 82 is continuously provided in the Y-axis direction from the boundary position P5 to the boundary position P5 ′ in the pp ′ cross section.
  • the floating region 17 is provided above the first cathode region 82.
  • the floating region 17 may be provided in contact with the first cathode region 82.
  • FIG. 9a is another enlarged view of region A in FIG. 1a.
  • the semiconductor device 100 of this example is further provided with a second conductivity type third cathode region 84 so as to sandwich the first cathode region 82 and the second cathode region 83 when the semiconductor substrate 10 is viewed from above.
  • the third cathode region 84 is provided in contact with the lower surface 23 on the positive side and the negative side in the X-axis direction of the cathode region 81.
  • the third cathode region 84 of this example is a P + type as an example.
  • FIG. 9b is an enlarged view of region B8 in FIG. 9a.
  • FIG. 9B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 9A to the end S ′ of the well region 11 on the X axis direction negative side.
  • the third cathode regions 84 are respectively provided on the positive side and the negative side of the cathode region 81 in the X-axis direction in the diode portion 80 when the semiconductor substrate 10 is viewed from above. .
  • the first cathode region 82 and the second cathode region 83 are alternately provided in the Y-axis direction between the third cathode regions 84 provided at both ends in the X-axis direction when the semiconductor substrate 10 is viewed from above. It is done.
  • the width Wch1 may be the same as the width Wch1 in the example shown in FIG. 2b.
  • the width Wcv2 may be the same as the width Wcv1 in the example illustrated in FIG.
  • the width Wcv3 is the width in the X-axis direction of the first cathode region 82 and the second cathode region 83 in the top view of the semiconductor substrate 10.
  • the width Wcv3 may be smaller than the width Wcv1.
  • the width Wcv3 may be not less than 70% and not more than 90% of the width Wcv1.
  • the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82, the second cathode region 83, and the third cathode region 84 is 60% or more and 90% or less. Good.
  • the ratio of the total area of the second cathode region 83 and the third cathode region 84 in the total area may be 10% or more and 40% or less.
  • the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82, the second cathode region 83, and the third cathode region 84 is 80%.
  • the ratio of the total area of the second cathode region 83 and the third cathode region 84 to the total area of the first cathode region 82, the second cathode region 83, and the third cathode region 84 is 20%.
  • FIG. 9c is an enlarged view of region C8 in FIG. 9b.
  • three first cathode regions 82 are provided in the Y-axis direction as an example.
  • a second cathode region 83 is provided between the first cathode regions 82 adjacent in the Y-axis direction.
  • a third cathode region 84 is provided in contact with the second cathode region 83.
  • the width Wcc is the width of the second cathode region 83 along the arrangement direction of the first cathode region 82 and the second cathode region 83 in the top view of the semiconductor substrate 10.
  • the width Wct is the width of the third cathode region 84 along the arrangement direction when the semiconductor substrate 10 is viewed from above.
  • the width Wct is larger than the width Wcc.
  • the arrangement direction is the Y-axis direction is shown, but the arrangement direction may be a direction different from the Y-axis direction.
  • the doping concentration of the third cathode region 84 may be equal to the doping concentration of the second cathode region 83. That is, in the region C8, the second cathode region 83 and the third cathode region 84 may be connected as a cathode region of the second conductivity type having the same doping concentration.
  • FIG. 9d is a diagram showing an example of a qq ′ cross section in FIG. 9b.
  • the configuration of the qq ′ cross section of the semiconductor device 100 of this example is the same as the configuration of the cross section aa ′ in FIG.
  • FIG. 9e is a diagram showing an example of the rr ′ cross section in FIG. 9b.
  • the first cathode region 82 is in contact with the first cathode region 82 on the positive side and the negative side in the X-axis direction, respectively.
  • a cathode region 84 is provided.
  • the third cathode region 84 on the X axis direction positive side may be sandwiched between the first cathode region 82 and the collector region 22 provided on the X axis direction positive side of the first cathode region 82 in the X axis direction.
  • the third cathode region 84 on the X axis direction negative side may be sandwiched between the first cathode region 82 and the collector region 22 provided on the X axis direction negative side of the first cathode region 82 in the X axis direction.
  • a third cathode region 84 is provided in contact with the second cathode region 83. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be suppressed.
  • FIG. 10a is another enlarged view of region A in FIG. 1a.
  • the semiconductor device 100 of this example is different from the semiconductor device 100 shown in FIG. 4A in that the floating region 17 is not provided inside the first cathode region 82 when the semiconductor substrate 10 is viewed from above. And different.
  • FIG. 10b is an enlarged view of region B9 in FIG. 10a.
  • FIG. 10B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 10A to the end S ′ of the well region 11 on the X axis direction negative side.
  • the first cathode regions 82 and the second cathode regions 83 are alternately provided in the X-axis direction in the diode portion 80.
  • ten first cathode regions 82 are provided in the X-axis direction
  • nine second cathode regions 83 are provided in the X-axis direction.
  • the width Wch2 may be the same as the width Wch2 in the example shown in FIG. 4b.
  • the width Wcv2 may be the same as the width Wcv2 in the example shown in FIG. 4b.
  • the width Wcv4 is a width in the X-axis direction of the second cathode region 83 when the semiconductor substrate 10 is viewed from above.
  • the width Wcv4 may be 5% or more and 30% or less of the width Wcv2.
  • the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82 and the second cathode region 83 may be 60% or more and 90% or less.
  • the ratio of the area of the second cathode region 83 to the total area may be 10% or more and 40% or less.
  • the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82 and the second cathode region 83 is 80%.
  • the ratio of the area of the second cathode region 83 to the total area of the first cathode region 82 and the second cathode region 83 is 20%.
  • FIG. 10c is a diagram showing an example of the ss ′ cross section in FIG. 10b.
  • the configuration of the ss ′ cross section in the semiconductor device 100 of this example is the same as the configuration of the ee ′ cross section in FIG.
  • FIG. 10d is a diagram showing an example of a tt ′ cross section in FIG. 10b.
  • the semiconductor device 100 of this example includes a first cathode region 82 and a second cathode region 83 in contact with the lower surface 23 in the tt ′ cross section.
  • the first cathode regions 82 and the second cathode regions 83 are provided alternately in the X-axis direction. For this reason, the semiconductor device 100 of this example can suppress the surge voltage at the time of reverse recovery of the diode unit 80.
  • FIG. 11a is another enlarged view of region A in FIG. 1a.
  • the semiconductor device 100 of this example is different from the semiconductor device 100 shown in FIG. 6A in that the floating region 17 is not provided inside the first cathode region 82 provided in a lattice shape in a top view of the semiconductor substrate 10. Different from the semiconductor device 100 shown in FIG.
  • FIG. 11b is an enlarged view of region B10 in FIG. 11a.
  • FIG. 11b shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 11a to the end S ′ of the well region 11 on the X axis direction negative side.
  • ten first cathode regions 82 are provided in the X-axis direction and three in the Y-axis direction.
  • the width Wch1 may be the same as the width Wch1 in the example shown in FIG. 2b.
  • the width Wcv2 may be the same as the width Wcv2 in the example shown in FIG. 4b.
  • the width Wcv4 may be the same as the width Wcv4 in the example illustrated in FIG.
  • the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82, the second cathode region 83, and the third cathode region 84 is 60% or more and 90% or less. Good.
  • the ratio of the total area of the second cathode region 83 and the third cathode region 84 in the total area may be 10% or more and 40% or less.
  • the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82, the second cathode region 83, and the third cathode region 84 is 80%.
  • the ratio of the total area of the second cathode region 83 and the third cathode region 84 to the total area of the first cathode region 82, the second cathode region 83, and the third cathode region 84 is 20%.
  • FIG. 11c is an enlarged view of region C9 in FIG. 11b.
  • the semiconductor device 100 of this example is provided with a third cathode region 84 so as to sandwich the first cathode region 82 and the second cathode region 83 when the semiconductor substrate 10 is viewed from above. That is, in the top view of the semiconductor substrate 10, the X of the second cathode region 83 is along the direction in which the third cathode region 84 sandwiches the first cathode region 82 and the second cathode region 83 (in this example, the X-axis direction).
  • a third cathode region 84 provided in contact with the second cathode region 83 is provided at the end U1 on the axially positive side.
  • the second cathode region 83 includes a third cathode region 84 provided in contact with the second cathode region 83 at the end U2 on the X axis direction negative side.
  • the third cathode region 84 may be provided in contact with each of the two ends of the second cathode region 83, as shown in FIG. 11c. That is, the third cathode region 84 may be provided in contact with each of the one end U1 and the other end U2 of the second cathode region 83.
  • the plurality of second cathode regions 83 and the plurality of third cathode regions 84 may be in contact with each other when the semiconductor substrate 10 is viewed from above. That is, each of the plurality of third cathode regions 84 may be provided in contact with each end of the plurality of second cathode regions 83, as shown in FIG. 11c. That is, in the region C9, the third cathode region 84 includes both the end portion U1 of the second cathode region 83 provided on the Y axis direction negative side and the end portion U1 of the second cathode region 83 provided on the Y axis direction positive side. It may be provided in contact with.
  • the third cathode region 84 has ends U2 and Y of the second cathode region 83 arranged adjacent to the second cathode region 83 provided on the Y axis direction positive side on the X axis direction positive side.
  • the second cathode region 83 provided on the negative side in the axial direction may be provided in contact with both ends U2 of the second cathode region 83 arranged adjacent to the positive side in the X-axis direction.
  • the width of the second cathode region 83 along the direction in which the third cathode region 84 sandwiches the first cathode region 82 and the second cathode region 83 is the width It may be equal to Wcv2.
  • the width Wcv2 may be larger than the width Wcc. That is, the second cathode region 83 may be a rectangle that is long in the X-axis direction.
  • the width of the second cathode region 83 along the arrangement direction of the first cathode region 82 and the second cathode region 83 (in this example, the Y-axis direction) in the top view of the semiconductor substrate 10 may be equal to the width Wch1. .
  • the width Wcv2 may be larger than the width Wch1.
  • Width Wcc may be smaller than width Wch1.
  • the width Wct may be larger than the width Wch1.
  • the width Wct may be equal to the width WF of the diode unit 80 in the Y-axis direction.
  • the doping concentration of the third cathode region 84 may be equal to the doping concentration of the second cathode region 83. That is, in the region C9, the second cathode region 83 and the third cathode region 84 may be connected as a cathode region of the second conductivity type having the same doping concentration.
  • the doping concentrations of all the second cathode regions 83 and the third cathode regions 84 in one diode portion 80 may be equal. Further, all the second cathode regions 83 and the third cathode regions 84 in one diode portion 80 may be connected as cathode regions of the second conductivity type having the same doping concentration. In other words, all the second cathode regions 83 and the third cathode regions 84 in one diode unit 80 may be integrated as a cathode region of the second conductivity type having the same doping concentration.
  • FIG. 11d is a diagram showing an example of a uu ′ cross section in FIG. 11b.
  • the configuration of the uu ′ section in the semiconductor device 100 of this example is the same as the configuration of the qq ′ section in the semiconductor device 100 of FIG. 9D.
  • FIG. 11e is a diagram showing an example of a vv ′ cross section in FIG. 11b.
  • the vv ′ cross section is an XZ plane passing through the line v ′′ -v ′ ′′ in FIG. 11d.
  • the semiconductor device 100 of this example includes a first cathode region 82 and a third cathode region 84 in contact with the lower surface 23 in the vv ′ cross section.
  • the first cathode regions 82 and the third cathode regions 84 are alternately provided in the X-axis direction.
  • the third cathode region 84 is provided in contact with one end U1 and the other end U2 of the second cathode region 83, respectively.
  • a third cathode region 84 is provided in contact with each end of the plurality of second cathode regions 83. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be suppressed.
  • FIG. 12 a is a diagram illustrating another example of the upper surface of the semiconductor device 200 according to the present embodiment.
  • the semiconductor device 200 is a diode such as FWD.
  • the semiconductor substrate 10 is provided with an active portion 72 and an outer peripheral region 74 similar to those of the semiconductor device 100.
  • the active portion 72 of this example is provided with the diode portion 80 and the transistor portion 70 may not be provided.
  • the active unit 72 may be provided with a plurality of diode units 80 in the Y-axis direction.
  • the diode unit 80 includes a first cathode region 82 and a second cathode region 83.
  • the first cathode region 82 is the first conductivity type.
  • the first cathode region in this example is an N + type as an example.
  • the second cathode region 83 has a conductivity type different from that of the first cathode region 82.
  • the second cathode region 83 of this example is a P + type as an example.
  • the width Wh is a width in the X-axis direction of the semiconductor device 200 when the semiconductor substrate 10 is viewed from above.
  • the width WF is a width in the Y-axis direction of the semiconductor device 200 when the semiconductor substrate 10 is viewed from above.
  • the configuration other than the first cathode region 82 and the second cathode region 83, that is, the configuration of the dummy trench portion 30 and the like is omitted.
  • the semiconductor device 200 of this example has a plurality of floating regions 17 provided separately from each other for each first cathode region 82 in a top view of the semiconductor substrate 10.
  • the floating region 17 is of the second conductivity type.
  • the floating region 17 of this example is a P + type as an example.
  • the floating region 17 is disposed so as to at least partially overlap the first cathode region 82 when the semiconductor substrate 10 is viewed from above.
  • FIG. 12 a shows an example in which the entire floating region 17 is disposed so as to overlap the first cathode region 82 in a top view of the semiconductor substrate 10.
  • the first cathode region 82 protrudes in the Y-axis direction from the floating region 17 in a top view of the semiconductor substrate 10.
  • both sides of the first cathode region 82 protrude from the floating region 17 in a top view of the semiconductor substrate 10 in the Y-axis direction. That is, the first cathode region 82 has portions that are not covered by the floating region 17 on both sides of the floating region 17 in the Y-axis direction.
  • the first cathode region 82 protrudes in the X-axis direction from the floating region 17.
  • both sides of the first cathode region 82 protrude from the floating region 17 in a top view of the semiconductor substrate 10 in the X-axis direction. That is, the first cathode region 82 has portions that are not covered by the floating region 17 on both sides of the floating region 17 in the X-axis direction.
  • the entire floating region 17 is disposed so as to overlap the first cathode region 82 when the semiconductor substrate 10 is viewed from above. That is, in the semiconductor device 200 of this example, the floating region 17 is provided inside the first cathode region 82 when the semiconductor substrate 10 is viewed from above. The floating region 17 is provided separately for each first cathode region 82. Note that at least a part of the floating region 17 may be disposed so as to overlap the first cathode region 82.
  • FIG. 12b is an enlarged view of the region E1 in FIG. 12a.
  • the semiconductor device 200 of this example is provided with the floating region 17 inside the first cathode region 82 in a top view of the semiconductor substrate 10.
  • the floating region 17 is provided separately from each other for each first cathode region 82, and is disposed to at least partially overlap the first cathode region 82.
  • This example is an example in which the entire floating region 17 in a top view of the semiconductor substrate 10 is disposed so as to overlap the first cathode region 82.
  • the floating region 17 may be provided in contact with the first cathode region 82.
  • FIG. 12c is a diagram showing an example of a cross section aa-aa ′ in FIG. 12b.
  • the semiconductor device 200 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in the aa-aa ′ cross section.
  • the emitter electrode 52 is provided on the upper surface 21 and the upper surface of the interlayer insulating film 38.
  • the collector electrode 24 is provided on the lower surface 23.
  • the semiconductor device 200 of this example has a drift region 18 of the first conductivity type provided on the semiconductor substrate 10.
  • the semiconductor device 200 of the present example includes a second conductivity type base region 14 provided in contact with the upper surface 21 and above the drift region 18.
  • the semiconductor device 200 of the present example includes a plurality of first cathode regions 82 and 83 of a first conductivity type that are in contact with the lower surface 23 and provided below the drift region 18 and are separated from each other.
  • the semiconductor device 200 may not have the high concentration region 19. Further, when the high concentration region 19 is not provided, the dummy trench portion 30 may not be provided.
  • FIG. 12d is a diagram showing an example of a bb-bb ′ cross section in FIG. 12b.
  • the bb-bb ′ cross section is an XZ plane passing through the line bb ′′ -bb ′ ′′ in FIG. 12c.
  • the floating region 17 is continuously provided in the X-axis direction from the end position P6 to the end position P6 ′ above the first cathode region 82 in the bb-bb ′ cross section. .
  • the floating region 17 may be provided in contact with the first cathode region 82.
  • the second cathode region 83 on the X axis direction positive side in FIG. 12d may extend to the outer peripheral region 74 on the X axis direction positive side in FIG. 12a.
  • the second cathode region 83 on the X axis direction negative side may extend to the outer peripheral region 74 on the X axis direction negative side in FIG.
  • a first conductivity type termination region having a doping concentration lower than that of the first cathode region 82 may be provided on the lower surface 23 instead of the second cathode region 83.
  • the doping concentration of the termination region may be 1/10 or less of the doping concentration of the first cathode region 82.
  • the floating region 17 is provided separately for each first cathode region 82 and is provided above the first cathode region 82 for each first cathode region 82. For this reason, the surge voltage at the time of reverse recovery of the semiconductor device 200 can be suppressed.
  • FIG. 13a is a diagram showing another example of the upper surface of the semiconductor device 200 according to the present embodiment.
  • the first cathode region 82 is an end portion on the negative side from the end region on the positive side in the Y-axis direction of the unit structure of the diode indicated by the region E2.
  • the semiconductor device 200 is different from the semiconductor device 200 shown in FIG. Further, the semiconductor device 200 shown in FIG. 12A differs from the semiconductor device 200 shown in FIG. 15A in that the first cathode regions 82 and the second cathode regions 83 are alternately provided in the X-axis direction.
  • FIG. 13b is an enlarged view of region E2 in FIG. 13a.
  • the first cathode region 82 is continuously provided from the end region on the positive side in the Y-axis direction of the unit structure of the diode to the end region on the negative side.
  • the first cathode regions 82 and the second cathode regions 83 are alternately provided in the X-axis direction.
  • the floating region 17 is provided inside the first cathode region 82 when the semiconductor substrate 10 is viewed from above. Ten floating regions 17 are provided in the X-axis direction. The floating region 17 is provided above the first cathode region 82. The floating region 17 may be provided in contact with the first cathode region 82.
  • FIG. 13c is a diagram showing an example of a cc-cc ′ cross section in FIG. 13b.
  • the first cathode region 82 continues in the Y-axis direction from the Y-axis direction positive end region to the negative-side end region of the semiconductor device 200.
  • the width Wch2 in the Y-axis direction of the first cathode region 82 is equal to the width WF in the Y-axis direction of the semiconductor device 200.
  • FIG. 13d is a diagram showing an example of a dd-dd ′ section in FIG. 13b.
  • the section dd-dd ′ is the XZ plane passing through the line dd ′′ -dd ′ ′′ in FIG. 13c.
  • the first cathode regions 82 and the second cathode regions 83 are alternately provided in contact with the lower surface 23 in the X-axis direction.
  • the floating region 17 is provided above the first cathode region 82 and in contact with the first cathode region 82. For this reason, the surge voltage at the time of reverse recovery of the semiconductor device 200 can be suppressed.
  • FIG. 14 a is a diagram showing another example of the upper surface of the semiconductor device 200 according to the present embodiment.
  • the first cathode regions 82 are separated from each other and provided in a lattice shape when the semiconductor substrate 10 is viewed from above.
  • FIG. 14A shows an example in which ten first cathode regions 82 are provided in the X-axis direction and three in the Y-axis direction in the diode unit structure shown by the region E3.
  • FIG. 14b is an enlarged view of the region E3 in FIG. 14a.
  • the semiconductor device 200 of this example is provided with the floating region 17 inside the first cathode region 82 in a top view of the semiconductor substrate 10.
  • Ten floating regions 17 are provided in the X-axis direction and three in the Y-axis direction.
  • a second cathode region 83 is provided between two first cathode regions 82 adjacent to each other in the Y-axis direction when the semiconductor substrate 10 is viewed from above. Between the two first cathode regions 82 adjacent in the X-axis direction, a second conductivity type third cathode region 84 is provided. A third cathode region 84 is also provided between two second cathode regions 83 adjacent in the X-axis direction when the semiconductor substrate 10 is viewed from above.
  • the third cathode region 84 is a P + type as an example.
  • the doping concentration of the third cathode region 84 may be equal to the doping concentration of the second cathode region 83.
  • the second cathode region 83 and the third cathode region 84 may be connected as cathode regions having the same doping concentration.
  • FIG. 14c is a diagram showing an example of a cross-section ee-ee ′ in FIG. 14b.
  • the configuration of the ee-ee ′ section in the semiconductor device 200 of this example is the same as the configuration of the aa-aa ′ section in the semiconductor device 200 shown in FIG.
  • FIG. 14d is a diagram showing an example of the ff-ff ′ cross section in FIG. 14b.
  • the ff-ff ′ cross section is the XZ plane passing through the line ff ′′ -ff ′ ′′ in FIG. 14c.
  • the configuration of the ff-ff ′ cross section in the semiconductor device 200 of this example is shown in FIG. 13d in that a third cathode region 84 is provided in place of the second cathode region 83 in the dd-dd ′ cross section shown in FIG. 13d. Different from the configuration of the dd-dd ′ cross section.
  • the first cathode region 82 and the third cathode region 84 are alternately provided in contact with the lower surface 23 in the X-axis direction, and the first cathode region 82 is located above the first cathode region 82.
  • a floating region 17 is provided in contact with 82. For this reason, the surge voltage at the time of reverse recovery of the semiconductor device 200 can be suppressed.
  • FIG. 15 a is a diagram illustrating an example of the upper surface of the semiconductor device 200 according to the present embodiment.
  • the semiconductor device 200 shown in FIG. 15a is different from the semiconductor device 200 shown in FIG. 12a in that the floating region 17 is not provided in the semiconductor device 200 shown in FIG. 12a.
  • the diode unit structure indicated by the region E4 is arranged in the Y-axis direction.
  • FIG. 15b is an enlarged view of region E4 in FIG. 15a.
  • the semiconductor device 200 of this example is provided with a second cathode region 83 on the positive side and the negative side of the first cathode region 82 in contact with the lower surface 23, respectively.
  • the second cathode region 83 may be connected to the second cathode region 83 adjacent to the first cathode region 82 in the Y-axis direction.
  • FIG. 15c is a diagram showing an example of a gg-gg ′ section in FIG. 15b.
  • the configuration of the gg-gg ′ cross section in the semiconductor device 200 of this example is that the floating region 17 is not provided above the first cathode region 82 in the cross section aa-aa ′ shown in FIG. 12c. -Different from the configuration of the cross section aa '.
  • FIG. 15d is a diagram showing an example of a hh-hh ′ cross section in FIG. 15b.
  • the hh-hh ′ cross section is an XZ plane passing through the line hh ′′ -hh ′ ′′ in FIG. 15C.
  • the configuration of the hh-hh ′ cross section in the semiconductor device 200 of the present example is that the floating region 17 is not provided and the collector regions 22 are not provided at both ends in the X-axis direction in the semiconductor device 100 shown in FIG. Except that the cathode region 83 is provided, the configuration is the same as that of the bb ′ cross section in the semiconductor device 100 shown in FIG. 2e.
  • the semiconductor device 200 of this example has a first cathode region 82 and a second cathode region 83 in contact with the lower surface 23.
  • the second cathode regions 83 are provided at both ends in the X axis direction.
  • the first cathode region 82 is provided between the second cathode regions 83 in the X-axis direction.
  • the second cathode region 83 is different in conductivity type or doping concentration from the first cathode region 82. For this reason, the surge voltage at the time of reverse recovery of the semiconductor device 200 can be suppressed.
  • FIG. 16 a is a diagram showing another example of the upper surface of the semiconductor device 200 according to the present embodiment.
  • the semiconductor device 200 of this example is different from the semiconductor device 200 shown in FIG. 13A in that the floating region 17 is not provided in the semiconductor device 200 shown in FIG. 13A.
  • the unit structures of the diode indicated by the region E5 are arranged in the Y-axis direction.
  • FIG. 16b is an enlarged view of region E5 in FIG. 16a.
  • the first cathode region 82 is continuously provided from the end region on the positive side in the Y-axis direction of the unit structure of the diode to the end region on the negative side.
  • the first cathode regions 82 and the second cathode regions 83 are alternately provided in the X-axis direction.
  • FIG. 16c is a diagram showing an example of a section ii-ii ′ in FIG. 16b.
  • the configuration of the semiconductor device 200 of this example in the section ii-ii ′ is that the floating region 17 is not provided above the first cathode region 82 in the section cc-cc ′ shown in FIG. 13c. -Different from the configuration of the cc 'cross section.
  • FIG. 16d is a diagram showing an example of a jj-jj ′ cross section in FIG. 16b.
  • the jj-jj ′ cross section is the XZ plane passing through the jj ′′ -jj ′ ′′ line in FIG. 16c.
  • the first cathode regions 82 and the second cathode regions 83 are alternately provided in contact with the lower surface 23 in the X-axis direction. For this reason, the surge voltage at the time of reverse recovery of the semiconductor device 200 can be suppressed.
  • FIG. 17a is a diagram showing another example of the upper surface of the semiconductor device 200 according to the present embodiment.
  • the semiconductor device 200 of this example is different from the semiconductor device 200 shown in FIG. 14A in that the floating region 17 is not provided in the semiconductor device 200 shown in FIG. 14A.
  • the diode unit structures indicated by the region E6 are arranged in the Y-axis direction.
  • FIG. 17b is an enlarged view of region E6 in FIG. 17a.
  • the first cathode regions 82 are separated from each other and provided in a grid pattern when the semiconductor substrate 10 is viewed from above.
  • FIG. 17c is a diagram showing an example of a kk-kk ′ cross section in FIG. 17b.
  • the configuration of the kk-kk ′ section in the semiconductor device 200 of this example is the same as the configuration of the gg-gg ′ section in the semiconductor device 200 shown in FIG. 15c.
  • FIG. 17d is a diagram showing an example of the mm-mm ′ cross section in FIG. 17b.
  • the mm-mm ′ cross section is the XZ plane that passes through the mm ′′ -mm ′ ′′ line in FIG. 17c.
  • the configuration of the mm-mm ′ cross section of the semiconductor device 200 of this example is that a third cathode region 84 is provided in place of the second cathode region 83 in the jj-jj ′ cross section of the semiconductor device 200 shown in FIG. It differs from the configuration of the jj-jj ′ cross section shown in FIG.
  • the first cathode region 82 and the third cathode region 84 are alternately provided in contact with the lower surface 23 in the X-axis direction. For this reason, the surge voltage at the time of reverse recovery of the semiconductor device 200 can be suppressed.
  • DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Well region, 12 ... Emitter region, 14 ... Base region, 15 ... Contact region, 17 ... Floating region, 18 ... Drift region, 20 ... Buffer region, 21 ... Upper surface, 22 ... Collector region, 23 ... Lower surface, 24 ... Collector electrode, 29 ... Linear part, 30 ... Dummy trench part, 31 ... Tip part, 32 ... dummy insulating film, 34 ... dummy conductive part, 38 ... interlayer insulating film, 39 ... straight line part, 40 ... gate trench part, 41 ... tip part, 48 ... gate runner, 49 ... contact hole, 50 ... gate metal layer, 52 ...
  • emitter electrode 53 ..., Kelvin pad, 54 ... contact hole, 55 ... gate pad 56 ... Tact hole, 58 ... current sense pad, 59 ... current sense part, 60 ... mesa part, 70 ... transistor part, 72 ... active part, 74 ... outer peripheral area, 76 ... -Outer peripheral edge, 80 ... Diode part, 81 ... Cathode region, 82 ... First cathode region, 83 ... Second cathode region, 84 ... Third cathode region, 90 ... Temperature Sense unit, 92 ... temperature sense wiring, 94 ... temperature measuring pad, 96 ... detection unit, 100 ... semiconductor device, 200 ... semiconductor device

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Abstract

The present invention comprises a semiconductor substrate, a transistor portion provided to the semiconductor substrate, and a diode portion that is provided to the semiconductor substrate and is arranged with the transistor portion along a pre-established arrangement direction. The diode portion has: a first-conductivity-type drift region provided to the semiconductor substrate; a second-conductivity-type base region, which is in contact with the upper surface of the semiconductor substrate and which is provided above the drift region; a plurality of first-conductivity-type first cathode regions and second cathode regions of a different conductivity type than the first cathode regions, the cathode regions being in contact with the lower surface of the semiconductor substrate and being provided below the drift region and set apart from each other; and a plurality of second-conductivity-type floating regions, which are provided so as to be set apart from each other in correspondence with each of the first cathode regions and which are disposed so as to at least partially overlap the first cathode regions.

Description

半導体装置Semiconductor device
　本発明は、半導体装置に関する。 The present invention relates to a semiconductor device.
　従来、絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）等の半導体装置が知られている（例えば、特許文献１参照）。
　特許文献１　国際公開ＷＯ２０１６／１２９０４１ Conventionally, a semiconductor device such as an insulated gate bipolar transistor (IGBT) is known (see, for example, Patent Document 1).
Patent Document 1 International Publication WO2016 / 129041
解決しようとする課題Challenges to be solved
　半導体装置においては、逆回復時のサージ電圧を抑制することが好ましい。 In a semiconductor device, it is preferable to suppress a surge voltage during reverse recovery.
一般的開示General disclosure
　本発明の第１の態様においては、半導体装置を提供する。半導体装置は、半導体基板と、半導体基板に設けられたトランジスタ部と、半導体基板に設けられ、予め定められた配列方向に沿ってトランジスタ部と配列されたダイオード部と、を備える。ダイオード部は、半導体基板に設けられた第１導電型のドリフト領域と、半導体基板の上面に接し、ドリフト領域よりも上方に設けられた第２導電型のベース領域と、半導体基板の下面に接し、ドリフト領域よりも下方に設けられた、互いに分離した複数の第１導電型の第１カソード領域および第１カソード領域とは導電型が異なる第２カソード領域と、第１カソード領域毎に互いに分離して設けられ、前記第１カソード領域と少なくとも部分的に重なって配置された複数の第２導電型のフローティング領域と、を有する。 In a first aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a transistor portion provided on the semiconductor substrate, and a diode portion provided on the semiconductor substrate and arranged with the transistor portion along a predetermined arrangement direction. The diode portion is in contact with a first conductivity type drift region provided on the semiconductor substrate, a second conductivity type base region provided above the drift region, and above the drift region, and a lower surface of the semiconductor substrate. A plurality of first cathode regions of a first conductivity type provided below the drift region and a second cathode region having a conductivity type different from that of the first cathode region and separated from each other for each first cathode region. And a plurality of second conductivity type floating regions arranged at least partially overlapping the first cathode region.
　第１カソード領域は、半導体基板の上面視で、フローティング領域よりも配列方向に張り出していてよい。第１カソード領域および第２カソード領域は、半導体基板の上面視で、配列方向に直交する延伸方向に交互に配置されてよい。フローティング領域は、半導体基板の上面視で、第１カソード領域および第２カソード領域の両方と重なって、延伸方向に複数設けられてよい。 The first cathode region may protrude in the arrangement direction from the floating region in a top view of the semiconductor substrate. The first cathode region and the second cathode region may be alternately arranged in the extending direction orthogonal to the arrangement direction in a top view of the semiconductor substrate. A plurality of floating regions may be provided in the extending direction so as to overlap both the first cathode region and the second cathode region in a top view of the semiconductor substrate.
　フローティング領域は、半導体基板の上面視で、第１カソード領域よりも延伸方向に張り出していてよい。第１カソード領域は、フローティング領域よりも配列方向に直交する延伸方向に張り出していてよい。 The floating region may protrude in the extending direction from the first cathode region in a top view of the semiconductor substrate. The first cathode region may protrude in the extending direction perpendicular to the arrangement direction than the floating region.
　第１カソード領域および第２カソード領域は、半導体基板の上面視で、配列方向に交互に配置されてよい。フローティング領域は、半導体基板の上面視で、第１カソード領域および第２カソード領域の両方と重なって、配列方向に複数設けられてよい。フローティング領域は、半導体基板の上面視で、第１カソード領域よりも配列方向に張り出していてよい。 The first cathode region and the second cathode region may be alternately arranged in the arrangement direction in a top view of the semiconductor substrate. A plurality of floating regions may be provided in the arrangement direction so as to overlap both the first cathode region and the second cathode region in a top view of the semiconductor substrate. The floating region may protrude in the arrangement direction from the first cathode region in a top view of the semiconductor substrate.
　本発明の第２の態様においては、半導体装置を提供する。半導体装置は、半導体基板と、半導体基板に設けられた第１導電型のドリフト領域と、半導体基板の上面に接し、前記ドリフト領域よりも上方に設けられた第２導電型のベース領域を備える。半導体装置は、半導体基板の下面に接し、ドリフト領域よりも下方に設けられた第１導電型の第１カソード領域と、半導体基板の下面に接し、ドリフト領域よりも下方に設けられ、第１カソード領域に挟まれて設けられた第２導電型の第２カソード領域と、半導体基板の下面に接し、ドリフト領域よりも下方に設けられ、第１カソード領域および第２カソード領域を挟むように設けられた第２導電型の第３カソード領域と、を備える。半導体装置は、半導体基板の上面視において、第１カソード領域と第２カソード領域との配列方向に沿った第３カソード領域の幅が、配列方向に沿った前記第２カソード領域の幅よりも大きい。 In a second aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a first conductivity type drift region provided on the semiconductor substrate, and a second conductivity type base region provided in contact with the upper surface of the semiconductor substrate and above the drift region. The semiconductor device is in contact with the lower surface of the semiconductor substrate and is provided below the drift region, the first conductivity type first cathode region, is in contact with the lower surface of the semiconductor substrate and is provided below the drift region, and the first cathode A second-conductivity-type second cathode region provided between the regions and a lower surface of the semiconductor substrate, provided below the drift region, and provided so as to sandwich the first and second cathode regions. And a third cathode region of the second conductivity type. In the semiconductor device, in the top view of the semiconductor substrate, the width of the third cathode region along the arrangement direction of the first cathode region and the second cathode region is larger than the width of the second cathode region along the arrangement direction. .
　半導体基板の上面視において、第３カソード領域が第１カソード領域および第２カソード領域を挟む方向に沿った第２カソード領域の幅は、配列方向に沿った第２カソード領域の幅よりも大きくてよい。半導体装置は、複数の第２カソード領域と、複数の第３カソード領域と、を備えてよい。複数の第２カソード領域と複数の第３カソード領域とは、半導体基板の上面視で接していてよい。 In the top view of the semiconductor substrate, the width of the second cathode region along the direction in which the third cathode region sandwiches the first cathode region and the second cathode region is larger than the width of the second cathode region along the arrangement direction. Good. The semiconductor device may include a plurality of second cathode regions and a plurality of third cathode regions. The plurality of second cathode regions and the plurality of third cathode regions may be in contact with each other in a top view of the semiconductor substrate.
　本発明の第３の態様においては、半導体装置を提供する。半導体装置は、半導体基板と、半導体基板に設けられた１つ以上のダイオード部と、を備える。ダイオード部は、半導体基板に設けられた第１導電型のドリフト領域と、半導体基板の上面に接し、ドリフト領域よりも上方に設けられた第２導電型のベース領域を備える。半導体装置は、半導体基板の下面に接し、ドリフト領域よりも下方に設けられた、互いに分離した複数の第１導電型の第１カソード領域および第１カソード領域とは導電型が異なる第２カソード領域と、第１カソード領域毎に互いに分離して設けられ、第１カソード領域と少なくとも部分的に重なって配置された複数の第２導電型のフローティング領域を有する。 In a third aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate and one or more diode portions provided on the semiconductor substrate. The diode portion includes a first conductivity type drift region provided on the semiconductor substrate and a second conductivity type base region provided in contact with the upper surface of the semiconductor substrate and above the drift region. The semiconductor device is in contact with the lower surface of the semiconductor substrate and is provided below the drift region and separated from each other, the first cathode region of the first conductivity type and the second cathode region having a conductivity type different from that of the first cathode region. And a plurality of second conductivity type floating regions, which are provided separately from each other for each first cathode region and are arranged at least partially overlapping the first cathode region.
　なお、上記の発明の概要は、本発明の必要な特徴の全てを列挙したものではない。また、これらの特徴群のサブコンビネーションもまた、発明となりうる。 Note that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.
本実施形態に係る半導体チップ１２０の上面の一例を示す図である。It is a figure which shows an example of the upper surface of the semiconductor chip 120 which concerns on this embodiment. 図１ａにおける領域Ｄの拡大図である。It is the enlarged view of the area | region D in FIG. 図１ａにおける領域Ａの拡大図である。It is the enlarged view of the area | region A in FIG. 図２ａにおける領域Ｂ１の拡大図である。It is the enlarged view of area | region B1 in FIG. 2a. 図２ｂにおける領域Ｃ１の拡大図である。FIG. 3 is an enlarged view of a region C1 in FIG. 2b. 図２ｂにおけるａ－ａ'断面の一例を示す図である。It is a figure which shows an example of the aa 'cross section in FIG. 2b. 図２ｂにおけるｂ－ｂ'断面の一例を示す図である。It is a figure which shows an example of the bb 'cross section in FIG. 2b. 図１ａにおける領域Ａの他の拡大図である。It is another enlarged view of the area | region A in FIG. 図３ａにおける領域Ｂ２の拡大図である。FIG. 3b is an enlarged view of region B2 in FIG. 3a. 図３ｂにおける領域Ｃ２の拡大図である。FIG. 3b is an enlarged view of a region C2 in FIG. 3b. 図３ｂにおけるｃ－ｃ'断面の一例を示す図である。It is a figure which shows an example of the cc 'cross section in FIG. 3b. 図３ｂにおけるｄ－ｄ'断面の一例を示す図である。It is a figure which shows an example of the dd 'cross section in FIG. 3b. 図１ａにおける領域Ａの他の拡大図である。It is another enlarged view of the area | region A in FIG. 図４ａにおける領域Ｂ３の拡大図である。It is the enlarged view of area | region B3 in FIG. 4a. 図４ｂにおけるｅ－ｅ'断面の一例を示す図である。It is a figure which shows an example of the ee 'cross section in FIG. 4b. 図４ｃにおけるｆ－ｆ'断面の一例を示す図である。It is a figure which shows an example of the ff 'cross section in FIG. 4c. 図１ａにおおける領域Ａの他の拡大図である。It is the other enlarged view of the area | region A in FIG. 図５ａにおける領域Ｂ４の拡大図である。It is the enlarged view of area | region B4 in FIG. 5a. 図５ｂにおける領域Ｃ４の拡大図である。It is the enlarged view of the area | region C4 in FIG. 5b. 図５ｂにおけるｇ－ｇ'断面の一例を示す図である。FIG. 5b is a diagram showing an example of a gg ′ cross section in FIG. 5b. 図５ｂにおけるｈ－ｈ'断面の一例を示す図である。It is a figure which shows an example of the hh 'cross section in FIG. 5b. 図１ａにおける領域Ａの他の拡大図である。It is another enlarged view of the area | region A in FIG. 図６ａにおける領域Ｂ５の拡大図である。FIG. 6b is an enlarged view of region B5 in FIG. 6a. 図６ｂにおける領域Ｃ５の拡大図である。FIG. 6b is an enlarged view of region C5 in FIG. 6b. 図６ｂにおけるｉ－ｉ'断面の一例を示す図である。It is a figure which shows an example of the ii 'cross section in FIG. 6b. 図６ｂにおけるｊ－ｊ'断面の一例を示す図である。It is a figure which shows an example of the j 'cross section in FIG. 6b. 図１ａにおける領域Ａの他の拡大図である。It is another enlarged view of the area | region A in FIG. 図７ａにおける領域Ｂ６の拡大図である。It is the enlarged view of area | region B6 in FIG. 7a. 図７ｂにおける領域Ｃ６の拡大図である。FIG. 7b is an enlarged view of a region C6 in FIG. 7b. 図７ｂにおけるｋ－ｋ'断面の一例を示す図である。FIG. 8 is a diagram showing an example of a kk ′ cross section in FIG. 7b. 図７ｂにおけるｍ－ｍ'断面の一例を示す図である。It is a figure which shows an example of the mm 'cross section in FIG. 7b. 図１ａにおける領域Ａの他の拡大図である。It is another enlarged view of the area | region A in FIG. 図８ａにおける領域Ｂ７の拡大図である。It is an enlarged view of area | region B7 in FIG. 8a. 図８ｂにおける領域Ｃ７の拡大図である。It is an enlarged view of the area | region C7 in FIG. 8b. 図８ｂにおけるｎ－ｎ'断面の一例を示す図である。It is a figure which shows an example of the nn 'cross section in FIG. 8b. 図８ｂにおけるｐ－ｐ'断面の一例を示す図である。It is a figure which shows an example of the pp 'cross section in FIG. 8b. 図１ａにおける領域Ａの他の拡大図である。It is another enlarged view of the area | region A in FIG. 図９ａにおける領域Ｂ８の拡大図である。It is an enlarged view of area | region B8 in FIG. 9a. 図９ｂにおける領域Ｃ８の拡大図である。FIG. 9b is an enlarged view of region C8 in FIG. 9b. 図９ｂにおけるｑ－ｑ'断面の一例を示す図であるFIG. 9B is a diagram showing an example of a qq ′ cross section in FIG. 9B. 図９ｂにおけるｒ－ｒ'断面の一例を示す図である。FIG. 9B is a diagram showing an example of an rr ′ cross section in FIG. 9B. 図１ａにおける領域Ａの他の拡大図である。It is another enlarged view of the area | region A in FIG. 図１０ａにおける領域Ｂ９の拡大図である。FIG. 10b is an enlarged view of region B9 in FIG. 10a. 図１０ｂにおけるｓ－ｓ'断面の一例を示す図である。FIG. 10b is a diagram showing an example of an ss ′ cross section in FIG. 10b. 図１０ｂにおけるｔ－ｔ'断面の一例を示す図である。FIG. 10B is a diagram showing an example of a tt ′ cross section in FIG. 10B. 図１ａにおける領域Ａの他の拡大図である。It is another enlarged view of the area | region A in FIG. 図１１ａにおける領域Ｂ１０の拡大図である。It is the enlarged view of area | region B10 in FIG. 11a. 図１１ｂにおける領域Ｃ１０の拡大図である。FIG. 12 is an enlarged view of a region C10 in FIG. 11b. 図１１ｂにおけるｕ－ｕ'断面の一例を示す図である。It is a figure which shows an example of the uu 'cross section in FIG. 11b. 図１１ｂにおけるｖ－ｖ'断面の一例を示す図である。FIG. 12 is a diagram showing an example of a vv ′ cross section in FIG. 11b. 本実施形態に係る半導体装置２００の上面の他の一例を示す図である。It is a figure which shows another example of the upper surface of the semiconductor device 200 which concerns on this embodiment. 図１２ａにおける領域Ｅ１の拡大図である。It is the enlarged view of the area | region E1 in FIG. 12a. 図１２ｂにおけるａａ－ａａ'断面の一例を示す図である。FIG. 12B is a diagram showing an example of a cross section aa-aa ′ in FIG. 12b. 図１２ｂにおけるｂｂ－ｂｂ'断面の一例を示す図である。FIG. 12B is a diagram showing an example of a bb-bb ′ cross section in FIG. 12b. 本実施形態に係る半導体装置２００の上面の他の一例を示す図である。It is a figure which shows another example of the upper surface of the semiconductor device 200 which concerns on this embodiment. 図１３ａにおける領域Ｅ２の拡大図である。It is the enlarged view of the area | region E2 in FIG. 13a. 図１３ｂにおけるｃｃ－ｃｃ'断面の一例を示す図である。It is a figure which shows an example of the cc-cc 'cross section in FIG. 13b. 図１３ｂにおけるｄｄ－ｄｄ'断面の一例を示す図である。It is a figure which shows an example of the dd-dd 'cross section in FIG. 13b. 本実施形態に係る半導体装置２００の上面の他の一例を示す図である。It is a figure which shows another example of the upper surface of the semiconductor device 200 which concerns on this embodiment. 図１４ａにおける領域Ｅ３の拡大図である。It is the enlarged view of the area | region E3 in FIG. 14a. 図１４ｂにおけるｅｅ－ｅｅ'断面の一例を示す図である。It is a figure which shows an example of the ee-ee 'cross section in FIG. 図１４ｂにおけるｆｆ－ｆｆ'断面の一例を示す図である。It is a figure which shows an example of the ff-ff 'cross section in FIG. 14b. 本実施形態に係る半導体装置２００の上面の一例を示す図である。It is a figure which shows an example of the upper surface of the semiconductor device 200 which concerns on this embodiment. 図１５ａにおける領域Ｅ４の拡大図である。It is an enlarged view of the area | region E4 in FIG. 15a. 図１５ｂにおけるｇｇ－ｇｇ'断面の一例を示す図である。It is a figure which shows an example of the gg-gg 'cross section in FIG. 15b. 図１５ｂにおけるｈｈ－ｈｈ'断面の一例を示す図である。It is a figure which shows an example of the hh-hh 'cross section in FIG. 15b. 本実施形態に係る半導体装置２００の上面の他の一例を示す図である。It is a figure which shows another example of the upper surface of the semiconductor device 200 which concerns on this embodiment. 図１６ａにおける領域Ｅ５の拡大図である。It is the enlarged view of the area | region E5 in FIG. 16a. 図１６ｂにおけるｉｉ－ｉｉ'断面の一例を示す図である。It is a figure which shows an example of the ii-ii 'cross section in FIG. 図１６ｂにおけるｊｊ－ｊｊ'断面の一例を示す図である。It is a figure which shows an example of the jj-jj 'cross section in FIG. 16b. 本実施形態に係る半導体装置２００の上面の他の一例を示す図である。It is a figure which shows another example of the upper surface of the semiconductor device 200 which concerns on this embodiment. 図１７ａにおける領域Ｅ６の拡大図である。It is the enlarged view of the area | region E6 in FIG. 17a. 図１７ｂにおけるｋｋ－ｋｋ'断面の一例を示す図である。It is a figure which shows an example of the kk-kk 'cross section in FIG. 図１７ｂにおけるｍｍ－ｍｍ'断面の一例を示す図である。It is a figure which shows an example of the mm-mm 'cross section in FIG.
　以下、発明の実施の形態を通じて本発明を説明するが、以下の実施形態は請求の範囲にかかる発明を限定するものではない。また、実施形態の中で説明されている特徴の組み合わせの全てが発明の解決手段に必須であるとは限らない。 Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.
　本明細書においては、半導体基板の深さ方向と平行な方向における一方の側を「上」、他方の側を「下」と称する。基板、層またはその他の部材の２つの主面のうち、一方の面を上面、他方の面を下面と称する。「上」、「下」の方向は重力方向、または、半導体装置の実装時における基板等への取り付け方向に限定されない。 In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as “upper” and the other side is referred to as “lower”. Of the two principal surfaces of the substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of “up” and “down” are not limited to the direction of gravity or the direction of attachment to a substrate or the like when the semiconductor device is mounted.
　本明細書では、Ｘ軸、Ｙ軸およびＺ軸の直交座標軸を用いて技術的事項を説明する場合がある。本明細書では、半導体基板の上面と平行な面をＸＹ面とし、半導体基板の深さ方向をＺ軸とする。 In this specification, technical matters may be described using the orthogonal coordinate axes of the X axis, the Y axis, and the Z axis. In this specification, a plane parallel to the upper surface of the semiconductor substrate is defined as an XY plane, and a depth direction of the semiconductor substrate is defined as a Z axis.
　各実施例においては、第１導電型をＮ型、第２導電型をＰ型とした例を示しているが、第１導電型をＰ型、第２導電型をＮ型としてもよい。この場合、各実施例における基板、層、領域等の導電型は、それぞれ逆の極性となる。 In each of the embodiments, the first conductivity type is an N type and the second conductivity type is a P type. However, the first conductivity type may be a P type and the second conductivity type may be an N type. In this case, the conductivity types of the substrates, layers, regions, etc. in the respective embodiments have opposite polarities.
　本明細書においてドーピング濃度とは、ドナーまたはアクセプタ化した不純物の濃度を指す。本明細書において、ドナーおよびアクセプタの濃度差をドーピング濃度とする場合がある。また、ドーピングされた領域におけるドーピング濃度分布がピークを有する場合、当該ピーク値を当該ドーピング領域におけるドーピング濃度としてよい。ドーピングされた領域におけるドーピング濃度がほぼ均一な場合等においては、当該ドーピング領域におけるドーピング濃度の平均値をドーピング濃度としてよい。 In this specification, the doping concentration refers to the concentration of impurities that have become donors or acceptors. In this specification, the concentration difference between the donor and the acceptor may be referred to as a doping concentration. Further, when the doping concentration distribution in the doped region has a peak, the peak value may be used as the doping concentration in the doping region. When the doping concentration in the doped region is substantially uniform, the average doping concentration in the doping region may be used as the doping concentration.
　図１ａは、本実施形態に係る半導体装置１００の上面の一例を示す図である。本例の半導体装置１００は、トランジスタ部７０およびダイオード部８０を備える半導体チップである。トランジスタ部７０は、ＩＧＢＴ等のトランジスタを含む。ダイオード部８０は、半導体基板１０の上面においてトランジスタ部７０と隣接して設けられたＦＷＤ（Ｆｒｅｅ　Ｗｈｅｅｌ　Ｄｉｏｄｅ）等のダイオードを含む。 FIG. 1 a is a diagram showing an example of the upper surface of the semiconductor device 100 according to the present embodiment. The semiconductor device 100 of this example is a semiconductor chip including a transistor unit 70 and a diode unit 80. The transistor unit 70 includes a transistor such as an IGBT. The diode unit 80 includes a diode such as an FWD (Free Wheel Diode) provided adjacent to the transistor unit 70 on the upper surface of the semiconductor substrate 10.
　半導体基板１０には、活性部７２が設けられる。活性部７２は、半導体装置１００をオン状態に制御した場合に、半導体基板１０の上面と下面との間で主電流が流れる領域である。即ち、半導体基板１０の上面から下面、または下面から上面に、半導体基板１０の内部を深さ方向に電流が流れる領域である。本明細書では、トランジスタ部７０およびダイオード部８０をそれぞれ素子部または素子領域と称する。素子部が設けられた領域を活性部７２としてよい。 The semiconductor substrate 10 is provided with an active portion 72. The active portion 72 is a region where a main current flows between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in an on state. That is, the current flows in the depth direction in the semiconductor substrate 10 from the upper surface to the lower surface or from the lower surface to the upper surface of the semiconductor substrate 10. In the present specification, the transistor unit 70 and the diode unit 80 are referred to as an element unit or an element region, respectively. The region where the element portion is provided may be the active portion 72.
　なお、半導体基板１０の上面視において、２つの素子部に挟まれた領域も活性部７２とする。図１ａの例では、素子部に挟まれてゲート金属層５０が設けられている領域も活性部７２に含めている。活性部７２は、半導体基板１０の上面視においてエミッタ電極が設けられた領域、およびエミッタ電極に挟まれた領域とすることもできる。図１ａの例では、トランジスタ部７０およびダイオード部８０の上方にエミッタ電極が設けられる。 Note that the region sandwiched between the two element portions in the top view of the semiconductor substrate 10 is also referred to as the active portion 72. In the example of FIG. 1 a, the active portion 72 includes a region sandwiched between the element portions and provided with the gate metal layer 50. The active portion 72 may be a region where the emitter electrode is provided in a top view of the semiconductor substrate 10 and a region sandwiched between the emitter electrodes. In the example of FIG. 1 a, an emitter electrode is provided above the transistor unit 70 and the diode unit 80.
　半導体基板１０の上面視において、活性部７２と半導体基板１０の外周端７６との間の領域を、外周領域７４とする。外周領域７４は、半導体基板１０の上面視において、活性部７２を囲んで設けられる。外周領域７４には、半導体装置１００と外部の装置とをワイヤ等で接続するための１つ以上の金属のパッドが配置されてよい。半導体装置１００は、活性部７２を囲むエッジ終端構造部を外周領域７４に有してよい。エッジ終端構造部は、半導体基板１０の上面側の電界集中を緩和する。エッジ終端構造部は、例えばガードリング、フィールドプレート、リサーフおよびこれらを組み合わせた構造を有してよい。 In the top view of the semiconductor substrate 10, a region between the active portion 72 and the outer peripheral edge 76 of the semiconductor substrate 10 is defined as an outer peripheral region 74. The outer peripheral region 74 is provided so as to surround the active portion 72 when the semiconductor substrate 10 is viewed from above. In the outer peripheral region 74, one or more metal pads for connecting the semiconductor device 100 and an external device with a wire or the like may be arranged. The semiconductor device 100 may have an edge termination structure portion surrounding the active portion 72 in the outer peripheral region 74. The edge termination structure part alleviates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion may have, for example, a guard ring, a field plate, a RESURF, and a combination of these.
　活性部７２には、トランジスタ部７０およびダイオード部８０が複数設けられてよい。トランジスタ部７０およびダイオード部８０は、ＸＹ平面内において交互に周期的に配列されてよい。図１ａは、トランジスタ部７０がＸ軸方向に３つ、Ｙ軸方向に７つ設けられ、ダイオード部８０がＸ軸方向に３つ、Ｙ軸方向に６つ設けられる一例を示している。Ｘ軸方向において対向するトランジスタ部７０の間には、ゲート金属層５０が設けられてよい。 The active unit 72 may be provided with a plurality of transistor units 70 and diode units 80. The transistor unit 70 and the diode unit 80 may be alternately and periodically arranged in the XY plane. FIG. 1a shows an example in which three transistor portions 70 are provided in the X axis direction and seven in the Y axis direction, and three diode portions 80 are provided in the X axis direction and six in the Y axis direction. A gate metal layer 50 may be provided between the transistor portions 70 facing each other in the X-axis direction.
　それぞれのダイオード部８０には、半導体基板１０の下面に第１導電型のカソード領域８１が設けられている。カソード領域８１は、図１ａに示すように、外周領域７４と接しない範囲に設けられてよい。 Each diode portion 80 is provided with a first conductivity type cathode region 81 on the lower surface of the semiconductor substrate 10. The cathode region 81 may be provided in a range not in contact with the outer peripheral region 74 as shown in FIG.
　ゲート金属層５０は、半導体基板１０の上面視で、活性部７２を囲うように設けられてよい。ゲート金属層５０は、外周領域７４に設けられるゲートパッド５５と電気的に接続される。ゲート金属層５０は、半導体基板１０の外周端７６に沿って設けられてよい。ゲートパッド５５は、Ｘ軸方向において、半導体基板１０の外周端７６と、活性部７２との間に配置されてよい。ゲートパッド５５と外周端７６との間には、ゲート金属層５０がＹ軸方向に延伸して設けられてよい。 The gate metal layer 50 may be provided so as to surround the active portion 72 when the semiconductor substrate 10 is viewed from above. Gate metal layer 50 is electrically connected to gate pad 55 provided in outer peripheral region 74. The gate metal layer 50 may be provided along the outer peripheral edge 76 of the semiconductor substrate 10. The gate pad 55 may be disposed between the outer peripheral end 76 of the semiconductor substrate 10 and the active portion 72 in the X-axis direction. A gate metal layer 50 may be provided extending in the Y-axis direction between the gate pad 55 and the outer peripheral end 76.
　温度センス部９０は、活性部７２の上方に設けられる。温度センス部９０は、半導体基板１０の上面視で、活性部７２の中央に設けられてよい。温度センス部９０は、活性部７２の温度を検知する。温度センス部９０は、単結晶または多結晶のシリコンで形成されるｐｎ接合型温度センスダイオードであってよい。 The temperature sensing unit 90 is provided above the active unit 72. The temperature sensing part 90 may be provided in the center of the active part 72 when the semiconductor substrate 10 is viewed from above. The temperature sensing unit 90 detects the temperature of the active unit 72. The temperature sensing unit 90 may be a pn junction type temperature sensing diode formed of single crystal or polycrystalline silicon.
　温度センス配線９２は、半導体基板１０の上面視で、活性部７２の上方に設けられる。温度センス配線９２は、温度センス部９０と接続される。温度センス配線９２は、外周領域７４まで、予め定められた方向（本例においてはＸ軸方向）に延伸し、外周領域７４に設けられた温度測定用パッド９４と接続される。温度測定用パッド９４から流れる電流は、温度センス配線９２および温度センス部９０に流れる。温度センス部９０がｐｎ接合型温度センスダイオードである場合、温度センス配線９２および温度測定用パッド９４は少なくとも２つ設けられ、その一方はｐｎ接合型温度センスダイオードのアノード端子と電気的に接続され、他方はｐｎ接合型温度センスダイオードのカソードと電気的に接続される。検知部９６は、温度センス部９０の予備として設けられる。 The temperature sense wiring 92 is provided above the active portion 72 when the semiconductor substrate 10 is viewed from above. The temperature sense wiring 92 is connected to the temperature sense unit 90. The temperature sensing wiring 92 extends in a predetermined direction (X-axis direction in this example) up to the outer peripheral region 74 and is connected to a temperature measurement pad 94 provided in the outer peripheral region 74. The current flowing from the temperature measurement pad 94 flows to the temperature sense wiring 92 and the temperature sense unit 90. When the temperature sensing unit 90 is a pn junction type temperature sensing diode, at least two temperature sensing wirings 92 and temperature measuring pads 94 are provided, one of which is electrically connected to the anode terminal of the pn junction type temperature sensing diode. The other is electrically connected to the cathode of the pn junction type temperature sensing diode. The detection unit 96 is provided as a spare for the temperature sensing unit 90.
　外周領域７４には、電流センス部５９および電流センスパッド５８、並びにケルビンパッド５３が設けられる。電流センス部５９は、ゲートパッド５５に流れる電流を検知する。電流センスパッド５８は、電流センス部５９に流れる電流を測定するためのパッドである。ケルビンパッド５３は、半導体基板１０の上面視で、活性部７２の上方に設けられるエミッタ電極と接続される。 In the outer peripheral region 74, a current sensing portion 59, a current sensing pad 58, and a Kelvin pad 53 are provided. The current sense unit 59 detects a current flowing through the gate pad 55. The current sense pad 58 is a pad for measuring the current flowing through the current sense unit 59. The Kelvin pad 53 is connected to an emitter electrode provided above the active portion 72 in a top view of the semiconductor substrate 10.
　図１ｂは、図１ａにおける領域Ｄの拡大図である。本例の半導体装置１００は、半導体基板１０の内部に設けられ、且つ、半導体基板１０の上面に露出する、ゲートトレンチ部４０、ダミートレンチ部３０、Ｐ＋型のウェル領域１１、Ｎ＋型のエミッタ領域１２、Ｐ－型のベース領域１４およびＰ＋型のコンタクト領域１５を備える。本明細書では、ゲートトレンチ部４０またはダミートレンチ部３０を単にトレンチ部と称する場合がある。また、本例の半導体装置１００は、半導体基板１０の上面の上方に設けられたエミッタ電極５２およびゲート金属層５０を備える。エミッタ電極５２およびゲート金属層５０は互いに分離して設けられる。 FIG. 1b is an enlarged view of region D in FIG. 1a. The semiconductor device 100 of this example is provided inside the semiconductor substrate 10 and exposed on the upper surface of the semiconductor substrate 10. The gate trench portion 40, the dummy trench portion 30, the P + type well region 11, and the N + type emitter region. 12 includes a P− type base region 14 and a P + type contact region 15. In the present specification, the gate trench portion 40 or the dummy trench portion 30 may be simply referred to as a trench portion. In addition, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.
　エミッタ電極５２およびゲート金属層５０と、半導体基板１０の上面との間には層間絶縁膜が設けられるが、図１ｂでは省略している。本例の層間絶縁膜には、コンタクトホール５６、コンタクトホール４９およびコンタクトホール５４が、当該層間絶縁膜を貫通して設けられる。ゲート金属層５０は、コンタクトホール４９を通って、ゲートランナー４８と接触する。 Although an interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 50 and the upper surface of the semiconductor substrate 10, it is omitted in FIG. In the interlayer insulating film of this example, a contact hole 56, a contact hole 49, and a contact hole 54 are provided through the interlayer insulating film. Gate metal layer 50 contacts gate runner 48 through contact hole 49.
　エミッタ電極５２は、コンタクトホール５４を通って、半導体基板１０の上面におけるエミッタ領域１２、コンタクト領域１５およびベース領域１４と接触する。また、エミッタ電極５２は、コンタクトホール５６を通って、ダミートレンチ部３０内のダミー導電部と接続される。エミッタ電極５２とダミー導電部との間には、不純物がドープされたポリシリコン等の、導電性を有する材料で形成された接続部２５が設けられてよい。接続部２５と半導体基板１０の上面との間には、酸化膜等の絶縁膜が設けられる。 The emitter electrode 52 is in contact with the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through the contact hole 54. The emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through the contact hole 56. Between the emitter electrode 52 and the dummy conductive portion, a connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided. An insulating film such as an oxide film is provided between the connection portion 25 and the upper surface of the semiconductor substrate 10.
　ゲートランナー４８は、不純物がドープされたポリシリコン等で形成される。ゲートランナー４８は、半導体基板１０の上面において、ゲートトレンチ部４０内のゲート導電部と接続される。ゲートランナー４８は、ダミートレンチ部３０内のダミー導電部とは接続されない。本例のゲートランナー４８は、コンタクトホール４９の下方から、ゲートトレンチ部４０の先端部４１まで形成される。 The gate runner 48 is formed of polysilicon doped with impurities. The gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate 10. Gate runner 48 is not connected to the dummy conductive portion in dummy trench portion 30. The gate runner 48 of this example is formed from below the contact hole 49 to the tip 41 of the gate trench 40.
　ゲートランナー４８と半導体基板１０の上面との間には、酸化膜等の絶縁膜が設けられる。ゲートトレンチ部４０の先端部４１において、ゲート導電部は、半導体基板１０の上面に露出している。ゲート導電部の上方における絶縁膜には、ゲート導電部およびゲートランナー４８を接続するコンタクトホールが設けられている。なお、図１ｂでは平面視で、エミッタ電極５２とゲートランナー４８が重なっている箇所があるが、エミッタ電極５２とゲートランナー４８は図示しない絶縁膜を挟んで互いに電気的に絶縁している。 An insulating film such as an oxide film is provided between the gate runner 48 and the upper surface of the semiconductor substrate 10. At the distal end portion 41 of the gate trench portion 40, the gate conductive portion is exposed on the upper surface of the semiconductor substrate 10. A contact hole for connecting the gate conductive portion and the gate runner 48 is provided in the insulating film above the gate conductive portion. In FIG. 1b, there is a portion where the emitter electrode 52 and the gate runner 48 overlap in plan view, but the emitter electrode 52 and the gate runner 48 are electrically insulated from each other with an insulating film (not shown) interposed therebetween.
　エミッタ電極５２およびゲート金属層５０は、金属を含む材料で形成される。例えば、各電極の少なくとも一部の領域はアルミニウムまたはアルミニウム‐シリコン合金で形成される。各電極は、アルミニウム等で形成された領域の下層にチタンやチタン化合物等で形成されたバリアメタルを有してよく、コンタクトホール内においてタングステン等で形成されたプラグを有してもよい。 The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. For example, at least a partial region of each electrode is formed of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium, a titanium compound, or the like below a region formed of aluminum or the like, and may have a plug formed of tungsten or the like in the contact hole.
　１つ以上のゲートトレンチ部４０および１つ以上のダミートレンチ部３０は、半導体基板１０の上面において、所定の配列方向（本例ではＹ軸方向）に沿って所定の間隔で配列される。本例のトランジスタ部７０においては、配列方向に沿って１つ以上のゲートトレンチ部４０と、１つ以上のダミートレンチ部３０とが交互に設けられている。 The one or more gate trench portions 40 and the one or more dummy trench portions 30 are arranged on the upper surface of the semiconductor substrate 10 at predetermined intervals along a predetermined arrangement direction (Y-axis direction in this example). In the transistor portion 70 of this example, one or more gate trench portions 40 and one or more dummy trench portions 30 are alternately provided along the arrangement direction.
　本例のゲートトレンチ部４０は、配列方向と垂直な長手方向（本例ではＸ軸方向）に沿って直線状に延伸する２つの直線部３９と、２つの直線部３９を接続する先端部４１とを有してよい。先端部４１の少なくとも一部は、半導体基板１０の上面において曲線状に設けられることが好ましい。ゲートトレンチ部４０の２つの直線部３９において、長手方向に沿った直線形状の端である端部同士を先端部４１が接続することで、直線部３９の端部における電界集中を緩和することができる。本明細書では、ゲートトレンチ部４０のそれぞれの直線部３９を、一つのゲートトレンチ部４０として扱う。 The gate trench portion 40 in this example includes two straight portions 39 extending linearly along a longitudinal direction (X-axis direction in this example) perpendicular to the arrangement direction, and a tip portion 41 connecting the two straight portions 39. May be included. It is preferable that at least a part of the tip portion 41 is provided in a curved shape on the upper surface of the semiconductor substrate 10. In the two straight portions 39 of the gate trench portion 40, the end portions 41, which are straight ends along the longitudinal direction, are connected to each other by the tip portion 41, so that electric field concentration at the end portions of the straight portions 39 can be reduced. it can. In the present specification, each straight line portion 39 of the gate trench portion 40 is treated as one gate trench portion 40.
　少なくとも一つのダミートレンチ部３０は、ゲートトレンチ部４０のそれぞれの直線部３９の間に設けられる。これらのダミートレンチ部３０は、ゲートトレンチ部４０と同様に、直線部２９および先端部３１を有してよい。他の例では、ダミートレンチ部３０は直線部２９を有し、先端部３１を有さなくてもよい。図１ｂに示した例では、トランジスタ部７０において、ゲートトレンチ部４０の２つの直線部３９の間に、ダミートレンチ部３０の２つの直線部２９が配置されている。 The at least one dummy trench portion 30 is provided between the respective straight portions 39 of the gate trench portion 40. Similar to the gate trench portion 40, these dummy trench portions 30 may have a straight portion 29 and a tip portion 31. In another example, the dummy trench part 30 has the straight part 29 and does not have to have the tip part 31. In the example illustrated in FIG. 1B, in the transistor portion 70, the two straight portions 29 of the dummy trench portion 30 are disposed between the two straight portions 39 of the gate trench portion 40.
　ダイオード部８０においては、複数のダミートレンチ部３０が、半導体基板１０の上面においてＸ軸方向に沿って配置されている。ダイオード部８０におけるダミートレンチ部３０のＸＹ面における形状は、トランジスタ部７０に設けられたダミートレンチ部３０と同様であってよい。 In the diode portion 80, a plurality of dummy trench portions 30 are arranged along the X-axis direction on the upper surface of the semiconductor substrate 10. The shape of the dummy trench portion 30 in the diode portion 80 on the XY plane may be the same as that of the dummy trench portion 30 provided in the transistor portion 70.
　ダミートレンチ部３０の先端部３１および直線部２９は、ゲートトレンチ部４０の先端部４１および直線部３９と同様の形状を有してよい。ダイオード部８０に設けられたダミートレンチ部３０と、トランジスタ部７０に設けられた直線形状のダミートレンチ部３０は、Ｙ軸方向における長さが同一であってよい。 The front end portion 31 and the straight portion 29 of the dummy trench portion 30 may have the same shape as the front end portion 41 and the straight portion 39 of the gate trench portion 40. The dummy trench part 30 provided in the diode part 80 and the linear dummy trench part 30 provided in the transistor part 70 may have the same length in the Y-axis direction.
　エミッタ電極５２は、ゲートトレンチ部４０、ダミートレンチ部３０、ウェル領域１１、エミッタ領域１２、ベース領域１４およびコンタクト領域１５の上方に設けられる。ウェル領域１１と、コンタクトホール５４の長手方向の端のうちゲート金属層５０が設けられる側の端とは、ＸＹ面内において離れて設けられる。 The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 and the end of the contact hole 54 in the longitudinal direction on the side where the gate metal layer 50 is provided are separated from each other in the XY plane.
　ウェル領域１１の拡散深さは、ゲートトレンチ部４０およびダミートレンチ部３０の深さよりも深くてよい。ゲートトレンチ部４０およびダミートレンチ部３０の、ゲート金属層５０側の一部の領域は、ウェル領域１１に設けられる。ゲートトレンチ部４０の先端部４１のＺ軸方向における底部、ダミートレンチ部３０の先端部３１のＺ軸方向における底部は、ウェル領域１１に覆われていてよい。 The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. Partial regions on the gate metal layer 50 side of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11. The bottom part in the Z-axis direction of the tip part 41 of the gate trench part 40 and the bottom part in the Z-axis direction of the tip part 31 of the dummy trench part 30 may be covered with the well region 11.
　トランジスタ部７０およびダイオード部８０のそれぞれには、各トレンチ部に挟まれたメサ部６０が１つ以上設けられる。メサ部６０とは、トレンチ部に挟まれた半導体基板１０の領域において、トレンチ部の最も深い底部よりも上面側の領域である。 Each of the transistor portion 70 and the diode portion 80 is provided with one or more mesa portions 60 sandwiched between the trench portions. The mesa portion 60 is a region on the upper surface side of the deepest bottom portion of the trench portion in the region of the semiconductor substrate 10 sandwiched between the trench portions.
　各トレンチ部に挟まれたメサ部６０には、ベース領域１４が設けられる。ベース領域１４は、ウェル領域１１よりもドーピング濃度の低い第２導電型（Ｐ－型）である。 The base region 14 is provided in the mesa portion 60 sandwiched between the trench portions. The base region 14 is a second conductivity type (P− type) having a doping concentration lower than that of the well region 11.
　メサ部６０のベース領域１４の上面には、ベース領域１４よりもドーピング濃度の高い第２導電型のコンタクト領域１５が設けられる。本例のコンタクト領域１５はＰ＋型である。半導体基板１０の上面において、ウェル領域１１は、コンタクト領域１５のうちＹ軸方向において最も端に配置されたコンタクト領域１５から、ゲート金属層５０の方向に離れて設けられてよい。半導体基板１０の上面において、ウェル領域１１とコンタクト領域１５との間には、ベース領域１４が露出している。 A contact region 15 of the second conductivity type having a higher doping concentration than the base region 14 is provided on the upper surface of the base region 14 of the mesa portion 60. The contact region 15 in this example is P + type. On the upper surface of the semiconductor substrate 10, the well region 11 may be provided away from the contact region 15 disposed at the end of the contact region 15 in the Y-axis direction in the direction of the gate metal layer 50. On the upper surface of the semiconductor substrate 10, the base region 14 is exposed between the well region 11 and the contact region 15.
　トランジスタ部７０においては、半導体基板１０の内部に設けられたドリフト領域よりもドーピング濃度が高い第１導電型のエミッタ領域１２が、メサ部６０－１の上面に選択的に設けられる。本例のエミッタ領域１２はＮ＋型である。エミッタ領域１２の半導体基板１０の深さ方向（－Ｚ軸方向）に隣接するベース領域１４のうち、ゲートトレンチ部４０に接する部分が、チャネル部として機能する。ゲートトレンチ部４０にオン電圧が印加されると、Ｚ軸方向においてエミッタ領域１２とドリフト領域との間に設けられたベース領域１４において、ゲートトレンチ部４０に隣接する部分に電子の反転層であるチャネルが形成される。ベース領域１４にチャネルが形成されることで、エミッタ領域１２とドリフト領域との間にキャリアが流れる。 In the transistor unit 70, the first conductivity type emitter region 12 having a higher doping concentration than the drift region provided in the semiconductor substrate 10 is selectively provided on the upper surface of the mesa unit 60-1. The emitter region 12 of this example is N + type. Of the base region 14 adjacent to the emitter region 12 in the depth direction (−Z axis direction) of the semiconductor substrate 10, a portion in contact with the gate trench portion 40 functions as a channel portion. When a turn-on voltage is applied to the gate trench portion 40, an electron inversion layer is formed in a portion adjacent to the gate trench portion 40 in the base region 14 provided between the emitter region 12 and the drift region in the Z-axis direction. A channel is formed. By forming a channel in the base region 14, carriers flow between the emitter region 12 and the drift region.
　本例では、各メサ部６０のＹ軸方向における両端部には、ベース領域１４－ｅが配置されている。本例では、それぞれのメサ部６０の上面において、ベース領域１４－ｅに対してメサ部６０の中央側で隣接する領域は、コンタクト領域１５である。また、ベース領域１４－ｅに対して、コンタクト領域１５とは逆側で接する領域はウェル領域１１である。 In this example, base regions 14-e are disposed at both ends of each mesa 60 in the Y-axis direction. In this example, on the upper surface of each mesa portion 60, the region adjacent to the base region 14-e on the center side of the mesa portion 60 is the contact region 15. Further, the region that is in contact with the base region 14-e on the opposite side to the contact region 15 is the well region 11.
　本例のトランジスタ部７０のメサ部６０－１においてＹ軸方向両端のベース領域１４－ｅに挟まれる領域には、コンタクト領域１５およびエミッタ領域１２がＹ軸方向に沿って交互に配置されている。コンタクト領域１５およびエミッタ領域１２のそれぞれは、隣接する一方のトレンチ部から、他方のトレンチ部まで設けられている。 In the mesa portion 60-1 of the transistor portion 70 of this example, the contact regions 15 and the emitter regions 12 are alternately arranged along the Y-axis direction in the region sandwiched between the base regions 14-e at both ends in the Y-axis direction. . Each of the contact region 15 and the emitter region 12 is provided from one adjacent trench portion to the other trench portion.
　トランジスタ部７０のメサ部６０のうち、ダイオード部８０との境界に設けられた１つ以上のメサ部６０－２には、メサ部６０－１のコンタクト領域１５よりも面積の大きいコンタクト領域１５が設けられている。メサ部６０－２にはエミッタ領域１２が設けられていなくてよい。本例のメサ部６０－２においては、ベース領域１４－ｅに挟まれた領域全体に、コンタクト領域１５が設けられている。 Among the mesa portions 60 of the transistor portion 70, one or more mesa portions 60-2 provided at the boundary with the diode portion 80 have a contact region 15 having a larger area than the contact region 15 of the mesa portion 60-1. Is provided. The emitter region 12 may not be provided in the mesa unit 60-2. In the mesa portion 60-2 of this example, the contact region 15 is provided in the entire region sandwiched between the base regions 14-e.
　本例のトランジスタ部７０の各メサ部６０－１においてコンタクトホール５４は、コンタクト領域１５およびエミッタ領域１２の各領域の上方に設けられる。メサ部６０－２におけるコンタクトホール５４は、コンタクト領域１５の上方に設けられる。各メサ部６０においてコンタクトホール５４は、ベース領域１４－ｅおよびウェル領域１１に対応する領域には設けられていない。トランジスタ部７０の各メサ部６０におけるコンタクトホール５４は、Ｙ軸方向において同一の長さを有してよい。 In each mesa portion 60-1 of the transistor portion 70 of this example, the contact hole 54 is provided above each of the contact region 15 and the emitter region 12. The contact hole 54 in the mesa portion 60-2 is provided above the contact region 15. In each mesa portion 60, the contact hole 54 is not provided in a region corresponding to the base region 14-e and the well region 11. The contact hole 54 in each mesa unit 60 of the transistor unit 70 may have the same length in the Y-axis direction.
　ダイオード部８０において、半導体基板１０の下面と接する領域には、カソード領域８１が設けられる。後述するように、カソード領域８１は、Ｎ＋型の第１カソード領域、Ｐ＋型の第２カソード領域およびＰ＋の第３カソード領域を含んでよい。図１ｂにおいては、カソード領域８１が設けられる領域を破線で示している。半導体基板１０の下面と接する領域においてカソード領域８１が設けられていない領域には、Ｐ＋型のコレクタ領域が設けられてよい。 In the diode portion 80, a cathode region 81 is provided in a region in contact with the lower surface of the semiconductor substrate 10. As will be described later, the cathode region 81 may include an N + type first cathode region, a P + type second cathode region, and a P + third cathode region. In FIG. 1b, the area | region where the cathode area | region 81 is provided is shown with the broken line. A P + type collector region may be provided in a region where the cathode region 81 is not provided in a region in contact with the lower surface of the semiconductor substrate 10.
　トランジスタ部７０は、Ｚ軸方向においてコレクタ領域と重なる領域のうち、コンタクト領域１５およびエミッタ領域１２が設けられたメサ部６０と、当該メサ部６０に隣接するトレンチ部とが設けられた領域であってよい。ただし、ダイオード部８０との境界におけるメサ部６０－２には、エミッタ領域１２に代えてコンタクト領域１５が設けられていてよい。 The transistor portion 70 is a region in which a mesa portion 60 provided with the contact region 15 and the emitter region 12 and a trench portion adjacent to the mesa portion 60 are provided in a region overlapping with the collector region in the Z-axis direction. It's okay. However, a contact region 15 may be provided in place of the emitter region 12 in the mesa unit 60-2 at the boundary with the diode unit 80.
　ダイオード部８０のメサ部６０－３の上面には、ベース領域１４が配置されている。ただし、ベース領域１４－ｅに隣接する領域には、コンタクト領域１５が設けられてもよい。コンタクト領域１５の上方で、コンタクトホール５４が終端している。なお、図１ｂの例では、ダイオード部８０が５つのメサ部６０－３とメサ部６０－３を挟む７つのダミートレンチ部３０を有しているが、ダイオード部８０におけるメサ部６０－３とダミートレンチ部３０の数は、これに限定されない。ダイオード部８０には、より多くのメサ部６０－３およびダミートレンチ部３０が設けられてよい。 The base region 14 is disposed on the upper surface of the mesa unit 60-3 of the diode unit 80. However, the contact region 15 may be provided in a region adjacent to the base region 14-e. A contact hole 54 terminates above the contact region 15. In the example of FIG. 1b, the diode unit 80 includes five mesa units 60-3 and seven dummy trench units 30 sandwiching the mesa unit 60-3. The number of dummy trench portions 30 is not limited to this. More mesa portions 60-3 and dummy trench portions 30 may be provided in the diode portion 80.
　図２ａは、図１ａにおける領域Ａの拡大図である。本例の半導体装置１００は、図２ａに示すように、ダイオード部８０のＹ軸方向正側およびＹ軸方向負側の双方に、当該ダイオード部８０と隣接して、トランジスタ部７０が設けられる。 FIG. 2a is an enlarged view of region A in FIG. 1a. In the semiconductor device 100 of this example, as illustrated in FIG. 2A, the transistor unit 70 is provided adjacent to the diode unit 80 on both the Y axis direction positive side and the Y axis direction negative side of the diode unit 80.
　幅ＷＩは、トランジスタ部７０のＹ軸方向の幅である。幅ＷＦはダイオード部８０のＹ軸方向の幅である。幅Ｗｈは、トランジスタ部７０およびダイオード部８０に対してＸ軸方向正側に配置されたウェル領域１１の端部から、トランジスタ部７０およびダイオード部８０に対してＸ軸方向負側に配置されたウェル領域１１の端部までの部分の幅である。当該部分には、ベース領域１４が半導体基板１０の上面側に設けられ、且つウェル領域１１が設けられていない。 The width WI is the width of the transistor unit 70 in the Y-axis direction. The width WF is the width of the diode portion 80 in the Y-axis direction. The width Wh is arranged on the X axis direction negative side with respect to the transistor unit 70 and the diode part 80 from the end of the well region 11 arranged on the X axis direction positive side with respect to the transistor part 70 and the diode part 80. This is the width of the portion up to the end of the well region 11. In this portion, the base region 14 is provided on the upper surface side of the semiconductor substrate 10 and the well region 11 is not provided.
　幅ＷＩは、幅ＷＦより大きくてよい。幅ＷＩは、幅ＷＦの２倍以上５倍以下であってよい。幅ＷＩは、１２００μｍ以上２０００μｍ以下であってよい。幅ＷＩは、一例として１５００μｍである。幅ＷＦは、４００μｍ以上６００μｍ以下であってよい。幅ＷＦは、一例として５００μｍである。 Width WI may be larger than width WF. The width WI may be not less than 2 times and not more than 5 times the width WF. The width WI may be 1200 μm or more and 2000 μm or less. The width WI is 1500 μm as an example. The width WF may be 400 μm or more and 600 μm or less. The width WF is 500 μm as an example.
　ダイオード部８０およびトランジスタ部７０のＸ軸方向正側には、Ｐ＋型のウェル領域１１の端部Ｓが設けられる。また、ダイオード部８０およびトランジスタ部７０のＸ軸方向負側には、Ｐ＋型のウェル領域１１の端部Ｓ'が設けられる。ウェル領域１１は、トランジスタ部７０とダイオード部８０が交互に配置された領域の外側に設けられている。言い換えると、端部Ｓよりトランジスタ部７０およびダイオード部８０の内部には、ウェル領域１１は設けられていない。 The end S of the P + type well region 11 is provided on the positive side in the X-axis direction of the diode unit 80 and the transistor unit 70. Further, an end S ′ of the P + type well region 11 is provided on the negative side in the X-axis direction of the diode portion 80 and the transistor portion 70. The well region 11 is provided outside the region where the transistor portions 70 and the diode portions 80 are alternately arranged. In other words, the well region 11 is not provided in the transistor portion 70 and the diode portion 80 from the end portion S.
　Ｘ軸方向正側のウェル領域１１の端部Ｓから、Ｘ軸方向負側のウェル領域１１の端部Ｓ'までの幅Ｗｈは、幅ＷＩより大きくてよい。幅Ｗｈは、幅ＷＩの１．５倍以上３倍以下であってよい。幅Ｗｈは、３０００μｍ以上３６００μｍ以下であってよい。幅Ｗｈは、一例として３１００μｍであってよい。 The width Wh from the end S of the well region 11 on the X axis direction positive side to the end S ′ of the well region 11 on the X axis direction negative side may be larger than the width WI. The width Wh may be not less than 1.5 times and not more than 3 times the width WI. The width Wh may be not less than 3000 μm and not more than 3600 μm. The width Wh may be 3100 μm as an example.
　本例の半導体装置１００におけるダイオード部８０において、カソード領域８１は、図２ａに示す通り、第１カソード領域８２および第２カソード領域８３を含む。本例の半導体装置１００は、Ｘ軸方向に延伸する第１カソード領域８２および第２カソード領域８３が、互いに分離して複数設けられる。本例においては、第１カソード領域８２および第２カソード領域８３は、半導体基板１０の上面視でＹ軸方向に交互に配置される。 In the diode unit 80 of the semiconductor device 100 of this example, the cathode region 81 includes a first cathode region 82 and a second cathode region 83 as shown in FIG. In the semiconductor device 100 of this example, a plurality of first cathode regions 82 and second cathode regions 83 extending in the X-axis direction are provided separately from each other. In this example, the first cathode regions 82 and the second cathode regions 83 are alternately arranged in the Y-axis direction when the semiconductor substrate 10 is viewed from above.
　第１カソード領域８２は第１導電型である。本例の第１カソード領域８２は、一例としてＮ＋型である。第２カソード領域８３は、第１カソード領域８２とは導電型が異なる。本例の第２カソード領域８３は、一例としてＰ＋型である。なお、図２ａにおいては、ダイオード部８０およびトランジスタ部７０に設けられる第１カソード領域８２および第２カソード領域８３、並びにフローティング領域１７以外の構成、即ちゲートトレンチ部４０およびダミートレンチ部３０等の構成を、省略して示している。 The first cathode region 82 is the first conductivity type. The first cathode region 82 of this example is an N + type as an example. The second cathode region 83 has a conductivity type different from that of the first cathode region 82. The second cathode region 83 of this example is a P + type as an example. In FIG. 2a, configurations other than the first cathode region 82 and the second cathode region 83 and the floating region 17 provided in the diode unit 80 and the transistor unit 70, that is, configurations of the gate trench unit 40, the dummy trench unit 30, and the like. Is omitted.
　ダイオード部８０においてＹ軸方向の最も正側に設けられる第１カソード領域８２は、半導体基板１０の上面視で、当該ダイオード部８０のＹ軸方向正側で隣接するトランジスタ部７０と接してよい。ダイオード部８０においてＹ軸方向の最も負側に設けられる第１カソード領域８２は、半導体基板１０の上面視で、当該ダイオード部８０のＹ軸方向負側で隣接するトランジスタ部７０と接してよい。 The first cathode region 82 provided on the most positive side in the Y-axis direction in the diode part 80 may be in contact with the adjacent transistor part 70 on the positive side in the Y-axis direction of the diode part 80 when the semiconductor substrate 10 is viewed from above. The first cathode region 82 provided on the most negative side in the Y-axis direction in the diode unit 80 may be in contact with the adjacent transistor unit 70 on the negative side in the Y-axis direction of the diode unit 80 in a top view of the semiconductor substrate 10.
　Ｘ軸方向において、第１カソード領域８２のＸ軸方向正側の端と端部Ｓとの間には、半導体基板１０の下面と接する領域に、第２導電型のコレクタ領域２２が設けられてよい。Ｘ軸方向において、第１カソード領域８２のＸ軸方向負側の端と端部Ｓ'との間にも、半導体基板１０の下面と接する領域に、コレクタ領域２２が設けられてよい。本例のコレクタ領域２２は、一例としてＰ＋型である。 In the X-axis direction, a second conductivity type collector region 22 is provided in a region in contact with the lower surface of the semiconductor substrate 10 between the end of the first cathode region 82 on the positive side in the X-axis direction and the end S. Good. In the X-axis direction, the collector region 22 may be provided in a region in contact with the lower surface of the semiconductor substrate 10 between the end on the negative side in the X-axis direction of the first cathode region 82 and the end S ′. The collector region 22 of this example is a P + type as an example.
　第１カソード領域８２および第２カソード領域８３を含むカソード領域８１と第１カソード領域８２および第２カソード領域８３以外の構成との位置関係は、図１ｂに示した上面図における位置関係であってよい。第１カソード領域８２および第２カソード領域８３以外の構成とは、例えばコンタクトホール５４、ダミートレンチ部３０、コンタクトホール５４のＸ軸方向の端部に設けられたコンタクト領域１５である。 The positional relationship between the cathode region 81 including the first cathode region 82 and the second cathode region 83 and the configuration other than the first cathode region 82 and the second cathode region 83 is the positional relationship in the top view shown in FIG. Good. The configurations other than the first cathode region 82 and the second cathode region 83 are, for example, the contact hole 54, the dummy trench portion 30, and the contact region 15 provided at the end of the contact hole 54 in the X-axis direction.
　ダイオード部８０において、半導体基板１０の上面視における第１カソード領域８２と第２カソード領域８３との合計面積に占める第１カソード領域８２の面積の割合は、６０％以上９０％以下であってよい。当該合計面積に占める第２カソード領域８３の面積の割合は、１０％以上４０％以下であってよい。一例として、当該合計面積に占める第１カソード領域８２の面積および第２カソード領域８３の面積の割合は、それぞれ８０％および２０％である。 In the diode portion 80, the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82 and the second cathode region 83 in the top view of the semiconductor substrate 10 may be 60% or more and 90% or less. . The ratio of the area of the second cathode region 83 to the total area may be 10% or more and 40% or less. As an example, the ratio of the area of the first cathode region 82 and the area of the second cathode region 83 to the total area is 80% and 20%, respectively.
　本例の半導体装置１００は、第１カソード領域８２毎に互いに分離して設けられた複数のフローティング領域１７を有する。フローティング領域１７は第２導電型である。本例のフローティング領域１７は、一例としてＰ＋型である。 The semiconductor device 100 of this example has a plurality of floating regions 17 provided separately for each first cathode region 82. The floating region 17 is of the second conductivity type. The floating region 17 of this example is a P + type as an example.
　フローティング領域１７は、半導体基板１０の上面視で、第１カソード領域８２と少なくとも部分的に重なって配置される。図２ａは、半導体基板１０の上面視で、フローティング領域１７の全体が、第１カソード領域８２と重なって配置される一例を示している。即ち、図２ａにおいて、第１カソード領域８２は、半導体基板１０の上面視で、フローティング領域１７よりも配列方向（Ｙ軸方向）に張り出している。また、第１カソード領域８２は、半導体基板１０の上面視で、フローティング領域１７よりも配列方向に直交する延伸方向（Ｘ軸方向）に張り出している。 The floating region 17 is disposed so as to at least partially overlap the first cathode region 82 when the semiconductor substrate 10 is viewed from above. FIG. 2 a shows an example in which the entire floating region 17 is arranged so as to overlap the first cathode region 82 in a top view of the semiconductor substrate 10. That is, in FIG. 2 a, the first cathode region 82 protrudes in the arrangement direction (Y-axis direction) from the floating region 17 in a top view of the semiconductor substrate 10. Further, the first cathode region 82 protrudes in the extending direction (X-axis direction) perpendicular to the arrangement direction from the floating region 17 in a top view of the semiconductor substrate 10.
　フローティング領域１７は、半導体基板１０の上面視で、トランジスタ部７０と重ならないように配置される。フローティング領域１７は、ダイオード部８０とトランジスタ部７０との境界にも接しないように配置される。 The floating region 17 is arranged so as not to overlap the transistor portion 70 when the semiconductor substrate 10 is viewed from above. The floating region 17 is arranged so as not to contact the boundary between the diode portion 80 and the transistor portion 70.
　図２ｂは、図２ａにおける領域Ｂ１の拡大図である。図２ｂは、図２ａにおけるダイオード部８０のＸ軸方向正側のウェル領域１１の端ＳからＸ軸方向負側のウェル領域１１の端Ｓ'までを、拡大して示している。図２ｂに示す通り、本例の半導体装置１００は、ダイオード部８０において、第１カソード領域８２のＸＹ平面内における内側において、Ｘ軸方向に延伸するフローティング領域１７が、一例としてＹ軸方向に３個設けられる。 FIG. 2b is an enlarged view of region B1 in FIG. 2a. FIG. 2B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 2A to the end S ′ of the well region 11 on the X axis direction negative side. As shown in FIG. 2b, in the semiconductor device 100 of this example, in the diode portion 80, the floating region 17 extending in the X-axis direction is arranged in the Y-axis direction as an example inside the first cathode region 82 in the XY plane. Are provided.
　Ｘ軸方向正側のウェル領域１１の端部Ｓから第１カソード領域８２のＸ軸方向正側の端までの上面視におけるＸ軸方向の幅Ｗｗｃは、ダイオード部８０の幅ＷＦより小さくてよい。幅Ｗｗｃは、幅ＷＦの０．２５倍以上０．７５倍以下であってよい。幅Ｗｗｃは、１５０μｍ以上３００μｍ以下であってよい。幅Ｗｗｃは、一例として２５０μｍである。 The width Wwc in the X-axis direction in a top view from the end S of the well region 11 on the X-axis direction positive side to the end on the X-axis direction positive side of the first cathode region 82 may be smaller than the width WF of the diode portion 80. . The width Wwc may be not less than 0.25 times and not more than 0.75 times the width WF. The width Wwc may be 150 μm or more and 300 μm or less. The width Wwc is 250 μm as an example.
　コンタクトホール５４のＸ軸方向正側の端部Ｔは、図２ｂに示すように、ウェル領域１１のＸ軸方向正側の端部ＳからＸ軸方向負側に幅Ｗｗｃａ離れて設けられる。また、コンタクトホール５４のＸ軸方向負側の端部Ｔ'は、ウェル領域１１のＸ軸方向負側の端部Ｓ'からＸ軸方向正側に幅Ｗｗｃａ離れて設けられる。コンタクトホール５４は、端部Ｔから端部Ｔ'まで、Ｘ軸方向に連続して設けられてよい。 The end T on the positive side in the X-axis direction of the contact hole 54 is provided with a width Wwca away from the end S on the positive side in the X-axis direction of the well region 11 on the negative side in the X-axis direction, as shown in FIG. Further, the end portion T ′ on the negative side in the X-axis direction of the contact hole 54 is provided to be separated from the end portion S ′ on the negative side in the X-axis direction of the well region 11 on the positive side in the X-axis direction by a width Wwca. The contact hole 54 may be provided continuously from the end T to the end T ′ in the X-axis direction.
　なお図２ｂにおいては、１つのコンタクトホール５４を図示しているが、実際には、図１ｂに示した上面図から明らかなように、端部ＴのＸ軸方向の位置および端部Ｔ'のＸ軸方向の位置がそれぞれ等しいコンタクトホール５４が、Ｙ軸方向に複数設けられる。 In FIG. 2b, one contact hole 54 is shown, but actually, as is clear from the top view shown in FIG. 1b, the position of the end T in the X-axis direction and the end T ' A plurality of contact holes 54 having the same position in the X-axis direction are provided in the Y-axis direction.
　ウェル領域１１のＸ軸方向正側の端部Ｓから、ダイオード部８０に設けられた複数のコンタクトホール５４のＸ軸方向正側の端部Ｔまでの幅Ｗｗｃａは、当該端部Ｔから第１カソード領域８２のＸ軸方向正側の端までの上面視におけるＸ軸方向の幅Ｗｗｃｂより小さくてよい。幅Ｗｗｃａは、幅Ｗｗｃｂの０．１倍以上０．９倍以下であってよい。幅Ｗｗｃａは、２０μｍ以上１１０μｍ以下であってよい。幅Ｗｗｃｂは、１２０μｍ以上１８０μｍ以下であってよい。幅Ｗｗｃａは、一例として１００μｍである。幅Ｗｗｃｂは、一例として１５０μｍである。幅Ｗｗｃａと幅Ｗｗｃｂの和は、幅Ｗｗｃである。 The width Wwca from the end S on the positive side in the X-axis direction of the well region 11 to the end T on the positive side in the X-axis direction of the plurality of contact holes 54 provided in the diode portion 80 is the first width from the end T. The width may be smaller than the width Wwcb in the X-axis direction in a top view up to the end on the positive side in the X-axis direction of the cathode region 82. The width Wwca may be not less than 0.1 times and not more than 0.9 times the width Wwcb. The width Wwca may be 20 μm or more and 110 μm or less. The width Wwcb may be 120 μm or more and 180 μm or less. The width Wwca is 100 μm as an example. The width Wwcb is 150 μm as an example. The sum of the width Wwca and the width Wwcb is the width Wwc.
　また、ウェル領域１１のＸ軸方向負側の端部Ｓ'から、ダイオード部８０に設けられた複数のコンタクトホール５４のＸ軸方向負側の端部Ｔ'までの幅も、幅Ｗｗｃａに等しくてよい。当該端部Ｔ'から第１カソード領域８２のＸ軸方向負側の端までの、半導体基板１０の上面視におけるＸ軸方向の幅も、幅Ｗｗｃｂに等しくてよい。なお、Ｘ軸方向負側のウェル領域１１の端部Ｓ'から第１カソード領域８２のＸ軸方向負側の端までの上面視におけるＸ軸方向の幅も、幅Ｗｗｃに等しくてよい。 The width from the end S ′ on the negative side in the X-axis direction of the well region 11 to the end T ′ on the negative side in the X-axis direction of the plurality of contact holes 54 provided in the diode portion 80 is also equal to the width Wwca. It's okay. The width in the X-axis direction in the top view of the semiconductor substrate 10 from the end T ′ to the end on the negative side in the X-axis direction of the first cathode region 82 may be equal to the width Wwcb. The width in the X-axis direction in a top view from the end S ′ of the well region 11 on the negative side in the X-axis direction to the end on the negative side in the X-axis direction of the first cathode region 82 may be equal to the width Wwc.
　第１カソード領域８２のＸ軸方向の幅Ｗｃｖ１は、幅Ｗｈよりも小さくてよい。幅Ｗｃｖ１は、幅Ｗｈから幅Ｗｗｃの２倍を減じた値に等しい。幅Ｗｃｖ１は、幅Ｗｈの９０％以上９６％以下であってよい。幅Ｗｃｖ１は、２７００μｍ以上３４５０μｍ以下であってよい。幅Ｗｃｖ１は、一例として２８５０μｍである。 The width Wcv1 in the X-axis direction of the first cathode region 82 may be smaller than the width Wh. The width Wcv1 is equal to a value obtained by subtracting twice the width Wwc from the width Wh. The width Wcv1 may be 90% or more and 96% or less of the width Wh. The width Wcv1 may be 2700 μm or more and 3450 μm or less. The width Wcv1 is 2850 μm as an example.
　第１カソード領域８２のＹ軸方向の幅Ｗｃｈ１は、幅ＷＦの５％以上４０％以下であってよい。幅Ｗｃｈ１は、２０μｍ以上２４０μｍ以下であってよい。 The width Wch1 in the Y-axis direction of the first cathode region 82 may be 5% to 40% of the width WF. The width Wch1 may be 20 μm or more and 240 μm or less.
　第１カソード領域８２のＸＹ平面内における内側には、図２ｂに示すように、フローティング領域１７が設けられる。フローティング領域１７は、エミッタ電極５２には接続されない。 Inside the first cathode region 82 in the XY plane, as shown in FIG. 2b, the floating region 17 is provided. The floating region 17 is not connected to the emitter electrode 52.
　それぞれの第１カソード領域８２において、フローティング領域１７のＹ軸方向の幅Ｗｆｌ１１は、幅Ｗｃｈ１の８９％以上９５％以下であってよい。また、それぞれの第１カソード領域８２において、フローティング領域１７のＸ軸方向の幅Ｗｆｌ２１は、幅Ｗｃｖ１の８９％以上９５％以下であってよい。 In each first cathode region 82, the width Wfl11 of the floating region 17 in the Y-axis direction may be 89% or more and 95% or less of the width Wch1. In each first cathode region 82, the width Wfl21 of the floating region 17 in the X-axis direction may be 89% or more and 95% or less of the width Wcv1.
　それぞれの第１カソード領域８２において、半導体基板１０の上面視で、第１カソード領域８２の面積に占めるフローティング領域１７の面積は、８０％以上９０％以下であってよい。半導体基板１０の上面視における第１カソード領域８２と第２カソード領域８３との合計面積に占める第１カソード領域８２の面積および第２カソード領域８３の面積が、それぞれ８０％および２０％の場合、当該面積に占めるフローティング領域１７の面積の割合は、６４％以上７２％以下であってよい。 In each first cathode region 82, the area of the floating region 17 occupying the area of the first cathode region 82 in the top view of the semiconductor substrate 10 may be 80% or more and 90% or less. When the area of the first cathode region 82 and the area of the second cathode region 83 in the total area of the first cathode region 82 and the second cathode region 83 in the top view of the semiconductor substrate 10 are 80% and 20%, respectively, The ratio of the area of the floating region 17 to the area may be 64% or more and 72% or less.
　Ｙ軸方向において、ダイオード部８０と、当該ダイオード部８０にＹ軸方向正側で隣接するトランジスタ部７０との境界から、Ｙ軸方向の最も正側に設けられるフローティング領域１７のＹ軸方向正側の端までの幅Ｗｃｆ１は、幅Ｗｃｈ１の３％以上６％以下であってよい。幅Ｗｃｆ１は、ゼロでなければよい。幅Ｗｃｆ１は、２μｍ以上６μｍ以下であってよい。幅Ｗｃｆ１は、一例として５μｍである。なお、Ｙ軸方向において、当該ダイオード部８０と、当該ダイオード部８０にＹ軸方向負側で隣接するトランジスタ部７０との境界から、Ｙ軸方向の最も負側に設けられるフローティング領域１７のＹ軸方向負側の端までの幅も、幅Ｗｃｆ１に等しくてよい。 In the Y-axis direction, the Y-axis direction positive side of the floating region 17 provided on the most positive side in the Y-axis direction from the boundary between the diode unit 80 and the transistor unit 70 adjacent to the diode unit 80 on the Y-axis direction positive side The width Wcf1 up to the end of may be 3% or more and 6% or less of the width Wch1. The width Wcf1 may not be zero. The width Wcf1 may be 2 μm or more and 6 μm or less. The width Wcf1 is 5 μm as an example. In the Y-axis direction, the Y-axis of the floating region 17 provided on the most negative side in the Y-axis direction from the boundary between the diode unit 80 and the transistor unit 70 adjacent to the diode unit 80 on the negative side in the Y-axis direction. The width to the end on the negative direction side may also be equal to the width Wcf1.
　それぞれの第１カソード領域８２において、第１カソード領域８２のＸ軸方向正側の端から、フローティング領域１７のＸ軸方向正側の端までの幅Ｗｃｆ２は、幅Ｗｃｖ１の３％以上６％以下であってよい。幅Ｗｃｆ２は、ゼロであってもよい。また、幅Ｗｃｆ２は、幅Ｗｃｆ１と等しくてもよいし、異なっていてもよい。幅Ｗｃｆ２は、２μｍ以上６μｍ以下であってよい。幅Ｗｃｆ２は、一例として５μｍである。なお、第１カソード領域８２のＹ軸方向負側の端から、Ｙ軸方向負側のフローティング領域１７のＹ軸方向負側の端までの幅も、幅Ｗｃｆ２に等しい。 In each first cathode region 82, the width Wcf2 from the X-axis direction positive end of the first cathode region 82 to the X-axis direction positive end of the floating region 17 is 3% or more and 6% or less of the width Wcv1. It may be. The width Wcf2 may be zero. Further, the width Wcf2 may be equal to or different from the width Wcf1. The width Wcf2 may be 2 μm or more and 6 μm or less. The width Wcf2 is 5 μm as an example. The width from the Y-axis direction negative side end of the first cathode region 82 to the Y-axis direction negative side end of the Y-axis direction negative side floating region 17 is also equal to the width Wcf2.
　なお、本例においてコンタクトホール５４のＹ軸方向の幅Ｗｃｎｔは、Ｗｃｆ１および幅Ｗｃｆ２より小さくてよい。幅Ｗｃｎｔは、０．３μｍ以上０．７μｍ以下であってよい。幅Ｗｃｎｔは、一例として０．５μｍである。 In this example, the width Wcnt in the Y-axis direction of the contact hole 54 may be smaller than Wcf1 and width Wcf2. The width Wcnt may be not less than 0.3 μm and not more than 0.7 μm. The width Wcnt is 0.5 μm as an example.
　図２ｃは、図２ｂにおける領域Ｃ１の拡大図である。図２ｃに示す通り、本例の半導体装置１００は、一例として第１カソード領域８２がＹ軸方向に３つ設けられる。Ｙ軸方向において、隣り合う第１カソード領域８２の間には、第２カソード領域８３が設けられる。 FIG. 2c is an enlarged view of region C1 in FIG. 2b. As shown in FIG. 2c, in the semiconductor device 100 of this example, three first cathode regions 82 are provided in the Y-axis direction as an example. A second cathode region 83 is provided between adjacent first cathode regions 82 in the Y-axis direction.
　幅Ｗｎｆ１は、Ｙ軸方向の最も正側の第１カソード領域８２において、当該第１カソード領域８２のＹ軸方向負側の端から、当該第１カソード領域８２に重なって配置されるフローティング領域１７のＹ軸方向負側の端までの、Ｙ軸方向における幅である。また、幅Ｗｎｆ１は、Ｙ軸方向の最も負側の第１カソード領域８２において、当該第１カソード領域８２のＹ軸方向正側の端から、当該第１カソード領域８２に重なって配置されるフローティング領域１７のＹ軸方向正側の端までの、Ｙ軸方向における幅である。 The width Wnf1 is the floating region 17 arranged so as to overlap the first cathode region 82 from the Y-axis direction negative end of the first cathode region 82 in the most positive first cathode region 82 in the Y-axis direction. Is the width in the Y-axis direction to the end on the negative side in the Y-axis direction. In addition, the width Wnf1 is a floating in the first cathode region 82 that is the most negative side in the Y-axis direction, overlapping the first cathode region 82 from the Y-axis direction positive end of the first cathode region 82. This is the width in the Y-axis direction up to the end on the Y-axis direction positive side of the region 17.
　Ｙ軸方向の最も正側の第１カソード領域８２および最も負側の第１カソード領域８２の双方を除く第１カソード領域８２においても、当該第１カソード領域８２のＹ軸方向正側の端から、当該第１カソード領域８２に重なって配置されるフローティング領域１７の正側の端までのＹ軸方向における幅は、幅Ｗｎｆ１と等しくてよい。当該第１カソード領域８２のＹ軸方向負側の端から、当該第１カソード領域８２に重なって配置されるフローティング領域１７の負側の端までのＹ軸方向における幅も、幅Ｗｎｆ１と等しくてよい。 Also in the first cathode region 82 excluding both the most positive first cathode region 82 and the most negative first cathode region 82 in the Y-axis direction, from the Y-axis direction positive end of the first cathode region 82. The width in the Y-axis direction up to the positive end of the floating region 17 disposed so as to overlap the first cathode region 82 may be equal to the width Wnf1. The width in the Y-axis direction from the end on the negative side in the Y-axis direction of the first cathode region 82 to the end on the negative side of the floating region 17 arranged so as to overlap the first cathode region 82 is also equal to the width Wnf1. Good.
　幅Ｗｎｆ１は、幅Ｗｃｆ１と等しくてよいが、異なっていてもよい。幅Ｗｎｆ１は、ゼロであってもよい。 Width Wnf1 may be equal to width Wcf1, but may be different. The width Wnf1 may be zero.
　本例の半導体装置１００は、ダイオード部８０に第１導電型の第１カソード領域８２および第２導電型の第２カソード領域８３が、Ｙ軸方向に交互に設けられる。また、複数の第２導電型のフローティング領域１７が、第１カソード領域８２毎に互いに分離して設けられ、半導体基板１０の上面視で、第１カソード領域８２と重なって配置される。このため、ダイオード部８０の逆回復時におけるサージ電圧を抑制することができる。 In the semiconductor device 100 of this example, the first conductive type first cathode regions 82 and the second conductive type second cathode regions 83 are alternately provided in the Y-axis direction in the diode portion 80. A plurality of second conductivity type floating regions 17 are provided separately from each other for each first cathode region 82, and are disposed so as to overlap the first cathode region 82 in a top view of the semiconductor substrate 10. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be suppressed.
　図２ｄは、図２ｂにおけるａ－ａ'断面の一例を示す図である。本例の半導体装置１００は、ａ－ａ'断面において、半導体基板１０、層間絶縁膜３８、エミッタ電極５２およびコレクタ電極２４を有する。エミッタ電極５２は、半導体基板１０の上面２１および層間絶縁膜３８の上面に設けられる。コレクタ電極２４は、半導体基板１０の下面２３に設けられる。エミッタ電極５２およびコレクタ電極２４は、金属等の導電材料で形成される。層間絶縁膜３８は、ＰＳＧ、ＢＰＳＧ等のシリケートガラスであってよい。また、層間絶縁膜３８は、酸化膜または窒化膜等であってもよい。 FIG. 2d is a diagram showing an example of a cross section aa ′ in FIG. 2b. The semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in the section aa ′. The emitter electrode 52 is provided on the upper surface 21 of the semiconductor substrate 10 and the upper surface of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a conductive material such as metal. The interlayer insulating film 38 may be silicate glass such as PSG or BPSG. The interlayer insulating film 38 may be an oxide film or a nitride film.
　半導体基板１０は、シリコン基板であってよく、炭化シリコン基板であってよく、窒化ガリウム等の窒化物半導体基板または酸化ガリウム基板等であってもよい。本例の半導体基板１０はシリコン基板である。 The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or a gallium oxide substrate. The semiconductor substrate 10 in this example is a silicon substrate.
　半導体基板１０は、第１導電型のドリフト領域１８を備える。本例のドリフト領域１８はＮ－型である。ドリフト領域１８は、半導体基板１０において、他のドーピング領域が設けられずに残存した領域であってよい。 The semiconductor substrate 10 includes a first conductivity type drift region 18. The drift region 18 in this example is N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without being provided with another doping region.
　半導体基板１０の上面２１には、１つ以上のゲートトレンチ部４０および１つ以上のダミートレンチ部３０が設けられる。各トレンチ部は、上面２１から、ベース領域１４を貫通して、ドリフト領域１８に到達して設けられている。 The upper surface 21 of the semiconductor substrate 10 is provided with one or more gate trench portions 40 and one or more dummy trench portions 30. Each trench portion is provided from the upper surface 21 through the base region 14 to reach the drift region 18.
　ダミートレンチ部３０は、上面２１に設けられたダミートレンチ、並びにダミートレンチ内に設けられたダミー絶縁膜３２およびダミー導電部３４を有する。ダミートレンチの上端は、Ｚ軸方向において上面２１と同じ位置であってよい。ダミー絶縁膜３２は、ダミートレンチの内壁を覆って設けられる。ダミー絶縁膜３２は、ダミートレンチの内壁の半導体を酸化または窒化して形成してよい。ダミー導電部３４は、ダミートレンチの内部においてダミー絶縁膜３２よりも内側に設けられる。即ち、ダミー絶縁膜３２は、ダミー導電部３４と半導体基板１０とを絶縁する。ダミー導電部３４は、ポリシリコン等の導電材料で形成される。 The dummy trench portion 30 includes a dummy trench provided on the upper surface 21, and a dummy insulating film 32 and a dummy conductive portion 34 provided in the dummy trench. The upper end of the dummy trench may be at the same position as the upper surface 21 in the Z-axis direction. The dummy insulating film 32 is provided so as to cover the inner wall of the dummy trench. The dummy insulating film 32 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy insulating film 32 inside the dummy trench. That is, the dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 is formed of a conductive material such as polysilicon.
　ダミー導電部４４は、ダミー絶縁膜３２を挟んで、ベース領域１４と対向する領域を含む。当該断面におけるダミートレンチ部３０は、上面２１において層間絶縁膜３８により覆われる。 The dummy conductive portion 44 includes a region facing the base region 14 with the dummy insulating film 32 interposed therebetween. The dummy trench portion 30 in the cross section is covered with the interlayer insulating film 38 on the upper surface 21.
　ａ－ａ'断面よりもＹ軸方向正側および負側のトランジスタ部７０においては、ゲートトレンチ部４０が設けられる。ゲートトレンチ部４０は、ＹＺ断面において、ダミートレンチ部３０と同一の構造を有してよい。ゲートトレンチ部４０は、上面２１側に設けられたゲートトレンチ、並びにゲートトレンチ内に設けられたゲート絶縁膜およびゲート導電部を有する。ゲート導電部に所定の電圧が印加されると、ベース領域１４のうちゲートトレンチに接する界面の表層に電子の反転層によるチャネルが形成される。 In the Y-axis direction positive side and negative side transistor part 70 with respect to the aa ′ cross section, a gate trench part 40 is provided. The gate trench portion 40 may have the same structure as the dummy trench portion 30 in the YZ section. The gate trench portion 40 includes a gate trench provided on the upper surface 21 side, and a gate insulating film and a gate conductive portion provided in the gate trench. When a predetermined voltage is applied to the gate conductive portion, a channel formed by an electron inversion layer is formed on the surface layer of the base region 14 in contact with the gate trench.
　ゲート導電部は、ダミー導電部３４と同一の材料で形成されてよい。例えば、ダミー導電部３４およびゲート導電部は、ポリシリコン等の導電材料で形成される。なお、ダミートレンチ部３０およびゲートトレンチ部４０の底部は下方側に凸の曲面状（断面においては曲線状）であってよい。 The gate conductive part may be formed of the same material as the dummy conductive part 34. For example, the dummy conductive portion 34 and the gate conductive portion are formed of a conductive material such as polysilicon. Note that the bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a curved surface (curved shape in cross section) convex downward.
　ダイオード部８０のメサ部６０－３において、ドリフト領域１８の上方には、ダミートレンチ部３０に接して一つ以上の第１導電型の高濃度領域１９が設けられてよい。高濃度領域１９は、一例としてＮ＋型である。高濃度領域１９は、メサ部６０－３に設けられてよいが、設けられなくてもよい。高濃度領域１９は、ダミートレンチ部３０に接してよいが、接さなくてもよい。高濃度領域１９が複数設けられる場合、それぞれの高濃度領域１９－１および高濃度領域１９－２は、Ｚ軸方向に並んで配置される。Ｚ軸方向において、高濃度領域１９－１と高濃度領域１９－２の間には、ドリフト領域１８が設けられてよい。 In the mesa portion 60-3 of the diode portion 80, one or more high-concentration regions 19 of the first conductivity type may be provided above the drift region 18 in contact with the dummy trench portion 30. The high concentration region 19 is, for example, an N + type. The high concentration region 19 may be provided in the mesa unit 60-3, but may not be provided. The high concentration region 19 may be in contact with the dummy trench portion 30, but may not be in contact with it. When a plurality of high concentration regions 19 are provided, the high concentration regions 19-1 and 19-2 are arranged side by side in the Z-axis direction. In the Z-axis direction, a drift region 18 may be provided between the high concentration region 19-1 and the high concentration region 19-2.
　メサ部６０－３において、高濃度領域１９の上方には、上面２１に接し、且つ、ダミートレンチ部３０に接して、第２導電型のベース領域１４が設けられる。本例のベース領域１４は、一例としてＰ－型である。 In the mesa portion 60-3, the second conductivity type base region 14 is provided above the high concentration region 19 in contact with the upper surface 21 and in contact with the dummy trench portion 30. The base region 14 in this example is a P-type as an example.
　高濃度領域１９においては、ドリフト領域１８と比べて、電荷中性条件により正孔の濃度が減少する。即ち、高濃度領域１９が、ベース領域１４からドリフト領域１８への正孔の注入を抑制する。これにより、ベース領域１４からドリフト領域１８への少数キャリアの注入効率が格段に低減する。高濃度領域１９の個数が多いほど、少数キャリアの注入効率の低減が可能となる。これにより、ダイオード部８０の逆回復特性、特にリカバリー電流を大きく低減することができる。 In the high concentration region 19, the hole concentration is reduced by the charge neutrality condition as compared with the drift region 18. That is, the high concentration region 19 suppresses the injection of holes from the base region 14 to the drift region 18. Thereby, the injection efficiency of minority carriers from the base region 14 to the drift region 18 is significantly reduced. As the number of high-concentration regions 19 increases, the minority carrier injection efficiency can be reduced. Thereby, the reverse recovery characteristic of the diode part 80, especially the recovery current can be greatly reduced.
　トランジスタ部７０のメサ部６０－２において、ドリフト領域１８の上方には、ダミートレンチ部３０に接して第２導電型のベース領域１４が設けられる。ベース領域１４の上方には、上面２１に接し、且つ、ダミートレンチ部３０に接して、第２導電型のコンタクト領域１５が設けられる。本例のベース領域は、一例としてＰ＋型である。コンタクト領域１５は、ダミートレンチ部３０に接してよいが、接さなくてもよい。 In the mesa portion 60-2 of the transistor portion 70, the base region 14 of the second conductivity type is provided above the drift region 18 in contact with the dummy trench portion 30. Above the base region 14, a second conductivity type contact region 15 is provided in contact with the upper surface 21 and in contact with the dummy trench portion 30. The base region of this example is a P + type as an example. The contact region 15 may be in contact with the dummy trench portion 30, but may not be in contact.
　ドリフト領域１８の下方には、第１導電型のバッファ領域２０が設けられてよい。バッファ領域２０は、一例としてＮ＋型である。バッファ領域２０のドーピング濃度は、ドリフト領域１８のドーピング濃度よりも高い。バッファ領域２０は、ベース領域１４の下面側から広がる空乏層が、Ｐ＋型のコレクタ領域２２、並びにＮ＋型の第１カソード領域８２およびＰ＋型の第２カソード領域８３に到達することを防ぐフィールドストップ層として機能してよい。 A buffer region 20 of the first conductivity type may be provided below the drift region 18. The buffer area 20 is an N + type as an example. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 is a field stop that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the P + type collector region 22, the N + type first cathode region 82, and the P + type second cathode region 83. It may function as a layer.
　トランジスタ部７０において、バッファ領域２０の下方には、下面２３に露出するＰ＋型のコレクタ領域２２が設けられる。ダイオード部８０において、バッファ領域２０の下方には、下面２３に露出するＮ＋型の第１カソード領域８２およびＰ＋型の第２カソード領域８３が設けられる。ダイオード部８０において、トランジスタ部７０と隣接する領域には、第１カソード領域８２が設けられる。 In the transistor unit 70, a P + type collector region 22 exposed on the lower surface 23 is provided below the buffer region 20. In the diode portion 80, an N + type first cathode region 82 and a P + type second cathode region 83 exposed on the lower surface 23 are provided below the buffer region 20. In the diode unit 80, a first cathode region 82 is provided in a region adjacent to the transistor unit 70.
　なお、ダイオード部８０は、下面２３に垂直な方向において、第１カソード領域８２および第２カソード領域８３と重なる領域である。また、トランジスタ部７０は、下面２３に垂直な方向においてコレクタ領域２２と重なる領域のうち、エミッタ領域１２およびコンタクト領域１５を含む所定の単位構成が規則的に配置された領域である。 The diode portion 80 is a region that overlaps the first cathode region 82 and the second cathode region 83 in the direction perpendicular to the lower surface 23. The transistor unit 70 is a region in which predetermined unit configurations including the emitter region 12 and the contact region 15 are regularly arranged in a region overlapping the collector region 22 in a direction perpendicular to the lower surface 23.
　本例の半導体装置１００は、ダイオード部８０において、第１カソード領域８２の上方にフローティング領域１７が設けられる。フローティング領域１７は、ａ－ａ'断面において、Ｙ軸方向に一例として３つ設けられる。フローティング領域１７は、第１カソード領域８２と接して設けられてよい。 In the semiconductor device 100 of this example, the floating region 17 is provided above the first cathode region 82 in the diode portion 80. As an example, three floating regions 17 are provided in the Y-axis direction in the section aa ′. The floating region 17 may be provided in contact with the first cathode region 82.
　本例においては、図２ｄに示す通り、半導体基板１０の下面２３と平行な面内において、コレクタ領域２２と第１カソード領域８２との境界位置が２つ存在する。境界位置Ｐ１は、当該２つの境界位置のうち、Ｙ軸方向正側の境界位置である。また、境界位置Ｐ１'は、当該２つの境界位置のうち、Ｙ軸方向負側の境界位置である。境界位置Ｐ１およびＰ１'は、ａ－ａ'断面と平行な断面における境界位置である。一例として、ａ－ａ'断面は、下面２３と垂直であり、且つ、ダミートレンチ部３０の配列方向と平行な面である。 In this example, as shown in FIG. 2 d, there are two boundary positions between the collector region 22 and the first cathode region 82 in a plane parallel to the lower surface 23 of the semiconductor substrate 10. The boundary position P1 is a boundary position on the Y axis direction positive side among the two boundary positions. The boundary position P1 ′ is a boundary position on the Y axis direction negative side among the two boundary positions. The boundary positions P1 and P1 ′ are boundary positions in a cross section parallel to the aa ′ cross section. As an example, the aa ′ cross section is a plane perpendicular to the lower surface 23 and parallel to the arrangement direction of the dummy trench portions 30.
　本例においては、図２ｄに示す通り、下面２３と平行な面内において、フローティング領域１７の端部位置が２つ存在する。端部位置Ｐ２は、下面２３と平行な面内において、Ｙ軸方向の最も正側に設けられるフローティング領域１７の、境界位置Ｐ１に最も近い端部位置である。また、端部位置Ｐ２'は、下面２３と平行な面内において、Ｙ軸方向の最も負側に設けられるフローティング領域１７の、境界位置Ｐ１'に最も近い端部位置である。 In this example, as shown in FIG. 2 d, there are two end positions of the floating region 17 in a plane parallel to the lower surface 23. The end position P2 is an end position closest to the boundary position P1 of the floating region 17 provided on the most positive side in the Y-axis direction in a plane parallel to the lower surface 23. The end position P2 ′ is the end position closest to the boundary position P1 ′ of the floating region 17 provided on the most negative side in the Y-axis direction in a plane parallel to the lower surface 23.
　フローティング領域１７は、端部位置Ｐ２から端部位置Ｐ２'まで、Ｙ軸方向に複数設けられてよい。本例の半導体装置１００は、フローティング領域１７は、端部位置Ｐ２から端部位置Ｐ２'まで、Ｙ軸方向に３つ設けられる。 A plurality of floating regions 17 may be provided in the Y-axis direction from the end position P2 to the end position P2 ′. In the semiconductor device 100 of this example, three floating regions 17 are provided in the Y-axis direction from the end position P2 to the end position P2 ′.
　幅Ｗｃｆ１は、境界位置Ｐ１から端部位置Ｐ２までのＹ軸方向における距離である。また、幅Ｗｃｆ１は、境界位置Ｐ１'から端部位置Ｐ２'までのＹ軸方向における距離である。幅Ｗｃｆ１を小さくすることで、ダイオード部８０の端部において、第１カソード領域８２からの電子の注入を抑制することができる。 The width Wcf1 is a distance in the Y-axis direction from the boundary position P1 to the end position P2. The width Wcf1 is a distance in the Y-axis direction from the boundary position P1 ′ to the end position P2 ′. By reducing the width Wcf1, the injection of electrons from the first cathode region 82 can be suppressed at the end of the diode portion 80.
　幅Ｗｄは、フローティング領域１７のＺ軸方向の幅である。幅Ｗｄは、幅Ｗｃｆ１より小さくてよい。幅Ｗｄは、幅Ｗｃｆ１の０．０５倍以上０．５倍以下であってよい。幅Ｗｄは、０．３μｍ以上１μｍ以下であってよい。幅Ｗｄは、一例として０．５μｍである。 The width Wd is the width of the floating region 17 in the Z-axis direction. The width Wd may be smaller than the width Wcf1. The width Wd may be not less than 0.05 times and not more than 0.5 times the width Wcf1. The width Wd may be not less than 0.3 μm and not more than 1 μm. The width Wd is 0.5 μm as an example.
　ａ－ａ'断面においてＹ軸方向中央に設けられる第１カソード領域８２においても、当該第１カソード領域８２のＹ軸方向正側の端から、当該第１カソード領域８２に重なって配置されるフローティング領域１７の正側の端までのＹ軸方向における幅は、幅Ｗｎｆ１と等しくてよい。当該第１カソード領域８２のＹ軸方向負側の端から、当該第１カソード領域８２に重なって配置されるフローティング領域１７の負側の端までのＹ軸方向における幅も、幅Ｗｎｆ１と等しくてよい。 Also in the first cathode region 82 provided at the center in the Y-axis direction in the aa ′ cross section, the floating is arranged so as to overlap the first cathode region 82 from the Y-axis direction positive end of the first cathode region 82. The width in the Y-axis direction to the positive end of the region 17 may be equal to the width Wnf1. The width in the Y-axis direction from the end on the negative side in the Y-axis direction of the first cathode region 82 to the end on the negative side of the floating region 17 arranged so as to overlap the first cathode region 82 is also equal to the width Wnf1. Good.
　それぞれの第１カソード領域８２において、フローティング領域１７のＹ軸方向の幅Ｗｆｌ１１は、幅Ｗｃｈ１の８９％以上９５％以下であってよい。幅Ｗｎｆ１は、幅Ｗｃｆ１と等しくてよいが、異なっていてもよい。幅Ｗｎｆ１は、ゼロであってもよい。 In each first cathode region 82, the width Wfl11 of the floating region 17 in the Y-axis direction may be 89% or more and 95% or less of the width Wch1. The width Wnf1 may be equal to the width Wcf1, but may be different. The width Wnf1 may be zero.
　図２ｅは、図２ｂにおけるｂ－ｂ'断面の一例を示す図である。ｂ－ｂ'断面は、図２ｄにおけるｂ''－ｂ'''線を通るＸＺ平面である。本例の半導体装置１００は、ダイオード部８０において、第１カソード領域８２の上方にフローティング領域１７が設けられる。 FIG. 2e is a diagram showing an example of a bb ′ cross section in FIG. 2b. The bb ′ cross section is the XZ plane passing through the b ″ -b ′ ″ line in FIG. 2d. In the semiconductor device 100 of this example, the floating region 17 is provided above the first cathode region 82 in the diode unit 80.
　本例においては、図２ｅに示す通り、半導体基板１０の下面２３と平行な面内において、コレクタ領域２２と第１カソード領域８２との境界位置が２つ存在する。境界位置Ｐ５は、当該２つの境界位置のうち、Ｘ軸方向負側の境界位置である。また、境界位置Ｐ５'は、当該２つの境界位置のうち、Ｘ軸方向正側の境界位置である。境界位置Ｐ５およびＰ５'は、ｂ－ｂ'断面と平行な断面における境界位置である。一例として、ｂ－ｂ'断面は、下面２３と垂直であり、且つ、ダミートレンチ部３０の延伸方向と平行な面である。 In this example, there are two boundary positions between the collector region 22 and the first cathode region 82 in a plane parallel to the lower surface 23 of the semiconductor substrate 10 as shown in FIG. 2e. The boundary position P5 is a boundary position on the negative side in the X-axis direction among the two boundary positions. The boundary position P5 ′ is a boundary position on the positive side in the X-axis direction among the two boundary positions. The boundary positions P5 and P5 ′ are boundary positions in a cross section parallel to the bb ′ cross section. As an example, the bb ′ cross section is a surface perpendicular to the lower surface 23 and parallel to the extending direction of the dummy trench portion 30.
　本例においては、図２ｅに示す通り、下面２３と平行な面内において、フローティング領域１７の端部位置が２つ存在する。端部位置Ｐ６は、下面２３と平行な面内において、Ｘ軸方向に複数配列されるフローティング領域１７のうち、Ｘ軸方向の最も負側に配置されるフローティング領域１７の、境界位置Ｐ５に最も近い端部位置である。また、端部位置Ｐ６'は、下面２３と平行な面内において、Ｙ軸方向に複数配列されるフローティング領域１７のうち、Ｘ軸方向の最も正側に配置されるフローティング領域１７の、境界位置Ｐ５'に最も近い端部位置である。本例においては、フローティング領域１７が、端部位置Ｐ６から端部位置Ｐ６'まで、Ｘ軸方向に連続して設けられる。 In this example, as shown in FIG. 2 e, there are two end positions of the floating region 17 in a plane parallel to the lower surface 23. The end position P6 is closest to the boundary position P5 of the floating region 17 arranged on the most negative side in the X-axis direction among the plurality of floating regions 17 arranged in the X-axis direction in a plane parallel to the lower surface 23. Close end position. The end position P6 ′ is a boundary position of the floating region 17 arranged on the most positive side in the X-axis direction among the plurality of floating regions 17 arranged in the Y-axis direction in a plane parallel to the lower surface 23. This is the end position closest to P5 ′. In this example, the floating region 17 is continuously provided in the X-axis direction from the end position P6 to the end position P6 ′.
　幅Ｗｆｌ２１は、フローティング領域１７のＸ軸方向における幅である。幅Ｗｃｆ２は、境界位置Ｐ５から端部位置Ｐ６までのＸ軸方向における距離である。また、幅Ｗｃｆ２は、境界位置Ｐ５'から端部位置Ｐ６'までのＸ軸方向における距離である。また、幅Ｗｃｖ１は、境界位置Ｐ５から境界位置Ｐ５'までのＸ軸方向における距離である。幅Ｗｆｌ２１は、幅Ｗｃｖ１の８９％以上９５％以下であってよい。本例の半導体装置１００は、ダイオード部８０において、フローティング領域１７を第１カソード領域８２の上方に設けているので、ダイオード部８０の逆回復時のサージ電圧を抑制することができる。ダイオード部８０における上面２１側および下面２３側に、それぞれＨｅ等を照射して局所的にライフタイムキラー領域を設け、キャリアの注入を抑制することができるが、ライフタイムキラー領域の形成はコストが高い。また、ダイオード部８０の逆回復時におけるサージ電圧が大きくなるので、ダイオード部８０を高速化することができない。 The width Wfl21 is the width of the floating region 17 in the X-axis direction. The width Wcf2 is a distance in the X-axis direction from the boundary position P5 to the end position P6. The width Wcf2 is a distance in the X-axis direction from the boundary position P5 ′ to the end position P6 ′. The width Wcv1 is a distance in the X-axis direction from the boundary position P5 to the boundary position P5 ′. The width Wfl21 may be 89% or more and 95% or less of the width Wcv1. In the semiconductor device 100 of this example, since the floating region 17 is provided above the first cathode region 82 in the diode unit 80, the surge voltage during reverse recovery of the diode unit 80 can be suppressed. A lifetime killer region can be locally provided by irradiating He or the like on the upper surface 21 side and the lower surface 23 side of the diode portion 80 to suppress carrier injection, but the formation of the lifetime killer region is costly. high. Moreover, since the surge voltage at the time of reverse recovery of the diode part 80 becomes large, the diode part 80 cannot be speeded up.
　なお、図２ｅにおけるＸ軸方向正側のコレクタ領域２２は、図１ａにおけるＸ軸方向正側の外周領域７４まで延伸していてよい。当該コレクタ領域２２は、トランジスタ部７０における下面２３に設けられたコレクタ領域２２とつながっていてよい。同様に、図１ａにおけるＸ軸方向の最も負側のダイオード部８０において、Ｘ軸方向負側に設けられるコレクタ領域２２は、図１ａにおけるＸ軸方向負側の外周領域７４まで延伸していてよい。外周領域７４の下方においては、下面２３には、コレクタ領域２２に代えて第１カソード領域８２よりもドーピング濃度の薄い第１導電型の終端領域が設けられてよい。終端領域のドーピング濃度は、第１カソード領域８２のドーピング濃度の１／１０以下であってよい。 Note that the collector region 22 on the X axis direction positive side in FIG. 2E may extend to the outer peripheral region 74 on the X axis direction positive side in FIG. 1A. The collector region 22 may be connected to the collector region 22 provided on the lower surface 23 of the transistor portion 70. Similarly, in the diode portion 80 on the most negative side in the X-axis direction in FIG. 1a, the collector region 22 provided on the negative side in the X-axis direction may extend to the outer peripheral region 74 on the negative side in the X-axis direction in FIG. . Below the outer peripheral region 74, a first conductivity type termination region having a doping concentration lower than that of the first cathode region 82 may be provided on the lower surface 23 instead of the collector region 22. The doping concentration of the termination region may be 1/10 or less of the doping concentration of the first cathode region 82.
　図３ａは、図１ａにおける領域Ａの他の拡大図である。本例の半導体装置１００は、図２ａに示す半導体装置１００において、複数のフローティング領域１７のうち、一部のフローティング領域１７が、半導体基板１０の上面視で、第１カソード領域８２および第２カソード領域８３の両方と重なって、配列方向に複数設けられる点で、図２ａに示す半導体装置１００と異なる。即ち、本例の半導体装置１００は、複数のフローティング領域１７のうち一部のフローティング領域１７が、半導体基板１０の上面視で、第１カソード領域８２と第２カソード領域８３とのＸ軸方向の境界と重なって、Ｙ軸方向に、第１カソード領域８２から第２カソード領域８３にわたって設けられる。 FIG. 3a is another enlarged view of region A in FIG. 1a. The semiconductor device 100 of this example is different from the semiconductor device 100 shown in FIG. 2A in that some of the floating regions 17 have a first cathode region 82 and a second cathode in the top view of the semiconductor substrate 10. The semiconductor device 100 is different from the semiconductor device 100 shown in FIG. That is, in the semiconductor device 100 of this example, some floating regions 17 among the plurality of floating regions 17 are in the X-axis direction between the first cathode region 82 and the second cathode region 83 when the semiconductor substrate 10 is viewed from above. It overlaps with the boundary and is provided from the first cathode region 82 to the second cathode region 83 in the Y-axis direction.
　図３ｂは、図３ａにおける領域Ｂ２の拡大図である。図３ｂは、図３ａにおけるダイオード部８０のＸ軸方向正側のウェル領域１１の端ＳからＸ軸方向負側のウェル領域１１の端Ｓ'までを、拡大して示している。なお、図３ｂ以降の図面においては、図２ｂおよび図２ｃにおいて示したコンタクトホール５４を省略して示す。 FIG. 3b is an enlarged view of region B2 in FIG. 3a. FIG. 3B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 3A to the end S ′ of the well region 11 on the X axis direction negative side. In FIG. 3b and subsequent drawings, the contact hole 54 shown in FIGS. 2b and 2c is omitted.
　本例の半導体装置１００は、図３ｂに示す通り、ダイオード部８０において、Ｘ軸方向に延伸しＹ軸方向に配列するフローティング領域１７が、一例として９個設けられる。本例の半導体装置１００は、一例として第１カソード領域８２が３つ設けられ、第２カソード領域８３が２つ設けられるので、第１カソード領域８２と第２カソード領域８３とのＸ軸方向に平行な境界が４か所存在する。このため、９個のフローティング領域１７のうち、４個のフローティング領域１７が、それぞれ当該境界と重なって設けられる。９個のフローティング領域１７のうち、５個のフローティング領域１７は、半導体基板１０の上面視で第１カソード領域８２の内側に設けられる。 As shown in FIG. 3B, the semiconductor device 100 of this example is provided with nine floating regions 17 extending in the X-axis direction and arranged in the Y-axis direction as an example in the diode unit 80. In the semiconductor device 100 of this example, three first cathode regions 82 and two second cathode regions 83 are provided as an example, so that the first cathode region 82 and the second cathode region 83 are arranged in the X-axis direction. There are four parallel boundaries. For this reason, of the nine floating regions 17, four floating regions 17 are provided so as to overlap with the boundary respectively. Of the nine floating regions 17, five floating regions 17 are provided inside the first cathode region 82 in a top view of the semiconductor substrate 10.
　それぞれの第１カソード領域８２において、半導体基板１０の上面視で、第１カソード領域８２の面積に占めるフローティング領域１７の面積は、８０％以上９０％以下であってよい。半導体基板１０の上面視における第１カソード領域８２と第２カソード領域８３との合計面積に占める第１カソード領域８２の面積および第２カソード領域８３の面積が、それぞれ８０％および２０％の場合、当該面積に占めるフローティング領域１７の面積の割合は、６４％以上７２％以下であってよい。 In each first cathode region 82, the area of the floating region 17 occupying the area of the first cathode region 82 in the top view of the semiconductor substrate 10 may be 80% or more and 90% or less. When the area of the first cathode region 82 and the area of the second cathode region 83 in the total area of the first cathode region 82 and the second cathode region 83 in the top view of the semiconductor substrate 10 are 80% and 20%, respectively, The ratio of the area of the floating region 17 to the area may be 64% or more and 72% or less.
　本例の半導体装置１００において、幅Ｗｃｆ１および幅Ｗｃｆ２は、それぞれ図２ｂに示す例における幅Ｗｃｆ１および幅Ｗｃｆ２と同じであってよい。幅Ｗｃｆ１は、ゼロでなければよい。幅Ｗｃｆ２は、ゼロであってもよい。 In the semiconductor device 100 of this example, the width Wcf1 and the width Wcf2 may be the same as the width Wcf1 and the width Wcf2 in the example illustrated in FIG. The width Wcf1 may not be zero. The width Wcf2 may be zero.
　本例の半導体装置１００において、フローティング領域１７のＸ軸方向の幅Ｗｆｌ２１は、図２ｂに示す例における幅Ｗｆｌ２１と同じであってよい。フローティング領域１７のＹ軸方向の幅Ｗｆｌ１２は、図２ｂに示す例における幅Ｗｆｌ１１よりも小さくてよい。 In the semiconductor device 100 of this example, the width Wfl21 of the floating region 17 in the X-axis direction may be the same as the width Wfl21 in the example illustrated in FIG. The width Wfl12 of the floating region 17 in the Y-axis direction may be smaller than the width Wfl11 in the example illustrated in FIG.
　図３ｃは、図３ｂにおける領域Ｃ２の拡大図である。図３ｃに示す通り、本例の半導体装置１００は、一例として第１カソード領域８２がＹ軸方向に９個設けられる。Ｙ軸方向において、隣り合う第１カソード領域８２の間には、第２カソード領域８３が設けられる。本例の半導体装置１００は、９個のフローティング領域１７のうち、４個のフローティング領域１７が、第１カソード領域８２と第２カソード領域８３とのＸ軸方向の境界と重なって設けられる。９個のフローティング領域１７のうち、５個のフローティング領域１７は、半導体基板１０の上面視で第１カソード領域８２の内側に設けられる。 FIG. 3c is an enlarged view of region C2 in FIG. 3b. As shown in FIG. 3C, in the semiconductor device 100 of this example, nine first cathode regions 82 are provided in the Y-axis direction as an example. A second cathode region 83 is provided between adjacent first cathode regions 82 in the Y-axis direction. In the semiconductor device 100 of this example, four floating regions 17 out of nine floating regions 17 are provided so as to overlap with the boundary in the X-axis direction between the first cathode region 82 and the second cathode region 83. Of the nine floating regions 17, five floating regions 17 are provided inside the first cathode region 82 in a top view of the semiconductor substrate 10.
　幅Ｗｆｎ１は、第１カソード領域８２と、当該第１カソード領域８２にＹ軸方向負側で隣接する第２カソード領域８３との境界と重なって設けられるフローティング領域１７の、Ｙ軸方向負側の端から当該境界までのＹ軸方向における幅である。また、幅Ｗｆｎ１は、第１カソード領域８２と、当該第１カソード領域８２にＹ軸方向正側で隣接する第２カソード領域８３との境界と重なって設けられるフローティング領域１７の、Ｙ軸方向正側の端から当該境界までのＹ軸方向における幅である。 The width Wfn1 is such that the floating region 17 provided on the negative side in the Y-axis direction of the floating region 17 provided to overlap the boundary between the first cathode region 82 and the second cathode region 83 adjacent to the first cathode region 82 on the negative side in the Y-axis direction. It is the width in the Y-axis direction from the end to the boundary. In addition, the width Wfn1 is the positive value in the Y-axis direction of the floating region 17 provided to overlap the boundary between the first cathode region 82 and the second cathode region 83 adjacent to the first cathode region 82 on the Y-axis direction positive side. This is the width in the Y-axis direction from the side end to the boundary.
　幅Ｗｆｆ１１は、フローティング領域１７と、当該フローティング領域１７に隣り合うフローティング領域１７とのＹ軸方向における間隔である。複数のフローティング領域１７の全てが、幅Ｗｆｆ１１の間隔でＹ軸方向に配列されてよいが、第１カソード領域８２と第２カソード領域８３との境界と重なるフローティング領域１７があれば、幅Ｗｆｆ１１と異なる間隔で配列されるフローティング領域１７があってもよい。 The width Wff11 is an interval in the Y-axis direction between the floating region 17 and the floating region 17 adjacent to the floating region 17. All of the plurality of floating regions 17 may be arranged in the Y-axis direction at intervals of the width Wff11. However, if there is the floating region 17 that overlaps the boundary between the first cathode region 82 and the second cathode region 83, the width Wff11 There may be floating regions 17 arranged at different intervals.
　幅Ｗｆｎ１は、幅Ｗｆｌ１２よりも小さい。幅Ｗｆｎ１は、幅Ｗｃｆ１と等しくてもよいし、異なっていてもよい。 Width Wfn1 is smaller than width Wfl12. The width Wfn1 may be equal to or different from the width Wcf1.
　図３ｄは、図３ｂにおけるｃ－ｃ'断面の一例を示す図である。本例の半導体装置１００は、ｃ－ｃ'断面において、半導体基板１０、層間絶縁膜３８、エミッタ電極５２およびコレクタ電極２４を有する。エミッタ電極５２は、半導体基板１０の上面２１および層間絶縁膜３８の上面に設けられる。コレクタ電極２４は、半導体基板１０の下面２３に設けられる。 FIG. 3d is a diagram showing an example of a cross section along the line cc ′ in FIG. 3b. The semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in the section cc ′. The emitter electrode 52 is provided on the upper surface 21 of the semiconductor substrate 10 and the upper surface of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10.
　本例の半導体装置１００は、ダイオード部８０において、第１カソード領域８２の上方にフローティング領域１７が設けられる。フローティング領域１７は、ｃ－ｃ'断面において、Ｙ軸方向に一例として９つ設けられる。フローティング領域１７は、第１カソード領域８２と接して設けられてよい。 In the semiconductor device 100 of this example, the floating region 17 is provided above the first cathode region 82 in the diode portion 80. As an example, nine floating regions 17 are provided in the Y-axis direction in the section cc ′. The floating region 17 may be provided in contact with the first cathode region 82.
　複数のフローティング領域１７のうち、一部のフローティング領域１７は、第１カソード領域８２と第２カソード領域８３との境界の上方に設けられる。当該境界の上方に設けられるフローティング領域１７は、当該第１カソード領域８２および当該第２カソード領域８３の双方に接して設けられる。本例の半導体装置１００においては、９つのフローティング領域１７のうち、４つのフローティング領域１７が、当該境界の上方に、第１カソード領域８２および第２カソード領域８３の双方に接して設けられる。本例の半導体装置１００は、第２導電型の第２カソード領域８３と第２導電型のフローティング領域１７とが接して設けられるので、図２ｄに示す半導体装置１００よりも、ダイオード部８０の逆回復時のサージ電圧を、さらに抑制することができる。 Among the plurality of floating regions 17, some floating regions 17 are provided above the boundary between the first cathode region 82 and the second cathode region 83. The floating region 17 provided above the boundary is provided in contact with both the first cathode region 82 and the second cathode region 83. In the semiconductor device 100 of this example, four floating regions 17 out of the nine floating regions 17 are provided in contact with both the first cathode region 82 and the second cathode region 83 above the boundary. In the semiconductor device 100 of this example, since the second conductivity type second cathode region 83 and the second conductivity type floating region 17 are provided in contact with each other, the diode unit 80 is more reverse than the semiconductor device 100 shown in FIG. The surge voltage at the time of recovery can be further suppressed.
　図３ｅは、図３ｂにおけるｄ－ｄ'断面の一例を示す図である。ｄ－ｄ'断面は、図３ｄにおけるｄ''－ｄ'''線を通るＸＺ平面である。本例の半導体装置１００におけるｄ－ｄ'断面の構成は、図２ｅに示す半導体装置１００におけるｂ－ｂ'断面の構成と同じである。 FIG. 3e is a diagram showing an example of a dd ′ cross section in FIG. 3b. The dd ′ cross section is an XZ plane passing through a d ″ -d ′ ″ line in FIG. 3D. The configuration of the section dd ′ in the semiconductor device 100 of this example is the same as the configuration of the section bb ′ in the semiconductor device 100 shown in FIG. 2e.
　図４ａは、図１ａにおける領域Ａの他の拡大図である。本例の半導体装置１００は、図２ａに示す半導体装置１００において、第１カソード領域８２および第２カソード領域８３が、半導体基板１０の上面視で、Ｘ軸方向に交互に配置される点で、図２ａに示す半導体装置１００と異なる。第１カソード領域８２および第２カソード領域８３は、Ｙ軸方向正側および負側の双方において、トランジスタ部７０と接して設けられる。 FIG. 4a is another enlarged view of region A in FIG. 1a. The semiconductor device 100 of this example is different from the semiconductor device 100 shown in FIG. 2A in that the first cathode regions 82 and the second cathode regions 83 are alternately arranged in the X-axis direction when the semiconductor substrate 10 is viewed from above. Different from the semiconductor device 100 shown in FIG. The first cathode region 82 and the second cathode region 83 are provided in contact with the transistor unit 70 on both the Y axis direction positive side and the negative side.
　ダイオード部８０において、半導体基板１０の上面視における第１カソード領域８２と第２カソード領域８３との合計面積に占める第１カソード領域８２の面積の割合は、６０％以上９０％以下であってよい。当該合計面積に占める第２カソード領域８３の面積の割合は、１０％以上４０％以下であってよい。一例として、当該合計面積に占める第１カソード領域８２の面積および第２カソード領域８３の面積は、それぞれ８０％および２０％である。 In the diode portion 80, the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82 and the second cathode region 83 in the top view of the semiconductor substrate 10 may be 60% or more and 90% or less. . The ratio of the area of the second cathode region 83 to the total area may be 10% or more and 40% or less. As an example, the area of the first cathode region 82 and the area of the second cathode region 83 occupying the total area are 80% and 20%, respectively.
　本例の半導体装置１００は、第１カソード領域８２毎に互いに分離して設けられた複数のフローティング領域１７を有する。本例の半導体装置１００は、第１カソード領域８２が、半導体基板１０の上面視で、フローティング領域１７よりも配列方向に張り出している。本例の半導体装置１００は、配列方向において、第１カソード領域８２の両側が、半導体基板１０の上面視でフローティング領域１７よりも配列方向に張り出している。即ち、第１カソード領域８２は、Ｙ軸方向におけるフローティング領域１７の両側において、フローティング領域１７に覆われていない部分を有する。なお、配列方向において、第１カソード領域８２の片側が、半導体基板１０の上面視でフローティング領域１７よりも配列方向に張り出していてもよい。 The semiconductor device 100 of this example has a plurality of floating regions 17 provided separately for each first cathode region 82. In the semiconductor device 100 of this example, the first cathode region 82 protrudes in the arrangement direction from the floating region 17 in a top view of the semiconductor substrate 10. In the semiconductor device 100 of this example, both sides of the first cathode region 82 protrude in the arrangement direction from the floating region 17 in a top view of the semiconductor substrate 10 in the arrangement direction. That is, the first cathode region 82 has portions that are not covered by the floating region 17 on both sides of the floating region 17 in the Y-axis direction. In the arrangement direction, one side of the first cathode region 82 may protrude from the floating region 17 in the arrangement direction when the semiconductor substrate 10 is viewed from above.
　また、本例の半導体装置１００は、第１カソード領域８２が、フローティング領域１７よりも延伸方向に張り出している。本例の半導体装置１００は、延伸方向において、第１カソード領域８２の両側が、半導体基板１０の上面視でフローティング領域１７よりも延伸方向に張り出している。即ち、第１カソード領域８２は、Ｘ軸方向におけるフローティング領域１７の両側において、フローティング領域１７に覆われていない部分を有する。なお、延伸方向において、第１カソード領域８２の片側が、半導体基板１０の上面視でフローティング領域１７よりも延伸方向に張り出していてもよい。 Further, in the semiconductor device 100 of this example, the first cathode region 82 protrudes in the extending direction from the floating region 17. In the semiconductor device 100 of this example, both sides of the first cathode region 82 project in the extending direction from the floating region 17 in a top view of the semiconductor substrate 10 in the extending direction. That is, the first cathode region 82 has portions that are not covered by the floating region 17 on both sides of the floating region 17 in the X-axis direction. Note that, in the extending direction, one side of the first cathode region 82 may protrude from the floating region 17 in the extending direction in a top view of the semiconductor substrate 10.
　本例の半導体装置１００は、半導体基板１０の上面視で、フローティング領域１７の全体が、第１カソード領域８２と重なって配置される。即ち、半導体基板１０の上面視で、第１カソード領域８２の内側に、フローティング領域１７を有する。 In the semiconductor device 100 of this example, the entire floating region 17 is disposed so as to overlap the first cathode region 82 in a top view of the semiconductor substrate 10. That is, the floating region 17 is provided inside the first cathode region 82 when the semiconductor substrate 10 is viewed from above.
　フローティング領域１７は、半導体基板１０の上面視で、トランジスタ部７０とは重ならないように配置される。フローティング領域１７は、ダイオード部８０とトランジスタ部７０との境界にも接しないように配置される。 The floating region 17 is arranged so as not to overlap the transistor portion 70 when the semiconductor substrate 10 is viewed from above. The floating region 17 is arranged so as not to contact the boundary between the diode portion 80 and the transistor portion 70.
　図４ｂは、図４ａにおける領域Ｂ３の拡大図である。図４ｂは、図４ａにおけるダイオード部８０のＸ軸方向正側のウェル領域１１の端ＳからＸ軸方向負側のウェル領域１１の端Ｓ'までを、拡大して示している。図２ｂに示す通り、本例の半導体装置１００は、ダイオード部８０において、第１カソード領域８２のＸＹ平面内における内側に、フローティング領域１７が、一例として１０個設けられる。 FIG. 4b is an enlarged view of region B3 in FIG. 4a. FIG. 4B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 4A to the end S ′ of the well region 11 on the X axis direction negative side. As shown in FIG. 2B, in the semiconductor device 100 of this example, in the diode portion 80, ten floating regions 17 are provided as an example inside the first cathode region 82 in the XY plane.
　本例の半導体装置１００において、幅Ｗｃｆ１および幅Ｗｃｆ２は、それぞれ図２ｂに示す例における幅Ｗｃｆ１および幅Ｗｃｆ２と同じであってよい。幅Ｗｃｆ１は、ゼロでなければよい。幅Ｗｃｆ２は、ゼロであってもよい。 In the semiconductor device 100 of this example, the width Wcf1 and the width Wcf2 may be the same as the width Wcf1 and the width Wcf2 in the example illustrated in FIG. The width Wcf1 may not be zero. The width Wcf2 may be zero.
　本例の半導体装置１００において、幅Ｗｎｆ２は、第１カソード領域８２と、当該第１カソード領域８２にＸ軸方向負側で隣接する第２カソード領域８３との境界から、当該第１カソード領域８２に重なって設けられるフローティング領域１７のＸ軸方向負側の端までの、Ｘ軸方向における幅である。また、幅Ｗｎｆ２は、第１カソード領域８２と、当該第１カソード領域８２にＸ軸方向正側で隣接する第２カソード領域８３との境界から、当該第１カソード領域８２に重なって設けられるフローティング領域１７のＸ軸方向正側の端までの、Ｘ軸方向における幅である。幅Ｗｎｆ２は、幅Ｗｃｆ２と同じであってよいが、異なっていてもよい。 In the semiconductor device 100 of this example, the width Wnf2 is determined from the boundary between the first cathode region 82 and the second cathode region 83 adjacent to the first cathode region 82 on the negative side in the X-axis direction. Is the width in the X-axis direction up to the end on the negative side in the X-axis direction of the floating region 17 provided to overlap. The width Wnf2 is a floating provided to overlap the first cathode region 82 from the boundary between the first cathode region 82 and the second cathode region 83 adjacent to the first cathode region 82 on the X axis direction positive side. This is the width in the X-axis direction up to the end on the X-axis direction positive side of the region 17. The width Wnf2 may be the same as the width Wcf2, but may be different.
　本例の半導体装置１００において、幅Ｗｃｈ２は、第１カソード領域８２および第２カソード領域８３のＹ軸方向の幅である。幅Ｗｃｈは、幅ＷＦに等しい。幅Ｗｃｖ２は、第１カソード領域８２のＸ軸方向の幅である。また、幅Ｗｆｌ１３は、フローティング領域１７のＹ軸方向の幅である。幅Ｗｆｌ２２は、フローティング領域１７のＸ軸方向の幅である。 In the semiconductor device 100 of this example, the width Wch2 is the width of the first cathode region 82 and the second cathode region 83 in the Y-axis direction. The width Wch is equal to the width WF. The width Wcv2 is the width of the first cathode region 82 in the X-axis direction. The width Wfl13 is the width of the floating region 17 in the Y-axis direction. The width Wfl22 is the width of the floating region 17 in the X-axis direction.
　それぞれの第１カソード領域８２において、フローティング領域１７のＹ軸方向の幅Ｗｆｌ１３は、幅Ｗｃｈ２の８９％以上９５％以下であってよい。それぞれの第１カソード領域８２において、フローティング領域１７のＸ軸方向の幅Ｗｆｌ２２は、幅Ｗｃｖ２の８９％以上９５％以下であってよい。 In each first cathode region 82, the width Wfl13 of the floating region 17 in the Y-axis direction may be 89% or more and 95% or less of the width Wch2. In each first cathode region 82, the width Wfl22 of the floating region 17 in the X-axis direction may be 89% or more and 95% or less of the width Wcv2.
　それぞれの第１カソード領域８２において、半導体基板１０の上面視で、第１カソード領域８２の面積に占めるフローティング領域１７の面積は、８０％以上９０％以下であってよい。半導体基板１０の上面視における第１カソード領域８２と第２カソード領域８３との合計面積に占める第１カソード領域８２の面積および第２カソード領域８３の面積が、それぞれ８０％および２０％の場合、当該面積に占めるフローティング領域１７の面積の割合は、６４％以上７２％以下であってよい。 In each first cathode region 82, the area of the floating region 17 occupying the area of the first cathode region 82 in the top view of the semiconductor substrate 10 may be 80% or more and 90% or less. When the area of the first cathode region 82 and the area of the second cathode region 83 in the total area of the first cathode region 82 and the second cathode region 83 in the top view of the semiconductor substrate 10 are 80% and 20%, respectively, The ratio of the area of the floating region 17 to the area may be 64% or more and 72% or less.
　図４ｃは、図４ｂにおけるｅ－ｅ'断面の一例を示す図である。本例の半導体装置１００は、ｅ－ｅ'断面において、半導体基板１０、層間絶縁膜３８、エミッタ電極５２およびコレクタ電極２４を有する。エミッタ電極５２は、半導体基板１０の上面２１および層間絶縁膜３８の上面に設けられる。コレクタ電極２４は、半導体基板１０の下面２３に設けられる。 FIG. 4c is a diagram showing an example of a cross section taken along line ee ′ in FIG. 4b. The semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in the ee ′ cross section. The emitter electrode 52 is provided on the upper surface 21 of the semiconductor substrate 10 and the upper surface of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10.
　本例の半導体装置１００は、ダイオード部８０において、第１カソード領域８２の上方にフローティング領域１７が設けられる。フローティング領域１７は、ｅ－ｅ'断面において、端部位置Ｐ２から端部位置Ｐ２'にわたり、連続して設けられる。フローティング領域１７は、第１カソード領域８２と接して設けられてよい。 In the semiconductor device 100 of this example, the floating region 17 is provided above the first cathode region 82 in the diode portion 80. The floating region 17 is continuously provided from the end position P2 to the end position P2 ′ in the ee ′ cross section. The floating region 17 may be provided in contact with the first cathode region 82.
　図４ｄは、図４ｂにおけるｆ－ｆ'断面の一例を示す図である。ｆ－ｆ'断面は、図４ｃにおけるｆ''－ｆ'''線を通るＸＺ平面である。フローティング領域１７は、ｆ－ｆ'断面において、Ｘ軸方向に一例として１０個設けられる。フローティング領域１７は、第１カソード領域８２と接してよい。本例の半導体装置１００において、幅Ｗｎｆ２は、幅Ｗｃｆ２と同じであってよいが、異なっていてもよい。フローティング領域１７のＸ軸方向の幅Ｗｆｌ２２は、幅Ｗｃｖ２の８９％以上９５％以下であってよい。本例の半導体装置１００は、ダイオード部８０において、フローティング領域１７を第１カソード領域８２の上方に設けているので、ダイオード部８０の逆回復時のサージ電圧（オーバーシュート電圧）を抑制することができる。 FIG. 4d is a diagram showing an example of the ff ′ cross section in FIG. 4b. The ff ′ cross section is an XZ plane passing through the f ″ -f ′ ″ line in FIG. 4C. As an example, 10 floating regions 17 are provided in the X-axis direction in the ff ′ cross section. The floating region 17 may be in contact with the first cathode region 82. In the semiconductor device 100 of this example, the width Wnf2 may be the same as the width Wcf2, but may be different. The width Wfl22 of the floating region 17 in the X-axis direction may be 89% or more and 95% or less of the width Wcv2. In the semiconductor device 100 of this example, since the floating region 17 is provided above the first cathode region 82 in the diode unit 80, the surge voltage (overshoot voltage) during reverse recovery of the diode unit 80 can be suppressed. it can.
　図５ａは、図１ａにおける領域Ａの他の拡大図である。本例の半導体装置１００は、図４ａに示す半導体装置において、複数のフローティング領域１７のうち、一部のフローティング領域１７が、半導体基板１０の上面視で、第１カソード領域８２および第２カソード領域８３の両方と重なって、Ｘ軸方向に複数設けられる点で、図２ａに示す半導体装置１００と異なる。即ち、本例の半導体装置１００は、複数のフローティング領域１７のうち一部のフローティング領域１７が、半導体基板１０の上面視で、第１カソード領域８２と第２カソード領域８３とのＹ軸方向の境界と重なって、Ｘ軸方向に、第１カソード領域８２から第２カソード領域８３にわたって設けられる。 FIG. 5a is another enlarged view of region A in FIG. 1a. In the semiconductor device 100 of this example, in the semiconductor device illustrated in FIG. 4A, some floating regions 17 among the plurality of floating regions 17 are the first cathode region 82 and the second cathode region in the top view of the semiconductor substrate 10. The semiconductor device 100 differs from the semiconductor device 100 shown in FIG. That is, in the semiconductor device 100 of this example, some floating regions 17 among the plurality of floating regions 17 are in the Y-axis direction between the first cathode region 82 and the second cathode region 83 when the semiconductor substrate 10 is viewed from above. It overlaps with the boundary and is provided from the first cathode region 82 to the second cathode region 83 in the X-axis direction.
　図５ｂは、図５ａにおける領域Ｂ４の拡大図である。図５ｂは、図５ａにおけるダイオード部８０のＸ軸方向正側のウェル領域１１の端ＳからＸ軸方向負側のウェル領域１１の端Ｓ'までを、拡大して示している。 FIG. 5b is an enlarged view of region B4 in FIG. 5a. FIG. 5b shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 5a to the end S ′ of the well region 11 on the X axis direction negative side.
　本例の半導体装置１００は、図５ｂに示す通り、本例の半導体装置１００は、ダイオード部８０において、フローティング領域１７が、一例として３０個設けられる。本例の半導体装置１００は、一例として第１カソード領域８２が１０個設けられ、第２カソード領域８３が９個設けられるので、第１カソード領域８２と第２カソード領域８３とのＹ軸方向に平行な境界が１８か所存在する。このため、３０個のフローティング領域１７のうち、１８個のフローティング領域１７が、それぞれ当該境界と重なって設けられる。 As shown in FIG. 5B, the semiconductor device 100 of this example is provided with 30 floating regions 17 as an example in the diode unit 80. As an example, the semiconductor device 100 of this example is provided with ten first cathode regions 82 and nine second cathode regions 83, and therefore, in the Y-axis direction between the first cathode region 82 and the second cathode region 83. There are 18 parallel boundaries. For this reason, of the 30 floating regions 17, 18 floating regions 17 are provided so as to overlap with the boundary respectively.
　Ｘ軸方向の最も正側に設けられる第１カソード領域８２は、当該第１カソード領域８２のＸ軸方向正側に設けられるコレクタ領域２２と隣接する。１つのフローティング領域１７が、当該第１カソード領域８２と当該コレクタ領域２２とのＹ軸方向に平行な境界と重なって設けられる。また、Ｘ軸方向の最も負側に設けられる第１カソード領域８２は、当該第１カソード領域８２のＸ軸方向負側に設けられるコレクタ領域２２と隣接する。他の１つのフローティング領域１７が、当該第１カソード領域８２と当該コレクタ領域２２とのＹ軸方向に平行な境界と重なって設けられる。３０個のフローティング領域１７のうち、残りの１０個のフローティング領域１７は、半導体基板１０の上面視で第１カソード領域８２の内側に設けられる。 The first cathode region 82 provided on the most positive side in the X-axis direction is adjacent to the collector region 22 provided on the X-axis direction positive side of the first cathode region 82. One floating region 17 is provided so as to overlap with a boundary parallel to the Y-axis direction between the first cathode region 82 and the collector region 22. The first cathode region 82 provided on the most negative side in the X-axis direction is adjacent to the collector region 22 provided on the X-axis direction negative side of the first cathode region 82. Another one floating region 17 is provided so as to overlap with a boundary parallel to the Y-axis direction between the first cathode region 82 and the collector region 22. Of the 30 floating regions 17, the remaining 10 floating regions 17 are provided inside the first cathode region 82 in a top view of the semiconductor substrate 10.
　それぞれの第１カソード領域８２において、半導体基板１０の上面視で、第１カソード領域８２の面積に占めるフローティング領域１７の面積は、８０％以上９０％以下であってよい。半導体基板１０の上面視における第１カソード領域８２と第２カソード領域８３との合計面積に占める第１カソード領域８２の面積および第２カソード領域８３の面積が、それぞれ８０％および２０％の場合、当該面積に占めるフローティング領域１７の面積の割合は、６４％以上７２％以下であってよい。 In each first cathode region 82, the area of the floating region 17 occupying the area of the first cathode region 82 in the top view of the semiconductor substrate 10 may be 80% or more and 90% or less. When the area of the first cathode region 82 and the area of the second cathode region 83 in the total area of the first cathode region 82 and the second cathode region 83 in the top view of the semiconductor substrate 10 are 80% and 20%, respectively, The ratio of the area of the floating region 17 to the area may be 64% or more and 72% or less.
　本例の半導体装置１００において、幅Ｗｃｆ１は、図４ｂに示す例における幅Ｗｃｆ１と同じであってよい。幅Ｗｃｆ１は、ゼロでなければよい。 In the semiconductor device 100 of this example, the width Wcf1 may be the same as the width Wcf1 in the example illustrated in FIG. The width Wcf1 may not be zero.
　本例の半導体装置１００において、フローティング領域１７のＹ軸方向の幅Ｗｆｌ１３は、図４ｂに示す例における幅Ｗｆｌ１３と同じであってよい。フローティング領域１７のＸ軸方向の幅Ｗｆｌ２３は、図４ｂに示す例における幅Ｗｆｌ２２よりも小さくてよい。 In the semiconductor device 100 of this example, the width Wfl13 of the floating region 17 in the Y-axis direction may be the same as the width Wfl13 in the example illustrated in FIG. The width Wfl23 in the X-axis direction of the floating region 17 may be smaller than the width Wfl22 in the example illustrated in FIG.
　本例の半導体装置１００において、幅Ｗｆｃ２は、Ｘ軸方向の最も正側に設けられるフローティング領域１７のＸ軸方向正側の端から、Ｘ軸方向の最も正側に設けられる第１カソード領域８２とＸ軸方向正側に設けられるコレクタ領域２２とのＹ軸方向に平行な境界までの、Ｘ軸方向における幅である。また、幅Ｗｆｃ２は、Ｘ軸方向の最も負側に設けられるフローティング領域１７のＸ軸方向負側の端から、Ｘ軸方向の最も負側に設けられる第１カソード領域８２とＸ軸方向負側に設けられるコレクタ領域２２とのＹ軸方向に平行な境界までの、Ｘ軸方向における幅である。 In the semiconductor device 100 of this example, the width Wfc2 is the first cathode region 82 provided on the most positive side in the X-axis direction from the end on the positive side in the X-axis direction of the floating region 17 provided on the most positive side in the X-axis direction. And the width in the X-axis direction to the boundary parallel to the Y-axis direction between the collector region 22 provided on the positive side in the X-axis direction. The width Wfc2 is equal to the first cathode region 82 provided on the most negative side in the X-axis direction from the end on the negative side in the X-axis direction of the floating region 17 provided on the most negative side in the X-axis direction. The width in the X-axis direction to the boundary parallel to the Y-axis direction with the collector region 22 provided in
　図５ｃは、図５ｂにおける領域Ｃ４の拡大図である。図５ｃに示す通り、本例の半導体装置１００は、第１カソード領域８２および第２カソード領域８３が、トランジスタ部７０のＹ軸方向正側の境界から負側の境界まで設けられる。図５ｃにおいてＸ軸方向の最も負側に設けられるフローティング領域１７は、半導体基板１０の上面視で、第１カソード領域８２および第２カソード領域８３と重なって設けられる。図５ｃにおいてＸ軸方向の最も正側に設けられるフローティング領域１７は、半導体基板１０の上面視で、第１カソード領域８２およびコレクタ領域２２と重なって設けられる。図５ｃにおいてＸ軸方向中央に設けられるフローティング領域１７は、半導体基板１０の上面視で、第１カソード領域８２と重なって設けられる。 FIG. 5c is an enlarged view of region C4 in FIG. 5b. As shown in FIG. 5c, in the semiconductor device 100 of this example, the first cathode region 82 and the second cathode region 83 are provided from the boundary on the Y axis direction positive side to the negative side boundary of the transistor unit 70. In FIG. 5 c, the floating region 17 provided on the most negative side in the X-axis direction is provided so as to overlap the first cathode region 82 and the second cathode region 83 when the semiconductor substrate 10 is viewed from above. In FIG. 5 c, the floating region 17 provided on the most positive side in the X-axis direction is provided so as to overlap the first cathode region 82 and the collector region 22 in a top view of the semiconductor substrate 10. The floating region 17 provided in the center in the X-axis direction in FIG.
　本例の半導体装置１００において、幅Ｗｆｎ２は、第１カソード領域８２と、当該第１カソード領域８２にＸ軸方向負側で隣接する第２カソード領域８３との境界から、当該第１カソード領域８２に重なって設けられるフローティング領域１７のＸ軸方向負側の端までの、Ｘ軸方向における幅である。また、幅Ｗｆｎ２は、領域Ｃ４の外ではあるが、第１カソード領域８２と、当該第１カソード領域８２にＸ軸方向正側で隣接する第２カソード領域８３との境界から、当該第１カソード領域８２に重なって設けられるフローティング領域１７のＸ軸方向正側の端までの、Ｘ軸方向における幅である。 In the semiconductor device 100 of this example, the width Wfn2 is determined from the boundary between the first cathode region 82 and the second cathode region 83 adjacent to the first cathode region 82 on the negative side in the X-axis direction. Is the width in the X-axis direction up to the end on the negative side in the X-axis direction of the floating region 17 provided to overlap. In addition, the width Wfn2 is outside the region C4, but from the boundary between the first cathode region 82 and the second cathode region 83 adjacent to the first cathode region 82 on the positive side in the X-axis direction, This is the width in the X-axis direction to the end on the positive side in the X-axis direction of the floating region 17 provided so as to overlap the region 82.
　本例の半導体装置１００において、幅Ｗｆｆ２１は、フローティング領域１７と、当該フローティング領域１７に隣り合うフローティング領域１７とのＸ軸方向における間隔である。複数のフローティング領域１７の全てが、幅Ｗｆｆ２１の間隔でＸ軸方向に配列されてよいが、第１カソード領域８２と第２カソード領域８３との境界と重なるフローティング領域１７があれば、幅Ｗｆｆ２１と異なる間隔で配列されるフローティング領域１７があってもよい。 In the semiconductor device 100 of this example, the width Wff21 is an interval in the X-axis direction between the floating region 17 and the floating region 17 adjacent to the floating region 17. All of the plurality of floating regions 17 may be arranged in the X-axis direction at intervals of the width Wff21. However, if there is the floating region 17 that overlaps the boundary between the first cathode region 82 and the second cathode region 83, the width Wff21 There may be floating regions 17 arranged at different intervals.
　幅Ｗｆｎ２は、幅Ｗｆｌ２３よりも小さい。幅Ｗｆｎ２は、幅Ｗｆｃ２と等しくてもよいが、異なっていてもよい。 Width Wfn2 is smaller than width Wfl23. The width Wfn2 may be equal to the width Wfc2, but may be different.
　図５ｄは、図５ｂにおけるｇ－ｇ'断面の一例を示す図である。本例の半導体装置１００におけるｄ－ｄ'断面の構成は、図４ｃに示す半導体装置１００におけるｅ－ｅ'断面の構成と同じである。 FIG. 5d is a diagram showing an example of a gg ′ cross section in FIG. 5b. The configuration of the dd ′ section in the semiconductor device 100 of this example is the same as the configuration of the ee ′ section in the semiconductor device 100 shown in FIG. 4c.
　図５ｅは、図５ｂにおけるｈ－ｈ'断面の一例を示す図である。ｈ－ｈ'断面は、図５ｄにおけるｈ''－ｈ'''線を通るＸＺ平面である。本例の半導体装置１００は、ダイオード部８０において、第１カソード領域８２の上方にフローティング領域１７が設けられる。フローティング領域１７は、第１カソード領域８２と接して設けられてよい。 FIG. 5e is a diagram showing an example of the hh ′ cross section in FIG. 5b. The hh ′ cross section is the XZ plane passing through the h ″ -h ′ ″ line in FIG. 5D. In the semiconductor device 100 of this example, the floating region 17 is provided above the first cathode region 82 in the diode unit 80. The floating region 17 may be provided in contact with the first cathode region 82.
　本例の半導体装置１００は、Ｘ軸方向の最も負側の第１カソード領域８２のＸ軸方向負側の端部位置Ｐ６''が、境界位置Ｐ５よりもＸ軸方向負側に設けられる。また、Ｘ軸方向の最も正側の第１カソード領域８２のＸ軸方向正側の端部位置Ｐ６'''が、境界位置Ｐ５'よりもＸ軸方向正側に設けられる。幅Ｗｆｃ２は、境界位置Ｐ５から端部位置Ｐ６''までのＸ軸方向における幅である。また、幅Ｗｆｃ２は、境界位置Ｐ５'から端部位置Ｐ６'''までのＸ軸方向における幅である。 In the semiconductor device 100 of this example, the end position P6 ″ on the X axis direction negative side of the first cathode region 82 on the most negative side in the X axis direction is provided on the X axis direction negative side with respect to the boundary position P5. Further, the end position P6 ′ ″ on the X axis direction positive side of the first cathode region 82 on the most positive side in the X axis direction is provided on the X axis direction positive side with respect to the boundary position P5 ′. The width Wfc2 is a width in the X-axis direction from the boundary position P5 to the end position P6 ″. The width Wfc2 is a width in the X-axis direction from the boundary position P5 ′ to the end position P6 ′ ″.
　複数のフローティング領域１７のうち、一部のフローティング領域１７は、第１カソード領域８２と第２カソード領域８３との境界の上方に設けられる。当該境界の上方に設けられるフローティング領域１７は、当該第１カソード領域８２および当該第２カソード領域８３の双方に接して設けられる。また、Ｘ軸方向の最も負側および最も正側に設けられるフローティング領域１７は、それぞれ境界位置Ｐ５および境界位置Ｐ５'の上方に設けられる。境界位置Ｐ５の上方に設けられるフローティング領域１７は、Ｘ軸方向の最も負側の第１カソード領域８２とＸ軸方向負側のコレクタ領域２２との双方に接して設けられる。また、境界位置Ｐ５'の上方に設けられるフローティング領域１７は、Ｘ軸方向の最も正側の第１カソード領域８２とＸ軸方向正側のコレクタ領域２２との双方に接して設けられる。 Among the plurality of floating regions 17, some floating regions 17 are provided above the boundary between the first cathode region 82 and the second cathode region 83. The floating region 17 provided above the boundary is provided in contact with both the first cathode region 82 and the second cathode region 83. The floating regions 17 provided on the most negative side and the most positive side in the X-axis direction are provided above the boundary position P5 and the boundary position P5 ′, respectively. The floating region 17 provided above the boundary position P5 is provided in contact with both the first cathode region 82 on the most negative side in the X-axis direction and the collector region 22 on the negative side in the X-axis direction. The floating region 17 provided above the boundary position P5 ′ is provided in contact with both the first cathode region 82 on the most positive side in the X-axis direction and the collector region 22 on the positive side in the X-axis direction.
　本例の半導体装置１００は、第２導電型の第２カソード領域８３と第２導電型のフローティング領域１７とが接して設けられる。このため、図４ｄに示す半導体装置１００よりも、ダイオード部８０の逆回復時のサージ電圧を、さらに抑制することができる。 In the semiconductor device 100 of this example, the second conductivity type second cathode region 83 and the second conductivity type floating region 17 are provided in contact with each other. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be further suppressed than the semiconductor device 100 shown in FIG.
　図６ａは、図１ａにおける領域Ａの他の拡大図である。本例の半導体装置１００は、半導体基板１０の上面視で、第１カソード領域８２が互いに分離して格子状に設けられる。格子状とは、第１カソード領域８２が、Ｘ軸方向およびＹ軸方向の双方に、周期的に配列されることを指す。図６ａは、第１カソード領域８２が、Ｘ軸方向に１０個設けられ、Ｙ軸方向に３個設けられる一例を示している。 FIG. 6a is another enlarged view of region A in FIG. 1a. In the semiconductor device 100 of this example, the first cathode regions 82 are separated from each other and provided in a lattice shape when the semiconductor substrate 10 is viewed from above. The lattice shape means that the first cathode regions 82 are periodically arranged in both the X-axis direction and the Y-axis direction. FIG. 6a shows an example in which ten first cathode regions 82 are provided in the X-axis direction and three in the Y-axis direction.
　半導体基板１０の上面視で、Ｙ軸方向に隣り合う２つの第１カソード領域８２の間には、第２カソード領域８３が設けられる。Ｘ軸方向に隣り合う２つの第１カソード領域８２の間には、第３カソード領域８４が設けられる。半導体基板１０の上面視で、Ｘ軸方向に隣り合う２つの第２カソード領域８３の間にも、第３カソード領域８４が設けられる。 A second cathode region 83 is provided between two first cathode regions 82 adjacent to each other in the Y-axis direction when the semiconductor substrate 10 is viewed from above. A third cathode region 84 is provided between two first cathode regions 82 adjacent in the X-axis direction. A third cathode region 84 is also provided between two second cathode regions 83 adjacent in the X-axis direction when the semiconductor substrate 10 is viewed from above.
　本例の半導体装置１００は、第１カソード領域８２毎に互いに分離して設けられた複数のフローティング領域１７を有する。本例の半導体装置１００は、第１カソード領域８２が、半導体基板１０の上面視でフローティング領域１７よりも配列方向に張り出している。本例の半導体装置１００は、配列方向において、第１カソード領域８２の両側が、半導体基板１０の上面視でフローティング領域１７よりも配列方向に張り出している。即ち、第１カソード領域８２は、Ｙ軸方向におけるフローティング領域１７の両側において、フローティング領域１７に覆われていない部分を有する。 The semiconductor device 100 of this example has a plurality of floating regions 17 provided separately for each first cathode region 82. In the semiconductor device 100 of this example, the first cathode region 82 protrudes in the arrangement direction from the floating region 17 in a top view of the semiconductor substrate 10. In the semiconductor device 100 of this example, both sides of the first cathode region 82 protrude in the arrangement direction from the floating region 17 in a top view of the semiconductor substrate 10 in the arrangement direction. That is, the first cathode region 82 has portions that are not covered by the floating region 17 on both sides of the floating region 17 in the Y-axis direction.
　また、本例の半導体装置１００は、第１カソード領域８２が、フローティング領域１７よりも延伸方向に張り出している。本例の半導体装置１００は、延伸方向において、第１カソード領域８２の両側が、半導体基板１０の上面視でフローティング領域１７よりも延伸方向に張り出している。即ち、第１カソード領域８２は、Ｘ軸方向におけるフローティング領域１７の両側において、フローティング領域１７に覆われていない部分を有する。 Further, in the semiconductor device 100 of this example, the first cathode region 82 protrudes in the extending direction from the floating region 17. In the semiconductor device 100 of this example, both sides of the first cathode region 82 project in the extending direction from the floating region 17 in a top view of the semiconductor substrate 10 in the extending direction. That is, the first cathode region 82 has portions that are not covered by the floating region 17 on both sides of the floating region 17 in the X-axis direction.
　本例の半導体装置１００は、半導体基板１０の上面視で、フローティング領域１７の全体が、第１カソード領域８２と重なって配置される。即ち、半導体基板１０の上面視で、格子状に設けられた第１カソード領域８２の内側に、フローティング領域１７を有する。 In the semiconductor device 100 of this example, the entire floating region 17 is disposed so as to overlap the first cathode region 82 in a top view of the semiconductor substrate 10. That is, the floating region 17 is provided inside the first cathode region 82 provided in a lattice shape when the semiconductor substrate 10 is viewed from above.
　フローティング領域１７は、半導体基板１０の上面視で、トランジスタ部７０とは重ならないように配置される。フローティング領域１７は、ダイオード部８０とトランジスタ部７０との境界にも接しないように配置される。 The floating region 17 is arranged so as not to overlap the transistor portion 70 when the semiconductor substrate 10 is viewed from above. The floating region 17 is arranged so as not to contact the boundary between the diode portion 80 and the transistor portion 70.
　図６ｂは、図６ａにおける領域Ｂ５の拡大図である。図６ｂは、図６ａにおけるダイオード部８０のＸ軸方向正側のウェル領域１１の端ＳからＸ軸方向負側のウェル領域１１の端Ｓ'までを、拡大して示している。図６ｂに示す通り、本例の半導体装置１００は、それぞれの第１カソード領域８２のＸＹ平面内における内側に、フローティング領域１７が設けられる。 FIG. 6b is an enlarged view of region B5 in FIG. 6a. 6B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 6A to the end S ′ of the well region 11 on the X axis direction negative side. As shown in FIG. 6B, in the semiconductor device 100 of the present example, the floating region 17 is provided inside the first cathode region 82 in the XY plane.
　本例の半導体装置１００において、幅Ｗｃｆ１および幅Ｗｃｆ２は、それぞれ図２ｂに示す例における幅Ｗｃｆ１および幅Ｗｃｆ２と同じであってよい。幅Ｗｃｆ１は、ゼロでなければよい。幅Ｗｃｆ２は、ゼロであってもよい。 In the semiconductor device 100 of this example, the width Wcf1 and the width Wcf2 may be the same as the width Wcf1 and the width Wcf2 in the example illustrated in FIG. The width Wcf1 may not be zero. The width Wcf2 may be zero.
　本例の半導体装置１００において、幅Ｗｆｌ１１は、図２ｂに示す例における幅Ｗｆｌ１１と同じであってよい。幅Ｗｆｌ２２は、図４ｂに示す例における幅Ｗｆｌ２２と同じであってよい。幅Ｗｃｈ１は、図２ｂに示す例における幅Ｗｃｈ１と同じであってよい。幅Ｗｃｖ２は、図４ｂに示す例における幅Ｗｃｖ２と同じであってよい。 In the semiconductor device 100 of this example, the width Wfl11 may be the same as the width Wfl11 in the example illustrated in FIG. The width Wfl22 may be the same as the width Wfl22 in the example shown in FIG. 4b. The width Wch1 may be the same as the width Wch1 in the example illustrated in FIG. The width Wcv2 may be the same as the width Wcv2 in the example shown in FIG. 4b.
　それぞれの第１カソード領域８２において、フローティング領域１７のＹ軸方向の幅Ｗｆｌ１１は、幅Ｗｃｈ１の８９％以上９５％以下であってよい。また、それぞれの第１カソード領域８２において、フローティング領域１７のＸ軸方向の幅Ｗｆｌ２２は、幅Ｗｃｖ２の８９％以上９５％以下であってよい。 In each first cathode region 82, the width Wfl11 of the floating region 17 in the Y-axis direction may be 89% or more and 95% or less of the width Wch1. In each first cathode region 82, the width Wfl22 of the floating region 17 in the X-axis direction may be 89% or more and 95% or less of the width Wcv2.
　それぞれの第１カソード領域８２において、半導体基板１０の上面視で、第１カソード領域８２の面積に占めるフローティング領域１７の面積は、８０％以上９０％以下であってよい。半導体基板１０の上面視における第１カソード領域８２、第２カソード領域８３および第３カソード領域８４の合計面積に占める第１カソード領域８２の面積および第２カソード領域８３と第３カソード領域８４の合計面積が、それぞれ８０％および２０％の場合、当該面積に占めるフローティング領域１７の面積の割合は、６４％以上７２％以下であってよい。 In each first cathode region 82, the area of the floating region 17 occupying the area of the first cathode region 82 in the top view of the semiconductor substrate 10 may be 80% or more and 90% or less. The area of the first cathode region 82 and the total of the second cathode region 83 and the third cathode region 84 in the total area of the first cathode region 82, the second cathode region 83, and the third cathode region 84 in the top view of the semiconductor substrate 10. When the areas are 80% and 20%, respectively, the ratio of the area of the floating region 17 to the area may be 64% or more and 72% or less.
　図６ｃは、図６ｂにおける領域Ｃ５の拡大図である。図６ｃに示す通り、本例の半導体装置１００は、半導体基板１０の上面視で、第１カソード領域８２と第２カソード領域８３との境界と平行な方向（Ｘ軸方向）における、第２カソード領域８３のＸ軸方向負側の端部Ｕ１において、第２カソード領域８３と接して設けられた第３カソード領域８４を備える。第３カソード領域８４は、第２カソード領域８３の２つの端部Ｕ１のそれぞれに接して設けられてよい。 FIG. 6c is an enlarged view of region C5 in FIG. 6b. As shown in FIG. 6c, the semiconductor device 100 of this example includes the second cathode in a direction (X-axis direction) parallel to the boundary between the first cathode region 82 and the second cathode region 83 when the semiconductor substrate 10 is viewed from above. A third cathode region 84 provided in contact with the second cathode region 83 is provided at the end portion U <b> 1 on the X axis direction negative side of the region 83. The third cathode region 84 may be provided in contact with each of the two ends U1 of the second cathode region 83.
　本例の半導体装置１００は、図６ｃに示す通り、一例として第１カソード領域８２がＹ軸方向に３つ設けられる。フローティング領域１７は、それぞれの第１カソード領域８２のＸＹ平面内における内側に設けられる。 As shown in FIG. 6C, the semiconductor device 100 of this example includes three first cathode regions 82 in the Y-axis direction as an example. The floating region 17 is provided inside the XY plane of each first cathode region 82.
　幅Ｗｎｆ２は、第１カソード領域８２のＸ軸方向負側の端から、当該第１カソード領域８２に重なって配置されるフローティング領域１７のＸ軸方向負側の端までの、Ｘ軸方向における幅である。また、幅Ｗｎｆ２は、領域Ｃ５の外ではあるが、Ｘ軸方向の最も負側および正側の第１カソード領域８２を除く第１カソード領域８２において、当該第１カソード領域８２のＸ軸方向正側の端から、当該第１カソード領域８２に重なって配置されるフローティング領域１７のＸ軸方向正側の端までの、Ｘ軸方向における幅である。 The width Wnf2 is the width in the X-axis direction from the end on the negative side in the X-axis direction of the first cathode region 82 to the end on the negative side in the X-axis direction of the floating region 17 arranged to overlap the first cathode region 82 It is. Further, the width Wnf2 is outside the region C5, but in the first cathode region 82 excluding the most negative and positive first cathode regions 82 in the X-axis direction, the first cathode region 82 is positive in the X-axis direction. This is the width in the X-axis direction from the end on the side to the end on the positive side in the X-axis direction of the floating region 17 disposed so as to overlap the first cathode region 82.
　幅Ｗｎｆ２は、幅Ｗｃｆ２と等しくてよいが、異なっていてもよい。幅Ｗｎｆ２は、ゼロであってもよい。 Width Wnf2 may be equal to width Wcf2, but may be different. The width Wnf2 may be zero.
　図６ｄは、図６ｂにおけるｉ－ｉ'断面の一例を示す図である。本例の半導体装置１００におけるｉ－ｉ'断面の構成は、図２ｄに示す半導体装置１００におけるａ－ａ'断面の構成と同じである。 FIG. 6d is a diagram showing an example of the ii ′ cross section in FIG. 6b. The configuration of the semiconductor device 100 of this example along the ii ′ cross section is the same as the configuration of the semiconductor device 100 shown in FIG.
　図６ｅは、図６ｂにおけるｊ－ｊ'断面の一例を示す図である。ｊ－ｊ'断面は、図６ｄにおけるｊ''－ｊ'''線を通るＸＺ平面である。本例の半導体装置１００におけるｊ－ｊ'断面の構成は、図４ｄに示す半導体装置１００におけるｆ－ｆ'断面において、第２カソード領域８３に代えて第３カソード領域８４が設けられる点で、図４ｄに示す半導体装置１００と異なる。 FIG. 6e is a diagram showing an example of a section ij ′ in FIG. 6b. The jj ′ cross section is the XZ plane passing through the j ″ -j ′ ″ line in FIG. 6d. The configuration of the jj ′ section in the semiconductor device 100 of this example is that a third cathode region 84 is provided in place of the second cathode region 83 in the ff ′ section in the semiconductor device 100 shown in FIG. Different from the semiconductor device 100 shown in FIG.
　本例の半導体装置１００は、格子状に互いに分離して設けられた第１カソード領域８２毎に、フローティング領域１７を有する。このため、ダイオード部８０の逆回復時におけるサージ電圧を抑制することができる。 The semiconductor device 100 of the present example includes the floating region 17 for each first cathode region 82 provided separately in a grid pattern. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be suppressed.
　図７ａは、図１ａにおける領域Ａの他の拡大図である。本例の半導体装置１００は、半導体基板１０の上面視で、フローティング領域１７が、第１カソード領域８２よりも延伸方向に張り出している。本例の半導体装置１００は、延伸方向において、フローティング領域１７の両側が、第１カソード領域８２よりも延伸方向に張り出している。即ち、フローティング領域１７が、Ｘ軸方向における第１カソード領域８２の全体と重なって設けられる。なお、フローティング領域１７のＸ軸方向正側および負側のいずれか一方が、第１カソード領域８２よりも延伸方向に張り出していてもよい。 FIG. 7a is another enlarged view of region A in FIG. 1a. In the semiconductor device 100 of this example, the floating region 17 projects in the extending direction from the first cathode region 82 in a top view of the semiconductor substrate 10. In the semiconductor device 100 of this example, both sides of the floating region 17 protrude in the extending direction from the first cathode region 82 in the extending direction. That is, the floating region 17 is provided so as to overlap the entire first cathode region 82 in the X-axis direction. Note that either one of the positive side and the negative side in the X-axis direction of the floating region 17 may protrude in the extending direction from the first cathode region 82.
　言い換えると、本例の半導体装置１００は、半導体基板１０の上面視で、フローティング領域１７のＸ軸方向正側の端部が、第１カソード領域８２のＸ軸方向正側の端部よりもＸ軸方向正側に設けられ、且つ、当該フローティング領域１７のＸ軸方向負側の端部が、当該第１カソード領域８２のＸ軸方向負側の端部よりもＸ軸方向負側に設けられる。 In other words, in the semiconductor device 100 of this example, when viewed from the top of the semiconductor substrate 10, the end on the positive side in the X-axis direction of the floating region 17 is X more than the end on the positive side in the X-axis direction of the first cathode region 82. Provided on the positive side in the axial direction, and the end on the negative side in the X-axis direction of the floating region 17 is provided on the negative side in the X-axis direction with respect to the end on the negative side in the X-axis direction of the first cathode region 82. .
　本例の半導体装置１００において、フローティング領域１７は格子状に設けられてよい。図７ａに示す半導体装置１００は、フローティング領域１７が、Ｘ軸方向に１０個、Ｙ軸方向に３個設けられる一例を示している。本例の半導体装置１００において、Ｘ軸方向のフローティング領域１７の個数は、Ｘ軸方向の第１カソード領域８２の個数と一致してよい。 In the semiconductor device 100 of this example, the floating regions 17 may be provided in a lattice shape. The semiconductor device 100 shown in FIG. 7A shows an example in which ten floating regions 17 are provided in the X-axis direction and three in the Y-axis direction. In the semiconductor device 100 of this example, the number of floating regions 17 in the X-axis direction may match the number of first cathode regions 82 in the X-axis direction.
　第１カソード領域８２に重なって設けられるフローティング領域１７は、当該第１カソード領域８２にＸ軸方向の正負いずれかの方向で隣り合う他の第１カソード領域８２に重なって設けられるフローティング領域１７と、Ｘ軸方向において互いに分離していてよいが、一体であってもよい。 The floating region 17 provided to overlap the first cathode region 82 includes the floating region 17 provided to overlap the other first cathode region 82 adjacent to the first cathode region 82 in either the positive or negative direction of the X-axis direction. , May be separated from each other in the X-axis direction, but may be integrated.
　図７ｂは、図７ａにおける領域Ｂ６の拡大図である。図７ｂは、図７ａにおけるダイオード部８０のＸ軸方向正側のウェル領域１１の端ＳからＸ軸方向負側のウェル領域１１の端Ｓ'までを、拡大して示している。図７ｂに示す通り、本例の半導体装置１００は、ダイオード部８０において、フローティング領域１７が、Ｘ軸方向における第１カソード領域８２の全体と重なって設けられる。 FIG. 7b is an enlarged view of region B6 in FIG. 7a. FIG. 7B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 7A to the end S ′ of the well region 11 on the X axis direction negative side. As shown in FIG. 7b, in the semiconductor device 100 of this example, the floating region 17 is provided in the diode portion 80 so as to overlap the entire first cathode region 82 in the X-axis direction.
　本例の半導体装置１００において、幅Ｗｃｆ１は、図２ｂに示す例における幅Ｗｃｆ１と同じであってよい。幅Ｗｃｆ１は、ゼロでなければよい。 In the semiconductor device 100 of this example, the width Wcf1 may be the same as the width Wcf1 in the example illustrated in FIG. The width Wcf1 may not be zero.
　本例の半導体装置１００において、フローティング領域１７のＹ軸方向の幅Ｗｆｌ１４は、図２ｂの半導体装置１００における幅Ｗｆｌ１１よりも大きくてもよく、小さくてもよく、等しくてもよい。フローティング領域１７のＸ軸方向の幅Ｗｆｌ２４は、図４ｂの半導体装置１００における幅Ｗｆｌ２２よりも大きくてよい。 In the semiconductor device 100 of this example, the width Wfl14 of the floating region 17 in the Y-axis direction may be larger, smaller, or equal to the width Wfl11 in the semiconductor device 100 of FIG. The width Wfl24 of the floating region 17 in the X-axis direction may be larger than the width Wfl22 in the semiconductor device 100 of FIG. 4b.
　本例の半導体装置１００において、フローティング領域１７のうち、半導体基板１０の上面視で第１カソード領域８２と重ならない領域は、第２カソード領域８３と重なってよい。Ｘ軸方向の最も正側に設けられる第１カソード領域８２と重なって設けられるフローティング領域１７のＸ軸方向正側の端は、半導体基板１０の上面視で、当該第１カソード領域８２のＸ軸方向正側に設けられるコレクタ領域２２の一部と重なってよい。Ｘ軸方向の最も負側に設けられる第１カソード領域８２と重なって設けられるフローティング領域１７のＸ軸方向負側の端は、半導体基板１０の上面視で、当該第１カソード領域８２のＸ軸方向負側に設けられるコレクタ領域２２の一部と重なってよい。 In the semiconductor device 100 of this example, a region of the floating region 17 that does not overlap with the first cathode region 82 in a top view of the semiconductor substrate 10 may overlap with the second cathode region 83. An end on the positive side in the X-axis direction of the floating region 17 provided so as to overlap with the first cathode region 82 provided on the most positive side in the X-axis direction is the X-axis of the first cathode region 82 in a top view of the semiconductor substrate 10. It may overlap with a part of the collector region 22 provided on the positive direction side. An end on the negative side in the X-axis direction of the floating region 17 provided so as to overlap with the first cathode region 82 provided on the most negative side in the X-axis direction is the X-axis of the first cathode region 82 in a top view of the semiconductor substrate 10. It may overlap with a part of the collector region 22 provided on the negative direction side.
　本例の半導体装置１００において、幅Ｗｆｃ２は、Ｘ軸方向の最も正側の第１カソード領域８２と重なって設けられるフローティング領域１７のＸ軸方向正側の端から、当該第１カソード領域８２のＸ軸方向正側の端までの、Ｘ軸方向における幅である。また、幅Ｗｆｃ２は、Ｘ軸方向の最も負側の第１カソード領域８２と重なって設けられるフローティング領域１７のＸ軸方向負側の端から、当該第１カソード領域８２のＸ軸方向負側の端までの、Ｘ軸方向における幅である。 In the semiconductor device 100 of this example, the width Wfc <b> 2 is the width of the first cathode region 82 from the end on the positive side in the X-axis direction of the floating region 17 provided so as to overlap with the first cathode region 82 on the most positive side in the X-axis direction. This is the width in the X-axis direction up to the end on the positive side in the X-axis direction. Further, the width Wfc2 extends from the end on the negative side in the X axis direction of the floating region 17 provided so as to overlap with the first negative cathode region 82 on the most negative side in the X axis direction to the negative side in the X axis direction of the first cathode region 82. This is the width in the X-axis direction to the end.
　幅Ｗｆｃ２は、図４ｂに示す半導体装置１００における幅Ｗｃｈ２と等しくてよいが、異なっていてもよい。 The width Wfc2 may be equal to or different from the width Wch2 in the semiconductor device 100 shown in FIG. 4b.
　それぞれの第１カソード領域８２において、半導体基板１０の上面視で、第１カソード領域８２の面積に占めるフローティング領域１７の面積は、８０％以上９０％以下であってよい。半導体基板１０の上面視における第１カソード領域８２と第２カソード領域８３との合計面積に占める第１カソード領域８２の面積および第２カソード領域８３の面積が、それぞれ８０％および２０％の場合、当該面積に占めるフローティング領域１７の面積の割合は、６４％以上７２％以下であってよい。 In each first cathode region 82, the area of the floating region 17 occupying the area of the first cathode region 82 in the top view of the semiconductor substrate 10 may be 80% or more and 90% or less. When the area of the first cathode region 82 and the area of the second cathode region 83 in the total area of the first cathode region 82 and the second cathode region 83 in the top view of the semiconductor substrate 10 are 80% and 20%, respectively, The ratio of the area of the floating region 17 to the area may be 64% or more and 72% or less.
　図７ｃは、図７ｂにおける領域Ｃ６の拡大図である。図７ｃに示す通り、本例の半導体装置１００は、半導体基板１０の上面視で、フローティング領域１７が、Ｘ軸方向における第１カソード領域８２の全体と重なって設けられる。 FIG. 7c is an enlarged view of region C6 in FIG. 7b. As shown in FIG. 7C, in the semiconductor device 100 of this example, the floating region 17 is provided so as to overlap the entire first cathode region 82 in the X-axis direction when the semiconductor substrate 10 is viewed from above.
　本例の半導体装置１００は、一例として、第１カソード領域８２がＹ軸方向に３つ設けられる。また、幅Ｗｆｌ２４は、幅Ｗｃｖ２よりも大きい。 As an example, the semiconductor device 100 of this example includes three first cathode regions 82 in the Y-axis direction. Further, the width Wfl24 is larger than the width Wcv2.
　幅Ｗｆｎ２は、領域Ｃ６において、半導体基板１０の上面視で、第１カソード領域８２のＸ軸方向負側の端から、当該第１カソード領域８２に重なって設けられるフローティング領域１７のＸ軸方向負側の端までの、Ｘ軸方向における幅である。幅Ｗｆｎ２は、幅Ｗｆｃ２と等しくてよいが、異なっていてもよい。 The width Wfn2 is negative in the X-axis direction of the floating region 17 provided to overlap the first cathode region 82 from the end on the negative side in the X-axis direction of the first cathode region 82 in the region C6 when the semiconductor substrate 10 is viewed from above. It is the width in the X-axis direction to the end on the side. The width Wfn2 may be equal to the width Wfc2, but may be different.
　図７ｄは、図７ｂにおけるｋ－ｋ'断面の一例を示す図である。本例の半導体装置１００は、ｋ－ｋ'断面において、第１カソード領域８２が、端部Ｐ１から端部Ｐ１'まで、Ｙ軸方向に連続して設けられる。第１カソード領域８２の上方には、フローティング領域１７が設けられる。フローティング領域１７は、第１カソード領域８２と接して設けられてよい。 FIG. 7d is a diagram showing an example of a kk ′ cross section in FIG. 7b. In the semiconductor device 100 of this example, the first cathode region 82 is continuously provided in the Y-axis direction from the end portion P1 to the end portion P1 ′ in the kk ′ cross section. The floating region 17 is provided above the first cathode region 82. The floating region 17 may be provided in contact with the first cathode region 82.
　本例において、フローティング領域１７はＹ軸方向に３つ設けられる。幅Ｗｆｌ１４は、図２ｄに示す例における幅Ｗｆｌ１１よりも大きくてよく、小さくてよく、等しくてもよい。 In this example, three floating regions 17 are provided in the Y-axis direction. The width Wfl14 may be larger, smaller, or equal to the width Wfl11 in the example shown in FIG. 2d.
　図７ｅは、図７ｂにおけるｍ－ｍ'断面の一例を示す図である。ｍ－ｍ'断面は、図７ｄにおけるｍ''－ｍ'''線を通るＸＺ平面である。図７ｅに示すように、本例の半導体装置１００は、ｍ－ｍ'断面において、第１カソード領域８２および第２カソード領域８３が、Ｘ軸方向に交互に設けられる。 FIG. 7e is a diagram showing an example of a mm ′ cross section in FIG. 7b. The mm ′ cross section is the XZ plane passing through the m ″ -m ′ ″ line in FIG. 7d. As shown in FIG. 7e, in the semiconductor device 100 of this example, the first cathode regions 82 and the second cathode regions 83 are alternately provided in the X-axis direction in the mm ′ cross section.
　第１カソード領域８２の上方には、フローティング領域１７が設けられる。また、第１カソード領域８２の上方に設けられるフローティング領域１７は、当該第１カソード領域８２にＸ軸方向で隣り合う第２カソード領域８３の一部の上方にも設けられる。このため、幅Ｗｆｌ２４は幅Ｗｃｖ２よりも大きい。 The floating region 17 is provided above the first cathode region 82. The floating region 17 provided above the first cathode region 82 is also provided above a part of the second cathode region 83 adjacent to the first cathode region 82 in the X-axis direction. For this reason, the width Wfl24 is larger than the width Wcv2.
　Ｘ軸方向の最も正側に設けられるフローティング領域１７は、Ｘ軸方向正側に設けられるコレクタ領域２２の一部の上方にも設けられてよい。Ｘ軸方向の最も負側に設けられるフローティング領域１７は、Ｘ軸方向負側のコレクタ領域２２の一部の上方にも設けられてよい。 The floating region 17 provided on the most positive side in the X-axis direction may be provided above a part of the collector region 22 provided on the positive side in the X-axis direction. The floating region 17 provided on the most negative side in the X-axis direction may also be provided above a part of the collector region 22 on the X-axis direction negative side.
　フローティング領域１７は、第１カソード領域８２と接して設けられてよい。また、フローティング領域１７は、第２カソード領域８３と接して設けられてよい。また、フローティング領域１７は、コレクタ領域２２と接して設けられてよい。 The floating region 17 may be provided in contact with the first cathode region 82. The floating region 17 may be provided in contact with the second cathode region 83. The floating region 17 may be provided in contact with the collector region 22.
　本例の半導体装置１００は、フローティング領域１７が第１カソード領域８２のＸ軸方向における全体と重なって設けられる。また、フローティング領域１７は、第１カソード領域８２のＸ軸方向における両端において、第２カソード領域８３と重なって設けられる。このため、ダイオード部８０の逆回復時におけるサージ電圧を、図６ａに示す半導体装置１００よりも、さらに抑制することができる。 In the semiconductor device 100 of this example, the floating region 17 is provided so as to overlap the entire first cathode region 82 in the X-axis direction. The floating region 17 is provided so as to overlap the second cathode region 83 at both ends in the X-axis direction of the first cathode region 82. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be further suppressed than the semiconductor device 100 shown in FIG. 6a.
　図８ａは、図１ａにおける領域Ａの他の拡大図である。本例の半導体装置１００は、半導体基板１０の上面視で、互いに分離した複数の第１カソード領域８２が、図２ａに示す半導体装置１００と同様に、Ｘ軸方向に延伸して設けられる。半導体基板１０の上面視で、Ｙ軸方向に隣り合う第１カソード領域８２の間には、第２カソード領域８３が設けられる。 FIG. 8a is another enlarged view of region A in FIG. 1a. In the semiconductor device 100 of this example, a plurality of first cathode regions 82 separated from each other in a top view of the semiconductor substrate 10 are provided extending in the X-axis direction, like the semiconductor device 100 illustrated in FIG. A second cathode region 83 is provided between the first cathode regions 82 adjacent to each other in the Y axis direction when the semiconductor substrate 10 is viewed from above.
　ダイオード部８０において、Ｙ軸方向の最も正側に設けられる第１カソード領域８２は、当該ダイオード部８０のＹ軸方向正側に隣接するトランジスタ部と接してよい。Ｙ軸方向の最も負側に設けられる第１カソード領域８２は、当該ダイオード部８０のＹ軸方向負側に隣接するトランジスタ部と接してよい。 In the diode unit 80, the first cathode region 82 provided on the most positive side in the Y-axis direction may be in contact with the transistor unit adjacent to the positive side of the diode unit 80 in the Y-axis direction. The first cathode region 82 provided on the most negative side in the Y-axis direction may be in contact with the transistor portion adjacent on the Y-axis direction negative side of the diode portion 80.
　本例の半導体装置１００において、フローティング領域１７は格子状に設けられてよい。図８ａに示す半導体装置１００は、フローティング領域１７が、Ｘ軸方向に２０個、Ｙ軸方向に３個設けられる一例を示している。本例の半導体装置１００において、Ｙ軸方向のフローティング領域１７の個数は、Ｙ軸方向の第１カソード領域８２の個数と一致してよい。 In the semiconductor device 100 of this example, the floating regions 17 may be provided in a lattice shape. The semiconductor device 100 shown in FIG. 8A shows an example in which 20 floating regions 17 are provided in the X axis direction and 3 in the Y axis direction. In the semiconductor device 100 of this example, the number of floating regions 17 in the Y-axis direction may match the number of first cathode regions 82 in the Y-axis direction.
　本例の半導体装置１００は、半導体基板１０の上面視で、フローティング領域１７が、第１カソード領域８２よりも配列方向に張り出している。本例の半導体装置１００において、配列方向に設けられる３つのフローティング領域１７のうち、中央のフローティング領域１７は、配列方向において当該フローティング領域１７の両側が、第１カソード領域８２よりも張り出している。即ち、フローティング領域１７が、配列方向における第１カソード領域８２の全体と重なって設けられる。 In the semiconductor device 100 of this example, the floating region 17 protrudes in the arrangement direction from the first cathode region 82 in a top view of the semiconductor substrate 10. In the semiconductor device 100 of this example, among the three floating regions 17 provided in the arrangement direction, the central floating region 17 has both sides of the floating region 17 projecting beyond the first cathode region 82 in the arrangement direction. That is, the floating region 17 is provided so as to overlap the entire first cathode region 82 in the arrangement direction.
　配列方向に設けられる３つのフローティング領域１７のうち、Ｙ軸方向正側のフローティング領域１７は、配列方向において当該フローティング領域１７のＹ軸方向負側が、第１カソード領域８２よりも張り出している。即ち、当該フローティング領域１７のＹ軸方向負側の端部は、当該第１カソード領域８２のＹ軸方向負側の端部よりもＹ軸方向負側に設けられる。 Among the three floating regions 17 provided in the arrangement direction, the Y region in the Y axis direction of the floating region 17 on the positive side in the Y axis direction protrudes beyond the first cathode region 82 in the Y direction in the arrangement direction. That is, the Y-axis direction negative end of the floating region 17 is provided on the Y-axis direction negative side of the first cathode region 82 on the Y-axis negative side.
　また、配列方向に設けられる３つのフローティング領域１７のうち、Ｙ軸方向負側のフローティング領域１７は、配列方向において当該フローティング領域１７のＹ軸方向正側が、第１カソード領域８２よりも張り出している。即ち、当該フローティング領域１７のＹ軸方向正側の端部は、当該第１カソード領域８２のＹ軸方向正側の端部よりもＹ軸方向正側に設けられる。なお、フローティング領域１７は、トランジスタ部７０とは重なって設けられない。 Of the three floating regions 17 provided in the arrangement direction, the floating region 17 on the negative side in the Y-axis direction protrudes beyond the first cathode region 82 in the Y-axis direction positive side of the floating region 17 in the arrangement direction. . That is, the end on the Y axis direction positive side of the floating region 17 is provided closer to the Y axis direction positive side than the end portion of the first cathode region 82 on the Y axis direction positive side. Note that the floating region 17 is not provided so as to overlap the transistor portion 70.
　図８ｂは、図８ａにおける領域Ｂ７の拡大図である。図８ｂは、図８ａにおけるダイオード部８０のＸ軸方向正側のウェル領域１１の端ＳからＸ軸方向負側のウェル領域１１の端Ｓ'までを、拡大して示している。図８ｂに示す通り、本例の半導体装置１００は、ダイオード部８０において、複数の第１カソード領域８２のうち、トランジスタ部７０に接しない第１カソード領域８２と重なって設けられるフローティング領域１７が、当該第１カソード領域８２のＹ軸方向における全体と重なって設けられる。 FIG. 8b is an enlarged view of region B7 in FIG. 8a. FIG. 8B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 8A to the end S ′ of the well region 11 on the X axis direction negative side. As shown in FIG. 8b, in the semiconductor device 100 of this example, the floating region 17 provided to overlap the first cathode region 82 that does not contact the transistor unit 70 among the plurality of first cathode regions 82 in the diode unit 80 includes: The first cathode region 82 is provided so as to overlap the entire Y-axis direction.
　本例の半導体装置１００において、幅Ｗｃｆ１および幅Ｗｃｆ２は、それぞれ図２ｂに示す例における幅Ｗｃｆ１および幅Ｗｃｆ２と同じであってよい。幅Ｗｃｆ１は、ゼロでなければよい。幅Ｗｃｆ２は、ゼロであってもよい。 In the semiconductor device 100 of this example, the width Wcf1 and the width Wcf2 may be the same as the width Wcf1 and the width Wcf2 in the example illustrated in FIG. The width Wcf1 may not be zero. The width Wcf2 may be zero.
　本例の半導体装置１００において、Ｙ軸方向の最も正側および負側に設けられるフローティング領域１７のＹ軸方向の幅Ｗｆｌ１５は、図２ｂの半導体装置１００における幅Ｗｆｌ１１よりも大きくてもよく、小さくてもよく、等しくてもよい。Ｙ軸方向の中央に設けられるフローティング領域１７のＹ軸方向の幅Ｗｆｌ１６は、図２ｂの半導体装置１００における幅Ｗｆｌ１１よりも大きくてもよく、小さくてもよく、等しくてもよい。また、幅Ｗｆｌ１６は、幅Ｗｆｌ５よりも大きくてよい。 In the semiconductor device 100 of this example, the width Wfl15 in the Y-axis direction of the floating region 17 provided on the most positive side and the negative side in the Y-axis direction may be larger or smaller than the width Wfl11 in the semiconductor device 100 in FIG. Or may be equal. The width Wfl16 in the Y-axis direction of the floating region 17 provided at the center in the Y-axis direction may be larger, smaller, or equal to the width Wfl11 in the semiconductor device 100 of FIG. Further, the width Wfl16 may be larger than the width Wfl5.
　本例の半導体装置１００において、フローティング領域１７のＸ軸方向の幅Ｗｆｌ２５は、図４ｂの例における幅Ｗｆｌ２２よりも大きくてよく、小さくてもよく、等しくてもよい。幅Ｗｆｌ２２は、幅Ｗｆｌ１５よりも大きくてよく、小さくてもよく、等しくてもよい。幅Ｗｆｌ２２は、幅Ｗｆｌ１６よりも大きくてよく、小さくてもよく、等しくてもよい。 In the semiconductor device 100 of this example, the width Wfl25 of the floating region 17 in the X-axis direction may be larger, smaller, or equal to the width Wfl22 in the example of FIG. The width Wfl22 may be larger, smaller, or equal to the width Wfl15. Width Wfl22 may be larger than width Wfl16, may be smaller, or may be equal.
　図８ｃは、図８ｂにおける領域Ｃ７の拡大図である。図８ｃに示す通り、本例の半導体装置１００は、複数のフローティング領域１７のうち、半導体基板１０の上面視で、Ｙ軸方向中央に設けられる第１カソード領域８２と重なって設けられるフローティング領域１７は、当該第１カソード領域８２のＹ軸方向における全体と重なって設けられる。 FIG. 8c is an enlarged view of region C7 in FIG. 8b. As shown in FIG. 8 c, the semiconductor device 100 of this example includes the floating region 17 provided to overlap the first cathode region 82 provided at the center in the Y-axis direction when the semiconductor substrate 10 is viewed from the top among the plurality of floating regions 17. Is provided so as to overlap the entire first cathode region 82 in the Y-axis direction.
　本例の半導体装置１００において、幅Ｗｆｎ１は、第１カソード領域８２のＹ軸方向正側の端から、当該端と重なって設けられるフローティング領域１７のＹ軸方向正側の端までの、Ｙ軸方向における幅である。また、幅Ｗｆｎ１は、第１カソード領域８２のＹ軸方向負側の端から、当該端と重なって設けられるフローティング領域１７のＹ軸方向負側の端までの、Ｙ軸方向における幅である。 In the semiconductor device 100 of this example, the width Wfn1 is the Y axis from the end on the Y axis direction positive side of the first cathode region 82 to the end on the Y axis direction positive side of the floating region 17 provided to overlap with the end. The width in the direction. The width Wfn1 is a width in the Y-axis direction from the end on the Y-axis direction negative side of the first cathode region 82 to the end on the Y-axis direction negative side of the floating region 17 provided so as to overlap with the end.
　幅Ｗｆｎ１は、図３ｃの例における幅Ｗｆｎ１と等しくてよい。幅Ｗｆｎ１は、幅Ｗｃｆ１と等しくてよい。 The width Wfn1 may be equal to the width Wfn1 in the example of FIG. The width Wfn1 may be equal to the width Wcf1.
　図８ｄは、図８ｂにおけるｎ－ｎ'断面の一例を示す図である。本例の半導体装置１００は、ｎ－ｎ'断面において、第１カソード領域８２および第２カソード領域８３が、Ｙ軸方向に交互に設けられる。第１カソード領域８２の上方には、フローティング領域１７が設けられる。第１カソード領域８２の上方に設けられるフローティング領域１７は、当該第１カソード領域８２にＹ軸方向で隣り合う第２カソード領域８３の一部の上方にも設けられる。このため、幅Ｗｆｌ１６は幅Ｗｃｈ１よりも大きい。 FIG. 8d is a diagram showing an example of the nn ′ cross section in FIG. 8b. In the semiconductor device 100 of this example, the first cathode regions 82 and the second cathode regions 83 are alternately provided in the Y-axis direction in the nn ′ cross section. The floating region 17 is provided above the first cathode region 82. The floating region 17 provided above the first cathode region 82 is also provided above a part of the second cathode region 83 adjacent to the first cathode region 82 in the Y-axis direction. For this reason, the width Wfl16 is larger than the width Wch1.
　フローティング領域１７は、第１カソード領域８２と接して設けられてよい。また、フローティング領域１７は、第２カソード領域８３と接して設けられてよい。 The floating region 17 may be provided in contact with the first cathode region 82. The floating region 17 may be provided in contact with the second cathode region 83.
　本例の半導体装置１００は、Ｙ軸方向中央に設けられるフローティング領域１７が、第１カソード領域８２のＹ軸方向における全体と重なって設けられる。また、当該フローティング領域１７は、当該第１カソード領域８２のＹ軸方向における両端において、第２カソード領域８３と重なって設けられる。このため、ダイオード部８０の逆回復時におけるサージ電圧を、図６ａに示す半導体装置１００よりも、さらに抑制することができる。 In the semiconductor device 100 of this example, the floating region 17 provided in the center in the Y-axis direction is provided so as to overlap the entire first cathode region 82 in the Y-axis direction. The floating region 17 is provided so as to overlap the second cathode region 83 at both ends in the Y-axis direction of the first cathode region 82. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be further suppressed than the semiconductor device 100 shown in FIG. 6a.
　図８ｅは、図８ｂにおけるｐ－ｐ'断面の一例を示す図である。ｐ－ｐ'断面は、図８ｄにおけるｐ''－ｐ'''線を通るＸＺ平面である。図８ｅに示すように、本例の半導体装置１００は、ｐ－ｐ'断面において、第１カソード領域８２が、境界位置Ｐ５から境界位置Ｐ５'まで、Ｙ軸方向に連続して設けられる。第１カソード領域８２の上方には、フローティング領域１７が設けられる。フローティング領域１７は、第１カソード領域８２と接して設けられてよい。 FIG. 8e is a diagram showing an example of a pp ′ section in FIG. 8b. The pp ′ cross section is an XZ plane passing through the p ″ -p ′ ″ line in FIG. As shown in FIG. 8e, in the semiconductor device 100 of this example, the first cathode region 82 is continuously provided in the Y-axis direction from the boundary position P5 to the boundary position P5 ′ in the pp ′ cross section. The floating region 17 is provided above the first cathode region 82. The floating region 17 may be provided in contact with the first cathode region 82.
　図９ａは、図１ａにおける領域Ａの他の拡大図である。本例の半導体装置１００は、半導体基板１０の上面視で、第１カソード領域８２および第２カソード領域８３を挟むように、第２導電型の第３カソード領域８４がさらに設けられる。本例の半導体装置１００において、第３カソード領域８４は、カソード領域８１のＸ軸方向正側および負側に、下面２３に接してそれぞれ設けられる。本例の第３カソード領域８４は、一例としてＰ＋型である。 FIG. 9a is another enlarged view of region A in FIG. 1a. The semiconductor device 100 of this example is further provided with a second conductivity type third cathode region 84 so as to sandwich the first cathode region 82 and the second cathode region 83 when the semiconductor substrate 10 is viewed from above. In the semiconductor device 100 of this example, the third cathode region 84 is provided in contact with the lower surface 23 on the positive side and the negative side in the X-axis direction of the cathode region 81. The third cathode region 84 of this example is a P + type as an example.
　図９ｂは、図９ａにおける領域Ｂ８の拡大図である。図９ｂは、図９ａにおけるダイオード部８０のＸ軸方向正側のウェル領域１１の端ＳからＸ軸方向負側のウェル領域１１の端Ｓ'までを、拡大して示している。図９ｂに示す通り、本例の半導体装置１００は、ダイオード部８０において、半導体基板１０の上面視で、カソード領域８１のＸ軸方向正側および負側に、第３カソード領域８４がそれぞれ設けられる。半導体基板１０の上面視で、Ｘ軸方向の両端に設けられる第３カソード領域８４のＸ軸方向の間には、第１カソード領域８２および第２カソード領域８３が、Ｙ軸方向に交互に設けられる。 FIG. 9b is an enlarged view of region B8 in FIG. 9a. FIG. 9B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 9A to the end S ′ of the well region 11 on the X axis direction negative side. As shown in FIG. 9b, in the semiconductor device 100 of the present example, the third cathode regions 84 are respectively provided on the positive side and the negative side of the cathode region 81 in the X-axis direction in the diode portion 80 when the semiconductor substrate 10 is viewed from above. . The first cathode region 82 and the second cathode region 83 are alternately provided in the Y-axis direction between the third cathode regions 84 provided at both ends in the X-axis direction when the semiconductor substrate 10 is viewed from above. It is done.
　幅Ｗｃｈ１は、図２ｂに示す例における幅Ｗｃｈ１と同じであってよい。幅Ｗｃｖ２は、図２ｂに示す例における幅Ｗｃｖ１と同じであってよい。 The width Wch1 may be the same as the width Wch1 in the example shown in FIG. 2b. The width Wcv2 may be the same as the width Wcv1 in the example illustrated in FIG.
　幅Ｗｃｖ３は、半導体基板１０の上面視における、第１カソード領域８２および第２カソード領域８３のＸ軸方向の幅である。幅Ｗｃｖ３は、幅Ｗｃｖ１よりも小さくてよい。幅Ｗｃｖ３は、幅Ｗｃｖ１の７０％以上９０％以下であってよい。 The width Wcv3 is the width in the X-axis direction of the first cathode region 82 and the second cathode region 83 in the top view of the semiconductor substrate 10. The width Wcv3 may be smaller than the width Wcv1. The width Wcv3 may be not less than 70% and not more than 90% of the width Wcv1.
　半導体基板１０の上面視において、第１カソード領域８２、第２カソード領域８３および第３カソード領域８４の合計面積に占める第１カソード領域８２の面積の割合は、６０％以上９０％以下であってよい。当該合計面積に占める第２カソード領域８３および第３カソード領域８４の合計面積の割合は、１０％以上４０％以下であってよい。一例として、第１カソード領域８２、第２カソード領域８３および第３カソード領域８４の合計面積に占める第１カソード領域８２の面積の割合は、８０％である。一例として、第１カソード領域８２、第２カソード領域８３および第３カソード領域８４の合計面積に占める第２カソード領域８３および第３カソード領域８４の合計面積の割合は、２０％である。 In the top view of the semiconductor substrate 10, the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82, the second cathode region 83, and the third cathode region 84 is 60% or more and 90% or less. Good. The ratio of the total area of the second cathode region 83 and the third cathode region 84 in the total area may be 10% or more and 40% or less. As an example, the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82, the second cathode region 83, and the third cathode region 84 is 80%. As an example, the ratio of the total area of the second cathode region 83 and the third cathode region 84 to the total area of the first cathode region 82, the second cathode region 83, and the third cathode region 84 is 20%.
　図９ｃは、図９ｂにおける領域Ｃ８の拡大図である。図９ｃに示す通り、本例の半導体装置１００は、一例として第１カソード領域８２がＹ軸方向に３つ設けられる。Ｙ軸方向に隣り合う第１カソード領域８２の間には、第２カソード領域８３が設けられる。さらに、半導体基板１０の上面視で、第１カソード領域８２と第２カソード領域８３との境界と平行な方向（Ｘ軸方向）における、第２カソード領域８３のＸ軸方向正側の端部Ｕ１において、第２カソード領域８３と接して第３カソード領域８４が設けられる。 FIG. 9c is an enlarged view of region C8 in FIG. 9b. As shown in FIG. 9c, in the semiconductor device 100 of the present example, three first cathode regions 82 are provided in the Y-axis direction as an example. A second cathode region 83 is provided between the first cathode regions 82 adjacent in the Y-axis direction. Furthermore, when viewed from the top of the semiconductor substrate 10, the end portion U1 on the positive side in the X-axis direction of the second cathode region 83 in the direction parallel to the boundary between the first cathode region 82 and the second cathode region 83 (X-axis direction). , A third cathode region 84 is provided in contact with the second cathode region 83.
　本例の半導体装置１００において、幅Ｗｃｃは、半導体基板１０の上面視で、第１カソード領域８２と第２カソード領域８３との配列方向に沿った第２カソード領域８３の幅である。幅Ｗｃｔは、半導体基板１０の上面視で、当該配列方向に沿った第３カソード領域８４の幅である。本例の半導体装置１００において、幅Ｗｃｔは、幅Ｗｃｃよりも大きい。なお、本例においては、当該配列方向がＹ軸方向である一例を示しているが、当該配列方向がＹ軸方向と異なる方向であってもよい。 In the semiconductor device 100 of this example, the width Wcc is the width of the second cathode region 83 along the arrangement direction of the first cathode region 82 and the second cathode region 83 in the top view of the semiconductor substrate 10. The width Wct is the width of the third cathode region 84 along the arrangement direction when the semiconductor substrate 10 is viewed from above. In the semiconductor device 100 of this example, the width Wct is larger than the width Wcc. In this example, an example in which the arrangement direction is the Y-axis direction is shown, but the arrangement direction may be a direction different from the Y-axis direction.
　第３カソード領域８４のドーピング濃度は、第２カソード領域８３のドーピング濃度と等しくてよい。即ち、領域Ｃ８において、第２カソード領域８３および第３カソード領域８４は、ドーピング濃度の等しい第２導電型のカソード領域としてつながっていてよい。 The doping concentration of the third cathode region 84 may be equal to the doping concentration of the second cathode region 83. That is, in the region C8, the second cathode region 83 and the third cathode region 84 may be connected as a cathode region of the second conductivity type having the same doping concentration.
　図９ｄは、図９ｂにおけるｑ－ｑ'断面の一例を示す図である。本例の半導体装置１００におけるｑ－ｑ'断面の構成は、図２ｄにおけるａ－ａ'断面の構成において、フローティング領域１７を除いた構成に等しい。 FIG. 9d is a diagram showing an example of a qq ′ cross section in FIG. 9b. The configuration of the qq ′ cross section of the semiconductor device 100 of this example is the same as the configuration of the cross section aa ′ in FIG.
　図９ｅは、図９ｂにおけるｒ－ｒ'断面の一例を示す図である。図９ｅに示すように、本例の半導体装置１００は、ｒ－ｒ'断面において、第１カソード領域８２のＸ軸方向正側および負側に、第１カソード領域８２に接して、それぞれ第３カソード領域８４が設けられる。Ｘ軸方向正側の第３カソード領域８４は、Ｘ軸方向において、第１カソード領域８２と、当該第１カソード領域８２のＸ軸方向正側に設けられるコレクタ領域２２とに挟まれてよい。Ｘ軸方向負側の第３カソード領域８４は、Ｘ軸方向において、第１カソード領域８２と、当該第１カソード領域８２のＸ軸方向負側に設けられるコレクタ領域２２とに挟まれてよい。 FIG. 9e is a diagram showing an example of the rr ′ cross section in FIG. 9b. As shown in FIG. 9e, in the semiconductor device 100 of this example, in the rr ′ cross section, the first cathode region 82 is in contact with the first cathode region 82 on the positive side and the negative side in the X-axis direction, respectively. A cathode region 84 is provided. The third cathode region 84 on the X axis direction positive side may be sandwiched between the first cathode region 82 and the collector region 22 provided on the X axis direction positive side of the first cathode region 82 in the X axis direction. The third cathode region 84 on the X axis direction negative side may be sandwiched between the first cathode region 82 and the collector region 22 provided on the X axis direction negative side of the first cathode region 82 in the X axis direction.
　本例の半導体装置１００は、第１カソード領域８２と第２カソード領域８３との境界と平行な方向（Ｘ軸方向）における、第２カソード領域８３のＸ軸方向正側の端部Ｕ１において、第２カソード領域８３と接して第３カソード領域８４が設けられる。このため、ダイオード部８０の逆回復時におけるサージ電圧を抑制することができる。 In the semiconductor device 100 of this example, at the end U1 on the X axis direction positive side of the second cathode region 83 in the direction (X axis direction) parallel to the boundary between the first cathode region 82 and the second cathode region 83, A third cathode region 84 is provided in contact with the second cathode region 83. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be suppressed.
　図１０ａは、図１ａにおける領域Ａの他の拡大図である。本例の半導体装置１００は、図４ａに示す半導体装置１００において、半導体基板１０の上面視で、第１カソード領域８２の内側にフローティング領域１７を有さない点で、図４ａに示す半導体装置１００と異なる。 FIG. 10a is another enlarged view of region A in FIG. 1a. The semiconductor device 100 of this example is different from the semiconductor device 100 shown in FIG. 4A in that the floating region 17 is not provided inside the first cathode region 82 when the semiconductor substrate 10 is viewed from above. And different.
　図１０ｂは、図１０ａにおける領域Ｂ９の拡大図である。図１０ｂは、図１０ａにおけるダイオード部８０のＸ軸方向正側のウェル領域１１の端ＳからＸ軸方向負側のウェル領域１１の端Ｓ'までを、拡大して示している。図１０ｂに示す通り、本例の半導体装置１００は、ダイオード部８０において、第１カソード領域８２および第２カソード領域８３がＸ軸方向に交互に設けられる。本例の半導体装置１００は、ダイオード部８０において、第１カソード領域８２がＸ軸方向に１０個設けられ、第２カソード領域８３がＸ軸方向に９個設けられる。 FIG. 10b is an enlarged view of region B9 in FIG. 10a. FIG. 10B shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 10A to the end S ′ of the well region 11 on the X axis direction negative side. As shown in FIG. 10b, in the semiconductor device 100 of this example, the first cathode regions 82 and the second cathode regions 83 are alternately provided in the X-axis direction in the diode portion 80. In the semiconductor device 100 of this example, in the diode portion 80, ten first cathode regions 82 are provided in the X-axis direction, and nine second cathode regions 83 are provided in the X-axis direction.
　幅Ｗｃｈ２は、図４ｂに示す例における幅Ｗｃｈ２と同じであってよい。幅Ｗｃｖ２は、図４ｂに示す例における幅Ｗｃｖ２と同じであってよい。 The width Wch2 may be the same as the width Wch2 in the example shown in FIG. 4b. The width Wcv2 may be the same as the width Wcv2 in the example shown in FIG. 4b.
　幅Ｗｃｖ４は、半導体基板１０の上面視における、第２カソード領域８３のＸ軸方向の幅である。幅Ｗｃｖ４は、幅Ｗｃｖ２の５％以上３０％以下であってよい。 The width Wcv4 is a width in the X-axis direction of the second cathode region 83 when the semiconductor substrate 10 is viewed from above. The width Wcv4 may be 5% or more and 30% or less of the width Wcv2.
　半導体基板１０の上面視において、第１カソード領域８２および第２カソード領域８３の合計面積に占める第１カソード領域８２の面積の割合は、６０％以上９０％以下であってよい。当該合計面積に占める第２カソード領域８３の面積の割合は、１０％以上４０％以下であってよい。一例として、第１カソード領域８２および第２カソード領域８３の合計面積に占める第１カソード領域８２の面積の割合は、８０％である。一例として、第１カソード領域８２および第２カソード領域８３の合計面積に占める第２カソード領域８３の面積の割合は、２０％である。 In the top view of the semiconductor substrate 10, the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82 and the second cathode region 83 may be 60% or more and 90% or less. The ratio of the area of the second cathode region 83 to the total area may be 10% or more and 40% or less. As an example, the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82 and the second cathode region 83 is 80%. As an example, the ratio of the area of the second cathode region 83 to the total area of the first cathode region 82 and the second cathode region 83 is 20%.
　図１０ｃは、図１０ｂにおけるｓ－ｓ'断面の一例を示す図である。本例の半導体装置１００におけるｓ－ｓ'断面の構成は、図４ｃにおけるｅ－ｅ'断面の構成において、フローティング領域１７を除いた構成に等しい。 FIG. 10c is a diagram showing an example of the ss ′ cross section in FIG. 10b. The configuration of the ss ′ cross section in the semiconductor device 100 of this example is the same as the configuration of the ee ′ cross section in FIG.
　図１０ｄは、図１０ｂにおけるｔ－ｔ'断面の一例を示す図である。本例の半導体装置１００は、ｔ－ｔ'断面において、下面２３に接して第１カソード領域８２および第２カソード領域８３を有する。第１カソード領域８２および第２カソード領域８３は、Ｘ軸方向に交互に設けられる。このため、本例の半導体装置１００は、ダイオード部８０の逆回復時におけるサージ電圧を抑制することができる。 FIG. 10d is a diagram showing an example of a tt ′ cross section in FIG. 10b. The semiconductor device 100 of this example includes a first cathode region 82 and a second cathode region 83 in contact with the lower surface 23 in the tt ′ cross section. The first cathode regions 82 and the second cathode regions 83 are provided alternately in the X-axis direction. For this reason, the semiconductor device 100 of this example can suppress the surge voltage at the time of reverse recovery of the diode unit 80.
　図１１ａは、図１ａにおける領域Ａの他の拡大図である。本例の半導体装置１００は、図６ａに示す半導体装置１００において、半導体基板１０の上面視で、格子状に設けられた第１カソード領域８２の内側にフローティング領域１７を有さない点で、図６ａに示す半導体装置１００と異なる。 FIG. 11a is another enlarged view of region A in FIG. 1a. The semiconductor device 100 of this example is different from the semiconductor device 100 shown in FIG. 6A in that the floating region 17 is not provided inside the first cathode region 82 provided in a lattice shape in a top view of the semiconductor substrate 10. Different from the semiconductor device 100 shown in FIG.
　図１１ｂは、図１１ａにおける領域Ｂ１０の拡大図である。図１１ｂは、図１１ａにおけるダイオード部８０のＸ軸方向正側のウェル領域１１の端ＳからＸ軸方向負側のウェル領域１１の端Ｓ'までを、拡大して示している。図１１ｂに示す通り、本例の半導体装置１００は、ダイオード部８０において、第１カソード領域８２がＸ軸方向に１０個設けられ、Ｙ軸方向に３個設けられる。 FIG. 11b is an enlarged view of region B10 in FIG. 11a. FIG. 11b shows an enlarged view from the end S of the well region 11 on the X axis direction positive side of the diode portion 80 in FIG. 11a to the end S ′ of the well region 11 on the X axis direction negative side. As shown in FIG. 11B, in the semiconductor device 100 of this example, in the diode portion 80, ten first cathode regions 82 are provided in the X-axis direction and three in the Y-axis direction.
　幅Ｗｃｈ１は、図２ｂに示す例における幅Ｗｃｈ１と同じであってよい。幅Ｗｃｖ２は、図４ｂに示す例における幅Ｗｃｖ２と同じであってよい。幅Ｗｃｖ４は、図１０ｂに示す例における幅Ｗｃｖ４と同じであってよい。 The width Wch1 may be the same as the width Wch1 in the example shown in FIG. 2b. The width Wcv2 may be the same as the width Wcv2 in the example shown in FIG. 4b. The width Wcv4 may be the same as the width Wcv4 in the example illustrated in FIG.
　半導体基板１０の上面視において、第１カソード領域８２、第２カソード領域８３および第３カソード領域８４の合計面積に占める第１カソード領域８２の面積の割合は、６０％以上９０％以下であってよい。当該合計面積に占める第２カソード領域８３および第３カソード領域８４の合計面積の割合は、１０％以上４０％以下であってよい。一例として、第１カソード領域８２、第２カソード領域８３および第３カソード領域８４の合計面積に占める第１カソード領域８２の面積の割合は、８０％である。一例として、第１カソード領域８２、第２カソード領域８３および第３カソード領域８４の合計面積に占める第２カソード領域８３および第３カソード領域８４の合計面積の割合は、２０％である。 In the top view of the semiconductor substrate 10, the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82, the second cathode region 83, and the third cathode region 84 is 60% or more and 90% or less. Good. The ratio of the total area of the second cathode region 83 and the third cathode region 84 in the total area may be 10% or more and 40% or less. As an example, the ratio of the area of the first cathode region 82 to the total area of the first cathode region 82, the second cathode region 83, and the third cathode region 84 is 80%. As an example, the ratio of the total area of the second cathode region 83 and the third cathode region 84 to the total area of the first cathode region 82, the second cathode region 83, and the third cathode region 84 is 20%.
　図１１ｃは、図１１ｂにおける領域Ｃ９の拡大図である。図１１ｃに示すように、本例の半導体装置１００は、半導体基板１０の上面視で、第１カソード領域８２および第２カソード領域８３を挟むように、第３カソード領域８４が設けられる。即ち、半導体基板１０の上面視で、第３カソード領域８４が第１カソード領域８２および第２カソード領域８３を挟む方向（本例においてはＸ軸方向）に沿った、第２カソード領域８３のＸ軸方向正側の端部Ｕ１において、第２カソード領域８３と接して設けられた第３カソード領域８４を備える。また、第２カソード領域８３のＸ軸方向負側の端部Ｕ２において、第２カソード領域８３と接して設けられた第３カソード領域８４を備える。 FIG. 11c is an enlarged view of region C9 in FIG. 11b. As shown in FIG. 11c, the semiconductor device 100 of this example is provided with a third cathode region 84 so as to sandwich the first cathode region 82 and the second cathode region 83 when the semiconductor substrate 10 is viewed from above. That is, in the top view of the semiconductor substrate 10, the X of the second cathode region 83 is along the direction in which the third cathode region 84 sandwiches the first cathode region 82 and the second cathode region 83 (in this example, the X-axis direction). A third cathode region 84 provided in contact with the second cathode region 83 is provided at the end U1 on the axially positive side. The second cathode region 83 includes a third cathode region 84 provided in contact with the second cathode region 83 at the end U2 on the X axis direction negative side.
　第３カソード領域８４は、図１１ｃに示す通り、第２カソード領域８３の２つの端部のそれぞれに対して、接して設けられてよい。即ち、第３カソード領域８４は、第２カソード領域８３の一方の端部Ｕ１および他方の端部Ｕ２のそれぞれに対して、接して設けられてよい。 The third cathode region 84 may be provided in contact with each of the two ends of the second cathode region 83, as shown in FIG. 11c. That is, the third cathode region 84 may be provided in contact with each of the one end U1 and the other end U2 of the second cathode region 83.
　また、複数の第２カソード領域８３と複数の第３カソード領域８４とは、半導体基板１０の上面視で接していてよい。即ち、複数のそれぞれの第３カソード領域８４は、図１１ｃに示す通り、複数の第２カソード領域８３のそれぞれの端部に接して設けられてよい。即ち、領域Ｃ９において、第３カソード領域８４は、Ｙ軸方向負側に設けられる第２カソード領域８３の端部Ｕ１およびＹ軸方向正側に設けられる第２カソード領域８３の端部Ｕ１の双方に接して、設けられてよい。また、当該第３カソード領域８４は、Ｙ軸方向正側に設けられる当該第２カソード領域８３に対してＸ軸方向正側に隣り合って配置される第２カソード領域８３の端部Ｕ２およびＹ軸方向負側に設けられる当該第２カソード領域８３に対してＸ軸方向正側に隣り合って配置される第２カソード領域８３の端部Ｕ２の双方にも、接して設けられてよい。 Further, the plurality of second cathode regions 83 and the plurality of third cathode regions 84 may be in contact with each other when the semiconductor substrate 10 is viewed from above. That is, each of the plurality of third cathode regions 84 may be provided in contact with each end of the plurality of second cathode regions 83, as shown in FIG. 11c. That is, in the region C9, the third cathode region 84 includes both the end portion U1 of the second cathode region 83 provided on the Y axis direction negative side and the end portion U1 of the second cathode region 83 provided on the Y axis direction positive side. It may be provided in contact with. In addition, the third cathode region 84 has ends U2 and Y of the second cathode region 83 arranged adjacent to the second cathode region 83 provided on the Y axis direction positive side on the X axis direction positive side. The second cathode region 83 provided on the negative side in the axial direction may be provided in contact with both ends U2 of the second cathode region 83 arranged adjacent to the positive side in the X-axis direction.
　半導体基板１０の上面視で、第３カソード領域８４が第１カソード領域８２および第２カソード領域８３を挟む方向（本例においてはＸ軸方向）に沿った第２カソード領域８３の幅は、幅Ｗｃｖ２と等しくてよい。幅Ｗｃｖ２は、幅Ｗｃｃよりも大きくてよい。即ち、第２カソード領域８３は、Ｘ軸方向に長い長方形であってよい。 In the top view of the semiconductor substrate 10, the width of the second cathode region 83 along the direction in which the third cathode region 84 sandwiches the first cathode region 82 and the second cathode region 83 (in this example, the X-axis direction) is the width It may be equal to Wcv2. The width Wcv2 may be larger than the width Wcc. That is, the second cathode region 83 may be a rectangle that is long in the X-axis direction.
　半導体基板１０の上面視で、第１カソード領域８２と第２カソード領域８３との配列方向（本例においてはＹ軸方向）に沿った第２カソード領域８３の幅は、幅Ｗｃｈ１と等しくてよい。幅Ｗｃｖ２は、幅Ｗｃｈ１よりも大きくてよい。 The width of the second cathode region 83 along the arrangement direction of the first cathode region 82 and the second cathode region 83 (in this example, the Y-axis direction) in the top view of the semiconductor substrate 10 may be equal to the width Wch1. . The width Wcv2 may be larger than the width Wch1.
　幅Ｗｃｃは、幅Ｗｃｈ１よりも小さくてよい。幅Ｗｃｔは、幅Ｗｃｈ１よりも大きくてよい。幅Ｗｃｔは、ダイオード部８０のＹ軸方向の幅ＷＦと等しくてよい。 Width Wcc may be smaller than width Wch1. The width Wct may be larger than the width Wch1. The width Wct may be equal to the width WF of the diode unit 80 in the Y-axis direction.
　第３カソード領域８４のドーピング濃度は、第２カソード領域８３のドーピング濃度と等しくてよい。即ち、領域Ｃ９において、第２カソード領域８３および第３カソード領域８４は、ドーピング濃度の等しい第２導電型のカソード領域として、つながっていてよい。 The doping concentration of the third cathode region 84 may be equal to the doping concentration of the second cathode region 83. That is, in the region C9, the second cathode region 83 and the third cathode region 84 may be connected as a cathode region of the second conductivity type having the same doping concentration.
　また、図１１ａおよび図１１ｂの半導体基板１０の上面視において、１つのダイオード部８０における全ての第２カソード領域８３および第３カソード領域８４のドーピング濃度が等しくてよい。また、１つのダイオード部８０における全ての第２カソード領域８３および第３カソード領域８４が、ドーピング濃度の等しい第２導電型のカソード領域としてつながっていてよい。いいかえると、１つのダイオード部８０における全ての第２カソード領域８３および第３カソード領域８４は、ドーピング濃度の等しい第２導電型のカソード領域として、一体であってよい。 Further, in the top view of the semiconductor substrate 10 of FIGS. 11a and 11b, the doping concentrations of all the second cathode regions 83 and the third cathode regions 84 in one diode portion 80 may be equal. Further, all the second cathode regions 83 and the third cathode regions 84 in one diode portion 80 may be connected as cathode regions of the second conductivity type having the same doping concentration. In other words, all the second cathode regions 83 and the third cathode regions 84 in one diode unit 80 may be integrated as a cathode region of the second conductivity type having the same doping concentration.
　図１１ｄは、図１１ｂにおけるｕ－ｕ'断面の一例を示す図である。本例の半導体装置１００におけるｕ－ｕ'断面の構成は、図９ｄの半導体装置１００におけるｑ－ｑ'断面の構成と同じである。 FIG. 11d is a diagram showing an example of a uu ′ cross section in FIG. 11b. The configuration of the uu ′ section in the semiconductor device 100 of this example is the same as the configuration of the qq ′ section in the semiconductor device 100 of FIG. 9D.
　図１１ｅは、図１１ｂにおけるｖ－ｖ'断面の一例を示す図である。ｖ－ｖ'断面は、図１１ｄにおけるｖ''－ｖ'''線を通るＸＺ平面である。本例の半導体装置１００は、ｖ－ｖ'断面において、下面２３に接して第１カソード領域８２および第３カソード領域８４を有する。第１カソード領域８２および第３カソード領域８４は、Ｘ軸方向に交互に設けられる。 FIG. 11e is a diagram showing an example of a vv ′ cross section in FIG. 11b. The vv ′ cross section is an XZ plane passing through the line v ″ -v ′ ″ in FIG. 11d. The semiconductor device 100 of this example includes a first cathode region 82 and a third cathode region 84 in contact with the lower surface 23 in the vv ′ cross section. The first cathode regions 82 and the third cathode regions 84 are alternately provided in the X-axis direction.
　本例の半導体装置１００は、第３カソード領域８４が、第２カソード領域８３の一方の端部Ｕ１および他方の端部Ｕ２のそれぞれに対して、接して設けられる。また、第３カソード領域８４が、複数の第２カソード領域８３のそれぞれの端部に接して設けられる。このため、ダイオード部８０の逆回復時におけるサージ電圧を抑制することができる。 In the semiconductor device 100 of this example, the third cathode region 84 is provided in contact with one end U1 and the other end U2 of the second cathode region 83, respectively. A third cathode region 84 is provided in contact with each end of the plurality of second cathode regions 83. For this reason, the surge voltage at the time of reverse recovery of the diode part 80 can be suppressed.
　図１２ａは、本実施形態に係る半導体装置２００の上面の他の一例を示す図である。半導体装置２００は、ＦＷＤ等のダイオードである。半導体基板１０には、半導体装置１００と同様の活性部７２、外周領域７４が設けられる。ただし本例の活性部７２には、ダイオード部８０が設けられ、トランジスタ部７０は設けられていなくてよい。 FIG. 12 a is a diagram illustrating another example of the upper surface of the semiconductor device 200 according to the present embodiment. The semiconductor device 200 is a diode such as FWD. The semiconductor substrate 10 is provided with an active portion 72 and an outer peripheral region 74 similar to those of the semiconductor device 100. However, the active portion 72 of this example is provided with the diode portion 80 and the transistor portion 70 may not be provided.
　活性部７２には、ダイオード部８０がＹ軸方向に複数設けられてよい。ダイオード部８０は、第１カソード領域８２および第２カソード領域８３を備える。 The active unit 72 may be provided with a plurality of diode units 80 in the Y-axis direction. The diode unit 80 includes a first cathode region 82 and a second cathode region 83.
　本例の半導体装置２００において、第１カソード領域８２は第１導電型である。本例の第１カソード領域は、一例としてＮ＋型である。第２カソード領域８３は、第１カソード領域８２とは導電型が異なる。本例の第２カソード領域８３は、一例としてＰ＋型である。 In the semiconductor device 200 of this example, the first cathode region 82 is the first conductivity type. The first cathode region in this example is an N + type as an example. The second cathode region 83 has a conductivity type different from that of the first cathode region 82. The second cathode region 83 of this example is a P + type as an example.
　幅Ｗｈは、半導体基板１０の上面視における、半導体装置２００のＸ軸方向の幅である。幅ＷＦは、半導体基板１０の上面視における、半導体装置２００のＹ軸方向の幅である。なお、図１２ａにおいて、第１カソード領域８２および第２カソード領域８３以外の構成、即ちダミートレンチ部３０等の構成を、省略して示している。 The width Wh is a width in the X-axis direction of the semiconductor device 200 when the semiconductor substrate 10 is viewed from above. The width WF is a width in the Y-axis direction of the semiconductor device 200 when the semiconductor substrate 10 is viewed from above. In FIG. 12a, the configuration other than the first cathode region 82 and the second cathode region 83, that is, the configuration of the dummy trench portion 30 and the like is omitted.
　本例の半導体装置２００は、半導体基板１０の上面視で、第１カソード領域８２毎に互いに分離して設けられた複数のフローティング領域１７を有する。フローティング領域１７は第２導電型である。本例のフローティング領域１７は、一例としてＰ＋型である。 The semiconductor device 200 of this example has a plurality of floating regions 17 provided separately from each other for each first cathode region 82 in a top view of the semiconductor substrate 10. The floating region 17 is of the second conductivity type. The floating region 17 of this example is a P + type as an example.
　フローティング領域１７は、半導体基板１０の上面視で、第１カソード領域８２と少なくとも部分的に重なって配置される。図１２ａは、半導体基板１０の上面視で、フローティング領域１７の全体が、第１カソード領域８２と重なって配置される一例を示している。 The floating region 17 is disposed so as to at least partially overlap the first cathode region 82 when the semiconductor substrate 10 is viewed from above. FIG. 12 a shows an example in which the entire floating region 17 is disposed so as to overlap the first cathode region 82 in a top view of the semiconductor substrate 10.
　本例の半導体装置２００は、第１カソード領域８２が、半導体基板１０の上面視で、フローティング領域１７よりもＹ軸方向に張り出している。本例の半導体装置２００は、Ｙ軸方向において、第１カソード領域８２の両側が、半導体基板１０の上面視でフローティング領域１７よりも張り出している。即ち、第１カソード領域８２は、Ｙ軸方向におけるフローティング領域１７の両側において、フローティング領域１７に覆われていない部分を有する。 In the semiconductor device 200 of this example, the first cathode region 82 protrudes in the Y-axis direction from the floating region 17 in a top view of the semiconductor substrate 10. In the semiconductor device 200 of this example, both sides of the first cathode region 82 protrude from the floating region 17 in a top view of the semiconductor substrate 10 in the Y-axis direction. That is, the first cathode region 82 has portions that are not covered by the floating region 17 on both sides of the floating region 17 in the Y-axis direction.
　また、本例の半導体装置２００は、第１カソード領域８２が、フローティング領域１７よりもＸ軸方向に張り出している。本例の半導体装置２００は、Ｘ軸方向において、第１カソード領域８２の両側が、半導体基板１０の上面視でフローティング領域１７よりも張り出している。即ち、第１カソード領域８２は、Ｘ軸方向におけるフローティング領域１７の両側において、フローティング領域１７に覆われていない部分を有する。 Further, in the semiconductor device 200 of this example, the first cathode region 82 protrudes in the X-axis direction from the floating region 17. In the semiconductor device 200 of this example, both sides of the first cathode region 82 protrude from the floating region 17 in a top view of the semiconductor substrate 10 in the X-axis direction. That is, the first cathode region 82 has portions that are not covered by the floating region 17 on both sides of the floating region 17 in the X-axis direction.
　本例の半導体装置２００は、半導体基板１０の上面視で、フローティング領域１７の全体が、第１カソード領域８２と重なって配置される。即ち、本例の半導体装置２００は、半導体基板１０の上面視で、第１カソード領域８２の内側にフローティング領域１７が設けられる。フローティング領域１７は、第１カソード領域８２毎に互いに分離して設けられる。なお、フローティング領域１７の少なくとも一部が、第１カソード領域８２と重なって配置されてもよい。 In the semiconductor device 200 of this example, the entire floating region 17 is disposed so as to overlap the first cathode region 82 when the semiconductor substrate 10 is viewed from above. That is, in the semiconductor device 200 of this example, the floating region 17 is provided inside the first cathode region 82 when the semiconductor substrate 10 is viewed from above. The floating region 17 is provided separately for each first cathode region 82. Note that at least a part of the floating region 17 may be disposed so as to overlap the first cathode region 82.
　図１２ｂは、図１２ａにおける領域Ｅ１の拡大図である。図１２ｂに示すように、本例の半導体装置２００は、半導体基板１０の上面視で、第１カソード領域８２の内側にフローティング領域１７が設けられる。フローティング領域１７は、第１カソード領域８２毎に互いに分離して設けられ、第１カソード領域８２と少なくとも部分的に重なって配置される。本例は、半導体基板１０の上面視におけるフローティング領域１７の全体が、第１カソード領域８２と重なって配置される一例である。フローティング領域１７は、第１カソード領域８２と接して設けられてよい。 FIG. 12b is an enlarged view of the region E1 in FIG. 12a. As shown in FIG. 12 b, the semiconductor device 200 of this example is provided with the floating region 17 inside the first cathode region 82 in a top view of the semiconductor substrate 10. The floating region 17 is provided separately from each other for each first cathode region 82, and is disposed to at least partially overlap the first cathode region 82. This example is an example in which the entire floating region 17 in a top view of the semiconductor substrate 10 is disposed so as to overlap the first cathode region 82. The floating region 17 may be provided in contact with the first cathode region 82.
　図１２ｃは、図１２ｂにおけるａａ－ａａ'断面の一例を示す図である。本例の半導体装置２００は、ａａ－ａａ'断面において、半導体基板１０、層間絶縁膜３８、エミッタ電極５２およびコレクタ電極２４を有する。エミッタ電極５２は、上面２１および層間絶縁膜３８の上面に設けられる。コレクタ電極２４は、下面２３に設けられる。 FIG. 12c is a diagram showing an example of a cross section aa-aa ′ in FIG. 12b. The semiconductor device 200 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in the aa-aa ′ cross section. The emitter electrode 52 is provided on the upper surface 21 and the upper surface of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23.
　本例の半導体装置２００は、半導体基板１０に設けられた第１導電型のドリフト領域１８を有する。また、本例の半導体装置２００は、上面２１に接し、ドリフト領域１８よりも上方に設けられた第２導電型のベース領域１４を有する。また、本例の半導体装置２００は、下面２３に接し、ドリフト領域１８よりも下方に設けられた、互いに分離した複数の第１導電型の第１カソード領域８２および第２カソード領域８３を有する。半導体装置２００は、高濃度領域１９を有さなくてもよい。さらに、高濃度領域１９を有さない場合は、ダミートレンチ部３０を有さなくてもよい。 The semiconductor device 200 of this example has a drift region 18 of the first conductivity type provided on the semiconductor substrate 10. In addition, the semiconductor device 200 of the present example includes a second conductivity type base region 14 provided in contact with the upper surface 21 and above the drift region 18. In addition, the semiconductor device 200 of the present example includes a plurality of first cathode regions 82 and 83 of a first conductivity type that are in contact with the lower surface 23 and provided below the drift region 18 and are separated from each other. The semiconductor device 200 may not have the high concentration region 19. Further, when the high concentration region 19 is not provided, the dummy trench portion 30 may not be provided.
　図１２ｄは、図１２ｂにおけるｂｂ－ｂｂ'断面の一例を示す図である。ｂｂ－ｂｂ'断面は、図１２ｃにおけるｂｂ''－ｂｂ'''線を通るＸＺ平面である。本例の半導体装置２００は、ｂｂ－ｂｂ'断面において、フローティング領域１７が、第１カソード領域８２の上方に、端部位置Ｐ６から端部位置Ｐ６'まで、Ｘ軸方向に連続して設けられる。フローティング領域１７は、第１カソード領域８２と接して設けられてよい。 FIG. 12d is a diagram showing an example of a bb-bb ′ cross section in FIG. 12b. The bb-bb ′ cross section is an XZ plane passing through the line bb ″ -bb ′ ″ in FIG. 12c. In the semiconductor device 200 of this example, the floating region 17 is continuously provided in the X-axis direction from the end position P6 to the end position P6 ′ above the first cathode region 82 in the bb-bb ′ cross section. . The floating region 17 may be provided in contact with the first cathode region 82.
　なお、図１２ｄにおけるＸ軸方向正側の第２カソード領域８３は、図１２ａにおけるＸ軸方向正側の外周領域７４まで延伸していてよい。また、Ｘ軸方向負側の第２カソード領域８３は、図１２ａにおけるＸ軸方向負側の外周領域７４まで延伸していてよい。外周領域７４の下方においては、下面２３には、第２カソード領域８３に代えて、第１カソード領域８２よりもドーピング濃度の薄い第１導電型の終端領域が設けられてよい。終端領域のドーピング濃度は、第１カソード領域８２のドーピング濃度の１／１０以下であってよい。 It should be noted that the second cathode region 83 on the X axis direction positive side in FIG. 12d may extend to the outer peripheral region 74 on the X axis direction positive side in FIG. 12a. Further, the second cathode region 83 on the X axis direction negative side may extend to the outer peripheral region 74 on the X axis direction negative side in FIG. Below the outer peripheral region 74, a first conductivity type termination region having a doping concentration lower than that of the first cathode region 82 may be provided on the lower surface 23 instead of the second cathode region 83. The doping concentration of the termination region may be 1/10 or less of the doping concentration of the first cathode region 82.
　本例の半導体装置２００は、フローティング領域１７は、第１カソード領域８２毎に互いに分離して設けられ、第１カソード領域８２毎に、第１カソード領域８２の上方に設けられる。このため、半導体装置２００の逆回復時のサージ電圧を抑制することができる。 In the semiconductor device 200 of this example, the floating region 17 is provided separately for each first cathode region 82 and is provided above the first cathode region 82 for each first cathode region 82. For this reason, the surge voltage at the time of reverse recovery of the semiconductor device 200 can be suppressed.
　図１３ａは、本実施形態に係る半導体装置２００の上面の他の一例を示す図である。本例の半導体装置２００は、図１２ａに示す半導体装置２００において、第１カソード領域８２が、領域Ｅ２で示した、ダイオードの単位構造のＹ軸方向正側の端部領域から負側の端部領域まで、連続して設けられる点で、図１２ａに示す半導体装置２００と異なる。また、図１２ａに示す半導体装置２００において、第１カソード領域８２と第２カソード領域８３が、Ｘ軸方向に交互に設けられる点で、図１５ａに示す半導体装置２００と異なる。 FIG. 13a is a diagram showing another example of the upper surface of the semiconductor device 200 according to the present embodiment. In the semiconductor device 200 of this example, in the semiconductor device 200 shown in FIG. 12A, the first cathode region 82 is an end portion on the negative side from the end region on the positive side in the Y-axis direction of the unit structure of the diode indicated by the region E2. The semiconductor device 200 is different from the semiconductor device 200 shown in FIG. Further, the semiconductor device 200 shown in FIG. 12A differs from the semiconductor device 200 shown in FIG. 15A in that the first cathode regions 82 and the second cathode regions 83 are alternately provided in the X-axis direction.
　図１３ｂは、図１３ａにおける領域Ｅ２の拡大図である。図１３ｂに示すように、本例の半導体装置２００は、第１カソード領域８２が、ダイオードの単位構造のＹ軸方向正側の端部領域から負側の端部領域まで、連続して設けられる。また、第１カソード領域８２と第２カソード領域８３が、Ｘ軸方向に交互に設けられる。 FIG. 13b is an enlarged view of region E2 in FIG. 13a. As shown in FIG. 13b, in the semiconductor device 200 of this example, the first cathode region 82 is continuously provided from the end region on the positive side in the Y-axis direction of the unit structure of the diode to the end region on the negative side. . The first cathode regions 82 and the second cathode regions 83 are alternately provided in the X-axis direction.
　本例の半導体装置２００は、半導体基板１０の上面視で、第１カソード領域８２の内側にフローティング領域１７が設けられる。フローティング領域１７は、Ｘ軸方向に１０個設けられる。フローティング領域１７は、第１カソード領域８２の上方に設けられる。フローティング領域１７は、第１カソード領域８２と接して設けられてよい。 In the semiconductor device 200 of this example, the floating region 17 is provided inside the first cathode region 82 when the semiconductor substrate 10 is viewed from above. Ten floating regions 17 are provided in the X-axis direction. The floating region 17 is provided above the first cathode region 82. The floating region 17 may be provided in contact with the first cathode region 82.
　図１３ｃは、図１３ｂにおけるｃｃ－ｃｃ'断面の一例を示す図である。本例の半導体装置２００は、ｃｃ－ｃｃ'断面において、第１カソード領域８２が、半導体装置２００のＹ軸方向正側の端部領域から負側の端部領域まで、Ｙ軸方向に連続して設けられる。第１カソード領域８２のＹ軸方向の幅Ｗｃｈ２は、半導体装置２００のＹ軸方向の幅ＷＦと等しい。 FIG. 13c is a diagram showing an example of a cc-cc ′ cross section in FIG. 13b. In the semiconductor device 200 of this example, in the cc-cc ′ cross section, the first cathode region 82 continues in the Y-axis direction from the Y-axis direction positive end region to the negative-side end region of the semiconductor device 200. Provided. The width Wch2 in the Y-axis direction of the first cathode region 82 is equal to the width WF in the Y-axis direction of the semiconductor device 200.
　図１３ｄは、図１３ｂにおけるｄｄ－ｄｄ'断面の一例を示す図である。ｄｄ－ｄｄ'断面は、図１３ｃにおけるｄｄ''－ｄｄ'''線を通るＸＺ平面である。本例の半導体装置２００は、Ｘ軸方向において、下面２３に接して第１カソード領域８２および第２カソード領域８３が交互に設けられる。また、フローティング領域１７が、第１カソード領域８２の上方に、第１カソード領域８２と接して設けられる。このため、半導体装置２００の逆回復時のサージ電圧を抑制することができる。 FIG. 13d is a diagram showing an example of a dd-dd ′ section in FIG. 13b. The section dd-dd ′ is the XZ plane passing through the line dd ″ -dd ′ ″ in FIG. 13c. In the semiconductor device 200 of this example, the first cathode regions 82 and the second cathode regions 83 are alternately provided in contact with the lower surface 23 in the X-axis direction. The floating region 17 is provided above the first cathode region 82 and in contact with the first cathode region 82. For this reason, the surge voltage at the time of reverse recovery of the semiconductor device 200 can be suppressed.
　図１４ａは、本実施形態に係る半導体装置２００の上面の他の一例を示す図である。本例の半導体装置２００は、半導体基板１０の上面視で、第１カソード領域８２が互いに分離して格子状に設けられる。図１４ａは、領域Ｅ３で示した、ダイオードの単位構造において、第１カソード領域８２がＸ軸方向に１０個設けられ、Ｙ軸方向に３個設けられる一例を示している。 FIG. 14 a is a diagram showing another example of the upper surface of the semiconductor device 200 according to the present embodiment. In the semiconductor device 200 of this example, the first cathode regions 82 are separated from each other and provided in a lattice shape when the semiconductor substrate 10 is viewed from above. FIG. 14A shows an example in which ten first cathode regions 82 are provided in the X-axis direction and three in the Y-axis direction in the diode unit structure shown by the region E3.
　図１４ｂは、図１４ａにおける領域Ｅ３の拡大図である。図１４ｂに示すように、本例の半導体装置２００は、半導体基板１０の上面視で、第１カソード領域８２の内側にフローティング領域１７が設けられる。フローティング領域１７は、Ｘ軸方向に１０個、Ｙ軸方向に３個設けられる。 FIG. 14b is an enlarged view of the region E3 in FIG. 14a. As shown in FIG. 14 b, the semiconductor device 200 of this example is provided with the floating region 17 inside the first cathode region 82 in a top view of the semiconductor substrate 10. Ten floating regions 17 are provided in the X-axis direction and three in the Y-axis direction.
　半導体基板１０の上面視で、Ｙ軸方向に隣り合う２つの第１カソード領域８２の間には、第２カソード領域８３が設けられる。Ｘ軸方向に隣り合う２つの第１カソード領域８２の間には、第２導電型の第３カソード領域８４が設けられる。半導体基板１０の上面視で、Ｘ軸方向に隣り合う２つの第２カソード領域８３の間にも、第３カソード領域８４が設けられる。 A second cathode region 83 is provided between two first cathode regions 82 adjacent to each other in the Y-axis direction when the semiconductor substrate 10 is viewed from above. Between the two first cathode regions 82 adjacent in the X-axis direction, a second conductivity type third cathode region 84 is provided. A third cathode region 84 is also provided between two second cathode regions 83 adjacent in the X-axis direction when the semiconductor substrate 10 is viewed from above.
　第３カソード領域８４は、一例としてＰ＋型である。第３カソード領域８４のドーピング濃度は、第２カソード領域８３のドーピング濃度と等しくてよい。第２カソード領域８３および第３カソード領域８４は、ドーピング濃度の等しいカソード領域としてつながっていてよい。 The third cathode region 84 is a P + type as an example. The doping concentration of the third cathode region 84 may be equal to the doping concentration of the second cathode region 83. The second cathode region 83 and the third cathode region 84 may be connected as cathode regions having the same doping concentration.
　図１４ｃは、図１４ｂにおけるｅｅ－ｅｅ'断面の一例を示す図である。本例の半導体装置２００におけるｅｅ－ｅｅ'断面の構成は、図１２ｃに示す半導体装置２００におけるａａ－ａａ'断面の構成と同じである。 FIG. 14c is a diagram showing an example of a cross-section ee-ee ′ in FIG. 14b. The configuration of the ee-ee ′ section in the semiconductor device 200 of this example is the same as the configuration of the aa-aa ′ section in the semiconductor device 200 shown in FIG.
　図１４ｄは、図１４ｂにおけるｆｆ－ｆｆ'断面の一例を示す図である。ｆｆ－ｆｆ'断面は、図１４ｃにおけるｆｆ''－ｆｆ'''線を通るＸＺ平面である。本例の半導体装置２００におけるｆｆ－ｆｆ'断面の構成は、図１３ｄに示すｄｄ－ｄｄ'断面において、第２カソード領域８３に代えて第３カソード領域８４が設けられる点で、図１３ｄに示すｄｄ－ｄｄ'断面の構成と異なる。 FIG. 14d is a diagram showing an example of the ff-ff ′ cross section in FIG. 14b. The ff-ff ′ cross section is the XZ plane passing through the line ff ″ -ff ′ ″ in FIG. 14c. The configuration of the ff-ff ′ cross section in the semiconductor device 200 of this example is shown in FIG. 13d in that a third cathode region 84 is provided in place of the second cathode region 83 in the dd-dd ′ cross section shown in FIG. 13d. Different from the configuration of the dd-dd ′ cross section.
　本例の半導体装置２００は、Ｘ軸方向において、下面２３に接して第１カソード領域８２および第３カソード領域８４が交互に設けられ、且つ、第１カソード領域８２の上方に、第１カソード領域８２に接してフローティング領域１７が設けられる。このため、半導体装置２００の逆回復時のサージ電圧を抑制することができる。 In the semiconductor device 200 of this example, the first cathode region 82 and the third cathode region 84 are alternately provided in contact with the lower surface 23 in the X-axis direction, and the first cathode region 82 is located above the first cathode region 82. A floating region 17 is provided in contact with 82. For this reason, the surge voltage at the time of reverse recovery of the semiconductor device 200 can be suppressed.
　図１５ａは、本実施形態に係る半導体装置２００の上面の一例を示す図である。図１５ａに示す半導体装置２００は、図１２ａに示す半導体装置２００において、フローティング領域１７が設けられない点で、図１２ａに示す半導体装置２００と異なる。本例の半導体装置２００は、領域Ｅ４で示されるダイオードの単位構造が、Ｙ軸方向に配列されている。 FIG. 15 a is a diagram illustrating an example of the upper surface of the semiconductor device 200 according to the present embodiment. The semiconductor device 200 shown in FIG. 15a is different from the semiconductor device 200 shown in FIG. 12a in that the floating region 17 is not provided in the semiconductor device 200 shown in FIG. 12a. In the semiconductor device 200 of this example, the diode unit structure indicated by the region E4 is arranged in the Y-axis direction.
　図１５ｂは、図１５ａにおける領域Ｅ４の拡大図である。図１ｂに示すように、本例の半導体装置２００は、第１カソード領域８２のＸ軸方向正側および負側に、それぞれ下面２３に接して第２カソード領域８３が設けられる。当該第２カソード領域８３は、第１カソード領域８２のＹ軸方向に隣接する第２カソード領域８３と、つながっていてよい。 FIG. 15b is an enlarged view of region E4 in FIG. 15a. As shown in FIG. 1b, the semiconductor device 200 of this example is provided with a second cathode region 83 on the positive side and the negative side of the first cathode region 82 in contact with the lower surface 23, respectively. The second cathode region 83 may be connected to the second cathode region 83 adjacent to the first cathode region 82 in the Y-axis direction.
　図１５ｃは、図１５ｂにおけるｇｇ－ｇｇ'断面の一例を示す図である。本例の半導体装置２００におけるｇｇ－ｇｇ'断面の構成は、図１２ｃに示すａａ－ａａ'断面において、第１カソード領域８２の上方にフローティング領域１７が設けられない点で、図１２ｃに示すａａ－ａａ'断面の構成と異なる。 FIG. 15c is a diagram showing an example of a gg-gg ′ section in FIG. 15b. The configuration of the gg-gg ′ cross section in the semiconductor device 200 of this example is that the floating region 17 is not provided above the first cathode region 82 in the cross section aa-aa ′ shown in FIG. 12c. -Different from the configuration of the cross section aa '.
　図１５ｄは、図１５ｂにおけるｈｈ－ｈｈ'断面の一例を示す図である。ｈｈ－ｈｈ'断面は、図１５ｃにおけるｈｈ''－ｈｈ'''線を通るＸＺ平面である。 FIG. 15d is a diagram showing an example of a hh-hh ′ cross section in FIG. 15b. The hh-hh ′ cross section is an XZ plane passing through the line hh ″ -hh ′ ″ in FIG. 15C.
　本例の半導体装置２００におけるｈｈ－ｈｈ'断面の構成は、図２ｅに示す半導体装置１００において、フローティング領域１７が設けられない点およびＸ軸方向の両端にコレクタ領域２２が設けられず、第２カソード領域８３が設けられる点を除き、図２ｅに示す半導体装置１００におけるｂ－ｂ'断面の構成と同じである。 The configuration of the hh-hh ′ cross section in the semiconductor device 200 of the present example is that the floating region 17 is not provided and the collector regions 22 are not provided at both ends in the X-axis direction in the semiconductor device 100 shown in FIG. Except that the cathode region 83 is provided, the configuration is the same as that of the bb ′ cross section in the semiconductor device 100 shown in FIG. 2e.
　本例の半導体装置２００は、下面２３に接して第１カソード領域８２および第２カソード領域８３を有する。第２カソード領域８３は、Ｘ軸方向の両端に設けられる。第１カソード領域８２は、Ｘ軸方向において第２カソード領域８３に挟まれて設けられる。第２カソード領域８３は、第１カソード領域８２とは導電型またはドーピング濃度が異なる。このため、半導体装置２００の逆回復時のサージ電圧を抑制することができる。 The semiconductor device 200 of this example has a first cathode region 82 and a second cathode region 83 in contact with the lower surface 23. The second cathode regions 83 are provided at both ends in the X axis direction. The first cathode region 82 is provided between the second cathode regions 83 in the X-axis direction. The second cathode region 83 is different in conductivity type or doping concentration from the first cathode region 82. For this reason, the surge voltage at the time of reverse recovery of the semiconductor device 200 can be suppressed.
　図１６ａは、本実施形態に係る半導体装置２００の上面の他の一例を示す図である。本例の半導体装置２００は、図１３ａに示す半導体装置２００において、フローティング領域１７が設けられない点で、図１３ａに示す半導体装置２００と異なる。本例の半導体装置２００は、領域Ｅ５で示されるダイオードの単位構造が、Ｙ軸方向に配列されている。 FIG. 16 a is a diagram showing another example of the upper surface of the semiconductor device 200 according to the present embodiment. The semiconductor device 200 of this example is different from the semiconductor device 200 shown in FIG. 13A in that the floating region 17 is not provided in the semiconductor device 200 shown in FIG. 13A. In the semiconductor device 200 of this example, the unit structures of the diode indicated by the region E5 are arranged in the Y-axis direction.
　図１６ｂは、図１６ａにおける領域Ｅ５の拡大図である。図１６ｂに示すように、本例の半導体装置２００は、第１カソード領域８２が、ダイオードの単位構造のＹ軸方向正側の端部領域から負側の端部領域まで、連続して設けられる。また、第１カソード領域８２と第２カソード領域８３が、Ｘ軸方向に交互に設けられる。 FIG. 16b is an enlarged view of region E5 in FIG. 16a. As shown in FIG. 16b, in the semiconductor device 200 of this example, the first cathode region 82 is continuously provided from the end region on the positive side in the Y-axis direction of the unit structure of the diode to the end region on the negative side. . The first cathode regions 82 and the second cathode regions 83 are alternately provided in the X-axis direction.
　図１６ｃは、図１６ｂにおけるｉｉ－ｉｉ'断面の一例を示す図である。本例の半導体装置２００におけるｉｉ－ｉｉ'断面の構成は、図１３ｃに示すｃｃ－ｃｃ'断面において、第１カソード領域８２の上方にフローティング領域１７が設けられない点で、図１３ｃに示すｃｃ－ｃｃ'断面の構成と異なる。 FIG. 16c is a diagram showing an example of a section ii-ii ′ in FIG. 16b. The configuration of the semiconductor device 200 of this example in the section ii-ii ′ is that the floating region 17 is not provided above the first cathode region 82 in the section cc-cc ′ shown in FIG. 13c. -Different from the configuration of the cc 'cross section.
　図１６ｄは、図１６ｂにおけるｊｊ－ｊｊ'断面の一例を示す図である。ｊｊ－ｊｊ'断面は、図１６ｃにおけるｊｊ''－ｊｊ'''線を通るＸＺ平面である。本例の半導体装置２００は、Ｘ軸方向において、下面２３に接して第１カソード領域８２および第２カソード領域８３が交互に設けられる。このため、半導体装置２００の逆回復時のサージ電圧を抑制することができる。 FIG. 16d is a diagram showing an example of a jj-jj ′ cross section in FIG. 16b. The jj-jj ′ cross section is the XZ plane passing through the jj ″ -jj ′ ″ line in FIG. 16c. In the semiconductor device 200 of this example, the first cathode regions 82 and the second cathode regions 83 are alternately provided in contact with the lower surface 23 in the X-axis direction. For this reason, the surge voltage at the time of reverse recovery of the semiconductor device 200 can be suppressed.
　図１７ａは、本実施形態に係る半導体装置２００の上面の他の一例を示す図である。本例の半導体装置２００は、図１４ａに示す半導体装置２００において、フローティング領域１７が設けられない点で、図１４ａに示す半導体装置２００と異なる。本例の半導体装置２００は、領域Ｅ６で示されるダイオードの単位構造が、Ｙ軸方向に配列されている。 FIG. 17a is a diagram showing another example of the upper surface of the semiconductor device 200 according to the present embodiment. The semiconductor device 200 of this example is different from the semiconductor device 200 shown in FIG. 14A in that the floating region 17 is not provided in the semiconductor device 200 shown in FIG. 14A. In the semiconductor device 200 of this example, the diode unit structures indicated by the region E6 are arranged in the Y-axis direction.
　図１７ｂは、図１７ａにおける領域Ｅ６の拡大図である。図１７ｂに示すように、本例の半導体装置２００は、ダイオードの単位構造において、半導体基板１０の上面視で第１カソード領域８２が互いに分離して格子状に設けられる。 FIG. 17b is an enlarged view of region E6 in FIG. 17a. As shown in FIG. 17B, in the semiconductor device 200 of this example, in the unit structure of the diode, the first cathode regions 82 are separated from each other and provided in a grid pattern when the semiconductor substrate 10 is viewed from above.
　図１７ｃは、図１７ｂにおけるｋｋ－ｋｋ'断面の一例を示す図である。本例の半導体装置２００におけるｋｋ－ｋｋ'断面の構成は、図１５ｃに示す半導体装置２００におけるｇｇ－ｇｇ'断面の構成と同じである。 FIG. 17c is a diagram showing an example of a kk-kk ′ cross section in FIG. 17b. The configuration of the kk-kk ′ section in the semiconductor device 200 of this example is the same as the configuration of the gg-gg ′ section in the semiconductor device 200 shown in FIG. 15c.
　図１７ｄは、図１７ｂにおけるｍｍ－ｍｍ'断面の一例を示す図である。ｍｍ－ｍｍ'断面は、図１７ｃにおけるｍｍ''－ｍｍ'''線を通るＸＺ平面である。本例の半導体装置２００におけるｍｍ－ｍｍ'断面の構成は、図１６ｄに示す半導体装置２００におけるｊｊ－ｊｊ'断面において、第２カソード領域８３に代えて第３カソード領域８４が設けられる点で、図１６ｄに示すｊｊ－ｊｊ'断面の構成と異なる。 FIG. 17d is a diagram showing an example of the mm-mm ′ cross section in FIG. 17b. The mm-mm ′ cross section is the XZ plane that passes through the mm ″ -mm ′ ″ line in FIG. 17c. The configuration of the mm-mm ′ cross section of the semiconductor device 200 of this example is that a third cathode region 84 is provided in place of the second cathode region 83 in the jj-jj ′ cross section of the semiconductor device 200 shown in FIG. It differs from the configuration of the jj-jj ′ cross section shown in FIG.
　本例の半導体装置２００は、Ｘ軸方向において、下面２３に接して第１カソード領域８２および第３カソード領域８４が交互に設けられる。このため、半導体装置２００の逆回復時のサージ電圧を抑制することができる。 In the semiconductor device 200 of this example, the first cathode region 82 and the third cathode region 84 are alternately provided in contact with the lower surface 23 in the X-axis direction. For this reason, the surge voltage at the time of reverse recovery of the semiconductor device 200 can be suppressed.
　以上、本発明を実施の形態を用いて説明したが、本発明の技術的範囲は上記実施の形態に記載の範囲には限定されない。上記実施の形態に、多様な変更または改良を加えることが可能であることが当業者に明らかである。その様な変更または改良を加えた形態も本発明の技術的範囲に含まれ得ることが、請求の範囲の記載から明らかである。 As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.
　請求の範囲、明細書、および図面中において示した装置、システム、プログラム、および方法における動作、手順、ステップ、および段階等の各処理の実行順序は、特段「より前に」、「先立って」等と明示しておらず、また、前の処理の出力を後の処理で用いるのでない限り、任意の順序で実現しうることに留意すべきである。請求の範囲、明細書、および図面中の動作フローに関して、便宜上「まず、」、「次に、」等を用いて説明したとしても、この順で実施することが必須であることを意味するものではない。 The execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior”. It should be noted that they can be implemented in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for the sake of convenience, it means that it is essential to carry out in this order. is not.
１０・・・半導体基板、１１・・・ウェル領域、１２・・・エミッタ領域、１４・・・ベース領域、１５・・・コンタクト領域、１７・・・フローティング領域、１８・・・ドリフト領域、２０・・・バッファ領域、２１・・・上面、２２・・・コレクタ領域、２３・・・下面、２４・・・コレクタ電極、２９・・・直線部、３０・・・ダミートレンチ部、３１・・・先端部、３２・・・ダミー絶縁膜、３４・・・ダミー導電部、３８・・・層間絶縁膜、３９・・・直線部、４０・・・ゲートトレンチ部、４１・・・先端部、４８・・・ゲートランナー、４９・・・コンタクトホール、５０・・・ゲート金属層、５２・・・エミッタ電極、５３・・・、ケルビンパッド、５４・・・コンタクトホール、５５・・・ゲートパッド、５６・・・コンタクトホール、５８・・・電流センスパッド、５９・・・電流センス部、６０・・・メサ部、７０・・・トランジスタ部、７２・・・活性部、７４・・・外周領域、７６・・・外周端、８０・・・ダイオード部、８１・・・カソード領域、８２・・・第１カソード領域、８３・・・第２カソード領域、８４・・・第３カソード領域、９０・・・温度センス部、９２・・・温度センス配線、９４・・・温度測定用パッド、９６・・・検知部、１００・・・半導体装置、２００・・・半導体装置 DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Well region, 12 ... Emitter region, 14 ... Base region, 15 ... Contact region, 17 ... Floating region, 18 ... Drift region, 20 ... Buffer region, 21 ... Upper surface, 22 ... Collector region, 23 ... Lower surface, 24 ... Collector electrode, 29 ... Linear part, 30 ... Dummy trench part, 31 ... Tip part, 32 ... dummy insulating film, 34 ... dummy conductive part, 38 ... interlayer insulating film, 39 ... straight line part, 40 ... gate trench part, 41 ... tip part, 48 ... gate runner, 49 ... contact hole, 50 ... gate metal layer, 52 ... emitter electrode, 53 ..., Kelvin pad, 54 ... contact hole, 55 ... gate pad 56 ... Tact hole, 58 ... current sense pad, 59 ... current sense part, 60 ... mesa part, 70 ... transistor part, 72 ... active part, 74 ... outer peripheral area, 76 ... -Outer peripheral edge, 80 ... Diode part, 81 ... Cathode region, 82 ... First cathode region, 83 ... Second cathode region, 84 ... Third cathode region, 90 ... Temperature Sense unit, 92 ... temperature sense wiring, 94 ... temperature measuring pad, 96 ... detection unit, 100 ... semiconductor device, 200 ... semiconductor device

Claims (11)

  1. 　半導体基板と、
    　前記半導体基板に設けられたトランジスタ部と、
    　前記半導体基板に設けられ、予め定められた配列方向に沿って前記トランジスタ部と配列されたダイオード部と、
    　を備え、
    　前記ダイオード部は、
    　　前記半導体基板に設けられた第１導電型のドリフト領域と、
    　　前記半導体基板の上面に接し、前記ドリフト領域よりも上方に設けられた第２導電型のベース領域と、
    　　前記半導体基板の下面に接し、前記ドリフト領域よりも下方に設けられた、互いに分離した複数の第１導電型の第１カソード領域および前記第１カソード領域とは導電型が異なる第２カソード領域と、
    　　前記第１カソード領域毎に互いに分離して設けられ、前記第１カソード領域と少なくとも部分的に重なって配置された複数の第２導電型のフローティング領域と、
    　を有する、
    　半導体装置。     A semiconductor substrate;
    A transistor portion provided on the semiconductor substrate;
    A diode part provided on the semiconductor substrate and arranged with the transistor part along a predetermined arrangement direction;
    With
    The diode part is
    A first conductivity type drift region provided in the semiconductor substrate;
    A base region of a second conductivity type in contact with the upper surface of the semiconductor substrate and provided above the drift region;
    A plurality of first cathode regions of a first conductivity type that are in contact with a lower surface of the semiconductor substrate and are provided below the drift region and are separated from each other, and a second cathode region having a conductivity type different from that of the first cathode region ,
    A plurality of second conductivity type floating regions provided separately from each other for each of the first cathode regions, and disposed at least partially overlapping the first cathode region;
    Having
    Semiconductor device.
  2. 　前記第１カソード領域は、前記半導体基板の上面視で、前記フローティング領域よりも前記配列方向に張り出している、請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the first cathode region protrudes in the arrangement direction from the floating region in a top view of the semiconductor substrate.
  3. 　前記第１カソード領域および前記第２カソード領域は、前記上面視で、前記配列方向に直交する延伸方向に交互に配置され、
    　前記フローティング領域は、前記上面視で、前記第１カソード領域および前記第２カソード領域の両方と重なって、前記延伸方向に複数設けられる、
    　請求項２に記載の半導体装置。     The first cathode region and the second cathode region are alternately arranged in an extending direction perpendicular to the arrangement direction in the top view,
    A plurality of the floating regions are provided in the extending direction so as to overlap both the first cathode region and the second cathode region in the top view.
    The semiconductor device according to claim 2.
  4. 　前記フローティング領域は、前記上面視で、前記第１カソード領域よりも前記延伸方向に張り出している、請求項３に記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the floating region protrudes in the extending direction from the first cathode region in the top view.
  5. 　前記第１カソード領域は、前記フローティング領域よりも前記配列方向に直交する延伸方向に張り出している、請求項１から３のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 3, wherein the first cathode region protrudes in an extending direction perpendicular to the arrangement direction with respect to the floating region.
  6. 　前記第１カソード領域および前記第２カソード領域は、前記半導体基板の上面視で、前記配列方向に交互に配置され、
    　前記フローティング領域は、前記上面視で、前記第１カソード領域および前記第２カソード領域の両方と重なって、前記配列方向に複数設けられる、
    　請求項５に記載の半導体装置。     The first cathode regions and the second cathode regions are alternately arranged in the arrangement direction in a top view of the semiconductor substrate,
    A plurality of the floating regions are provided in the arrangement direction so as to overlap both the first cathode region and the second cathode region in the top view.
    The semiconductor device according to claim 5.
  7. 　前記フローティング領域は、前記上面視で、前記第１カソード領域よりも前記配列方向に張り出している、請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the floating region protrudes in the arrangement direction from the first cathode region in the top view.
  8. 　半導体基板と、
    　前記半導体基板に設けられた第１導電型のドリフト領域と、
    　前記半導体基板の上面に接し、前記ドリフト領域よりも上方に設けられた第２導電型のベース領域と、
    　前記半導体基板の下面に接し、前記ドリフト領域よりも下方に設けられた第１導電型の第１カソード領域と、
    　前記半導体基板の下面に接し、前記ドリフト領域よりも下方に設けられ、前記第１カソード領域に挟まれて設けられた第２導電型の第２カソード領域と、
    　前記半導体基板の下面に接し、前記ドリフト領域よりも下方に設けられ、前記第１カソード領域および前記第２カソード領域を挟むように設けられた第２導電型の第３カソード領域と、
    　を備え、
    　前記半導体基板の上面視において、前記第１カソード領域と前記第２カソード領域との配列方向に沿った前記第３カソード領域の幅が、前記配列方向に沿った前記第２カソード領域の幅よりも大きい、
    　半導体装置。     A semiconductor substrate;
    A first conductivity type drift region provided in the semiconductor substrate;
    A base region of a second conductivity type in contact with the upper surface of the semiconductor substrate and provided above the drift region;
    A first cathode region of a first conductivity type in contact with a lower surface of the semiconductor substrate and provided below the drift region;
    A second cathode region of a second conductivity type in contact with the lower surface of the semiconductor substrate, provided below the drift region, and sandwiched between the first cathode regions;
    A third cathode region of a second conductivity type in contact with the lower surface of the semiconductor substrate and provided below the drift region and sandwiching the first cathode region and the second cathode region;
    With
    In the top view of the semiconductor substrate, the width of the third cathode region along the arrangement direction of the first cathode region and the second cathode region is larger than the width of the second cathode region along the arrangement direction. large,
    Semiconductor device.
  9. 　前記上面視において、前記第３カソード領域が前記第１カソード領域および前記第２カソード領域を挟む方向に沿った前記第２カソード領域の幅が、前記配列方向に沿った前記第２カソード領域の幅よりも大きい、請求項８に記載の半導体装置。 In the top view, the width of the second cathode region along the direction in which the third cathode region sandwiches the first cathode region and the second cathode region is the width of the second cathode region along the arrangement direction. The semiconductor device according to claim 8, wherein the semiconductor device is larger.
  10. 　複数の前記第２カソード領域と、複数の前記第３カソード領域と、を備え、
    　複数の前記第２カソード領域と複数の前記第３カソード領域とが、前記上面視で接している、
    　請求項８または９に記載の半導体装置。     A plurality of the second cathode regions, and a plurality of the third cathode regions,
    The plurality of second cathode regions and the plurality of third cathode regions are in contact with each other when viewed from above.
    The semiconductor device according to claim 8 or 9.
  11. 　半導体基板と、
    　前記半導体基板に設けられた１つ以上のダイオード部と、
    　を備え、
    　前記ダイオード部は、
    　　前記半導体基板に設けられた第１導電型のドリフト領域と、
    　　前記半導体基板の上面に接し、前記ドリフト領域よりも上方に設けられた第２導電型のベース領域と、
    　　前記半導体基板の下面に接し、前記ドリフト領域よりも下方に設けられた、互いに分離した複数の第１導電型の第１カソード領域および前記第１カソード領域とは導電型が異なる第２カソード領域と、
    　　前記第１カソード領域毎に互いに分離して設けられ、前記第１カソード領域と少なくとも部分的に重なって配置された複数の第２導電型のフローティング領域と、
    　を有する、
    　半導体装置。     A semiconductor substrate;
    One or more diode portions provided on the semiconductor substrate;
    With
    The diode part is
    A first conductivity type drift region provided in the semiconductor substrate;
    A base region of a second conductivity type in contact with the upper surface of the semiconductor substrate and provided above the drift region;
    A plurality of first cathode regions of a first conductivity type that are in contact with a lower surface of the semiconductor substrate and are provided below the drift region and are separated from each other, and a second cathode region having a conductivity type different from that of the first cathode region ,
    A plurality of second conductivity type floating regions provided separately from each other for each of the first cathode regions, and disposed at least partially overlapping the first cathode region;
    Having
    Semiconductor device.
PCT/JP2019/009485 2018-03-15 2019-03-08 Semiconductor device WO2019176810A1 (en)

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