WO2019172822A1 - Balanced resistive frequency mixer - Google Patents

Balanced resistive frequency mixer Download PDF

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Publication number
WO2019172822A1
WO2019172822A1 PCT/SE2019/050181 SE2019050181W WO2019172822A1 WO 2019172822 A1 WO2019172822 A1 WO 2019172822A1 SE 2019050181 W SE2019050181 W SE 2019050181W WO 2019172822 A1 WO2019172822 A1 WO 2019172822A1
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signal
power divider
balun
mode
filter
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PCT/SE2019/050181
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French (fr)
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Omid HABIBPOUR
Herbert Zirath
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Chalmers Ventures Ab
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1441Balanced arrangements with transistors using field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1606Graphene
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1458Double balanced arrangements, i.e. where both input signals are differential
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1466Passive mixer arrangements
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1491Arrangements to linearise a transconductance stage of a mixer arrangement

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Superheterodyne Receivers (AREA)
  • Networks Using Active Elements (AREA)

Abstract

A balanced resistive mixer (100) comprising graphene field effect transistors (108) operating as variable resistors, an LO power divider (102), an RF power divider (116); an IF balun (120); and a two-port network (148) having a first port (150) connected to a first output 130 of the RF power divider, a drain terminal (128) of the first G-FET and to a first input (140) of the IF balun and a second port (152) connected to a second output (134) of the RF power divider, a drain terminal (132) of the second G-FET, and to a second input (142) of the IF balun; wherein the LO power divider provides an LO-signal either in common mode or in differential mode, and the RF power divider is configured to provide an RF-signal in the opposite mode, the two port network being configured to operate as a short circuit for the LO-signal mode and as an open circuit for the RF-signal mode.

Description

BALANCED RESISTIVE FREQUENCY MIXER
Field of the Invention
The present invention relates to a balanced resistive frequency mixer.
In particular, the invention relates to an improved configuration of a balanced resistive frequency mixer with high linearity.
Background of the Invention
Frequency mixers are commonly used in communication equipment to modulate signals and to generate desired frequencies. In a frequency mixer, an intermediate frequency (IF) signal is generated as the sum and the difference of the original frequencies of two input signals, i.e. a local oscillator (LO) signal and a radio frequency (RF) signal.
Resistive mixers are a type of mixers with very high linearity. In a resistive mixer, a time varying conductance G(t) is generated by using a local oscillator signal VLo(t). By applying an input RF-signal VRF(t) to the time varying conductor, a current wave i(t) = G(t) x VRF(t) is generated which contains the desired IF-signal. Generally, G(t) is a function of both the LO- and the RF-signal, i.e. G(t)=f(VLo(t),VRF(t)). Therefore, in addition to the IF- signal, an unwanted signal component related to the LO-signal is generated which cannot be easily removed by filtering.
In resistive mixers, field effect transistors (FETs) are often utilized as variable resistors to provide the time varying conductance, and the LO-signal is applied to the gate to control the value of the resistivity. For example, a High Electron Mobility Transistor (HEMT) may be used. Mixers with a high linearity, i.e. a linear relation between lDs and VDs, are needed for the generation and retrieving of high spectral efficiency signals.
In a HEMT, the slope of the lDs vs VD s strongly depends on VDs, i.e. VRF, as is the case for convention al transistors. An example of a HEMT Mixer is provided in“Novel Single Device Balanced Resistive HEMT Mixers", IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 43, NO. 12, DECEMBER 1995. However, it is still desirable to provide an improved resistive mixer with high linearity where the IF-signal is free from LO-signal components.
Summary
In view of above-mentioned and other drawbacks of the prior art, it is an object of the present invention to provide an improved resistive mixer.
According a first aspect of the invention, there is provided a balanced resistive mixer configured to convert a first signal (RF) having a first frequency into a second signal (IF) having a second frequency using a third signal (LO) having a third frequency, wherein the first signal is an RF-signal, the second signal is an IF-signal and the third signal is an LO-signal. The mixer comprises: an LO power divider configured to receive an LO-signal, wherein a first output of the LO power divider is connected to the gate of a first graphene field effect transistor (G-FET) configured to operate as a variable resistor, and a second output of the LO power divider is connected to the gate of a second graphene field effect transistor (G-FET) configured to operate as a variable resistor; an RF power divider configured to receive an RF-signal; an IF balun configured to provide an IF-signal; and a two-port network having a first port connected to a first output of the RF power divider, a drain terminal of the first G-FET and to a first input of the IF balun and a second port connected to a second output of the RF power divider, a drain terminal of the second G-FET, and to a second input (142) of the IF balun.
The LO power divider is configured to provide an LO-signal either in common mode or in differential mode, and the RF power divider is configured to provide an RF-signal in the opposite mode of the LO-signal, the two port network being configured to operate as a short circuit for the LO-signal mode and as an open circuit for the RF-signal mode.
It has been found that a graphene field effect transistor has a linearity which is significantly improved in comparison with a HEMT-transistor. Hence, a G-FET based resistive mixer is a preferred choice in terms of linearity of the mixer. However, a G-FET requires a higher gate voltage which in turn leads to an increased LO-leakage. In particular, due to a high gate capacitance in the G-FET, the gate voltage can leak to the drain port which brings the transistor to a less linear region. Thereby, the main challenge that prevents reaching high performance in a G-FET based mixer is the LO leakage. In a G- FET mixer, a larger LO signal is generally required as compared to in a conventional field effect transistor (FET). Hence, the LO leakage swings the G-FET operating points to large VD s voltages where the l-V characteristics is more nonlinear. Therefore, there is a need for a circuit design that can cancel LO leakage at the drain terminal of the G-FET. The LO-leakage can not be cancelled by using a filter since the filter could severely affect RF signal.
Accordingly, the present invention is based on the realization that while it is desirable to use a G-FET transistor in a resistive mixer, further measures are required to achieve a high performance mixer. Thereby, a two-port network is provided which is configured to cancel the leakage of the LO- signal. It is well known that the LO-signal may be provided either as a common mode (even mode) signal or as a differential mode (odd mode) signal. The two-port network is thereby configured such that the LO-signal sees a short circuit while the RF-signal sees an open circuit, thereby cancelling out the LO-signal at the drain terminal of the G-FET. Accordingly, the two port network is configured based on the selected mode of the LO- signal such that if the LO-signal is in the common mode, the two port network is configured to act as an open circuit for common mode signals, and if the LO-signal is in the differential mode, the two port network is configured to act as an open circuit for differential mode signals.
According to one embodiment of the invention, the LO-power divider may be a balun configured to provide a differential mode LO-signal and the RF-power divider is a 3dB power divider to provide a common mode RF- signal.
According to one embodiment of the invention, the LO-power divider is a 3dB power divider to provide a common mode LO-signal and the RF-power divider is a balun to provide a differential mode RF-signal.
According to one embodiment of the invention, the two-port network comprises two coupled transmission line, wherein each transmission line is terminated by a load. The two coupled transmission lines are set close enough together such that energy passing through one is coupled to the other. A coupled transmission line is commonly referred to as a“Coupled-line” coupler.
According to one embodiment of the invention, when the LO-signal is a differential mode signal, the loads are configured to provide a reflection coefficient, G, of +j, where j is the imaginary unit.
According to one embodiment of the invention, when the LO-signal is a common mode signal, the loads are configured to provide a reflection coefficient, G, of -j, where j is the imaginary unit. Thereby, the loads are configured to provide a two-port network operating as a short circuit for the LO-signal in the respective mode. The skilled person readily realizes that the described reflection coefficients for the two port network can be achieved in many different ways. Moreover the loads will then have an impedance of +jZ0 or -jZ0 for differential mode and common mode LO-signals, respectively, where Z0 is the system impedance.
According to one embodiment of the invention, when the LO-signal is provided in the differential mode, the two port network is configured to have a bandwidth which does not overlap with a bandwidth of the IF-signal. Since the IF-signal is a differential mode signal, it is preferable to configure the two-port network so that is does not operate as a short circuit for the IF-signal, which can be achieved by configuring the two port network so that a bandwidth for which the short circuit is provided does not overlap with the IF frequency or bandwidth.
According to one embodiment of the invention the balanced resistive mixer may further comprise a first and a second IF-filter configured to filter, i.e. to block, frequencies outside of the IF-signal frequency, wherein the first IF-filter is arranged between the drain terminal of the first graphene field effect transistor and a first input of the IF balun, and the second IF-filter is arranged between the drain terminal of the second graphene field effect transistor and a second input of the IF balun. The first and second IF-filters thus act as bandpass filters. Thereby, it can be further ensured that no part of the LO- signal or the RF-signal is included in the resulting IF signal.
According to one embodiment of the invention the balanced resistive mixer may further comprise a first and a second RF-filter configured to filter, i.e. to block, frequencies outside of the RF-signal frequency, wherein the first RF-filter is arranged between a drain terminal of the first graphene field effect transistor and a first output of the RF power divider, and the second RF-filter is arranged between a drain terminal of the second graphene field effect transistor and a second output of the RF power divider. The first and second RF-filters thus act as bandpass filters.
Further features of, and advantages with, the present invention will become apparent when studying the appended claims and the following description. The skilled person realize that different features of the present invention may be combined to create embodiments other than those described in the following, without departing from the scope of the present invention.
Brief Description of the Drawings
These and other aspects of the present invention will now be described in more detail, with reference to the appended drawings showing an example embodiment of the invention, wherein:
Fig. 1 is a schematic circuit layout of a balanced resistive mixer according to an embodiment of the invention;
Fig. 2A schematically illustrates features of a known RF mixer;
Fig. 2B schematically illustrates features of a mixer according to an embodiment of the invention;
Figs 3A-B schematically illustrate features of a mixer according to an embodiment of the invention;
Figs. 4A-B schematically illustrate a two-port networks according to embodiments of the invention;
Figs. 5A-B schematically illustrate a two-port networks according to embodiments of the invention; Fig. 6A schematically illustrates a mixer and a two-port network according to an embodiment of the invention; and
Fig. 6B schematically illustrates a mixer and a two-port network according to an embodiment of the invention.
Detailed Description of Example Embodiments
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which currently preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided for thoroughness and completeness, and fully convey the scope of the invention to the skilled person. Like reference characters refer to like elements throughout.
Fig. 1 is a schematic circuit layout of a balanced resistive mixer 100 according to various embodiments of the invention. The balanced resistive mixer 100 is configured to convert a first signal having a first frequency into a second signal having a second frequency using a third signal having a third frequency, wherein the first signal is a radio frequency signal, RF-signal, the second signal is an, intermediate frequency signal, IF-signal and the third signal is a local oscillator signal, LO-signal. The first, second and third frequencies may also be referred to as fRF, f|F, and fLo, respectively, to represent the frequencies of the RF, IF and LO-signals. In the described frequency mixer, the intermediate frequency is determined as f|F = |fRF ± fLo| to achieve up or down mixing of the signals. The mixer 100 can thereby act as an upconverter or a downconverter.
The mixer 100 comprises an LO power divider 102 configured to receive an LO-signal at an input port 103 of the LO power divider 102, wherein a first output 104 of the LO power divider 102 is connected to the gate terminal 106 of a first graphene field effect transistor, G-FET, 108 configured to operate as a variable resistor, and a second output 1 10 of the LO power divider 102 is connected to the gate terminal 1 12 of a second graphene field effect transistor, G-FET, 114 configured to operate as a variable resistor.
The mixer 100 further comprises an RF power divider 116 configured to receive an RF-signal at an input port 118 thereof and an IF balun 120 configured to provide an IF-signal at an IF output port 122. The illustrated mixer 100 comprises a first and a second RF-filter 124, 126 acting as bandpass filters configured to filter frequencies outside of the RF-signal frequency. The first RF-filter 124 is arranged between a drain terminal 128 of the first G-FET 108 and a first output 130 of the RF power divider 116, and the second RF-filter 126 is arranged between a drain terminal 132 of the second G-FET 114 and a second output 134 of the RF power divider 116.
The mixer 100 further comprises a first and a second IF-filter, 136, 138 acting as bandpass filters configured to filter frequencies outside of the IF- signal frequency, wherein the first IF-filter 136 is arranged between the drain 128 terminal of the first G-FET 108 and a first input 140 of the IF balun 120, and the second IF-filter 138 is arranged between the drain terminal 132 of the second G-FET 114 and a second input 142 of the IF balun 120.
The respective source terminals 144, 146 of the first and second G- FET 108, 114 are connected to ground.
In order to reduce or eliminate components of the LO-signal in the resulting IF-signal, the mixer 100 comprises a two-port network 148. The two- port network 100 has a first port 150 connected to the first output 130 of the RF power divider 116, via the first RF-filter 124, the drain terminal 128 of the first G-FET and to a first input 140 of the IF balun 120, via the first IF-filter 136. The second port 152 of the two port network 148 is connected to the second output 134 of the RF power divider 116, via the second RF-filter 126, the drain terminal 132 of the second G-FET 114, and to the second input 142 of the IF balun 120, via the second IF-filter 138.
The LO power divider 102 is configured to provide an LO-signal either in common mode or in differential mode, and the RF power divider 116 is configured to provide an RF-signal in the opposite mode of the LO-signal. When the LO-signal is provided as a common mode signal, the LO power divider 102 is a conventional 3dB power divider, also referred to as a power splitter, dividing the LO-signal on the input port 103 to provide half the input power at each of its output ports 104, 110. The RF power divider 116 is then a balun, also configured to divide the RF-signal on the input port 118 to provide half the input power at each of its output ports 130, 134 but with the difference that the signal on one of the output ports is inverted, i.e. phase shifted by 180°, with respect to the signal on the other output port. Similarly, if the LO-signal is provided as a differential mode signal, the LO power divider 102 is a balun and the RF power divider 116 is 3dB power divider.
The two port network 148 is configured to operate as a short circuit for the LO-signal mode and as an open circuit for the RF-signal mode. Thereby, the LO-signal sees the two-port network 148 as a short circuit both in common mode and in differential mode, whereas the RF signal which is in the opposite mode (i.e. differential/common) will see the two-port network 148 as an open circuit, thereby remaining unaffected by the two-port network 148.
In a resistive mixer, transistors are operated as variable resistors. To provide an illustrative example, Fig 2A shows output characteristics (lDs vs VDs) of an InP HEMT and Fig. 2B shows the output characteristics of a graphene FET for different gate voltages, VGs- It can be seen that for the graphene FET, lDs is more linear and also more symmetric as a function of VDS- For |Vds|< 0.3 V, lDs of the graphene FET is completely linear and symmetric allowing the development of a mixer with ultra-high linearity.
However, due to gate capacitance of the G-FET, which is higher than that of e.g. the HEMT, the gate voltage can leak to the drain port which brings the device to a less linear region. This is where the significance of the two-port network 148 comes in since the two-port network 148 can be configured to cancel the LO-leakage from the drain terminals 128, 132, thereby allowing the graphene FET mixer 100 to exhibit a linear behavior.
Fig. 3A is an S-parameter representation of a two-port system 148 with the following S-parameters:
Figure imgf000010_0001
If the system is excited with common mode, i.e. V^ = V2 = 1 V, we have
vi — vl + v1 2
where Vt l and V1 2 are the voltages generated at port 1 due to Vt + and V2 respectively.
V1 1 = Vi+(1 + Sn) = IV
Figure imgf000011_0001
Hence, l^ = 1 - 1 = 0. Therefore, for a common mode excitation the circuit behaves like a short circuit. For differential mode Vt + = -V2 = 1 with the same equations V = 1 + 1 = 2, hence, the circuit behaves like an open circuit.
If the two-port system 148 instead has the following S-parameters:
Figure imgf000011_0002
with the same equations as above, it can concluded that in this network, for a differential mode excitation, there will be a short circuit behavior and for a common mode excitation, it behaves like an open circuit.
The described two-port network can be realized by a coupled line structure comprising two coupled transmission lines 300, 302 each terminated by a respective load 304, 306 as illustrated by Fig. 3B.
By selecting the following parameters as an illustrative example
120.71 (for Z0 = 50/3)
20.71 (for Z0 = 50/3)
Figure imgf000011_0003
requency)
the S-parameters of the two-port system becomes
Figure imgf000011_0004
where rL is the reflected coefficient of the terminated impedance. If rL = j then
5 = !1
G oJ
and if rL = -j then
Figure imgf000012_0001
It is possible to form a two-port network exhibiting both open and short behavior using stubs, where the physical length of the stub will be different for the two cases since the length and the termination of the stub determines the resulting phase shift.
Figs. 4A-B illustrate examples of two port networks for rL = j, where the following loads provides TL = j\
For open circuit stub with Q = 45, Z = Z0, as illustrated in Fig. 4A and for short circuit stub with Q = 135, Z = Z0, as illustrated in Fig. 4B.
Figs. 5A-B illustrate examples of two port networks for rL = -j, where the following loads provides rL = -j:
For open circuit stub with Q = 135, Z = Z0, as illustrated in Fig. 5A and for short circuit stub with Q = 45, Z = Z0, as illustrated in Fig. 4C.
It should be noted that two-port networks exhibiting the above described behavior may be achievable using other circuit elements, such as capacitors.
Fig. 6A schematically illustrates a mixer 100 comprising the two-port networks 400, 402 of Figs 4A-B and Fig. 6B schematically illustrates a mixer 100 comprising the two-port networks 500, 502 of Figs 5A-B. The remaining components of the mixers of Figs. 6A-B are the same as illustrated in Fig. 1.
Even though the invention has been described with reference to specific exemplifying embodiments thereof, many different alterations, modifications and the like will become apparent for those skilled in the art. Also, it should be noted that parts of the resistive frequency mixer may be omitted, interchanged or arranged in various ways, the mixer yet being able to perform the functionality of the present invention.
Additionally, variations to the disclosed embodiments can be understood and effected by the skilled person in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A balanced resistive mixer (100) configured to convert a first signal having a first frequency into a second signal having a second
frequency using a third signal having a third frequency, wherein the first signal is a radio frequency signal, RF-signal, the second signal is an intermediate frequency signal, IF-signal, and the third signal is a local oscillator signal, LO- signal, the balanced resistive mixer comprising:
an LO power divider (102) configured to receive an LO-signal, wherein a first output (104) of the LO power divider is connected to a gate terminal (106) of a first graphene field effect transistor (108), G-FET, configured to operate as a variable resistor, and a second output (110) of the LO power divider is connected to a gate terminal (112) of a second graphene field effect transistor (114), G-FET, configured to operate as a variable resistor;
an RF power divider (116) configured to receive an RF-signal;
an IF balun (120) configured to provide an IF-signal; and
a two-port network (148) having a first port (150) connected to a first output 130 of the RF power divider, a drain terminal (128) of the first G-FET and to a first input (140) of the IF balun and a second port (152) connected to a second output (134) of the RF power divider, a drain terminal (132) of the second G-FET, and to a second input (142) of the IF balun;
wherein the LO power divider is configured to provide an LO-signal either in common mode or in differential mode, and wherein the RF power divider is configured to provide an RF-signal in the opposite mode of the LO- signal, and wherein the two port network is configured to operate as a short circuit for the LO-signal mode and as an open circuit for the RF-signal mode.
2. The balanced resistive mixer according to claim 1 , wherein the LO-power divider is a balun configured to provide a differential mode LO- signal and the RF-power divider is a 3dB power divider configured to provide a common mode RF-signal.
3. The balanced resistive mixer according to claim 1 , wherein the LO-power divider is a 3dB power divider configured to provide a common mode LO-signal and the RF-power divider is a balun configured to provide a differential mode RF-signal.
4. The balanced resistive mixer according to any one of the preceding claims, wherein the two-port network comprises two coupled transmission lines, wherein each transmission line is terminated by a load.
5. The balanced resistive mixer according to claim 4, wherein, when the LO-signal is a differential mode signal, the loads are configured to provide a reflection coefficient, G, of +j, where j is the imaginary unit.
6. The balanced resistive mixer according to claim 4, wherein, when the LO-signal is a common mode signal, the loads are configured to provide a transmission line reflection coefficient G = -j, where j is the imaginary unit.
7. The balanced resistive mixer according to any one of the preceding claims, wherein when the LO-signal is provided in the differential mode, the two port network is configured to have a bandwidth which does not overlap with a bandwidth of the IF-signal.
8. The balanced resistive mixer according to any one of the preceding claims, further comprising a first and a second IF-filter configured to block frequencies outside of the IF-signal frequency, wherein the first IF- filter is arranged between the drain terminal of the first graphene field effect transistor and a first input of the IF balun, and the second IF-filter is arranged between the drain terminal of the second graphene field effect transistor and a second input of the IF balun.
9. The balanced resistive mixer according to any one of the preceding claims, further comprising a first and a second RF-filter configured to filter frequencies outside of the RF-signal frequency, wherein the first RF- filter is arranged between a drain terminal of the first graphene field effect transistor and a first output of the RF power divider, and the second RF-filter is arranged between a drain terminal of the second graphene field effect transistor and a second output of the RF power divider.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113014246A (en) * 2021-02-20 2021-06-22 广东省科学院半导体研究所 Voltage level shifter and electronic device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997023036A1 (en) * 1995-12-20 1997-06-26 Watkins-Johnson Company Quasi-double balanced passive reflection fet mixer
EP1653603A1 (en) * 2004-10-27 2006-05-03 Synergy Microwave Corproation Passive reflection mixer
US20100087159A1 (en) * 2008-10-02 2010-04-08 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Mixer with local oscillator feed-forward and method of mixing signals with local oscillator feed-forward

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997023036A1 (en) * 1995-12-20 1997-06-26 Watkins-Johnson Company Quasi-double balanced passive reflection fet mixer
EP1653603A1 (en) * 2004-10-27 2006-05-03 Synergy Microwave Corproation Passive reflection mixer
US20100087159A1 (en) * 2008-10-02 2010-04-08 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Mixer with local oscillator feed-forward and method of mixing signals with local oscillator feed-forward

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
M. ANDERSSON ET AL.: "A 185-215-GHz Subharmonic Resistive Graphene FET Integrated Mixer on Silicon", IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, vol. 65, no. 1, January 2017 (2017-01-01), pages 165 - 172, XP011639927, ISSN: 0018-9480, doi:10.1109/TMTT.2016.2615928 *
O. HABIBPOUR ET AL.: "A 30-GHz Integrated Subharmonic Mixer Based on a Multichannel Graphene FET", IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, vol. 61, no. 2, February 2013 (2013-02-01), pages 841 - 847, XP011492609, ISSN: 0018-9480, doi:10.1109/TMTT.2012.2236434 *
O. HABIBPOUR ET AL.: "A W-band MMIC Resistive Mixer Based on Epitaxial Graphene FET", IEEE MICROWAVE AND WIRELESS COMPONENTS LETTER, vol. 27, no. 2, February 2017 (2017-02-01), pages 168 - 170, XP011640944, ISSN: 1531-1309, doi:10.1109/LMWC.2016.2646998 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113014246A (en) * 2021-02-20 2021-06-22 广东省科学院半导体研究所 Voltage level shifter and electronic device
CN113014246B (en) * 2021-02-20 2022-02-22 广东省科学院半导体研究所 Voltage level shifter and electronic device

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