WO2019171501A1 - Unité cpu d'automate programmable industriel, automate programmable industriel, procédé, ordinateur et programme informatique - Google Patents

Unité cpu d'automate programmable industriel, automate programmable industriel, procédé, ordinateur et programme informatique Download PDF

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Publication number
WO2019171501A1
WO2019171501A1 PCT/JP2018/008798 JP2018008798W WO2019171501A1 WO 2019171501 A1 WO2019171501 A1 WO 2019171501A1 JP 2018008798 W JP2018008798 W JP 2018008798W WO 2019171501 A1 WO2019171501 A1 WO 2019171501A1
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WIPO (PCT)
Prior art keywords
instruction
programmable logic
unit
arithmetic
logic device
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PCT/JP2018/008798
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English (en)
Japanese (ja)
Inventor
夏実 石黒
伴彰 ▲高▼木
潤 仲川
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2018/008798 priority Critical patent/WO2019171501A1/fr
Priority to JP2019502024A priority patent/JP6591116B1/ja
Priority to CN201880090694.9A priority patent/CN111819503B/zh
Priority to DE112018007018.2T priority patent/DE112018007018B4/de
Priority to TW108106511A priority patent/TWI701592B/zh
Publication of WO2019171501A1 publication Critical patent/WO2019171501A1/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts

Definitions

  • the present invention relates to a CPU unit of a programmable logic controller, a programmable logic controller, a method, a computer, and a computer program.
  • the CPU Central Processing Unit
  • ASIC application specific integrated circuit
  • MPU microprocessor
  • the ASIC executes a specific process determined at the time of design, and the microprocessor executes a process that cannot be processed by the ASIC. Since the computing performance of the microprocessor is not as high as that of the ASIC, the processing capability of the microprocessor has been a difficulty in speeding up the operation of the CPU unit.
  • Patent Document 1 discloses a method for speeding up a process for causing a reconfigurable processor corresponding to a programmable logic device to execute a part of the process of a microprocessor.
  • a programmable logic device executes a program element that includes a function that takes time to process
  • a microprocessor executes a program element that does not include a function.
  • the programmable logic device executes only the processing of the program element including the function.
  • the present invention has been made in view of the above circumstances, and in a programmable logic controller, when processing of a microprocessor is distributed to programmable logic devices, it is possible to select an arithmetic device after creating a program, It is an object of the present invention to make it possible to change an arithmetic device without requiring correction.
  • the CPU unit of the programmable logic controller includes a microprocessor and a programmable logic device as an arithmetic unit.
  • Each instruction in the user program includes arithmetic unit information indicating the arithmetic unit that processes the instruction selected by the user.
  • the microprocessor processes instructions if the computing device information indicates a microprocessor.
  • a programmable logic device processes instructions when the computing device information indicates a programmable logic device.
  • the microprocessor or the programmable logic device processes an instruction based on the changed arithmetic device information.
  • the microprocessor processes the instruction and calculates the instruction. If the device information indicates a programmable logic device, the programmable logic device processes the instructions.
  • the microprocessor or the programmable logic device processes an instruction based on the changed arithmetic device information.
  • FIG. 1 The block diagram which shows the structure of PLC which concerns on embodiment of this invention Flowchart of program scan of CPU unit of PLC according to embodiment Detailed flowchart of program execution of FIG.
  • the flowchart which shows the process of selection of an arithmetic unit in the automatic selection mode of the engineering tool which changes the arithmetic unit information which concerns on embodiment
  • PLC programmable logic controller
  • the detector 901 including a sensor, a switch, etc. is connected to the input unit 200.
  • An on / off signal output from a sensor, switch, or the like of the detector 901 is supplied from the input unit 200 to the CPU unit 100.
  • the input unit 200 supplies the CPU unit 100 with an ON signal as a notification that the switch of the detector 901 has been turned ON and an OFF signal as a notification that the switch has been turned OFF.
  • the on signal is represented by “1”
  • the off signal is represented by “0”
  • the input unit 200 supplies “1” to the CPU unit 100 when the switch is turned on.
  • the input unit 200 supplies “0” to the CPU unit 100 when the switch is turned off.
  • the output unit 300 is connected to a controlled device 902 including an actuator, an indicator light, and the like.
  • the CPU unit 100 supplies the output unit 300 with an on / off signal for controlling the actuator, indicator lamp, and the like of the controlled device 902.
  • the CPU unit 100 supplies an ON signal to the output unit 300 as an instruction to drive the actuator of the controlled device 902 and an OFF signal as an instruction to stop the actuator.
  • the on signal is represented as “1”
  • the off signal is represented as “0”
  • the CPU unit 100 supplies “1” to the output unit in order to drive the actuator.
  • the CPU unit 100 supplies “0” to the output unit to stop the actuator.
  • the CPU unit 100, the input unit 200, and the output unit 300 are connected via a shared bus 400 and communicate via the shared bus 400. Although not shown, the CPU unit 100, the input unit 200, and the output unit 300 are connected to the power supply unit via the base unit, and operate by the power supplied from the power supply unit.
  • the CPU unit 100 includes a storage unit 110 that stores various data, a tool interface 120 for communication with an engineering tool 500 to be described later, a shared bus interface 130 for communication via the shared bus 400, and an arithmetic device.
  • An arithmetic unit 140 including an ASIC (Application Specific Integrated Circuit) 141, a microprocessor 142 (hereinafter referred to as MPU 142), and an FPGA (Field Programmable Gate Array) 143 is included.
  • Each part of the CPU unit 100 is connected via a bus 190.
  • the FPGA 143 is an example of a programmable logic device.
  • the storage unit 110 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a memory card, and the like.
  • the storage unit 110 stores a user program 111.
  • the user program 111 is a program for controlling the controlled device 902.
  • a user creates a user program 111 using an engineering tool 500 described later.
  • the created user program 111 is converted into a mnemonic assembly language, then uploaded to the CPU unit 100 of the PLC 1 and stored in the storage unit 110.
  • each command is turned on or off by the input of an on / off signal. Only instructions that are turned on are executed.
  • Each instruction in the user program 111 includes arithmetic device information as information indicating which arithmetic device of the arithmetic unit 140 executes the instruction.
  • ASIC 141 is represented by “1”
  • MPU 142 is represented by “2”
  • FPGA 143 is represented by “3”
  • a bit string indicating these values is added to each instruction.
  • the arithmetic unit information cannot be changed for a specific instruction decided to be processed by the ASIC.
  • the tool interface 120 is an interface for the CPU unit 100 to communicate with the engineering tool 500.
  • the tool interface 120 operates according to the control of the calculation unit 140.
  • the shared bus interface 130 is a communication interface for the CPU unit 100 to communicate with the input unit 200 and the output unit 300 via the shared bus 400.
  • the shared bus interface 130 operates according to the control of the arithmetic unit 140.
  • the calculation unit 140 executes each command of the user program 111 using the input data supplied from the input unit 200. More specifically, the arithmetic device specified by the arithmetic device information of each instruction in the user program 111 executes the instruction.
  • the input data is a value indicating an on / off signal output from a sensor, a switch, or the like of the detector 901.
  • the calculation unit 140 executes only the instruction that is turned on by the ON signal, and supplies the ON / OFF signal to the output unit 300 based on the output obtained as a result of the calculation.
  • the output unit 300 controls the controlled device 902 according to the supplied on / off signal.
  • the ASIC 141 includes a register 1411 that temporarily stores data when an instruction is executed, and a program counter 1412 that stores an address of an instruction to be executed next.
  • the ASIC 141 processes only specific commands in the execution of the user program 111. This is because the ASIC 141 can execute only specific instructions determined in the design stage. This specific instruction is called an ASIC compatible instruction.
  • An instruction other than the ASIC compatible instruction of the user program 111 is referred to as an ASIC non-compliant instruction.
  • the MPU 142 has a register 1421 for temporarily storing data when an instruction is executed.
  • the MPU 142 processes an instruction selected to be processed by the MPU 142 among non-ASIC instructions.
  • the FPGA 143 includes a register 1431 that temporarily stores data when an instruction is executed.
  • the FPGA 143 processes an instruction selected by the FPGA 143 to be processed among the ASIC non-compliant instructions.
  • the user can change the configuration of the logic circuit of the FPGA 143 after manufacturing. For example, if a new command is added to the user program 111 due to a change in the user program 111 and the command is not an ASIC-compatible command, the ASIC 141 cannot execute the added new command.
  • the FPGA 143 can execute a newly added instruction by changing the configuration of the logic circuit.
  • the MPU 142 can execute an ASIC non-corresponding instruction similarly to the FPGA 143, but the FPGA 143 is faster in processing speed. A method for selecting an instruction executed by the MPU 142 and an instruction executed by the FPGA 143 will be described later.
  • the input unit 200 includes a storage unit 210 for storing various data, a shared memory 220 for exchanging data with the CPU unit 100, a shared bus interface 230 for communication via the shared bus 400, and the entire input unit 200.
  • MPU 240 for controlling Each part of the input unit 200 is connected via a bus 290.
  • the storage unit 210 includes a ROM, a RAM, a memory card, and the like.
  • the storage unit 210 stores an operation program 211 for the operation of the input unit 200.
  • the shared memory 220 is a memory that can be read and written by both the CPU unit 100 and the input unit 200.
  • the shared memory 220 stores a value indicating an on / off signal output from a sensor, a switch, or the like of the detector 901.
  • the shared bus interface 230 is a communication interface for the input unit 200 to communicate with the CPU unit 100 via the shared bus 400.
  • the shared bus interface 130 operates according to the control of the MPU 240.
  • the MPU 240 executes the operation program 211 to turn on the state where the sensor, switch, etc. of the detector 901 detect some object, and turn off the state where no object is detected. Is stored in the shared memory 220. This value is an input on / off signal in the calculation in the CPU unit 100.
  • the output unit 300 includes a storage unit 310 for storing various data, a shared memory 320 for exchanging data with the CPU unit 100, a shared bus interface 330 for communication via the shared bus 400, and the entire output unit 300. And MPU 340 for controlling. Each part of the output unit 300 is connected via a bus 390.
  • the storage unit 310 includes a ROM, a RAM, a memory card, and the like.
  • the storage unit 310 stores an operation program 311 for the operation of the output unit 300.
  • the shared memory 320 is a memory in which both the CPU unit 100 and the output unit 300 can read and write.
  • the shared memory 320 stores a value indicating an on / off signal that is an output of the calculation of the CPU unit 100. This value is control data for controlling the actuator, indicator lamp, and the like of the controlled device 902 and is written into the shared memory 320 by the CPU unit 100.
  • the shared bus interface 330 is a communication interface for the output unit 300 to communicate with the CPU unit 100 via the shared bus 400.
  • the shared bus interface 330 operates according to the control of the MPU 340.
  • the MPU 340 executes the operation program 311 and controls the controlled device 902 based on the on / off signal supplied from the CPU unit 100. For example, when the ON signal is supplied, the MPU 340 turns on the actuator of the controlled device 902.
  • the user uses the engineering tool 500 to create the user program 111 that is executed by the CPU unit 100.
  • the created user program 111 is uploaded to the CPU unit 100 in a state where the engineering tool 500 and the CPU unit 100 are connected by the communication cable 501.
  • the engineering tool 500 is a device in which an application for creating a program is installed in a personal computer.
  • the engineering tool 500 includes a storage unit 510 that stores various data, an operation input unit 520 that receives user operations, a display unit 530 that displays an image on a display device, and a tool interface 540 for communication with the CPU unit 100. And a CPU 550 that controls the entire engineering tool 500.
  • Each part of the engineering tool 500 is connected by a bus 590.
  • the storage unit 510 includes an operating system 511 and a program creation application 512.
  • the operating system 511 is a program for controlling the engineering tool 500 as a whole.
  • the program creation application 512 is a program for creating a user program 111 and selecting an arithmetic device for each command of the created user program 111.
  • the operation input unit 520 includes an input device such as a keyboard and a mouse, receives an operation input from the user, and outputs a signal based on the received operation to the CPU 550.
  • Display unit 530 includes an image display device, and outputs an image to the screen of the image display device under the control of CPU 550.
  • the operation input unit 520 and the display unit 530 function as a reception unit that receives a user instruction.
  • the tool interface 540 transmits / receives data to / from the CPU unit 100 connected by the communication cable 501 according to the control of the CPU 550.
  • the CPU 550 executes the operating system 511 to control the engineering tool 500 as a whole. Further, the CPU 550 implements a function of executing the program creation application 512 to create the user program 111 and a function of changing the selection of the arithmetic device for each instruction in the user program 111.
  • the CPU unit 100 described above executes the user program 111 as follows.
  • the CPU unit 100 sequentially processes the user program 111 from the top instruction and reads an END instruction indicating the end of the program, the CPU unit 100 returns to the processing of the top instruction again. This method is called a scan method.
  • the CPU unit 100 acquires the input necessary for executing each instruction and outputs the execution result of the instruction in addition to executing each instruction of the user program 111. Specifically, as shown in FIG. 2, the arithmetic unit 140 of the CPU unit 100 executes a series of processes of refresh processing (step S11), program execution (step S12), and end processing (step S13) as one cycle. And repeat this cycle.
  • step S11 the calculation unit 140 writes the output data obtained by executing the user program 111 in the previous cycle stored in the storage unit 110 in the shared memory 320 of the output unit 300. Thereafter, the output data is deleted from the storage unit 110. Further, the arithmetic unit 140 reads input data from the shared memory 220 of the input unit 200 via the shared bus 400 and stores the read input value in the storage unit 110.
  • the arithmetic unit 140 sequentially reads the instructions of the user program 111 from the beginning and executes the read instructions.
  • the ASIC 141 processes an ASIC compatible instruction
  • the MPU 142 or the FPGA 143 processes an ASIC non-compatible instruction.
  • the arithmetic unit 140 reads an END instruction indicating the end of the program of the user program 111
  • the arithmetic unit 140 ends the execution of the user program 111.
  • Processing of ASIC non-compliant instructions by MPU 142 or FPGA 143 is an example of steps in which either the microprocessor or programmable logic device of the present invention processes instructions.
  • the CPU unit 100 executes data transfer processing with a network unit (not shown) that communicates with other devices via the network, and other common processing.
  • the ASIC 141, the MPU 142, and the FPGA 143 share and process the instructions of the user program 111.
  • the operations of the ASIC 141, the MPU 142, and the FPGA 143 in the program execution step of Step S12 in FIG. 2 will be described in more detail.
  • the address of the first instruction of the user program 111 is stored in the program counter 1412 of the ASIC 141.
  • the ASIC 141 reads the instruction indicated by the address of the program counter 1412 from the user program 111 to the register 1411 (step S121).
  • the ASIC 141 also counts up the address of the program counter 1412. Therefore, an address indicating the next instruction is set in the program counter 1412.
  • the ASIC 141 determines whether or not the read instruction is an END instruction (step S122). If it is determined that the instruction is not an END instruction (step S122; No), the ASIC 141 determines whether or not the read instruction is an ASIC-compatible instruction (step S123). Specifically, it is determined whether or not the bit string indicating the arithmetic device information included in the instruction is a bit string indicating the ASIC 141.
  • step S123 If the ASIC 141 determines that the read instruction is an ASIC-compatible instruction (step S123; Yes), the ASIC 141 executes the instruction (step S124). Subsequently, the ASIC 141 reads the instruction at the address set in the program counter 1412 to the register 1411 (step S121).
  • step S123 when the ASIC 141 determines that the read instruction is not an ASIC compatible instruction (step S123; No), the ASIC 141 outputs the interrupt instruction to the MPU 142, and then holds the value of the program counter 1412 and stops.
  • the MPU 142 When the MPU 142 receives an interrupt instruction from the ASIC 141, the MPU 142 reads the instruction stored in the register 1411 of the ASIC 141 into its own register 1421. Based on the arithmetic unit information of the read instruction, the MPU 142 determines whether or not the instruction is an instruction selected to be processed by the MPU 142 (step S125). When the MPU 142 determines that the instruction is an instruction selected to be processed by the MPU 142 (step S125; Yes), the MPU 142 executes the instruction (step S126). After that, the MPU 142 writes a value instructing the restart into the register 1411 of the ASIC 141 in order to restart the ASIC 141. As a result, the ASIC 141 restarts, reads the instruction indicated by the address held in the program counter 1412 to the register 1411 (step S121), and resumes execution of the instruction.
  • the MPU 142 determines that the instruction read in step S125 is not the instruction selected to be processed by the MPU 142 (step S125; No)
  • the MPU 142 writes the instruction in the register 1431 of the FPGA 143 and executes the instruction in the FPGA 143.
  • the FPGA 143 executes the instruction stored in the register 1431 of the FPGA 143 and writes a return value indicating that the calculation is completed to the register 1431.
  • the MPU 142 writes a value instructing the restart into the register 1411 of the ASIC 141 in order to restart the ASIC 141.
  • the ASIC 141 reads the instruction indicated by the address held in the program counter 1412 to the register 1411 (step S121), and resumes the execution of the instruction.
  • step S122 when the ASIC 141 determines that the read instruction is an END instruction (step S122; Yes), the execution of the user program 111 is terminated. Thereafter, the CPU unit 100 executes the end process of step S13 in FIG.
  • the ASIC non-compliant instruction is processed by the MPU 142 or the FPGA 143 according to the value set in the arithmetic unit information.
  • a value indicating the MPU 142 is set as a default value in the arithmetic unit information of all ASIC non-corresponding instructions.
  • the user starts the program creation application 512 of the engineering tool 500 by operating the operation input unit 520 such as a keyboard and a mouse.
  • the user selects a “create user program” menu from the menu screen shown in FIG. 4 displayed on the display unit 530 and causes the display unit 530 to display a program creation screen (not shown).
  • the user creates and saves the user program 111 on a program creation screen (not shown).
  • the created user program 111 is stored in the storage unit 510 of the engineering tool 500.
  • the user operates the operation input unit 520 to display the menu screen shown in FIG. 4 on the display unit 530 again.
  • the user selects the “select arithmetic device” menu and causes the display unit 530 to display a submenu screen as shown in FIG.
  • the engineering tool 500 analyzes the user program 111, and the FPGA 143 executes and selects an instruction that can be accelerated and improved in performance as an instruction to be executed by the FPGA 143. Is set to a value indicating the FPGA 143.
  • manual selection modes 1 and 2 the user selects an arithmetic device for each command.
  • Automatic selection mode When executing the automatic selection mode, the user selects an arbitrary user program 111 as a target program on the submenu screen and designates “automatic selection mode”. In the illustrated example, “program 001” is selected as the user program 111.
  • the CPU 550 of the engineering tool 500 executes the program creation application 512 to perform the following processing.
  • the storage unit 510 stores the following information in advance.
  • N 1 Number of non-ASIC instructions. This value is the number of types of all ASIC non-corresponding instructions. It does not matter whether the user program 111 is included in the “program 001”.
  • G FPGA The total number of gates of FPGA 143. This value is a value based on the hardware specifications of the FPGA 143.
  • Time that can be reduced by using the FPGA 143 for each instruction (reducible time): T n (n 1, 2,..., N 1 ). here.
  • the difference between the processing time of the instruction of the MPU 142 and the processing time of the instruction of the FPGA 143 is set as a difference.
  • the reducible time is an example of the processing time of each instruction by the programmable logic device of the present invention.
  • said (2), (3), (4) is an example of the definition information of the programmable logic device of this invention.
  • processing time per gate of the FPGA 143 is obtained (step S22).
  • the instructions are sorted by the processing time P n per gate for each instruction obtained in step S22 (step S23). Here, it sorts in descending order.
  • the number of used gates G n of the instruction is sequentially added.
  • the total of use gate number G n is, while not exceeding the total number of gates G FPGA of FPGA143, continue the addition.
  • the counter i is set to “1”, and the number of used gates G n of the i-th instructions sorted in step S23 is set to the total value s as the current G i (step S24). .
  • step S25 it is determined whether or not the total value s is larger than the total gate number G FPGA (step S25). If it is determined that the total value s is equal to or less than the total gate number G FPGA (step S25; No), the FPGA 143 is set in the arithmetic unit information of the i-th instruction (step S26). The counter i is incremented, and the sum of the current total value s and the number of gates G i used for the i-th instruction is set as a new total value s (step S27). The process returns to step S25 again.
  • step S25 If it is determined in step S25 that the total value s is greater than G FPGA (step S25; Yes), the process ends.
  • the CPU 550 sets the FPGA 143 to the arithmetic device information of the instruction selected as the instruction to be executed by the FPGA 143.
  • the arithmetic unit information of an instruction not selected as an instruction to be executed by the FPGA 143 is not updated.
  • the CPU 550 functions as a determination unit that determines an instruction processed by the FPGA 143 and an instruction that the FPGA 143 does not process, and an update unit that updates arithmetic unit information of the instruction determined as an instruction processed by the FPGA 143.
  • the instruction selected as the instruction to be processed by the FPGA 143 is an example of the first instruction of the present invention.
  • the instruction not processed by the FPGA 143 is an example of the second instruction of the present invention.
  • the user When the processing in the automatic selection mode is completed, the user operates the operation input unit 520 to display the submenu screen shown in FIG. 5 again.
  • the user selects “Upload Program” on the submenu screen. It is assumed that the engineering tool 500 and the CPU unit 100 are connected with a communication cable 501 in advance.
  • “Upload Program” is selected, CPU 550 transfers “program 001”, which is user program 111 stored in storage unit 510, to storage unit 110 of CPU unit 100.
  • the CPU 550 functions as a transfer unit that transfers the user program 111 with the updated arithmetic device information to the CPU unit 100.
  • the FPGA 143 selects the instructions to be executed in order from the instruction having the largest processing time per gate. By assigning an instruction with a large processing load to the FPGA 143, the operation of the PLC 1 can be speeded up.
  • the user program 111 is analyzed and an instruction to be executed by the FPGA 143 is selected.
  • the user can select an arithmetic device for each instruction.
  • Manual selection mode 1 When executing the manual selection mode 1, the user operates the operation input unit 520 to display the submenu screen of FIG. 5, selects an arbitrary user program 111 as a target program on the submenu screen, “Selection mode 1” is designated.
  • the CPU 550 of the engineering tool 500 displays a selection screen as shown in FIG. On this screen, a list of ASIC non-corresponding instructions called in the user program 111 is displayed.
  • the list of non-ASIC instructions that are called in the user program 111 the number of calls that indicate the number of times each instruction is called in the user program 111, and the load caused by executing each instruction once Displays the resource load to represent and the current execution part of each instruction.
  • the value of the execution unit indicates whether the arithmetic unit that executes the instruction is the MPU 142 or the FPGA 143. When the execution unit is “S / W”, this indicates that the MPU 142 processes an instruction.
  • the execution unit When the execution unit is “H / W”, it indicates that the FPGA 143 processes an instruction. In the manual selection mode 1, all the same ASIC non-corresponding instructions are processed by any one of the designated arithmetic units of the MPU 142 and the FPGA 143. For example, when the execution unit of the instruction A is updated from “S / W” to “H / W”, the FPGA 143 processes all the instructions A in the user program 111.
  • the user changes the value of the execution part of the selected command and selects “Save” at the bottom of the screen to save the change. Therefore, the CPU 550 updates the arithmetic device information with the value of the selected execution unit for each instruction in the user program 111. For example, the user changes the execution part of the instruction A from “S / W” to “H / W” and selects “save”. In this case, the arithmetic unit information of all the instructions A in the user program 111 is updated to a value indicating the FPGA 143.
  • the number of calls for each command and the resource load are also displayed. Therefore, the user can select whether the MPU 142 or the FPGA 143 processes the instruction in consideration of the number of times each instruction is called and the resource load.
  • each instruction of the user program 111 is executed only when turned on, for example, not all the instructions A included in the user program 111 are executed within one cycle. Under such circumstances, it is also possible for the user who knows the situation in the field to make a more suitable selection by selecting which of the MPU 142 and FPGA 143 is used to process each command.
  • the manual selection mode 1 In the above-described manual selection mode 1, all the same ASIC non-corresponding instructions are processed by one of the designated arithmetic units of the MPU 142 or FPGA 143. For this reason, while the selected contents are not changed, the MPU 142 or the FPGA 143 is selected to execute the instruction regardless of how many times the instruction is called.
  • the manual selection mode 2 described below has a configuration that allows finer selection.
  • Manual selection mode 2 Next, the manual selection mode 2 will be described.
  • the user operates the operation input unit 520 to display the submenu screen of FIG. On the submenu screen, the user selects “program 001” as the target user program, and selects “manual selection mode 2” as the selection mode.
  • the CPU 550 of the engineering tool 500 displays the ladder diagram of the program 001 selected by the user and the execution unit of each instruction on the display unit 530, as shown in FIG. .
  • the value of the execution unit indicates which of the MPU 142 and the FPGA 143 is the arithmetic device that executes the instruction.
  • arithmetic units for all instructions in the user program 111 are individually selected.
  • all the same ASIC non-corresponding instructions are set to be processed by one of the MPU 142 and the FPGA 143.
  • the arithmetic unit of each ASIC non-corresponding instruction is individually specified. For example, even for the same instruction A, it is possible to specify that the instruction A called first is executed by the MPU 142 and the instruction A called next is executed by the FPGA 143.
  • the user changes the value of the execution part of the selected command and selects “Save” at the bottom of the screen to save the change. Therefore, the CPU 550 updates the arithmetic device information with the value of the selected execution unit for each instruction in the user program 111.
  • the user selects “Upload Program” on the submenu screen shown in FIG. 5 and changes the arithmetic device information in the same manner as in the automatic selection mode.
  • the program 111 is uploaded to the CPU unit 100.
  • the manual selection mode 2 has the following advantages. Since each instruction of the user program 111 is executed only when it is turned on, not all instructions included in the user program 111 are executed within one cycle. There is such a situation, and a user who knows the situation in the field can select which of the MPU 142 and the FPGA 143 to process each command, and a more suitable selection can be made.
  • information indicating the MPU 142 or the FPGA 143 is set in the arithmetic device information included in the ASIC non-compliant instruction.
  • the arithmetic device indicated by the arithmetic device information processes the instruction.
  • the arithmetic device information can be changed using the engineering tool 500. With such a configuration, the user does not need to be aware of the arithmetic device that executes each process at the time of creating the program, and can select the arithmetic device after creating the program. Furthermore, the arithmetic unit can be changed without requiring significant program correction.
  • the automatic selection mode analysis is performed based on the number of calls in the user program 111 for the same ASIC non-compliant instruction, the processing time for each instruction, and the number of gates used to execute each instruction.
  • the operation of the PLC 1 can be speeded up.
  • a suitable arithmetic device can be selected without the user himself / herself being set, the operation is easy even for a user who does not have hardware knowledge.
  • the processing for selecting the arithmetic device is executed again in the automatic selection mode, and the user program 111 with the updated arithmetic device information may be uploaded to the CPU unit 100, so that the operation is easy.
  • the specifications of the FPGA 143 are changed without changing the user program 111
  • the created user program 111 is executed by the CPU unit 100 having a different specification, the above (1) to (4)
  • These parameters may be stored in the storage unit 510 of the engineering tool 500 and the processing for selecting the arithmetic device may be executed again in the automatic selection mode. In this way, a suitable arithmetic device can be selected.
  • the individual user programs 111 are analyzed based on the specifications of the FPGA 143, so that it is possible to suitably select an arithmetic device according to the execution environment.
  • manual selection modes 1 and 2 it is possible for the user who knows the situation at the site to select a computing device that processes each command, thereby making a selection more suitable than the automatic selection mode. Also in the manual selection modes 1 and 2, since the arithmetic device can be changed after the user program 111 is created, it is not necessary to be aware of the arithmetic device when the user program 111 is created. Similarly, when the user program 111 is changed, after the user program 111 is corrected, it is only necessary to select the arithmetic device again. Therefore, it is not necessary to be aware of the arithmetic device even when the user program 111 is changed.
  • the computing device information can be easily changed using the engineering tool 500, when the created user program 111 is executed by the CPU unit 100 having a different specification, the optimum computing device is selected. Until it is possible, the selection of the computing device can be repeated several times.
  • manual selection mode 1 can be used to evaluate the performance of PLC1. For example, it is possible to measure the processing time when processing is performed by the MPU 142 and the processing time when processing is performed by the FPGA 143 for one instruction, and obtain the difference between the actual processing times. For each instruction, statistical data of the actual processing time of the arithmetic unit is created in advance. Based on this statistical data, in the manual selection mode 1 or the manual selection mode 2, an arithmetic device can be selected for each instruction. Also, in the manual selection mode, only a certain instruction at a specific location can be executed by an arithmetic device different from other instructions in the user program 111 of the MPU 142 or FPGA 143. In this way, it can also be used for finding bugs in the user program 111.
  • a ladder diagram may also be displayed as shown in FIG.
  • the user can confirm where the instruction is called in the user program 111, and the user can select an arithmetic device in consideration of this point.
  • the time that can be reduced by using the FPGA 143 was used as an example of the processing time of each instruction by the programmable logic device. Or you may use the actual measured value of the processing time of each command by a programmable logic device. Alternatively, a theoretically predicted value may be used as the processing time of each instruction by the programmable logic device.
  • the selection method of the arithmetic unit is assigned to the FPGA 143 in order from the instruction having the longest processing time per gate as described above, but is not limited to this method.
  • the instructions may be assigned to the FPGA 143 in descending order of the value obtained by multiplying the number of calls of each instruction in the user program 111 by the processing time of each instruction by the programmable logic device.
  • the instructions are assigned to the FPGA 143 in descending order of the value obtained by multiplying the number of calls of each instruction in the user program 111, the processing time of each instruction by the programmable logic device, and the number of gates used in each instruction. Also good.
  • the FPGA 143 may be assigned simply in order from the instruction with the largest number of calls, or in order from the instruction having the longer processing time of each instruction by the programmable logic device.
  • Recording media for recording the above programs include USB memory, flexible disk, CD, DVD, Blu-ray (registered trademark), MO, SD card, Memory Stick (registered trademark), magnetic disk, optical disk, magneto-optical disk, Computer-readable recording media including semiconductor memory and magnetic tape can be used.
  • 1 PLC 100 CPU unit, 110 storage unit, 111 user program, 120 tool interface, 130 shared bus interface, 140 arithmetic unit, 141 ASIC, 1411 register, 1412 program counter, 142 MPU, 1421 register, 143 FPGA, 1431 register, 190 bus, 200 input unit, 210 storage unit, 211 operation program, 220 shared memory, 230 shared bus interface, 240 MPU, 290 bus, 300 output unit, 310 storage unit, 311 operation program, 320 shared memory, 330 shared bus interface 340 MPU, 390 bus, 400 shared bus, 500 engineering tool, 501 communication cable Le, 510 storage unit, 511 operating system, 512 programming application, 520 operation input section, 530 display unit, 540 tool interface, 550 CPU, 590 Bus, 901 detector, 902 the controlled device

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)

Abstract

L'invention concerne une unité central de traitement (CPU) (100) qui est dotée, comme dispositifs de calcul destinés à traiter une commande, d'un circuit intégré prédiffusé programmable (FPGA) (143) et d'une unité centrale à microprocesseur (MPU) (142). La commande contient des informations de dispositif de calcul indiquant un dispositif de calcul sélectionné par un utilisateur comme dispositif de calcul destiné à traiter la commande. La MPU (142) traite la commande si les informations de dispositif de calcul indiquent la MPU (142). Le FPGA (143) traite la commande si les informations de dispositif de calcul indiquent le FPGA (143). Lorsque les informations de dispositif de calcul sont modifiées, la MPU (142) ou le FPGA (143) traite la commande sur la base des informations de dispositif de calcul modifiées.
PCT/JP2018/008798 2018-03-07 2018-03-07 Unité cpu d'automate programmable industriel, automate programmable industriel, procédé, ordinateur et programme informatique WO2019171501A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/JP2018/008798 WO2019171501A1 (fr) 2018-03-07 2018-03-07 Unité cpu d'automate programmable industriel, automate programmable industriel, procédé, ordinateur et programme informatique
JP2019502024A JP6591116B1 (ja) 2018-03-07 2018-03-07 プログラマブルロジックコントローラのｃｐｕユニット、プログラマブルロジックコントローラ、方法、及びコンピュータ
CN201880090694.9A CN111819503B (zh) 2018-03-07 2018-03-07 可编程逻辑控制器的cpu单元、可编程逻辑控制器、方法以及计算机
DE112018007018.2T DE112018007018B4 (de) 2018-03-07 2018-03-07 CPU-Einheit einer programmierbaren Logiksteuerung, programmierbare Logiksteuerung, Verfahren und Computer
TW108106511A TWI701592B (zh) 2018-03-07 2019-02-26 可程式邏輯控制器的ｃｐｕ單元、可程式邏輯控制器、方法、電腦及電腦程式

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002278606A (ja) * 2001-03-15 2002-09-27 Omron Corp プログラミングツール及び制御装置
JP2006243841A (ja) * 2005-02-28 2006-09-14 Omron Corp Ｐｌｃ用ツール装置
JP2006294005A (ja) * 2005-03-14 2006-10-26 Omron Corp プログラマブル・コントローラ
WO2009038682A1 (fr) * 2007-09-21 2009-03-26 Siemens Energy & Automation, Inc. Systèmes, dispositifs, et/ou procédés pour gérer un traitement de contrôleur logique programmable
JP2016212710A (ja) * 2015-05-12 2016-12-15 三菱電機株式会社 ラダープログラム構文解析ツール

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818736A (en) * 1996-10-01 1998-10-06 Honeywell Inc. System and method for simulating signal flow through a logic block pattern of a real time process control system
US7024495B2 (en) 2001-03-30 2006-04-04 Omron Corporation Programmable controller
KR100745959B1 (ko) * 2002-04-17 2007-08-02 후지쯔 가부시끼가이샤 집적 회로의 개발 방법 및 집적 회로의 개발 방법을 기록한 프로그램 기록 매체
JP2009251782A (ja) * 2008-04-03 2009-10-29 Koyo Electronics Ind Co Ltd プログラマブルコントローラの高速化方法等
JP6443190B2 (ja) * 2015-04-06 2018-12-26 オムロン株式会社 プログラマブルロジックコントローラ、プログラマブルロジックコントローラの制御方法、及び、制御プログラム

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002278606A (ja) * 2001-03-15 2002-09-27 Omron Corp プログラミングツール及び制御装置
JP2006243841A (ja) * 2005-02-28 2006-09-14 Omron Corp Ｐｌｃ用ツール装置
JP2006294005A (ja) * 2005-03-14 2006-10-26 Omron Corp プログラマブル・コントローラ
WO2009038682A1 (fr) * 2007-09-21 2009-03-26 Siemens Energy & Automation, Inc. Systèmes, dispositifs, et/ou procédés pour gérer un traitement de contrôleur logique programmable
JP2016212710A (ja) * 2015-05-12 2016-12-15 三菱電機株式会社 ラダープログラム構文解析ツール

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DE112018007018B4 (de) 2024-05-02
TW201939273A (zh) 2019-10-01
JP6591116B1 (ja) 2019-10-16
TWI701592B (zh) 2020-08-11
CN111819503B (zh) 2021-08-24
DE112018007018T5 (de) 2020-11-05
CN111819503A (zh) 2020-10-23

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