WO2019167113A1 - Display panel - Google Patents

Display panel Download PDF

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Publication number
WO2019167113A1
WO2019167113A1 PCT/JP2018/007195 JP2018007195W WO2019167113A1 WO 2019167113 A1 WO2019167113 A1 WO 2019167113A1 JP 2018007195 W JP2018007195 W JP 2018007195W WO 2019167113 A1 WO2019167113 A1 WO 2019167113A1
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WO
WIPO (PCT)
Prior art keywords
layer
display panel
display
film
frame
Prior art date
Application number
PCT/JP2018/007195
Other languages
French (fr)
Japanese (ja)
Inventor
精一 三ツ井
家根田　剛士
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to PCT/JP2018/007195 priority Critical patent/WO2019167113A1/en
Publication of WO2019167113A1 publication Critical patent/WO2019167113A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H05B33/04—Sealing arrangements, e.g. against humidity
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/22—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of auxiliary dielectric or reflective layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present invention relates to a display panel.
  • Display panels are used in various electronic devices such as televisions, personal computers, mobile phones, smartphones, instrument panels, CID (Center Information Display), game machines, wristwatch-type terminals, and the like.
  • CID Center Information Display
  • game machines such as televisions, personal computers, mobile phones, smartphones, instrument panels, CID (Center Information Display), game machines, wristwatch-type terminals, and the like.
  • Patent Document 1 discloses an organic EL display panel in which a through hole penetrating the panel surface is formed as an opening in a light emitting area in order to attach a step motor.
  • Japanese Patent Publication Japanese Patent Laid-Open No. 2014-235790 (Released on December 15, 2014)”
  • a cross section of a functional layer including a light emitting layer in the light emitting element is exposed in the opening, the cross section displays the display area. Moisture penetrates. When moisture permeates into the display area, the characteristics of the light emitting element deteriorate, causing problems such as a decrease in the reliability of the display panel.
  • a vacuum vapor deposition method using a vapor deposition mask having a mask opening that allows vapor deposition particles to pass through is generally used.
  • a fine metal mask (FMM) provided with a highly accurate opening is used to form the light emitting layer.
  • the light emitting layer is separately deposited for each light emitting element (in other words, for each pixel) using FMM.
  • the FMM is distorted.
  • the pattern accuracy of the mask opening is lowered, and the vapor deposition particles that have passed through the mask opening are deposited at a position deviated from the original vapor deposition position. For this reason, the display quality of the obtained display panel is lowered.
  • the present invention has been made in view of the above-described problems, and has an object of having a notch that penetrates the panel surface, no moisture permeation into the display area, and high reliability and display quality. It is to provide a display panel.
  • a display panel includes a resin layer, an inorganic layer provided on the upper layer of the resin layer, and a planarizing film provided on the upper layer of the inorganic layer.
  • a TFT layer a plurality of light emitting elements provided on an upper layer of the planarizing film, and a sealing layer for sealing the plurality of light emitting elements, wherein the sealing layer includes an organic sealing film, An inorganic sealing film that seals the organic sealing film, and a first frame-shaped bank surrounding an edge of the organic sealing film; and spaced apart from the first frame-shaped bank and of the first frame-shaped bank
  • a display panel having a second frame-shaped bank surrounding the periphery and a plurality of pixels, and having an opening in which a notch in which an end of the display panel is notched is formed so as to penetrate the panel surface In the opening, the inorganic layer is open and covers the end of the opening.
  • a sealing film is provided, and the plurality of pixels include the light emitting element and display, and a plurality of display pixels that are provided between the opening and the plurality of display pixels and do not perform display
  • the non-display pixel and the light emitting element includes a first electrode and an edge cover that exposes the first electrode and covers an end portion of the first electrode from the resin layer side.
  • a functional layer, and a second electrode provided in common to the plurality of light emitting elements, the functional layer including at least a light emitting layer, the plurality of display pixels and the plurality of non-display pixels
  • a plurality of island layers provided in an island shape for each pixel, and a common layer formed of a functional layer other than the light emitting layer and provided in common to the plurality of display pixels.
  • the end of the second frame bank on the side of the notch and the end of the opening sealing film on the side of the display pixel are larger than the size of one island layer. It is characterized by long distance.
  • a display panel having an opening penetrating the panel surface, no moisture permeation into the display area, and high reliability and display quality can be realized.
  • FIG. 3 is a plan view illustrating a configuration example of a display panel according to Embodiment 1.
  • FIG. 3 is a plan view illustrating a detailed configuration example of a display panel according to Embodiment 1.
  • FIG. 3 is a cross-sectional view illustrating a cross-sectional configuration example of a display panel according to Embodiment 1.
  • FIG. 6 is a cross-sectional view illustrating a cross-sectional configuration example of a display panel according to Embodiment 2.
  • FIG. 10 is a plan view illustrating a detailed configuration example of a display panel according to Embodiment 3.
  • FIG. 10 is a cross-sectional view illustrating a cross-sectional configuration example of a display panel according to Embodiment 3.
  • FIG. 10 is a plan view illustrating a detailed configuration example of a display panel according to Embodiment 4.
  • FIG. 6 is a cross-sectional view illustrating a cross-sectional configuration example of a display panel according to Embodiment 4.
  • FIG. 10 is a plan view showing a detailed configuration example of a display panel according to Embodiment 5.
  • FIG. 10 is a cross-sectional view illustrating a cross-sectional configuration example of a display panel according to Embodiment 5.
  • FIG. 1 is a plan view illustrating a configuration example of the display panel 1 according to the first embodiment.
  • the display panel 1 includes a display area DA and an opening DB arranged on the display surface.
  • the opening DB is disposed at the end of the display panel 1.
  • a notch DC in which an end of the display panel 1 is notched is formed so as to penetrate the panel surface of the display panel 1.
  • One part of the terminal device provided with the display panel 1 is mounted on the notch DC. This component is, for example, a camera module.
  • the display panel 1 displays information in the display area DA.
  • FIG. 2 is a plan view showing a detailed configuration example of the display panel 1 according to the first embodiment.
  • FIG. 3 is a cross-sectional view illustrating a cross-sectional configuration example of the display panel 1 according to the first embodiment.
  • FIG. 3 shows a cross section taken along line A-A ′ of FIG.
  • the display panel 1 is a top emission type that emits light upward, and in order from the lower side, the base material 10, the resin layer 12, the barrier layer 3 (base coat layer), the TFT layer 4, the light emitting element layer 5, and the sealing Layer 6 is provided.
  • Examples of the material for the resin layer 12 include polyimide, epoxy, and polyamide. Examples of the material of the substrate 10 include polyethylene terephthalate (PET).
  • PET polyethylene terephthalate
  • the barrier layer 3 is a layer that prevents moisture and impurities from reaching the TFT layer 4 or the light emitting element layer 5 when the display panel 1 is used.
  • the barrier layer 3 is composed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked film thereof formed by CVD.
  • the TFT layer 4 includes a semiconductor film 15, an inorganic insulating film 16 (inorganic layer), a gate electrode G, an inorganic insulating film 18, a capacitor electrode C, an inorganic insulating film 20, a source electrode S, a drain electrode D, and a planarizing film 21.
  • the inorganic insulating film 16 is provided on the upper layer of the semiconductor film 15.
  • the gate electrode G is provided in the upper layer of the inorganic insulating film 16.
  • the inorganic insulating film 18 is provided on the upper layer of the gate electrode G.
  • the capacitive electrode C is provided in the upper layer of the inorganic insulating film 18.
  • the inorganic insulating film 20 is provided in the upper layer of the capacitive electrode C.
  • the source electrode S and the drain electrode D are provided in the upper layer of the inorganic insulating film 20.
  • the planarization film 21 is provided on the upper layer of the source electrode S and the drain electrode D.
  • a thin film transistor Tr (light emission control transistor) is configured to include the semiconductor film 15, the inorganic insulating film 16 (gate insulating film), the gate electrode G, the source electrode S, and the drain electrode D.
  • the thin film transistor Tr drives the light emitting element PX.
  • the source electrode S is connected to the source region of the semiconductor film 15.
  • the drain electrode D is connected to the drain region of the semiconductor film 15.
  • the semiconductor film 15 is made of, for example, low temperature polysilicon (LTPS) or an oxide semiconductor.
  • LTPS low temperature polysilicon
  • FIG. 3 the thin film transistor Tr having the semiconductor film 15 as a channel is shown in a top gate structure.
  • the inorganic insulating films 16, 18, and 20 are formed of, for example, a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a laminated film thereof formed by a CVD method.
  • the planarizing film 21 is made of a photosensitive organic material that can be applied, such as polyimide or acrylic.
  • the gate electrode G, the source electrode S, the drain electrode D, and the terminal are, for example, aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper ( It is comprised by the metal single layer film or laminated film containing at least 1 of Cu).
  • the light emitting element layer 5 is, for example, an organic light emitting diode (OLED) layer.
  • the light emitting element layer 5 includes an anode electrode 22 (first electrode), a planarization film 23 (edge cover), a functional layer 24, and a cathode electrode 25 (second electrode).
  • the anode electrode 22 is disposed in the upper layer of the planarizing film 21.
  • the planarizing film 23 is disposed on the planarizing film 21.
  • the functional layer 24 is disposed on the anode electrode 22 or on the planarization film 23.
  • the cathode electrode 25 is disposed on the upper layer of the functional layer 24.
  • the anode electrode 22 and the cathode electrode 25 can be disposed at positions opposite to each other.
  • the light emitting element layer 5 has a plurality of light emitting elements PX.
  • the plurality of light emitting elements PX are provided in the upper layer of the planarizing film 21.
  • Each light emitting element PX is, for example, an organic light emitting diode.
  • Each light emitting element PX includes an anode electrode 22, a planarizing film 23, a functional layer 24, and a cathode electrode 25 in this order from the resin layer 12 side.
  • the planarization film 23 has an opening exposing the anode electrode 22 and covers the end of the anode electrode 22.
  • the anode electrode 22 is provided for each light emitting element PX.
  • the cathode electrode 25 is provided in common for the plurality of light emitting elements PX.
  • the cathode electrode 25 has an opening (cathode opening) whose end is cut out along the opening DB.
  • the planarization films 21 and 23 have a slit S ⁇ b> 1 surrounding the cathode electrode 25 along the opening of the cathode electrode 25 in the opening of the cathode electrode 25 in plan view.
  • the anode electrode 22 is composed of, for example, a laminate of ITO (Indium Tin Oxide) and an alloy containing Ag, and has light reflectivity.
  • the cathode electrode 25 is made of a light-transmitting conductive material such as ITO or IZO (Indium Zinc Oxide).
  • the display panel 1 has a plurality of pixels.
  • the plurality of pixels include a plurality of display pixels SPA and a plurality of non-display pixels SPB.
  • the plurality of display pixels SP are arranged in the display area DA.
  • Each display pixel SPA is a pixel that has one of the light emitting elements PX and performs display.
  • Each non-display pixel SPB is a pixel that is disposed between the cutout portion DC and the plurality of display pixels SPA in the opening DB and does not perform display.
  • the corresponding thin film transistor Tr is formed in the display pixel SPA, and the corresponding thin film transistor Tr is not provided in the non-display pixel SPB.
  • the functional layer 24 has a plurality of island layers 26 and one common layer 27.
  • the plurality of island layers 26 include at least a light emitting layer, and are provided in an island shape for each pixel in the plurality of display pixels SPA and the plurality of non-display pixels SPB.
  • the common layer 27 includes functional layers other than the light emitting layer, and is provided in common to the plurality of display pixels SPA. The common layer 27 is not provided for any non-display pixel SPA.
  • the light emitting element layer 5 is an organic light emitting diode layer
  • the display pixel SPA for example, a hole injection layer, a hole transport layer, an upper layer than the bottom surface of the planarization film 23 (a portion where the anode electrode 22 is exposed),
  • An island layer 26, an electron transport layer, and an electron injection layer are stacked. At least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer other than the island layer 26 is configured as the common layer 27.
  • the light emitting element layer 5 is an organic light emitting diode layer
  • holes and electrons are recombined in the island layer 26 by the drive current between the anode electrode 22 and the cathode electrode 25.
  • the excitons generated thereby fall to the ground state, and light is emitted from the island layer 26.
  • the cathode electrode 25 is translucent and the anode electrode 22 is light-reflective, the light emitted from the island layer 26 is directed upward and becomes top emission.
  • the light emitting element layer 5 is not limited to a configuration having an organic light emitting diode, but may be a configuration having an inorganic light emitting diode or a quantum dot light emitting diode.
  • a fine metal mask for forming a plurality of island layers 26 is used.
  • the same mask opening is patterned so that the island layer 26 is deposited not only in the display area DA but also in the area where the opening DB and the notch DC are to be formed.
  • the mask openings corresponding to the island layers 26 have the same size and the same shape. Thereby, since a distortion does not arise in a fine metal mask, the pattern precision of a mask opening does not fall, but the vapor deposition particle which passed the mask opening is vapor-deposited correctly in the position originally vapor-deposited. Accordingly, it is possible to prevent the display quality of the obtained display panel 1 from being deteriorated.
  • a common metal mask for forming the common layer 27 is used.
  • the mask opening is patterned so that the common layer 27 is deposited only at the positions where the plurality of display pixels SPA are formed in the display area DA.
  • the common layer 27 is not vapor-deposited at the portion where the non-display pixel SPB is formed in the opening DB and the region where the cutout portion DC is to be formed.
  • the island layer 26 in the non-display pixel SPB has the same shape and the same size as the island layer 26 in the display pixel SPA.
  • “the same shape and the same size” means that when the evaporation material of the island-like layer 26 is deposited using a mask having the same shape and the same size mask pattern, the same shape and This means that island layers 26 of the same size are formed as a result. Therefore, in the display panel 1, the island layer 26 in the display pixel SPA and the island layer 26 in the non-display pixel SPB do not necessarily have the same shape and the same size.
  • the size of the island layer 26 means the width of the island layer 26.
  • the width of the island layer 26 means a width in a direction horizontal to the substrate of the island layer 26 as viewed from a direction orthogonal to the display surface of the display panel 1. More specifically, the size (width) of the island layer 26 means the maximum width (the vertical width in FIG. 2) in the island layer 26 constituting the display pixel SPA.
  • the entire island layer 26 in the non-display pixel SPB overlaps with the planarizing film 23.
  • the planarization film 23 provided below the island layer 26 does not have an opening.
  • the sealing layer 6 is translucent and includes an inorganic sealing film 28, an organic sealing film 29, and an inorganic sealing film 30.
  • the inorganic sealing film 28 is provided in the upper layer of the cathode electrode 25 so as to cover the cathode electrode 25.
  • the organic sealing film 29 is provided in the upper layer of the inorganic sealing film 28.
  • the inorganic sealing film 30 is provided in the upper layer of the inorganic sealing film 28 so as to cover the organic sealing film 29. In other words, the inorganic sealing film 30 seals the organic sealing film 29.
  • the inorganic sealing films 28 and 30 are made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminated film thereof formed by CVD using a mask.
  • the organic sealing film 29 is, for example, a light-transmitting organic film thicker than the inorganic sealing films 28 and 30, and is made of a photosensitive organic material that can be applied such as polyimide or acrylic.
  • an ink containing such an organic material is applied onto the inorganic sealing film 30 by inkjet and then cured by UV irradiation.
  • the sealing layer 6 covers the light emitting element layer 5 to prevent water, oxygen, and the like from entering the light emitting element layer 5.
  • the display panel 1 includes frame banks 61 and 62. Both the frame banks 61 and 62 are arranged in the display area DA and the opening DB.
  • the frame bank 61 (first frame bank) surrounds the edge of the organic sealing film 29.
  • the frame bank 62 (second frame bank) is separated from the frame bank 61 and surrounds the frame bank 61.
  • the frame bank 61 includes a planarizing film 23.
  • An island layer 26 is formed on the planarizing film 23 that constitutes the frame bank 61.
  • the frame bank 61 is covered with the inorganic sealing films 28 and 30.
  • the frame-like bank 62 includes the planarizing film 21 and the planarizing film 23.
  • the planarizing film 23 is provided on the planarizing film 21.
  • An island layer 26 is formed on the planarizing film 23 that constitutes the frame bank 61.
  • the frame bank 61 is covered with the inorganic sealing films 28 and 30.
  • the display panel 1 includes a gate wiring GL and a connection wiring 71 (conductive layer) connected to the cathode electrode 25.
  • the gate line GL is provided in the display area DA.
  • the connection wiring 71 is provided along a part of the frame bank 61 in the display area DA.
  • a contact hole (not shown) is formed at a position overlapping the cathode electrode 25 in the display area DA.
  • the connection wiring 71 is electrically connected to the cathode electrode 25 through this contact hole.
  • the inorganic insulating films 16, 18, and 20 have openings that expose the barrier layer 3.
  • an opening sealing film 63 is provided so as to cover the end of the opening.
  • the opening sealing film 63 includes the planarization layer 21 and the planarization layer 23.
  • the planarization layer 23 is provided on the planarization layer 21.
  • at least one island-like layer 26 is provided on the planarization layer 23.
  • the entire at least one island-like layer 26 overlaps with the opening sealing film 63. This means that when the display panel 1 is manufactured, the material of the island layer 26 is deposited not only on the display area DA but also on the upper layer of the opening sealing film 63 in the opening DB.
  • the inorganic sealing films 28 and 30 have openings through which the inorganic insulating film 20 is exposed.
  • the end portions of the inorganic sealing films 28 and 30 are between the frame-shaped bank 62 and the opening sealing film 63.
  • the island-like layer 26 is provided between the frame bank 62 and the opening sealing film 63.
  • the end on the notch portion DC side in the frame bank 62 and the end on the display pixel SPA side in the opening sealing film 63 are longer than the size of one island layer 26.
  • the distance 81 between the end portion on the cutout portion DC side in the frame-shaped bank 62 and the end portion on the display pixel SPA side in the opening sealing film 63 is larger than the size of one island layer 26. .
  • the organic sealing film 29 may overflow to the vicinity of the frame bank 62 in the opening DB without being sufficiently blocked by the frame bank 61. At this time, if the organic sealing film 29 is not sufficiently sealed by the inorganic sealing film 30, the organic sealing film 29 may be in direct contact with the frame bank 62. However, as described above, the end on the notch portion DC side in the frame-shaped bank 62 and the end on the display pixel SPA side in the opening sealing film 63 are separated longer than the size of one island layer 26. ing. Thus, the island layer 26 does not function as a moisture transfer path across the frame-shaped bank 62 and the opening sealing film 63. Therefore, it is possible to prevent moisture from penetrating into the light emitting element PX side in the display area DA.
  • the end of the frame bank 61 on the notch portion DC side and the end of the frame bank 62 on the display pixel SPA side are longer than the size of one island layer 26.
  • the distance 82 between the end on the notch portion DC side in the frame-shaped bank 61 and the end on the display pixel SPA side in the frame-shaped bank 62 is larger than the size of one island layer 26.
  • the island layer 26 is not formed across the frame bank 61 and the frame bank 62, so the island layer 26 is formed between the frame bank 61 and the frame bank 62.
  • the island layer 26 does not function as a moisture passage path. Therefore, it is possible to prevent moisture from penetrating into the light emitting element PX side in the display area DA.
  • FIG. 4 is a cross-sectional view illustrating a cross-sectional configuration example of the display panel 1 according to the second embodiment.
  • the inorganic sealing films 28 and 30 have an opening for exposing a part of the island layer 26.
  • the end on the notch portion DC side in the frame-shaped bank 62 and the ends of the inorganic sealing films 28 and 30 are separated from each other by a length longer than the size of one island layer 26.
  • the distance 83 between the end of the frame-shaped bank 62 on the notch portion DC side and the end of the inorganic sealing films 28 and 30 is larger than the size of one island-like layer 26.
  • the exposed island layer 26 does not overlap the frame bank 62.
  • the organic sealing film 29 is in direct contact with the frame-shaped bank 62, the exposed island-shaped layer 26 is in contact with the organic sealing film 29 through the frame-shaped bank 62, so that the island-shaped layer 26 is moisture. It is possible to prevent moisture from penetrating the display area DA.
  • FIG. 5 is a plan view illustrating a detailed configuration example of the display panel 1 according to the third embodiment.
  • FIG. 6 is a cross-sectional view illustrating a cross-sectional configuration example of the display panel 1 according to the third embodiment.
  • FIG. 6 shows a cross section taken along the line AA ′ in FIG.
  • connection wiring 71 is formed between the notch portion DC and the plurality of display pixels SPA so as to overlap the non-display pixel SPB and surround the notch portion DC.
  • the connection wiring 71 is formed by the anode electrode 22 corresponding to the non-display pixel SPB.
  • the connection wiring 71 is provided in the same layer as the anode electrode 22 corresponding to the display pixel SPA.
  • the cathode electrode 25 and the source electrode S (wiring) of the TFT layer are electrically connected via the connection wiring 71.
  • the low voltage output from the low voltage power supply is input to the cathode electrode 25 through the source electrode S and the connection wiring 71.
  • a range 84 in which the connection wiring 71 and the cathode electrode 25 are in contact with each other and electrically connected in the opening DB is larger than the size of one island layer 26. Thereby, a portion where the connection wiring 71 and the cathode electrode 25 do not overlap with the island layer 26 is always included in the range 84, so that the contact resistance between the connection wiring 71 and the cathode electrode 25 can be lowered.
  • FIG. 7 is a plan view illustrating a detailed configuration example of the display panel 1 according to the fourth embodiment.
  • FIG. 8 is a cross-sectional view illustrating a cross-sectional configuration example of the display panel 1 according to the fourth embodiment.
  • FIG. 8 shows a cross section taken along the line AA ′ in FIG.
  • the barrier layer 3 and the inorganic insulating films 16, 18, and 20 have the slit S 2 along the notch DC.
  • the slit S2 is formed immediately below the frame-shaped bank 62 in the opening DB.
  • the planarizing film 21 constituting the frame-shaped bank 62 is embedded.
  • the planarizing film 21 embedded in the slit S ⁇ b> 2 is the same as the planarizing film 21 constituting the frame bank 62.
  • the planarizing film 21 constituting the frame bank 62 branches into a portion embedded in the slit S2 along the notch DC and a portion formed in the upper layer of the inorganic insulating film 20 along the frame bank 61. Has been.
  • the inorganic insulating films 16, 18, and 20 have the slits S2 in the opening DB, it is possible to prevent the opening DB from being cracked.
  • FIG. 9 is a plan view illustrating a detailed configuration example of the display panel 1 according to the fifth embodiment.
  • FIG. 10 is a cross-sectional view illustrating a cross-sectional configuration example of the display panel 1 according to the fifth embodiment.
  • FIG. 10 shows a cross section taken along the line AA ′ in FIG.
  • the barrier layer 3 and the inorganic insulating films 16, 18, and 20 have the slits S2 along the notch DC.
  • a bank 64 is formed at a location outside the frame bank 62 in the opening DB so as to overlap the slit S2 and surround the notch DC.
  • the bank 64 includes a planarizing film 21 and a planarizing film 23.
  • An island layer 26 is formed on the planarizing film 23 constituting the bank 64.
  • the bank 64 is covered with the inorganic sealing films 28 and 30.
  • the bank 64 that does not include the planarizing film 21 is formed in the opening DB so as to overlap the slit S2.
  • the inorganic insulating films 16, 18, and 20 have the slits S2 in the opening DB, it is possible to prevent the opening DB from being cracked.
  • the electro-optical element (electro-optical element whose luminance and transmittance are controlled by current) included in the display panel 1 according to each embodiment is not particularly limited.
  • the display device according to each embodiment includes, for example, an organic EL (Electro Luminescence) display including an OLED (Organic Light Emitting Diode) as an electro-optical element, and an inorganic light-emitting diode as an electro-optical element.
  • OLED Organic Light Emitting Diode
  • inorganic light-emitting diode as an electro-optical element.
  • Inorganic EL displays, and QLED displays equipped with QLEDs (Quantum dot emitting Light emitting diodes) as electro-optical elements are exemplified.
  • a TFT layer having a resin layer, an inorganic layer provided above the resin layer, and a planarizing film provided on the inorganic layer, and a plurality of light emission provided on the planarizing film
  • An element and a sealing layer that seals the plurality of light emitting elements, and the sealing layer includes an organic sealing film and an inorganic sealing film that seals the organic sealing film, A first frame bank surrounding an edge of the organic sealing film, a second frame bank spaced from the first frame bank and surrounding the first frame bank, and a display panel having a plurality of pixels
  • the display panel has an opening in which a notch is formed by notching an end of the display panel, and the inorganic layer is opened in the opening.
  • An opening sealing film is provided so as to cover an end of the opening, and the plurality of pixels include the light emitting element.
  • a plurality of display pixels that perform one display, and a plurality of non-display pixels that are provided between the notch portion and the plurality of display pixels and that do not perform display, and the light emitting element is on the resin layer side
  • an edge cover that exposes the first electrode and covers an end of the first electrode, a functional layer, and the light emitting element.
  • a plurality of island-like layers provided in an island shape for each of the plurality of display pixels and the plurality of non-display pixels;
  • the island layer in the non-display pixel has the same shape and the same as the island layer in the display pixel, and the common layer provided in common to the plurality of display pixels.
  • the display panel and the display pixel side end of the opening sealing film characterized in that apart longer than the size of one of said island layer.
  • Aspect 2 An end of the first frame bank on the notch portion side and an end of the second frame bank on the display pixel side are longer than the size of one island layer.
  • Aspect 3 The end of the notch in the second frame-shaped bank and the end of the inorganic sealing film on the side of the notch are longer than the size of one island-like layer.
  • Aspect 4 a conductive layer formed by the first electrode so as to overlap the non-display pixel and surround the cutout portion between the cutout portion and the plurality of display pixels. 4. The display panel according to any one of aspects 1 to 3, wherein the second electrode and the wiring of the TFT layer are electrically connected through the conductive layer.
  • Aspect 5 A display panel according to Aspect 4, wherein a width of a range in which the conductive layer and the second electrode are in contact with each other in the opening is larger than a size of one island layer.
  • Aspect 6 The display panel according to any one of Aspects 1 to 5, wherein the whole of the island layer in the non-display pixel overlaps with an edge cover.
  • Aspect 7 The display panel according to any one of Aspects 1 to 6, wherein at least one of the island-like layers entirely overlaps the opening sealing film.
  • Aspect 8 The display according to any one of Aspects 1 to 7, wherein the inorganic layer has a slit along the notch, and the planarizing film is embedded in the slit. panel.
  • the bank includes the planarizing film embedded in the slit, and an edge cover formed in an upper layer of the planarizing film, and further includes a bank formed so as to surround the notch.
  • the second frame-shaped bank has the planarizing film and an edge cover formed on an upper layer of the planarizing film, and the planarizing film embedded in the slit is the first
  • Aspect 12 The flattening film constituting the second frame-shaped bank is branched into a portion along the cutout portion and a portion along the first frame-shaped bank. Display panel.

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Abstract

The length of separation between an end portion of a frame-shaped bank (62) on the cut-out section (DC) side thereof and an end portion of an opening-seal film (63) on the display pixel (SPA) side thereof is greater than the size of one island-shaped layer (26).

Description

表示パネルDisplay panel
　本発明は、表示パネルに関する。 The present invention relates to a display panel.
　表示パネルは、例えば、テレビ、パーソナルコンピュータ、携帯電話、スマートフォン、インストルメントパネル、ＣＩＤ（Center Information Display）、ゲーム機、腕時計型端末等、様々な電子機器で利用されている。 Display panels are used in various electronic devices such as televisions, personal computers, mobile phones, smartphones, instrument panels, CID (Center Information Display), game machines, wristwatch-type terminals, and the like.
　そのような中、ボタン、ダイヤル、針、カメラ等と表示パネルとを一体化させたユーザインターフェース・アプリケーションが求められており、表示領域内に、パネル面を貫通する、切り欠きあるいは穴等の開口部が設けられた表示パネルの開発が望まれている。例えば、特許文献１には、ステップモータを取り付けるために、発光エリアに、開口部として、パネル面を貫通する貫通穴が形成された有機ＥＬ表示パネルが開示されている。 Under such circumstances, there is a need for a user interface application that integrates a display panel with buttons, dials, hands, cameras, etc., and an opening such as a notch or a hole that penetrates the panel surface in the display area. Development of a display panel provided with a section is desired. For example, Patent Document 1 discloses an organic EL display panel in which a through hole penetrating the panel surface is formed as an opening in a light emitting area in order to attach a step motor.
日本国公開特許公報「特開２０１４－２３５７９０号（２０１４年１２月１５日公開）」Japanese Patent Publication “Japanese Patent Laid-Open No. 2014-235790 (Released on December 15, 2014)”
　しかし、支持体の表裏面を貫通する開口部が設けられた表示パネルにおいて、開口部に、発光素子における、発光層を含む機能層等の断面が露出していると、断面から表示領域内に水分が浸透してしまう。表示領域内に水分が浸透すると、発光素子の特性が劣化し、表示パネルの信頼性の低下等の問題を引き起こす。 However, in a display panel provided with an opening that penetrates the front and back surfaces of the support, if a cross section of a functional layer including a light emitting layer in the light emitting element is exposed in the opening, the cross section displays the display area. Moisture penetrates. When moisture permeates into the display area, the characteristics of the light emitting element deteriorate, causing problems such as a decrease in the reliability of the display panel.
　機能層の形成には、一般的に、蒸着粒子を通過させるマスク開口を有する蒸着マスクを用いた真空蒸着法が用いられる。蒸着マスクとして、発光層の形成には、高精度な開口部が設けられたファインメタルマスク（ＦＭＭ）が用いられる。発光層は、ＦＭＭを用いて、発光素子ごと（言い換えれば、画素ごと）に塗り分け蒸着される。 For the formation of the functional layer, a vacuum vapor deposition method using a vapor deposition mask having a mask opening that allows vapor deposition particles to pass through is generally used. As the vapor deposition mask, a fine metal mask (FMM) provided with a highly accurate opening is used to form the light emitting layer. The light emitting layer is separately deposited for each light emitting element (in other words, for each pixel) using FMM.
　このため、表示領域内への水分の浸透を防止するには、機能層の形成に使用される蒸着マスクのマスク開口を、開口部の形成領域に機能層が蒸着されないようにパターン形成する必要がある。 For this reason, in order to prevent moisture from penetrating into the display region, it is necessary to pattern the mask opening of the vapor deposition mask used for forming the functional layer so that the functional layer is not deposited in the region where the opening is formed. is there.
　しかし、上述したようなＦＭＭに、開口部の形成領域に機能層が蒸着されないようにマスク開口をパターン形成すると、ＦＭＭに歪みが生じる。この結果、マスク開口のパターン精度が低下し、該マスク開口を通過した蒸着粒子が、本来蒸着される位置からずれた位置に蒸着されてしまう。このため、得られる表示パネルの表示品位が低下する。 However, if the mask opening is patterned in the FMM as described above so that the functional layer is not deposited in the opening forming region, the FMM is distorted. As a result, the pattern accuracy of the mask opening is lowered, and the vapor deposition particles that have passed through the mask opening are deposited at a position deviated from the original vapor deposition position. For this reason, the display quality of the obtained display panel is lowered.
　本発明は、上述した問題点に鑑みなされたものであり、その目的は、パネル面を貫通する切り欠き部を有し、表示領域内への水分の浸透がなく、信頼性および表示品位が高い表示パネルを提供することにある。 The present invention has been made in view of the above-described problems, and has an object of having a notch that penetrates the panel surface, no moisture permeation into the display area, and high reliability and display quality. It is to provide a display panel.
　本発明の一態様に係る表示パネルは、前記の課題を解決するために、樹脂層と、前記樹脂層の上層に設けられた無機層および前記無機層の上層に設けられた平坦化膜を有するＴＦＴ層と、前記平坦化膜の上層に設けられた複数の発光素子と、前記複数の発光素子を封止する封止層と、を備え、前記封止層が、有機封止膜と、前記有機封止膜を封止する無機封止膜と、を含み、前記有機封止膜の縁を囲む第１枠状バンクと、前記第１枠状バンクと離間しかつ前記第１枠状バンクの周囲を囲む第２枠状バンクと、複数の画素を有する表示パネルであって、パネル面を貫通するように、当該表示パネルの端部が切り欠けられた切り欠き部が形成される開口部を有し、前記開口部において、前記無機層は開口されており該開口の端部を覆うように開口封止膜が設けられ、前記複数の画素が、前記発光素子を有しかつ表示を行う複数の表示画素と、前記開口部と前記複数の表示画素との間に設けられかつ表示を行わない複数の非表示画素と、を含み、前記発光素子は、前記樹脂層側から、第１電極と、前記第１電極を露出するように開口が設けられかつ前記第１電極の端部を覆うエッジカバーと、機能層と、及び前記複数の発光素子に共通して設けられる第２電極と、を有し、前記機能層は、少なくとも発光層を含み、前記複数の表示画素および前記複数の非表示画素に、画素ごとに島状に設けられた複数の島状層と、発光層以外の機能層からなり、前記複数の表示画素に共通に設けられた共通層と、を含み、前記非表示画素における島状層は、前記表示画素における島状層と同一の形状かつ同一の大きさであり、前記第２枠状バンクにおける前記切り欠き部側の端部と、前記開口封止膜における前記表示画素側の端部とが、１つの前記島状層の大きさよりも長く離れていることを特徴としている。 In order to solve the above problems, a display panel according to one embodiment of the present invention includes a resin layer, an inorganic layer provided on the upper layer of the resin layer, and a planarizing film provided on the upper layer of the inorganic layer. A TFT layer, a plurality of light emitting elements provided on an upper layer of the planarizing film, and a sealing layer for sealing the plurality of light emitting elements, wherein the sealing layer includes an organic sealing film, An inorganic sealing film that seals the organic sealing film, and a first frame-shaped bank surrounding an edge of the organic sealing film; and spaced apart from the first frame-shaped bank and of the first frame-shaped bank A display panel having a second frame-shaped bank surrounding the periphery and a plurality of pixels, and having an opening in which a notch in which an end of the display panel is notched is formed so as to penetrate the panel surface In the opening, the inorganic layer is open and covers the end of the opening. A sealing film is provided, and the plurality of pixels include the light emitting element and display, and a plurality of display pixels that are provided between the opening and the plurality of display pixels and do not perform display The non-display pixel, and the light emitting element includes a first electrode and an edge cover that exposes the first electrode and covers an end portion of the first electrode from the resin layer side. And a functional layer, and a second electrode provided in common to the plurality of light emitting elements, the functional layer including at least a light emitting layer, the plurality of display pixels and the plurality of non-display pixels A plurality of island layers provided in an island shape for each pixel, and a common layer formed of a functional layer other than the light emitting layer and provided in common to the plurality of display pixels. Is the island layer the same shape as the island layer in the display pixel? The end of the second frame bank on the side of the notch and the end of the opening sealing film on the side of the display pixel are larger than the size of one island layer. It is characterized by long distance.
　パネル面を貫通する開口部を有し、表示領域内への水分の浸透がなく、信頼性および表示品位が高い表示パネルを実現することができる。 A display panel having an opening penetrating the panel surface, no moisture permeation into the display area, and high reliability and display quality can be realized.
実施形態１に係る表示パネルの構成例を示す平面図である。3 is a plan view illustrating a configuration example of a display panel according to Embodiment 1. FIG. 実施形態１に係る表示パネルの詳細な構成例を示す平面図である。3 is a plan view illustrating a detailed configuration example of a display panel according to Embodiment 1. FIG. 実施形態１に係る表示パネルの断面構成例を示す断面図である。3 is a cross-sectional view illustrating a cross-sectional configuration example of a display panel according to Embodiment 1. FIG. 実施形態２に係る表示パネルの断面構成例を示す断面図である。6 is a cross-sectional view illustrating a cross-sectional configuration example of a display panel according to Embodiment 2. FIG. 実施形態３に係る表示パネルの詳細な構成例を示す平面図である。10 is a plan view illustrating a detailed configuration example of a display panel according to Embodiment 3. FIG. 実施形態３に係る表示パネルの断面構成例を示す断面図である。10 is a cross-sectional view illustrating a cross-sectional configuration example of a display panel according to Embodiment 3. FIG. 実施形態４に係る表示パネルの詳細な構成例を示す平面図である。10 is a plan view illustrating a detailed configuration example of a display panel according to Embodiment 4. FIG. 実施形態４に係る表示パネルの断面構成例を示す断面図である。6 is a cross-sectional view illustrating a cross-sectional configuration example of a display panel according to Embodiment 4. FIG. 実施形態５に係る表示パネルの詳細な構成例を示す平面図である。10 is a plan view showing a detailed configuration example of a display panel according to Embodiment 5. FIG. 実施形態５に係る表示パネルの断面構成例を示す断面図である。10 is a cross-sectional view illustrating a cross-sectional configuration example of a display panel according to Embodiment 5. FIG.
　〔実施形態１〕
　（表示パネル１の構成例）
　図１は、実施形態１に係る表示パネル１の構成例を示す平面図である。表示パネル１は、その表示面に配置される表示領域ＤＡおよび開口部ＤＢを備えている。開口部ＤＢは、表示パネル１の端部に配置される。開口部ＤＢには、表示パネル１のパネル面を貫通するように、表示パネル１の端部が切り欠けられた切り欠き部ＤＣが形成される。切り欠き部ＤＣには、表示パネル１が備えられる端末装置の一部品が搭載される。この部品は、例えばカメラモジュールである。表示パネル１は、表示領域ＤＡに情報を表示する。 Embodiment 1
(Configuration example of display panel 1)
FIG. 1 is a plan view illustrating a configuration example of the display panel 1 according to the first embodiment. The display panel 1 includes a display area DA and an opening DB arranged on the display surface. The opening DB is disposed at the end of the display panel 1. In the opening DB, a notch DC in which an end of the display panel 1 is notched is formed so as to penetrate the panel surface of the display panel 1. One part of the terminal device provided with the display panel 1 is mounted on the notch DC. This component is, for example, a camera module. The display panel 1 displays information in the display area DA.
　図２は、実施形態１に係る表示パネル１の詳細な構成例を示す平面図である。図３は、実施形態１に係る表示パネル１の断面構成例を示す断面図である。図２のＡ－Ａ’箇所の断面を、図３に示す。 FIG. 2 is a plan view showing a detailed configuration example of the display panel 1 according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a cross-sectional configuration example of the display panel 1 according to the first embodiment. FIG. 3 shows a cross section taken along line A-A ′ of FIG.
　表示パネル１は、上方に向けて発光するトップエミッション型であり、下側から順に、基材１０、樹脂層１２、バリア層３（ベースコート層）、ＴＦＴ層４、発光素子層５、および封止層６を備えている。 The display panel 1 is a top emission type that emits light upward, and in order from the lower side, the base material 10, the resin layer 12, the barrier layer 3 (base coat layer), the TFT layer 4, the light emitting element layer 5, and the sealing Layer 6 is provided.
　樹脂層１２の材料としては、例えば、ポリイミド、エポキシ、ポリアミド等が挙げられる。基材１０の材料としては、例えばポリエチレンテレフタレート（ＰＥＴ）が挙げられる。 Examples of the material for the resin layer 12 include polyimide, epoxy, and polyamide. Examples of the material of the substrate 10 include polyethylene terephthalate (PET).
　バリア層３は、表示パネル１の使用時に、水分および不純物がＴＦＴ層４または発光素子層５に到達することを防ぐ層である。バリア層３は、例えば、ＣＶＤにより形成される、酸化シリコン膜、窒化シリコン膜、あるいは酸窒化シリコン膜、またはこれらの積層膜によって構成される。 The barrier layer 3 is a layer that prevents moisture and impurities from reaching the TFT layer 4 or the light emitting element layer 5 when the display panel 1 is used. The barrier layer 3 is composed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked film thereof formed by CVD.
　ＴＦＴ層４は、半導体膜１５、無機絶縁膜１６（無機層）、ゲート電極Ｇ、無機絶縁膜１８、容量電極Ｃ、無機絶縁膜２０、ソース電極Ｓ、ドレイン電極Ｄ、および平坦化膜２１を有する。無機絶縁膜１６は、半導体膜１５の上層に設けられる。ゲート電極Ｇは、無機絶縁膜１６の上層に設けられる。無機絶縁膜１８は、ゲート電極Ｇの上層に設けられる。容量電極Ｃは、無機絶縁膜１８の上層に設けられる。無機絶縁膜２０は、容量電極Ｃの上層に設けられる。ソース電極Ｓおよびドレイン電極Ｄは、無機絶縁膜２０の上層に設けられる。平坦化膜２１は、ソース電極Ｓおよびドレイン電極Ｄの上層に設けられる。 The TFT layer 4 includes a semiconductor film 15, an inorganic insulating film 16 (inorganic layer), a gate electrode G, an inorganic insulating film 18, a capacitor electrode C, an inorganic insulating film 20, a source electrode S, a drain electrode D, and a planarizing film 21. Have. The inorganic insulating film 16 is provided on the upper layer of the semiconductor film 15. The gate electrode G is provided in the upper layer of the inorganic insulating film 16. The inorganic insulating film 18 is provided on the upper layer of the gate electrode G. The capacitive electrode C is provided in the upper layer of the inorganic insulating film 18. The inorganic insulating film 20 is provided in the upper layer of the capacitive electrode C. The source electrode S and the drain electrode D are provided in the upper layer of the inorganic insulating film 20. The planarization film 21 is provided on the upper layer of the source electrode S and the drain electrode D.
　ＴＦＴ層４において、半導体膜１５、無機絶縁膜１６（ゲート絶縁膜）、ゲート電極Ｇ、ソース電極Ｓ、およびドレイン電極Ｄを含むように、薄膜トランジスタＴｒ（発光制御トランジスタ）が構成される。薄膜トランジスタＴｒは、発光素子ＰＸを駆動する。ソース電極Ｓは、半導体膜１５のソース領域に接続される。ドレイン電極Ｄは、半導体膜１５のドレイン領域に接続される。半導体膜１５は、例えば低温ポリシリコン（ＬＴＰＳ）あるいは酸化物半導体によって構成される。図３では、半導体膜１５をチャネルとする薄膜トランジスタＴｒが、トップゲート構造で示されている。 In the TFT layer 4, a thin film transistor Tr (light emission control transistor) is configured to include the semiconductor film 15, the inorganic insulating film 16 (gate insulating film), the gate electrode G, the source electrode S, and the drain electrode D. The thin film transistor Tr drives the light emitting element PX. The source electrode S is connected to the source region of the semiconductor film 15. The drain electrode D is connected to the drain region of the semiconductor film 15. The semiconductor film 15 is made of, for example, low temperature polysilicon (LTPS) or an oxide semiconductor. In FIG. 3, the thin film transistor Tr having the semiconductor film 15 as a channel is shown in a top gate structure.
　無機絶縁膜１６・１８・２０は、例えば、ＣＶＤ法によって形成された、酸化シリコン（ＳｉＯｘ）膜あるいは窒化シリコン（ＳｉＮｘ）膜またはこれらの積層膜によって構成される。平坦化膜２１は、例えば、ポリイミドまたはアクリルなどの塗布可能な感光性有機材料によって構成される。 The inorganic insulating films 16, 18, and 20 are formed of, for example, a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a laminated film thereof formed by a CVD method. The planarizing film 21 is made of a photosensitive organic material that can be applied, such as polyimide or acrylic.
　ゲート電極Ｇ、ソース電極Ｓ、ドレイン電極Ｄ、および端子は、例えば、アルミニウム（Ａｌ）、タングステン（Ｗ）、モリブデン（Ｍｏ）、タンタル（Ｔａ）、クロム（Ｃｒ）、チタン（Ｔｉ）、銅（Ｃｕ）の少なくとも１つを含む金属の単層膜あるいは積層膜によって構成される。 The gate electrode G, the source electrode S, the drain electrode D, and the terminal are, for example, aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper ( It is comprised by the metal single layer film or laminated film containing at least 1 of Cu).
　発光素子層５は、例えば、有機発光ダイオード（ＯＬＥＤ）層である。発光素子層５は、アノード電極２２（第１電極）、平坦化膜２３（エッジカバー）、機能層２４、およびカソード電極２５（第２電極）を有する。アノード電極２２は、平坦化膜２１の上層に配置される。平坦化膜２３は、平坦化膜２１の上層に配置される。機能層２４は、アノード電極２２の上層または平坦化膜２３の上層に配置される。カソード電極２５は、機能層２４の上層に配置される。表示パネル１において、アノード電極２２とカソード電極２５とは互いに逆の位置に配置され得る。 The light emitting element layer 5 is, for example, an organic light emitting diode (OLED) layer. The light emitting element layer 5 includes an anode electrode 22 (first electrode), a planarization film 23 (edge cover), a functional layer 24, and a cathode electrode 25 (second electrode). The anode electrode 22 is disposed in the upper layer of the planarizing film 21. The planarizing film 23 is disposed on the planarizing film 21. The functional layer 24 is disposed on the anode electrode 22 or on the planarization film 23. The cathode electrode 25 is disposed on the upper layer of the functional layer 24. In the display panel 1, the anode electrode 22 and the cathode electrode 25 can be disposed at positions opposite to each other.
　発光素子層５は、複数の発光素子ＰＸを有する。複数の発光素子ＰＸは、平坦化膜２１の上層に設けられる。各発光素子ＰＸは、例えば、有機発光ダイオードである。各発光素子ＰＸは、樹脂層１２側から順に、アノード電極２２、平坦化膜２３、機能層２４、およびカソード電極２５を有する。各発光素子ＰＸにおいて、平坦化膜２３は、アノード電極２２を露出する開口を有しており、かつ、アノード電極２２の端部を覆っている。アノード電極２２は、発光素子ＰＸごとに設けられる。カソード電極２５は、複数の発光素子ＰＸに共通して設けられる。図２に示すように、カソード電極２５は、開口部ＤＢに沿って端部が切り欠かれた開口（陰極開口）を有する。図３に示すように、平面視で、カソード電極２５の開口内において、平坦化膜２１および２３が、カソード電極２５の開口に沿ってカソード電極２５を囲むスリットＳ１を有する。 The light emitting element layer 5 has a plurality of light emitting elements PX. The plurality of light emitting elements PX are provided in the upper layer of the planarizing film 21. Each light emitting element PX is, for example, an organic light emitting diode. Each light emitting element PX includes an anode electrode 22, a planarizing film 23, a functional layer 24, and a cathode electrode 25 in this order from the resin layer 12 side. In each light emitting element PX, the planarization film 23 has an opening exposing the anode electrode 22 and covers the end of the anode electrode 22. The anode electrode 22 is provided for each light emitting element PX. The cathode electrode 25 is provided in common for the plurality of light emitting elements PX. As shown in FIG. 2, the cathode electrode 25 has an opening (cathode opening) whose end is cut out along the opening DB. As shown in FIG. 3, the planarization films 21 and 23 have a slit S <b> 1 surrounding the cathode electrode 25 along the opening of the cathode electrode 25 in the opening of the cathode electrode 25 in plan view.
　アノード電極２２は、例えばＩＴＯ（Indium Tin Oxide）とＡｇを含む合金との積層によって構成され、かつ、光反射性を有する。カソード電極２５は、例えばＩＴＯまたはＩＺＯ（Indium Zinc Oxide）などの透光性の導電材によって構成される。 The anode electrode 22 is composed of, for example, a laminate of ITO (Indium Tin Oxide) and an alloy containing Ag, and has light reflectivity. The cathode electrode 25 is made of a light-transmitting conductive material such as ITO or IZO (Indium Zinc Oxide).
　表示パネル１は、複数の画素を有する。複数の画素は、複数の表示画素ＳＰＡおよび複数の非表示画素ＳＰＢを含む。複数の表示画素ＳＰは、表示領域ＤＡに配置される。各表示画素ＳＰＡは、いずれかの発光素子ＰＸを有し、かつ表示を行う画素である。各非表示画素ＳＰＢは、開口部ＤＢにおける切り欠き部ＤＣと複数の表示画素ＳＰＡとの間に配置され、かつ、表示を行わない画素である。表示パネル１において、表示画素ＳＰＡには、対応する薄膜トランジスタＴｒが形成され、非表示画素ＳＰＢには、対応する薄膜トランジスタＴｒが設けられない。 The display panel 1 has a plurality of pixels. The plurality of pixels include a plurality of display pixels SPA and a plurality of non-display pixels SPB. The plurality of display pixels SP are arranged in the display area DA. Each display pixel SPA is a pixel that has one of the light emitting elements PX and performs display. Each non-display pixel SPB is a pixel that is disposed between the cutout portion DC and the plurality of display pixels SPA in the opening DB and does not perform display. In the display panel 1, the corresponding thin film transistor Tr is formed in the display pixel SPA, and the corresponding thin film transistor Tr is not provided in the non-display pixel SPB.
　機能層２４は、複数の島状層２６および１つの共通層２７を有する。複数の島状層２６は、少なくとも発光層を含み、かつ、複数の表示画素ＳＰＡおよび複数の非表示画素ＳＰＢに、画素ごとに島状に設けられる。共通層２７は、発光層以外の機能層からなり、複数の表示画素ＳＰＡに共通に設けられる。共通層２７は、いずれの非表示画素ＳＰＡに対しても設けられない。発光素子層５が有機発光ダイオード層である場合、表示画素ＳＰＡにおいて、平坦化膜２３の底面（アノード電極２２が露出した部分）よりも上層に、例えば、正孔注入層、正孔輸送層、島状層２６、電子輸送層、電子注入層が積層される。島状層２６以外の正孔注入層、正孔輸送層、電子輸送層、および電子注入層のうち少なくともいずれかが、共通層２７として構成される。 The functional layer 24 has a plurality of island layers 26 and one common layer 27. The plurality of island layers 26 include at least a light emitting layer, and are provided in an island shape for each pixel in the plurality of display pixels SPA and the plurality of non-display pixels SPB. The common layer 27 includes functional layers other than the light emitting layer, and is provided in common to the plurality of display pixels SPA. The common layer 27 is not provided for any non-display pixel SPA. When the light emitting element layer 5 is an organic light emitting diode layer, in the display pixel SPA, for example, a hole injection layer, a hole transport layer, an upper layer than the bottom surface of the planarization film 23 (a portion where the anode electrode 22 is exposed), An island layer 26, an electron transport layer, and an electron injection layer are stacked. At least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer other than the island layer 26 is configured as the common layer 27.
　発光素子層５が有機発光ダイオード層である場合、アノード電極２２およびカソード電極２５間の駆動電流によって正孔と電子が島状層２６内で再結合する。これによって生じたエキシトンが基底状態に落ちることによって、島状層２６から光が放出される。カソード電極２５が透光性であり、アノード電極２２が光反射性であるため、島状層２６から放出された光は上方に向かい、トップエミッションとなる。 When the light emitting element layer 5 is an organic light emitting diode layer, holes and electrons are recombined in the island layer 26 by the drive current between the anode electrode 22 and the cathode electrode 25. The excitons generated thereby fall to the ground state, and light is emitted from the island layer 26. Since the cathode electrode 25 is translucent and the anode electrode 22 is light-reflective, the light emitted from the island layer 26 is directed upward and becomes top emission.
　発光素子層５は、有機発光ダイオードを有する構成に限られず、無機発光ダイオードまたは量子ドット発光ダイオードを有する構成でもよい。 The light emitting element layer 5 is not limited to a configuration having an organic light emitting diode, but may be a configuration having an inorganic light emitting diode or a quantum dot light emitting diode.
　表示パネル１を製造する際、複数の島状層２６を形成するためのファインメタルマスクが使用される。ファインメタルマスクにおいて、表示領域ＤＡのみならず、開口部ＤＢと切り欠き部ＤＣの形成予定領域とにも島状層２６が蒸着されるように、同一のマスク開口がパターン形成されている。ファインメタルマスクにおいて、各島状層２６に対応するマスク開口は、いずれも同一の大きさかつ同一の形状を有する。これにより、ファインメタルマスクに歪みが生じることがないため、マスク開口のパターン精度が低下せず、マスク開口を通過した蒸着粒子が、本来蒸着される位置に正確に蒸着される。したがって、得られる表示パネル１の表示品位の低下を防止することができる。 When the display panel 1 is manufactured, a fine metal mask for forming a plurality of island layers 26 is used. In the fine metal mask, the same mask opening is patterned so that the island layer 26 is deposited not only in the display area DA but also in the area where the opening DB and the notch DC are to be formed. In the fine metal mask, the mask openings corresponding to the island layers 26 have the same size and the same shape. Thereby, since a distortion does not arise in a fine metal mask, the pattern precision of a mask opening does not fall, but the vapor deposition particle which passed the mask opening is vapor-deposited correctly in the position originally vapor-deposited. Accordingly, it is possible to prevent the display quality of the obtained display panel 1 from being deteriorated.
　表示パネル１を製造する際、共通層２７を形成するためのコモンメタルマスクが使用される。コモンメタルマスクにおいて、表示領域ＤＡにおける複数の表示画素ＳＰＡの形成箇所にのみ共通層２７が蒸着されるように、マスク開口がパターン形成されている。これにより、共通層２７は、開口部ＤＢにおける非表示画素ＳＰＢの形成箇所、および切り欠き部ＤＣの形成予定領域には、いずれも蒸着されない。 When the display panel 1 is manufactured, a common metal mask for forming the common layer 27 is used. In the common metal mask, the mask opening is patterned so that the common layer 27 is deposited only at the positions where the plurality of display pixels SPA are formed in the display area DA. As a result, the common layer 27 is not vapor-deposited at the portion where the non-display pixel SPB is formed in the opening DB and the region where the cutout portion DC is to be formed.
　非表示画素ＳＰＢにおける島状層２６は、表示画素ＳＰＡにおける島状層２６と同一の形状かつ同一の大きさを有する。ここでいう「同一の形状かつ同一の大きさ」とは、島状層２６の蒸着材料を同一の形状かつ同一の大きさのマスクパターンを有するマスクを用いて蒸着した場合に、同一の形状かつ同一の大きさの島状層２６が結果的に形成されることを意味する。したがって、表示パネル１において、表示画素ＳＰＡにおける島状層２６と非表示画素ＳＰＢにおける島状層２６とは、必ずしも完全に同一の形状かつ同一の大きさである必要はない。 The island layer 26 in the non-display pixel SPB has the same shape and the same size as the island layer 26 in the display pixel SPA. Here, “the same shape and the same size” means that when the evaporation material of the island-like layer 26 is deposited using a mask having the same shape and the same size mask pattern, the same shape and This means that island layers 26 of the same size are formed as a result. Therefore, in the display panel 1, the island layer 26 in the display pixel SPA and the island layer 26 in the non-display pixel SPB do not necessarily have the same shape and the same size.
　島状層２６の大きさとは、島状層２６の幅を意味する。島状層２６の幅とは、表示パネル１の表示面に直交する方向から見た、島状層２６の基板に水平な方向の幅を意味する。より詳細には、島状層２６の大きさ（幅）とは、表示画素ＳＰＡを構成する島状層２６における最大の幅（図２では縦方向の幅）を意味する。 The size of the island layer 26 means the width of the island layer 26. The width of the island layer 26 means a width in a direction horizontal to the substrate of the island layer 26 as viewed from a direction orthogonal to the display surface of the display panel 1. More specifically, the size (width) of the island layer 26 means the maximum width (the vertical width in FIG. 2) in the island layer 26 constituting the display pixel SPA.
　非表示画素ＳＰＢにおける島状層２６の全体が、平坦化膜２３と重畳する。言い換えると、非表示画素ＳＰＢにおいて、島状層２６の下層に設けられる平坦化膜２３は、開口を有していない。 The entire island layer 26 in the non-display pixel SPB overlaps with the planarizing film 23. In other words, in the non-display pixel SPB, the planarization film 23 provided below the island layer 26 does not have an opening.
　封止層６は、透光性であり、無機封止膜２８、有機封止膜２９、および無機封止膜３０を含む。無機封止膜２８は、カソード電極２５を覆うように、カソード電極２５の上層に設けられる。有機封止膜２９は、無機封止膜２８の上層に設けられる。無機封止膜３０は、有機封止膜２９を覆うように、無機封止膜２８の上層に設けられる。言い換えると、無機封止膜３０は、有機封止膜２９を封止する。 The sealing layer 6 is translucent and includes an inorganic sealing film 28, an organic sealing film 29, and an inorganic sealing film 30. The inorganic sealing film 28 is provided in the upper layer of the cathode electrode 25 so as to cover the cathode electrode 25. The organic sealing film 29 is provided in the upper layer of the inorganic sealing film 28. The inorganic sealing film 30 is provided in the upper layer of the inorganic sealing film 28 so as to cover the organic sealing film 29. In other words, the inorganic sealing film 30 seals the organic sealing film 29.
　無機封止膜２８・３０は、例えば、マスクを用いたＣＶＤにより形成される、酸化シリコン膜、窒化シリコン膜、あるいは酸窒化シリコン膜、またはこれらの積層膜によって構成される。有機封止膜２９は、例えば、無機封止膜２８・３０よりも厚い、透光性有機膜であり、ポリイミド、アクリル等の塗布可能な感光性有機材料によって構成される。例えば、このような有機材料を含むインクを無機封止膜３０上にインクジェット塗布した後、ＵＶ照射により硬化させる。封止層６は、発光素子層５を覆うことによって、水および酸素などが異物が発光素子層５に浸透することを防ぐ。 The inorganic sealing films 28 and 30 are made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminated film thereof formed by CVD using a mask. The organic sealing film 29 is, for example, a light-transmitting organic film thicker than the inorganic sealing films 28 and 30, and is made of a photosensitive organic material that can be applied such as polyimide or acrylic. For example, an ink containing such an organic material is applied onto the inorganic sealing film 30 by inkjet and then cured by UV irradiation. The sealing layer 6 covers the light emitting element layer 5 to prevent water, oxygen, and the like from entering the light emitting element layer 5.
　（枠状バンク６１および６２）
　表示パネル１は、枠状バンク６１および６２を備えている。枠状バンク６１および６２は、いずれも、表示領域ＤＡおよび開口部ＤＢに配置される。枠状バンク６１（第１枠状バンク）は、有機封止膜２９の縁を囲む。枠状バンク６２（第２枠状バンク）は、枠状バンク６１と離間しかつ枠状バンク６１の周囲を囲む。 (Frame banks 61 and 62)
The display panel 1 includes frame banks 61 and 62. Both the frame banks 61 and 62 are arranged in the display area DA and the opening DB. The frame bank 61 (first frame bank) surrounds the edge of the organic sealing film 29. The frame bank 62 (second frame bank) is separated from the frame bank 61 and surrounds the frame bank 61.
　枠状バンク６１は、平坦化膜２３を備えている。枠状バンク６１を構成する平坦化膜２３の上層に、島状層２６が形成される。枠状バンク６１は、無機封止膜２８・３０によって覆われている。 The frame bank 61 includes a planarizing film 23. An island layer 26 is formed on the planarizing film 23 that constitutes the frame bank 61. The frame bank 61 is covered with the inorganic sealing films 28 and 30.
　枠状バンク６２は、平坦化膜２１および平坦化膜２３を備えている。枠状バンク６２において、平坦化膜２１の上層に平坦化膜２３が設けられる。枠状バンク６１を構成する平坦化膜２３の上層に、島状層２６が形成される。枠状バンク６１は、無機封止膜２８・３０によって覆われている。 The frame-like bank 62 includes the planarizing film 21 and the planarizing film 23. In the frame bank 62, the planarizing film 23 is provided on the planarizing film 21. An island layer 26 is formed on the planarizing film 23 that constitutes the frame bank 61. The frame bank 61 is covered with the inorganic sealing films 28 and 30.
　表示パネル１は、ゲート配線ＧＬと、カソード電極２５に接続される接続配線７１（導電層）を備えている。ゲート配線ＧＬは、表示領域ＤＡに設けられている。接続配線７１は、表示領域ＤＡにおいて、枠状バンク６１の一部に沿って設けられている。表示領域ＤＡにおけるカソード電極２５に重畳する箇所に、図示しないコンタクトホールが形成されている。接続配線７１は、このコンタクトホールを通じてカソード電極２５に電気的に接続されている。 The display panel 1 includes a gate wiring GL and a connection wiring 71 (conductive layer) connected to the cathode electrode 25. The gate line GL is provided in the display area DA. The connection wiring 71 is provided along a part of the frame bank 61 in the display area DA. A contact hole (not shown) is formed at a position overlapping the cathode electrode 25 in the display area DA. The connection wiring 71 is electrically connected to the cathode electrode 25 through this contact hole.
　開口部ＤＢにおいて、無機絶縁膜１６・１８・２０は、バリア層３を露出させる開口を有する。開口部ＤＢにおいて、この開口の端部を覆うように、開口封止膜６３が設けられる。開口封止膜６３は、平坦化層２１および平坦化層２３を備えている。開口封止膜６３において、平坦化層２３は、平坦化層２１の上層に設けられる。開口封止膜６３において、少なくとも１つの島状層２６が平坦化層２３の上層に設けられる。表示パネル１において、少なくとも１つの島状層２６の全体が、開口封止膜６３と重畳している。このことは、表示パネル１の製造時に、島状層２６の材料が、表示領域ＤＡのみならず開口部ＤＢにおける開口封止膜６３の上層にも蒸着されることを、意味する。 In the opening DB, the inorganic insulating films 16, 18, and 20 have openings that expose the barrier layer 3. In the opening DB, an opening sealing film 63 is provided so as to cover the end of the opening. The opening sealing film 63 includes the planarization layer 21 and the planarization layer 23. In the opening sealing film 63, the planarization layer 23 is provided on the planarization layer 21. In the opening sealing film 63, at least one island-like layer 26 is provided on the planarization layer 23. In the display panel 1, the entire at least one island-like layer 26 overlaps with the opening sealing film 63. This means that when the display panel 1 is manufactured, the material of the island layer 26 is deposited not only on the display area DA but also on the upper layer of the opening sealing film 63 in the opening DB.
　開口部ＤＢにおいて、無機封止膜２８・３０は、無機絶縁膜２０を露出させる開口を有する。言い換えれば、開口部ＤＢにおいて、無機封止膜２８・３０の端部は、枠状バンク６２と開口封止膜６３との間にある。 In the opening DB, the inorganic sealing films 28 and 30 have openings through which the inorganic insulating film 20 is exposed. In other words, in the opening DB, the end portions of the inorganic sealing films 28 and 30 are between the frame-shaped bank 62 and the opening sealing film 63.
　開口部ＤＢにおいて、枠状バンク６２と開口封止膜６３との間に、島状層２６が設けられる。枠状バンク６２における切り欠き部ＤＣ側の端部と、開口封止膜６３における表示画素ＳＰＡ側の端部とは、１つの島状層２６の大きさよりも長く離れている。言い換えれば、枠状バンク６２における切り欠き部ＤＣ側の端部と、開口封止膜６３における表示画素ＳＰＡ側の端部との間の距離８１は、１つの島状層２６の大きさよりも大きい。 In the opening DB, the island-like layer 26 is provided between the frame bank 62 and the opening sealing film 63. The end on the notch portion DC side in the frame bank 62 and the end on the display pixel SPA side in the opening sealing film 63 are longer than the size of one island layer 26. In other words, the distance 81 between the end portion on the cutout portion DC side in the frame-shaped bank 62 and the end portion on the display pixel SPA side in the opening sealing film 63 is larger than the size of one island layer 26. .
　表示パネル１において、有機封止膜２９は、枠状バンク６１によって十分にせき止められることなく、開口部ＤＢにおける枠状バンク６２の近辺にまであふれ出ることがある。このとき、無機封止膜３０によって有機封止膜２９が十分に封止されなければ、有機封止膜２９が枠状バンク６２に直接接触する恐れがある。しかし、上述したように、枠状バンク６２における切り欠き部ＤＣ側の端部と、開口封止膜６３における表示画素ＳＰＡ側の端部とは、１つの島状層２６の大きさよりも長く離れている。これにより、島状層２６が枠状バンク６２と開口封止膜６３との間をまたがって、水分の移動経路として機能することがない。したがって、表示領域ＤＡにおける発光素子ＰＸ側に水分が浸透することを防ぐことができる。 In the display panel 1, the organic sealing film 29 may overflow to the vicinity of the frame bank 62 in the opening DB without being sufficiently blocked by the frame bank 61. At this time, if the organic sealing film 29 is not sufficiently sealed by the inorganic sealing film 30, the organic sealing film 29 may be in direct contact with the frame bank 62. However, as described above, the end on the notch portion DC side in the frame-shaped bank 62 and the end on the display pixel SPA side in the opening sealing film 63 are separated longer than the size of one island layer 26. ing. Thus, the island layer 26 does not function as a moisture transfer path across the frame-shaped bank 62 and the opening sealing film 63. Therefore, it is possible to prevent moisture from penetrating into the light emitting element PX side in the display area DA.
　表示パネル１において、枠状バンク６１における切り欠き部ＤＣ側の端部と、枠状バンク６２における表示画素ＳＰＡ側の端部とが、１つの島状層２６の大きさよりも長く離れている。言い換えれば、枠状バンク６１における切り欠き部ＤＣ側の端部と、枠状バンク６２における表示画素ＳＰＡ側の端部との距離８２は、１つの島状層２６の大きさよりも大きい。これにより、島状層２６が枠状バンク６１と枠状バンク６２とにまたがって形成されることがないので、枠状バンク６１と枠状バンク６２との間に島状層２６が形成された場合に、この島状層２６が水分の通過経路として機能することがない。したがって、表示領域ＤＡにおける発光素子ＰＸ側に水分が浸透することを防ぐことができる。 In the display panel 1, the end of the frame bank 61 on the notch portion DC side and the end of the frame bank 62 on the display pixel SPA side are longer than the size of one island layer 26. In other words, the distance 82 between the end on the notch portion DC side in the frame-shaped bank 61 and the end on the display pixel SPA side in the frame-shaped bank 62 is larger than the size of one island layer 26. As a result, the island layer 26 is not formed across the frame bank 61 and the frame bank 62, so the island layer 26 is formed between the frame bank 61 and the frame bank 62. In this case, the island layer 26 does not function as a moisture passage path. Therefore, it is possible to prevent moisture from penetrating into the light emitting element PX side in the display area DA.
　〔実施形態２〕
　図４は、実施形態２に係る表示パネル１の断面構成例を示す断面図である。 [Embodiment 2]
FIG. 4 is a cross-sectional view illustrating a cross-sectional configuration example of the display panel 1 according to the second embodiment.
　実施形態２に係る表示パネル１の開口部ＤＢにおいて、無機封止膜２８・３０は、島状層２６の一部を露出させる開口を有する。表示パネル１において、枠状バンク６２における切り欠き部ＤＣ側の端部と、無機封止膜２８・３０の端部とが、１つの島状層２６の大きさよりも長く離れている。言い換えれば、枠状バンク６２における切り欠き部ＤＣ側の端部と、無機封止膜２８・３０の端部との間の距離８３は、１つの島状層２６の大きさよりも大きい。これにより、露出した島状層２６が枠状バンク６２と重畳することがない。したがって、有機封止膜２９が枠状バンク６２に直接接触した場合に、露出した島状層２６が枠状バンク６２を介して有機封止膜２９に接触することによって、島状層２６が水分の通過経路となり、水分が表示領域ＤＡ側に浸透することを、防止できる。 In the opening DB of the display panel 1 according to the second embodiment, the inorganic sealing films 28 and 30 have an opening for exposing a part of the island layer 26. In the display panel 1, the end on the notch portion DC side in the frame-shaped bank 62 and the ends of the inorganic sealing films 28 and 30 are separated from each other by a length longer than the size of one island layer 26. In other words, the distance 83 between the end of the frame-shaped bank 62 on the notch portion DC side and the end of the inorganic sealing films 28 and 30 is larger than the size of one island-like layer 26. As a result, the exposed island layer 26 does not overlap the frame bank 62. Therefore, when the organic sealing film 29 is in direct contact with the frame-shaped bank 62, the exposed island-shaped layer 26 is in contact with the organic sealing film 29 through the frame-shaped bank 62, so that the island-shaped layer 26 is moisture. It is possible to prevent moisture from penetrating the display area DA.
　〔実施形態３〕
　図５は、実施形態３に係る表示パネル１の詳細な構成例を示す平面図である。図６は、実施形態３に係る表示パネル１の断面構成例を示す断面図である。図５のＡ－Ａ’箇所の断面を図６に示す。 [Embodiment 3]
FIG. 5 is a plan view illustrating a detailed configuration example of the display panel 1 according to the third embodiment. FIG. 6 is a cross-sectional view illustrating a cross-sectional configuration example of the display panel 1 according to the third embodiment. FIG. 6 shows a cross section taken along the line AA ′ in FIG.
　実施形態３に係る表示パネル１では、接続配線７１は、切り欠き部ＤＣと複数の表示画素ＳＰＡとの間において、非表示画素ＳＰＢと重畳しかつ切り欠き部ＤＣを囲むように形成される。接続配線７１は、非表示画素ＳＰＢに対応するアノード電極２２によって形成される。言い換えれば、接続配線７１は、表示画素ＳＰＡに対応するアノード電極２２と同一層に設けられる。表示パネル１において、接続配線７１を介して、カソード電極２５とＴＦＴ層のソース電極Ｓ（配線）とが、電気的に導通する。低電圧電源から出力された低電圧が、ソース電極Ｓおよび接続配線７１を通じてカソード電極２５に入力される。 In the display panel 1 according to Embodiment 3, the connection wiring 71 is formed between the notch portion DC and the plurality of display pixels SPA so as to overlap the non-display pixel SPB and surround the notch portion DC. The connection wiring 71 is formed by the anode electrode 22 corresponding to the non-display pixel SPB. In other words, the connection wiring 71 is provided in the same layer as the anode electrode 22 corresponding to the display pixel SPA. In the display panel 1, the cathode electrode 25 and the source electrode S (wiring) of the TFT layer are electrically connected via the connection wiring 71. The low voltage output from the low voltage power supply is input to the cathode electrode 25 through the source electrode S and the connection wiring 71.
　図６に示すように、開口部ＤＢにおいて接続配線７１とカソード電極２５とが接触して電気的に接続する範囲８４は、１つの島状層２６の大きさよりも大きい。これにより、接続配線７１とカソード電極２５が島状層２６と重畳しない箇所が範囲８４内に必ず含まれるので、接続配線７１とカソード電極２５とのコンタクト抵抗を低くすることができる。 As shown in FIG. 6, a range 84 in which the connection wiring 71 and the cathode electrode 25 are in contact with each other and electrically connected in the opening DB is larger than the size of one island layer 26. Thereby, a portion where the connection wiring 71 and the cathode electrode 25 do not overlap with the island layer 26 is always included in the range 84, so that the contact resistance between the connection wiring 71 and the cathode electrode 25 can be lowered.
　〔実施形態４〕
　図７は、実施形態４に係る表示パネル１の詳細な構成例を示す平面図である。図８は、実施形態４に係る表示パネル１の断面構成例を示す断面図である。図７のＡ－Ａ’箇所の断面を図８に示す。 [Embodiment 4]
FIG. 7 is a plan view illustrating a detailed configuration example of the display panel 1 according to the fourth embodiment. FIG. 8 is a cross-sectional view illustrating a cross-sectional configuration example of the display panel 1 according to the fourth embodiment. FIG. 8 shows a cross section taken along the line AA ′ in FIG.
　実施形態４に係る表示パネル１では、開口部ＤＢにおいて、切り欠き部ＤＣに沿ってバリア層３および無機絶縁膜１６・１８・２０がスリットＳ２を有している。スリットＳ２は、開口部ＤＢにおいて、枠状バンク６２の直下に形成されている。スリットＳ２には、枠状バンク６２を構成する平坦化膜２１が埋め込まれている。言い換えれば、スリットＳ２に埋め込まれる平坦化膜２１は、枠状バンク６２を構成する平坦化膜２１と同一である。枠状バンク６２を構成する平坦化膜２１は、切り欠き部ＤＣに沿ってスリットＳ２に埋め込まれる部分と、枠状バンク６１に沿って無機絶縁膜２０の上層に形成される部分とに、分岐されている。 In the display panel 1 according to the fourth embodiment, in the opening DB, the barrier layer 3 and the inorganic insulating films 16, 18, and 20 have the slit S 2 along the notch DC. The slit S2 is formed immediately below the frame-shaped bank 62 in the opening DB. In the slit S2, the planarizing film 21 constituting the frame-shaped bank 62 is embedded. In other words, the planarizing film 21 embedded in the slit S <b> 2 is the same as the planarizing film 21 constituting the frame bank 62. The planarizing film 21 constituting the frame bank 62 branches into a portion embedded in the slit S2 along the notch DC and a portion formed in the upper layer of the inorganic insulating film 20 along the frame bank 61. Has been.
　本実施形態では、開口部ＤＢにおいて無機絶縁膜１６・１８・２０がスリットＳ２を有することによって、開口部ＤＢにクラックが生じることを防止することができる。 In this embodiment, since the inorganic insulating films 16, 18, and 20 have the slits S2 in the opening DB, it is possible to prevent the opening DB from being cracked.
　〔実施形態５〕
　図９は、実施形態５に係る表示パネル１の詳細な構成例を示す平面図である。図１０は、実施形態５に係る表示パネル１の断面構成例を示す断面図である。図９のＡ－Ａ’箇所の断面を図１０に示す。 [Embodiment 5]
FIG. 9 is a plan view illustrating a detailed configuration example of the display panel 1 according to the fifth embodiment. FIG. 10 is a cross-sectional view illustrating a cross-sectional configuration example of the display panel 1 according to the fifth embodiment. FIG. 10 shows a cross section taken along the line AA ′ in FIG.
　実施形態５に係る表示パネル１では、開口部ＤＢにおいて、切り欠き部ＤＣに沿ってバリア層３および無機絶縁膜１６・１８・２０が、スリットＳ２を有している。開口部ＤＢにおける枠状バンク６２よりも外側の箇所に、スリットＳ２に重畳しかつ切り欠き部ＤＣを囲むように、バンク６４が形成されている。バンク６４は、平坦化膜２１および平坦化膜２３を備えている。バンク６４を構成する平坦化膜２３の上層に、島状層２６が形成される。バンク６４は、無機封止膜２８・３０によって覆われている。 In the display panel 1 according to the fifth embodiment, in the opening DB, the barrier layer 3 and the inorganic insulating films 16, 18, and 20 have the slits S2 along the notch DC. A bank 64 is formed at a location outside the frame bank 62 in the opening DB so as to overlap the slit S2 and surround the notch DC. The bank 64 includes a planarizing film 21 and a planarizing film 23. An island layer 26 is formed on the planarizing film 23 constituting the bank 64. The bank 64 is covered with the inorganic sealing films 28 and 30.
　スリットＳ２には、平坦化膜２１ではなく平坦化膜２３が埋め込まれてもよい。この場合、平坦化膜２１を備えないバンク６４が、スリットＳ２に重畳して開口部ＤＢに形成される。 In the slit S2, not the planarizing film 21 but the planarizing film 23 may be embedded. In this case, the bank 64 that does not include the planarizing film 21 is formed in the opening DB so as to overlap the slit S2.
　本実施形態では、開口部ＤＢにおいて無機絶縁膜１６・１８・２０がスリットＳ２を有することによって、開口部ＤＢにクラックが生じることを防止することができる。 In this embodiment, since the inorganic insulating films 16, 18, and 20 have the slits S2 in the opening DB, it is possible to prevent the opening DB from being cracked.
　各実施形態に係る表示パネル１が備える電気光学素子（電流によって輝度や透過率が制御される電気光学素子）は特に限定されるものではない。各実施形態に係る表示装置としては、例えば、電気光学素子としてＯＬＥＤ（Organic Light Emitting Diode：有機発光ダイオード）を備えた有機ＥＬ（Electro Luminescence：エレクトロルミネッセンス）ディスプレイ、電気光学素子として無機発光ダイオードを備えた無機ＥＬディスプレイ、電気光学素子としてＱＬＥＤ（Quantum dot Light Emitting Diode：量子ドット発光ダイオード）を備えたＱＬＥＤディスプレイ等が挙げられる。 The electro-optical element (electro-optical element whose luminance and transmittance are controlled by current) included in the display panel 1 according to each embodiment is not particularly limited. The display device according to each embodiment includes, for example, an organic EL (Electro Luminescence) display including an OLED (Organic Light Emitting Diode) as an electro-optical element, and an inorganic light-emitting diode as an electro-optical element. Inorganic EL displays, and QLED displays equipped with QLEDs (Quantum dot emitting Light emitting diodes) as electro-optical elements are exemplified.
　〔まとめ〕
　態様１：樹脂層と、前記樹脂層の上層に設けられた無機層および前記無機層の上層に設けられた平坦化膜を有するＴＦＴ層と、前記平坦化膜の上層に設けられた複数の発光素子と、前記複数の発光素子を封止する封止層と、を備え、前記封止層が、有機封止膜と、前記有機封止膜を封止する無機封止膜と、を含み、前記有機封止膜の縁を囲む第１枠状バンクと、前記第１枠状バンクと離間しかつ前記第１枠状バンクの周囲を囲む第２枠状バンクと、複数の画素を有する表示パネルであって、パネル面を貫通するように、当該表示パネルの端部が切り欠けられた切り欠き部が形成される開口部を有し、前記開口部において、前記無機層は開口されており該開口の端部を覆うように開口封止膜が設けられ、前記複数の画素が、前記発光素子を有しかつ表示を行う複数の表示画素と、前記切り欠き部と前記複数の表示画素との間に設けられかつ表示を行わない複数の非表示画素と、を含み、前記発光素子は、前記樹脂層側から、第１電極と、前記第１電極を露出するように開口が設けられかつ前記第１電極の端部を覆うエッジカバーと、機能層と、及び前記複数の発光素子に共通して設けられる第２電極と、を有し、前記機能層は、少なくとも発光層を含み、前記複数の表示画素および前記複数の非表示画素に、画素ごとに島状に設けられた複数の島状層と、発光層以外の機能層からなり、前記複数の表示画素に共通に設けられた共通層と、を含み、前記非表示画素における島状層は、前記表示画素における島状層と同一の形状かつ同一の大きさであり、前記第２枠状バンクにおける前記切り欠き部側の端部と、前記開口封止膜における前記表示画素側の端部とが、１つの前記島状層の大きさよりも長く離れていることを特徴とする表示パネル。 [Summary]
Aspect 1: a TFT layer having a resin layer, an inorganic layer provided above the resin layer, and a planarizing film provided on the inorganic layer, and a plurality of light emission provided on the planarizing film An element and a sealing layer that seals the plurality of light emitting elements, and the sealing layer includes an organic sealing film and an inorganic sealing film that seals the organic sealing film, A first frame bank surrounding an edge of the organic sealing film, a second frame bank spaced from the first frame bank and surrounding the first frame bank, and a display panel having a plurality of pixels The display panel has an opening in which a notch is formed by notching an end of the display panel, and the inorganic layer is opened in the opening. An opening sealing film is provided so as to cover an end of the opening, and the plurality of pixels include the light emitting element. A plurality of display pixels that perform one display, and a plurality of non-display pixels that are provided between the notch portion and the plurality of display pixels and that do not perform display, and the light emitting element is on the resin layer side To the first electrode, an edge cover that exposes the first electrode and covers an end of the first electrode, a functional layer, and the light emitting element. A plurality of island-like layers provided in an island shape for each of the plurality of display pixels and the plurality of non-display pixels; The island layer in the non-display pixel has the same shape and the same as the island layer in the display pixel, and the common layer provided in common to the plurality of display pixels. In the second frame bank Ri and the end of the out portion side, the display panel and the display pixel side end of the opening sealing film, characterized in that apart longer than the size of one of said island layer.
　態様２：前記第１枠状バンクにおける前記切り欠き部側の端部と、前記第２枠状バンクにおける前記表示画素側の端部とが、１つの前記島状層の大きさよりも長く離れていることを特徴とする態様１の表示パネル。 Aspect 2: An end of the first frame bank on the notch portion side and an end of the second frame bank on the display pixel side are longer than the size of one island layer. A display panel according to aspect 1, wherein
　態様３：前記第２枠状バンクにおける前記切り欠き部の端部と、前記無機封止膜におけ前記切り欠き部側の端部とが、１つの前記島状層の大きさよりも長く離れていることを特徴とする態様１または２の表示パネル。 Aspect 3: The end of the notch in the second frame-shaped bank and the end of the inorganic sealing film on the side of the notch are longer than the size of one island-like layer. A display panel according to aspect 1 or 2, wherein
　態様４：前記記切り欠き部と前記複数の表示画素との間において、前記非表示画素と重畳しかつ前記切り欠き部を囲むように前記第１電極によって形成される導電層をさらに備えており、前記導電層を介して、前記第２電極と前記ＴＦＴ層の配線とが電気的に導通することを特徴とする態様１～３のいずれか１項の表示パネル。 Aspect 4: a conductive layer formed by the first electrode so as to overlap the non-display pixel and surround the cutout portion between the cutout portion and the plurality of display pixels. 4. The display panel according to any one of aspects 1 to 3, wherein the second electrode and the wiring of the TFT layer are electrically connected through the conductive layer.
　態様５：前記開口部において前記導電層と前記第２電極とが接触する範囲の幅は、１つの前記島状層の大きさよりも大きいことを特徴とする態様４の表示パネル。 Aspect 5: A display panel according to Aspect 4, wherein a width of a range in which the conductive layer and the second electrode are in contact with each other in the opening is larger than a size of one island layer.
　態様６：前記非表示画素における前記島状層の全体が、エッジカバーと重畳することを特徴とする態様１～５のいずれか１項の表示パネル。 Aspect 6: The display panel according to any one of Aspects 1 to 5, wherein the whole of the island layer in the non-display pixel overlaps with an edge cover.
　態様７：少なくとも１つの前記島状層の全体が、前記開口封止膜と重畳することを特徴とする態様１～６のいずれか１項の表示パネル。 Aspect 7: The display panel according to any one of Aspects 1 to 6, wherein at least one of the island-like layers entirely overlaps the opening sealing film.
　態様８：前記切り欠き部に沿って前記無機層がスリットを有しており、前記スリットに、前記平坦化膜が埋め込まれていることを特徴とする態様１～７のいずれか１項の表示パネル。 Aspect 8: The display according to any one of Aspects 1 to 7, wherein the inorganic layer has a slit along the notch, and the planarizing film is embedded in the slit. panel.
　態様９：前記スリットに埋め込まれる前記平坦化膜と、前記平坦化膜の上層に形成されるエッジカバーとを有しており、かつ前記切り欠き部を囲むように形成されるバンクをさらに備えていることを特徴とする態様８の表示パネル。 Aspect 9: The bank includes the planarizing film embedded in the slit, and an edge cover formed in an upper layer of the planarizing film, and further includes a bank formed so as to surround the notch. A display panel according to aspect 8, wherein
　態様１０：前記第２枠状バンクは、前記平坦化膜と、前記平坦化膜のの上層に形成されるエッジカバーとを有しており、前記スリットに埋め込まれる前記平坦化膜は、前記第２枠状バンクを構成する前記平坦化膜と同一であることを特徴とする態様９の表示パネル。 Aspect 10: The second frame-shaped bank has the planarizing film and an edge cover formed on an upper layer of the planarizing film, and the planarizing film embedded in the slit is the first The display panel according to aspect 9, wherein the display panel is the same as the planarizing film constituting the two-frame bank.
　態様１２：前記第２枠状バンクを構成する前記平坦化膜は、前記切り欠き部に沿う部分と、前記第１枠状バンクに沿う部分とに分岐されていることを特徴とする態様１１の表示パネル。 Aspect 12: The flattening film constituting the second frame-shaped bank is branched into a portion along the cutout portion and a portion along the first frame-shaped bank. Display panel.
　本発明は前述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能である。異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態も、本発明の技術的範囲に含まれる。各実施形態にそれぞれ開示された技術的手段を組み合わせることによって、新しい技術的特徴を形成することもできる。 The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. Embodiments obtained by appropriately combining technical means disclosed in different embodiments are also included in the technical scope of the present invention. A new technical feature can also be formed by combining the technical means disclosed in each embodiment.
　１　表示パネル
　３　バリア層
　４　ＴＦＴ層
　５　発光素子層
　６　封止層
　１０　基材
　１２　樹脂層
　１５　半導体膜
　１６，１８，２０　無機絶縁膜
　２１，２３　平坦化層
　２２　アノード電極
　２４　機能層
　２５　カソード電極
　２６　島状層
　２７　共通層
　２８，３０　無機封止膜
　２９　有機封止膜
　６１，６２　枠状バンク
　６３　開口封止膜
　６４　バンク
　７１　接続配線
　ＤＡ　表示領域
　ＤＢ　開口部
　ＤＣ　切り欠き部
　８１，８２，８３　距離
　８４　範囲
　Ｓ１，Ｓ２　スリット
　ＳＰＡ　表示画素
　ＳＰＢ　非表示画素
　Ｔｒ　薄膜トランジスタ DESCRIPTION OF SYMBOLS 1 Display panel 3 Barrier layer 4 TFT layer 5 Light emitting element layer 6 Sealing layer 10 Base material 12 Resin layer 15 Semiconductor film 16, 18, 20 Inorganic insulating film 21, 23 Planarization layer 22 Anode electrode 24 Functional layer 25 Cathode electrode 26 Island-like layer 27 Common layer 28, 30 Inorganic sealing film 29 Organic sealing film 61, 62 Frame-like bank 63 Opening sealing film 64 Bank 71 Connection wiring DA display area DB opening DC notch 81, 82, 83 Distance 84 Range S1, S2 Slit SPA Display pixel SPB Non-display pixel Tr Thin film transistor

Claims (11)

  1. 　樹脂層と、前記樹脂層の上層に設けられた無機層および前記無機層の上層に設けられた平坦化膜を有するＴＦＴ層と、前記平坦化膜の上層に設けられた複数の発光素子と、前記複数の発光素子を封止する封止層と、を備え、前記封止層が、有機封止膜と、前記有機封止膜を封止する無機封止膜と、を含み、前記有機封止膜の縁を囲む第１枠状バンクと、前記第１枠状バンクと離間しかつ前記第１枠状バンクの周囲を囲む第２枠状バンクと、複数の画素を有する表示パネルであって、
    　パネル面を貫通するように、当該表示パネルの端部が切り欠けられた切り欠き部が形成される開口部を有し、
    　前記開口部において、前記無機層は開口されており該開口の端部を覆うように開口封止膜が設けられ、
    　前記複数の画素が、
    　　前記発光素子を有しかつ表示を行う複数の表示画素と、
    　　前記切り欠き部と前記複数の表示画素との間に設けられかつ表示を行わない複数の非表示画素と、を含み、
    　前記発光素子は、前記樹脂層側から、第１電極と、前記第１電極を露出するように開口が設けられかつ前記第１電極の端部を覆うエッジカバーと、機能層と、及び前記複数の発光素子に共通して設けられる第２電極と、を有し、
    　前記機能層は、
    　　少なくとも発光層を含み、前記複数の表示画素および前記複数の非表示画素に、画素ごとに島状に設けられた複数の島状層と、
    　　発光層以外の機能層からなり、前記複数の表示画素に共通に設けられた共通層と、を含み、
    　前記非表示画素における島状層は、前記表示画素における島状層と同一の形状かつ同一の大きさであり、
    　前記第２枠状バンクにおける前記切り欠き部側の端部と、前記開口封止膜における前記表示画素側の端部とが、１つの前記島状層の大きさよりも長く離れていることを特徴とする表示パネル。     A resin layer, an inorganic layer provided on the upper layer of the resin layer, a TFT layer having a planarizing film provided on the upper layer of the inorganic layer, and a plurality of light emitting elements provided on the upper layer of the planarizing film; A sealing layer that seals the plurality of light emitting elements, and the sealing layer includes an organic sealing film and an inorganic sealing film that seals the organic sealing film. A display panel having a plurality of pixels, a first frame-shaped bank surrounding an edge of a stop film, a second frame-shaped bank spaced from the first frame-shaped bank and surrounding the first frame-shaped bank, and ,
    Having an opening in which a notch is formed by cutting off the end of the display panel so as to penetrate the panel surface;
    In the opening, the inorganic layer is opened, and an opening sealing film is provided so as to cover an end of the opening,
    The plurality of pixels are
    A plurality of display pixels having the light emitting element and performing display;
    A plurality of non-display pixels that are provided between the notch and the plurality of display pixels and do not perform display,
    The light emitting element includes, from the resin layer side, a first electrode, an edge cover provided to expose the first electrode and covering an end of the first electrode, a functional layer, and the plurality A second electrode provided in common to the light emitting element of
    The functional layer is
    A plurality of island-shaped layers each including at least a light-emitting layer and provided in an island shape for each of the plurality of display pixels and the plurality of non-display pixels;
    A functional layer other than the light emitting layer, and a common layer provided in common to the plurality of display pixels,
    The island-like layer in the non-display pixel has the same shape and the same size as the island-like layer in the display pixel,
    The end of the second frame-shaped bank on the side of the notch and the end of the opening sealing film on the side of the display pixel are longer than the size of one island layer. Display panel.
  2. 　前記第１枠状バンクにおける前記切り欠き部側の端部と、前記第２枠状バンクにおける前記表示画素側の端部とが、１つの前記島状層の大きさよりも長く離れていることを特徴とする請求項１に記載の表示パネル。 An end of the first frame bank on the notch portion side and an end of the second frame bank on the display pixel side are longer than the size of one island layer. The display panel according to claim 1, wherein the display panel is a display panel.
  3. 　前記第２枠状バンクにおける前記切り欠き部の端部と、前記無機封止膜におけ前記切り欠き部側の端部とが、１つの前記島状層の大きさよりも長く離れていることを特徴とする請求項１または２に記載の表示パネル。 The end of the notch in the second frame bank and the end on the notch side of the inorganic sealing film are longer than the size of one island layer. The display panel according to claim 1, wherein the display panel is a display panel.
  4. 　前記切り欠き部と前記複数の表示画素との間において、前記非表示画素と重畳しかつ前記切り欠き部を囲むように前記第１電極によって形成される導電層をさらに備えており、
    　前記導電層を介して、前記第２電極と前記ＴＦＴ層の配線とが電気的に導通することを特徴とする請求項１～３のいずれか１項に記載の表示パネル。     A conductive layer formed by the first electrode so as to overlap the non-display pixel and surround the notch portion between the notch portion and the plurality of display pixels;
    4. The display panel according to claim 1, wherein the second electrode and the wiring of the TFT layer are electrically connected through the conductive layer.
  5. 　前記開口部において前記導電層と前記第２電極とが接触する範囲の幅は、１つの前記島状層の大きさよりも大きいことを特徴とする請求項４に記載の表示パネル。 The display panel according to claim 4, wherein a width of a range in which the conductive layer and the second electrode are in contact with each other in the opening is larger than a size of one island layer.
  6. 　前記非表示画素における前記島状層の全体が、エッジカバーと重畳することを特徴とする請求項１～５のいずれか１項に記載の表示パネル。 6. The display panel according to claim 1, wherein the whole of the island layer in the non-display pixel overlaps with an edge cover.
  7. 　少なくとも１つの前記島状層の全体が、前記開口封止膜と重畳することを特徴とする請求項１～６のいずれか１項に記載の表示パネル。 7. The display panel according to claim 1, wherein at least one of the island layers overlaps with the opening sealing film.
  8. 　前記切り欠き部に沿って前記無機層がスリットを有しており、
    　前記スリットに、前記平坦化膜が埋め込まれていることを特徴とする請求項１～７のいずれか１項に記載の表示パネル。     The inorganic layer has a slit along the notch,
    The display panel according to claim 1, wherein the planarizing film is embedded in the slit.
  9. 　前記スリットに埋め込まれる前記平坦化膜と、前記平坦化膜の上層に形成されるエッジカバーとを有しており、かつ前記切り欠き部を囲むように形成されるバンクをさらに備えていることを特徴とする請求項８に記載の表示パネル。 It has the leveling film embedded in the slit, and an edge cover formed in an upper layer of the leveling film, and further includes a bank formed so as to surround the notch. The display panel according to claim 8, wherein the display panel is characterized.
  10. 　前記第２枠状バンクは、前記平坦化膜と、前記平坦化膜の上層に形成されるエッジカバーとを有しており、
    　前記スリットに埋め込まれる前記平坦化膜は、前記第２枠状バンクを構成する前記平坦化膜と同一であることを特徴とする請求項９に記載の表示パネル。     The second frame-shaped bank includes the planarization film and an edge cover formed in an upper layer of the planarization film,
    The display panel according to claim 9, wherein the planarizing film embedded in the slit is the same as the planarizing film constituting the second frame-shaped bank.
  11. 　前記第２枠状バンクを構成する前記平坦化膜は、前記切り欠き部に沿う部分と、前記第１枠状バンクに沿う部分とに分岐されていることを特徴とする請求項１０に記載の表示パネル。 11. The flattening film constituting the second frame-shaped bank is branched into a portion along the cutout portion and a portion along the first frame-shaped bank. Display panel.
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