WO2019156644A1

WO2019156644A1 - The method enabling the reduction of resource utilization

Info

Publication number: WO2019156644A1
Application number: PCT/TR2018/050052
Authority: WO
Inventors: Bilal UĞURLU
Original assignee: Aselsan Elektroni̇k Sanayi̇ Ve Ti̇caret Anoni̇m Şi̇rketi̇
Priority date: 2018-02-12
Filing date: 2018-02-12
Publication date: 2019-08-15

Abstract

The invention relates to a method that enables to conduct DDC and downsampling processes on hardware components such as FPGA etc. by consuming less DSP resources.

Description

THE METHOD ENABLING THE REDUCTION OF RESOURCE UTILIZATION Technical Field

The invention relates to a method that enables to conduct Digital Down Conversion (DDC) and downsampling processes on hardware components such as FPGA (Field Programmable Gate Array) etc. by consuming less Digital Signal Processing (DSP) resource.

State of the Art

Intermediate frequency signal which is sampled with Analog/Digital Converter (ADC) in digital receiver boards for radar or similar applications is then downconverted to baseband by means of DDC method. Generally,“oversampling” process is conducted by selecting sampling rate significantly higher than IF signal bandwidth and then downsampling method is used to remove surplus data. For many applications, DDC process is simplified by selecting IF (f/ή equal to one fourth of sampling frequency (f_s). The simplification described herein is achieved by multiplying I (in-phase) channel by the repeating 1 , 0, -1 , 0, ... array and Q (quadrature) channel by the repeating 0, -1 , 0, 1 , ... array instead of complicated cosine and sine values. Actually, it is not a multiplication operation but a set of simple operations in which data are used as is or negative of value or“0” value is used by removing the data.

According to current methods, as the number of utilized channels increases, the number of required DSP resources may remain insufficient for the multichannel receiver structures whose pre-digital signal processing steps are realized on hardware components such as FPGA. For this reason, it has been required to develop a method for reducing hardware resource utilization so as to meet rising needs.

In conclusion, the aforementioned disadvantages and the inadequacy of existing solutions necessitate an innovation in the relevant technical field.

Purpose of Invention

The invention has been developed with inspiration from the existing conditions, and is intended to solve the above-mentioned problems. Compared to the existing methods, the said invention enables that a part of downsampling (|2) process is being taken to very beginning phase by using the advantage of “0” values located in multiplication arrays in DDC process and so multiplication arrays are formed as 1 , -1 , 1 , ... and -1 , 1 , -1 , ... for cosine and -sine, respectively, and then low pass filters may operate at the desired or lower rates or they utilize less resource.

In conventional method, the signal sampled is firstly multiplied by 1 , 0, -1 , 0, ... (cosine) and 0, -1 , 0, 1 , ... (sine) arrays and then generated I (in-phase) and Q (quadrature) channel signals are passed through a suitable low pass filter and as a last step, downsampling process is carried out by removing the desired amount of data from both channels.

According to method described herein, downsampling process is conducted in two parts. The first part is the distribution of sampled data to I and Q channels alternatively which means that double-index data are fed to I channel and single-index data are fed to Q channel. Therefore, the quantity of data transferred to both channels falls by half. Distribution of data to channels in this way converts the required multiplication operation for DDC to the multiplication by only 1 , -1 , 1 , ... and -1 , 1 , -1 , ... arrays for I and Q channels, respectively.. Thanks to data entering into channels by distributing alternatively, a filter generated by the double-index coefficients is applied to I channel and a filter generated by single-index coefficients is applied to Q channel instead of applying same low pass filter to both channels as preferred in conventional method. It reduces total filter lengths in half thereby decreasing the consumption of resource. If the desired total amount of downsampling is already 2, the process is ended accordingly; but if it is higher than 2, remaining part can be performed with a new and suitable low pass filter and data removal block in standard form.

In line with the aforementioned explanations, this invention reduces the consumption of DSP resources utilized in hardware designs such as FPGA. Therefore, it may be possible to realize multichannel receiver structures such as currently used phased array antennas by utilizing less hardware resource (smaller FPGA, more channels in one FPGA etc.).

The invention relates to a method that enables to conduct digital down conversion and downsampling processes by utilizing less resource on hardware components in order to achieve above-mentioned purposes and it consists of following steps: - routing of double-index samples to in-phase channel and single-index samples to quadrature channel out of the samples transferred by switch,

- multiplying of data in in-phase and quadrature channels by 1 , -1 , 1 , -1 , ... and - 1 , 1 , -1 , 1 ... arrays, respectively, using a finite state machine which consists of states in which the data is used as is or the negative of value is used, preventing any DSP resource usage,

- filtering of data passing through I channel by the filter generated by double index coefficients and Q channel by the filter generated by single-index coefficients of the original low-pass filter,

- delaying of data coming out of low-pass filter in quadrature channel in one clock signal which is equal to two sampling periods with register

The structural and characteristic features of the invention can be understood in more clearly with the following figures and the detailed description that refers to the said figures; therefore, the evaluation is required to be made by taking these figures and the detailed description into account.

The Figures to facilitate a Better Understanding of the Invention

Figure 1 shows the schematic view of current digital down conversion block.

Figure 2 shows the block schematic view of current downsampling.

Figure 3 shows the combined block diagram of current digital down conversion block and downsampling.

Figure 4 is the block diagram view of the structure indicating the method of the invention.

Figure 5 is the block diagram view of the structure indicating the method of the invention without register.

Description of Referenced Parts

1 . Switch 2. Multiplier

3. Filter

4. Register

Detailed Description of the Invention

This detailed description sets out the configurations that utilize the said method of the invention on reducing resource utilization with a view to ensuring better understanding of the subject.

In most implementations of radar or similar systems, the signal in intermediate frequency sampled with ADC located in digital receiver boards is then downconverted to baseband passing through DDC block. Generally, oversampling process is conducted by selecting sampling frequency significantly higher than IF signal bandwidth and then downsampling method is used to remove the sampled surplus data.

An example of DDC block is indicated in Figure 1 . Sine and cosine signals whose frequency is equal to IF and sampled with f_s are multiplied with sampled IF signal coming out of ADC and then passed through a low-pass filter (LPF). This operation results in two data channels which are“in-phase (I)” and“quadrature (Q)” components of the input signal and the said operation is named as digital down conversion.

Figure 2 indicates the block diagram of downsampling process achieved by taking only one sample out of sequential samples of M (downsampling index) quantity and removing other M-1 quantity. If input signal is composed of N samples, then output signal is composed of N/M samples.

In most implementations, DDC process is simplified by selecting IF equal to one fourth of sampling frequency (or equal to one fourth of 1 st Nyquist plot). The simplification described herein reveals that cosine and sine values are comprised of only sequential 1 , 0 and -1 values as indicated below equations whereas fip=i s/4 (that is (J0IF=TT/2) : cos(iuiFn)=cos((TT/2)n)=1 ,0,-1 ,0,1 ,0,... COIF =ti/2 n=0,1 ,2,... ,N-1 sin(iuiFn)=sin((TT/2)n)=0,1 ,0,-1 ,0,1 ,... COIF =TTT2 n=0,1 ,2. N-1 Cosine and sine values in DDC block have enabled effective simplification in resource utilization due to the fact that there is no more need to use multiplier for the designed circuit in case that it is comprised of 1 , 0 and -1 instead of complicated values that will come out if any other IF frequency is selected. The operation conducted instead of the multiplication operation creates a Finite State Machine (FSM) in which sequential states appear such as taking the data itself, taking "0” value instead of data or taking the negative of data (2’s complement).

In a conventional numerical integration block, the next step is downsampling process. Both operations can be conducted via single filter by pooling low-pass filters located in sequential digital down conversion and downsampling blocks with a suitable selection of cut-off frequency. An example of digital receiver structure with conventional methods is shown in Figure 3. where, it is determined as M=2.

As shown in Figure 3, in prior art, one of two data entering into filters located in“in- phase (I)” and“quadrature (Q)” channels is“0”. One of two data at the outlet of filters is removed as it is required for downsampling process. When looked at the significant data obtained at both channels after downsampling, it can be seen that some coefficients of filters have no contribution to the said coefficient. While single-index coefficients of the filter utilized for I channel are meaningless, double-index coefficients of the filter utilized for Q channel do not have any impact on the outcome.

The purpose of this invention is to prevent unnecessary multiplication operations conducted within the filters by taking the downsampling process from back to front and by extension, to reduce the number of multipliers (DSP blocks in FPGA) used in digital circuits. The alternatives of preferred method can be seen in Figure 4 and Figure 5.

The alternative method of the invention illustrated in Figure 4 is comprised of one switch (1 ) at the inlet side, one multiplier (2) and one low pass filter (3) in I channel and one multiplier (2), one low pass filter (3) and one register (4) in Q channel. Out of the samples transferred by switch (1 ), the double-index samples (Xe[n]) are directed to I channel and single-index samples (Xo[n]) are directed to Q channel. The data on I and Q channels are multiplied by 1 , -1 , 1 , ... and -1 , 1 , -1 , ... arrays, respectively, with multipliers (2). The multiplication operation described herein is carried out by a finite state machine in a form of transferring the data as is or transferring the negative of data respectively without using any multiplier hardware block (DSP block). Thereafter, the data passing through I channel are filtered by the filter (3) (LPFI) generated from double-index coefficients of low-pass filter used in conventional method and data passing through Q channel are filtered by the filter (3) (LPFQ) generated from the single-index coefficients. The desired outcome is achieved by delaying the data coming out of low-pass filter (3) in Q channel for one clock signal (f_s/2 frequency) which is equal to two sampling periods with register (4). Downsampling process has been conducted by means of the switch (1 ) feeding only single-index data to one channel and only double-index data to other channel instead of feeding all data to both channels at the beginning.

According to alternative method of the invention illustrated in Figure 5, one-sample delay in Q channel has been acquired by feeding“0” value data to channel before the single-index samples instead of using register (4) shown in Figure 4. Thus, the blocks in I and Q channels have been balanced and there is no need to use an extra register (4). x[n] = [xo xi X2 X3.. . XN-1 ] (N is even number) x_e[n] = [xo X2 X4 X6... XN-2] (N is even number) x₀[n] = [X1 X3 X5 X7.. . XN-I] (N is even number)

LPF[n] = [ho hi h2... hi_-i] (L is odd number)

LPFi[n] = [ho h2 h₄... hi_-i] (L is odd number)

LPFo[n] = [hi hi3 hs... hi_-2] (L is odd number)

In conventional method, the data sampled with ADC are firstly subjected to DDC by multiplying with relevant cosine and sine values. Two generated channels are then passed through LPF and downsampled. Thanks to the method developed in the invention, a part of downsampling (|2) process is being taken to very beginning phase by using the advantage of “0” values located in multiplication arrays in DDC process, and by extension, multiplication arrays are formed as 1 , -1 , 1 , ... and then LPFs may operate at lower rates or the desired rate utilizing less resource. The consumption of DSP resources utilized in the configurations based on this method is reduced accordingly. Therefore, it may be possible to realize multichannel receiver structures such as currently used phased array antennas by utilizing less hardware resources (smaller FPGA, more channel in one FPGA etc.).

Claims

1. A method that enables to conduct digital down conversion and downsampling processes by utilizing less resource on hardware components, characterized in that it is comprised of following steps: - double-index samples are directed to in-phase channel and single-index samples are directed to quadrature channel out of the samples transferred by switch (1 ),

- the data in in-phase and quadrature channels are multiplied by 1 , -1 , 1 , -1 , and -1 , 1 , -1 , 1 , ... arrays, respectively, with multipliers (2), - the data passing through I channel are filtered by the filter (3) generated by double-index coefficients and the data passing through Q channel are filtered by the filter (3) generated by single-index coefficients,

- the data coming out of low pass filter (3) in quadrature channel are delayed for one clock signal which is equal to two sampling periods with register (4).

2. A method according to claim 1 , wherein it consists of the operation step of feeding

“0” value data to quadrature channel before feeding the single-index samples in case that no register (4) is available in quadrature channel.