WO2019155083A1

WO2019155083A1 - Specific dielectric layer for capacitive device

Info

Publication number: WO2019155083A1
Application number: PCT/EP2019/053434
Authority: WO
Inventors: Aude LEULIET; Anne-Charlotte AMIAUD
Original assignee: Thales
Priority date: 2018-02-12
Filing date: 2019-02-12
Publication date: 2019-08-15
Also published as: EP3753033A1; FR3077920B1; FR3077920A1

Abstract

The invention relates to a dielectric layer for interacting with two electrodes in order to form a capacitive device, the dielectric layer being a stack of superimposed sub-layers, each sub-layer having a thickness of less than 1 nanometer, each sub-layer being made of a material that is doped or not, the material consisting of a plurality of chemical elements, each material of a sub-layer varying in relation to the other materials of the other sub-layers at the most only by at least one out of the stoichiometry of the elements and the doping level, and the materials of each sub-layer being selected such that the relative variation of capacitance for a predefined voltage applied to the dielectric layer is less than or equal to 3.10^-3.

Description

Specific dielectric layer for capacitive device

The present invention relates to a dielectric layer. The invention also relates to a device comprising such a layer. The present invention also relates to a determination method and associated products.

The technical field is the technical field of microelectronics. In such a field, the miniaturization of components is a major issue. This is particularly the case for capacitive devices. As many types of capacitive devices exist, the choice of type depends in particular on the application envisaged, the problems raised by miniaturization are illustrated for two particular cases.

For data storage, decoupling, energy storage or electronic filtering, it is known to use a capacitor MIM 10. A capacitor MIM 10 is an example of a capacitive device 12 as illustrated in FIG. MIM acronym refers to the term "Metal-Insulator-Metal". A MIM capacitor 10 is a plane capacitor formed by a stack of three layers forming, namely a first conductive layer 14, an insulating layer 16 and a second conductive layer 18. The first conductive layer is the first electrode 14 and the second conductive layer is the second electrode 18. The conductive layers are made of metal and the insulating layer is made of a dielectric material. The insulating layer 16 is thus also referred to as the dielectric layer 16.

In operation, a potential V is applied between the first electrode 14 and the second electrode 18 driving the charge of the capacitor according to the following law:

Q = CV

Or :

• Q the load, and

• C the value of capacitor capacitance.

The capacity depends on the geometry of the capacitor and the properties of the insulator according to the following mathematical formula:

or :

S is the contact surface between the electrode 14 or 18 and the insulating layer;

D is the thickness of the insulating layer 16;

• e ₀ is the dielectric permittivity of the vacuum, and

• e _n is the permittivity of the insulating layer 16. In general, for such a capacitor, it is desirable to increase the capacitance and the breakdown voltage of the capacitor while decreasing the dielectric losses and the leakage currents.

For this, the capacity of the capacitor can be increased by increasing the contact area between the electrode 14 or 18 and the insulating layer 16.

However, the increase of the contact surfaces is a technique that is not very suitable in the case of microelectronics.

It is also known to reduce the thickness of the layer of dielectric material.

However, the reduction of the thickness of the insulation causes a decrease in the voltage withstand of the capacitor. In addition, under strong electric field, charge carriers can be injected into the insulating material thus generating large leakage currents.

For microwave switching applications or sensors or small actuators, the capacitive devices 12 used are microelectromechanical systems MEMS 20 (acronym for "Micro-Electro-Mechanical-Systems") in particular because of their low power consumption. energy, their low insertion losses and their small size.

Many MEMS structures exist such as series structures, such as cantilever or bridge beams. A diagram of an exemplary bridge structure MEMS 20 is illustrated in FIG. 2. The MEMS 20 shown is a parallel capacitive radiofrequency MEMS. The MEMS 20 comprises an upper membrane 22, a layer of dielectric material 16 and a lower membrane 24. The upper membrane 22 and the layer of dielectric material 16 delimit between them a space 26 filled with air. The upper membrane 22 forms a high electrode 18 while the lower membrane 24 is the lower electrode 14. The upper electrode 18 is movable in position. The dielectric layer 16 allows isolation and reveals a capacitance.

In operation, in a first position called high state illustrated in Figure 3, in the absence of application of a voltage between the two electrodes 14 or 18, the upper membrane 22 is in the high position. The radiofrequency signal is then transmitted. In a second position called low state shown in Figure 4, the application of a voltage between the two electrodes 14 or 18 generates an electrostatic force causing the lowering of the upper membrane 22, resulting in the reduction of space 26 filled with air and thus increasing the capacity. The capacitance increases sufficiently for the radio frequency signal to be sent to ground. For such an application, the performance of the MEMS 20 is characterized by the losses, the operating voltage, the switching time and the power output. When the upper membrane 22 is in the high state, the radiofrequency signal passes and the insertion losses must be low of the order of 0.1 decibel (dB) whereas, in the low state, the radiofrequency signal is blocked and the insulation must be high, the radiofrequency signal is attenuated by at least 10 dB.

However, the integration of MEMS 20 is limited by their reliability. The failure may be mechanical but the life time is essentially limited by a charge accumulation phenomenon in the dielectric layer 16 which shifts the operating voltage of the MEMS 20 and causes either the bonding of the membrane or the switching off. .

In the two illustrated cases of the capacitor MIM 10 and a MEMS 20, the limitation in size of the capacitive device 12, and more specifically of the dielectric layer 16, results in a reduction in the lifetime of the devices whether for a phenomenon of breakdown or shift of the actuating voltage.

There is therefore a need for a capacitive device having a dielectric layer of reduced size ensuring a better life time.

For this purpose, the present description relates to a dielectric layer intended to interact with two electrodes to form a capacitive device, the dielectric layer being a stack of superimposed sub-layers, each sub-layer having a thickness of less than 1 nanometer, each sub-layer being layer being made of a doped or non-doped material, the material being composed of several chemical elements, each material of a sub-layer varying from the other materials of the other sub-layers by at least only one of the stoichiometry elements and the doping rate, the materials of each sub-layer being chosen so that the relative capacitance variation for a predefined voltage applied to the dielectric layer is less than or equal to 3.10 ³ .

According to particular embodiments, the dielectric layer comprises one or more of the following characteristics, taken in isolation or in any technically possible combination:

the dielectric layer has at least two sub-stacks, the sub-layers of at least one sub-stack having the same materials.

the dielectric layer has sub-stacks, of which the extreme sub-stacks of the dielectric layer have a doping gradient greater than 8 × 10 ²² / m ³ . the spatial evolution of the doping rate for the materials of at least a part of the sub-layers is a weighted sum of a Lorentzian function and a Gaussian function.

the dielectric layer has at least one sub-stack in which the evolution of the stoichiometric coefficient of an element as a function of the sub-layers follows a linear progression.

The present description also relates to a capacitive device comprising two electrodes and a dielectric layer intended to interact with the two electrodes, the dielectric layer being as previously described.

According to a particular embodiment, the capacitive device is a microelectromechanical system.

The present description also relates to a method for determining the material of a dielectric layer intended to interact with two electrodes to form a capacitive device, the dielectric layer being a stack of superimposed sub-layers, each sub-layer having a thickness of less than 1 nanometer, each sub-layer being made of a doped material or not, the material being composed of several chemical elements, each material of a sub-layer varying from other materials of other sub-layers at most only by at least l one among the stoichiometry of the elements and the doping rate. The method includes providing a preset voltage and optimizing the materials of each underlayer to provide that the relative capacitance variation for a predefined voltage applied to the dielectric layer is less than or equal to 3.10 ³ .

The present description also relates to a computer program product comprising a readable information medium, on which is stored a computer program comprising program instructions, the computer program being loadable on a data processing unit. and adapted to cause the implementation of a method as previously described.

The present description also relates to a readable medium of information storing a computer program comprising program instructions, the computer program being loadable on a data processing unit and adapted to lead to the implementation of a method such as than previously described when the computer program is implemented on the data processing unit. Other features and advantages of the invention will appear on reading the following description of embodiments of the invention, given by way of example only and with reference to the drawings which are:

- Figure 1, a schematic view of a MIM capacity;

FIG. 2, a schematic view of a capacitive radio frequency MEMS;

FIG. 3, a schematic view of the capacitive radiofrequency MEMS in a first position;

FIG. 4, a schematic view of the capacitive radiofrequency MEMS in a second position;

FIG. 5, a graph showing the spatial distribution of the charge trapped in a silicon nitride dielectric layer for an applied electric field of 60 volts (V) over 255 nanometers (nm);

- Figure 6, an enlarged view of Figure 5;

FIG. 7, a graph comparing experimental results of voltage shift of a capacitive radio frequency MEMS with simulated results;

FIG. 8, a graph showing the temporal variation of the quantity of charges in the dielectric layer;

FIG. 9, a graph showing the temporal variation of the offset of the operating voltage of a capacitive radio frequency MEMS;

FIG. 10, a graph showing the time variation over 200 s of the shift of the operating voltage of a capacitive radiofrequency MEMS for a silicon nitride dielectric layer having the stationary state before the application of a voltage of 60 V over 255 nm;

- Figure 1 1, a graph showing the spatial distribution of charges in a dielectric layer after an electrical stress of 3000 s for a single trap;

- Figure 12, a graph showing the spatial distribution of charges in a dielectric layer after an electrical stress of 3000 s for two traps;

FIG. 13, a graph showing the evolution of the operating voltage of a capacitive radiofrequency MEMS as a function of the applied voltage;

FIG. 14, a graph showing the spatial variation of the electric field in a silicon nitride dielectric layer;

FIG. 15, an enlarged view of FIG. 14, and

- Figure 16, a graph showing a variation of the conduction band required to obtain a homogeneous current in the dielectric for an applied voltage of 60 V. It is considered a dielectric layer 16 intended to interact with two electrodes 14 or 18 to form a capacitive device 12.

The capacitive device 12 is, for example, a MIM capacitor 10 as shown in FIG. 1 or an MEMS 20 as can be seen in FIGS. 2 to 4.

Alternatively, the capacitive device 12 is a subset of a transistor or memory. The dielectric layer 16 is a stack of superimposed sub-layers in a stacking direction.

In the example described, the number of sub-layers is greater than 100 layers, preferably greater than 200 layers.

Other numbers of layers, however, are possible.

In general, the number of layers is greater than or equal to 3.

Preferably, the number of layers is greater than or equal to 10, or even 25.

Each sub-layer is a planar sub-layer, that is to say that the sub-layer extends between two plane and parallel faces.

Each sub-layer has a thickness of less than 1 nanometer. The thickness of an underlayer is defined as the distance between the two faces of an underlayer, the distance being measured in the stacking direction.

Each underlayer being made of a doped material or not.

The material consists of several chemical elements.

A chemical element is an element of Mendeleev's painting.

In this case, the chemical element is chosen from the group consisting of nitrogen N, silicon Si, hydrogen H, oxygen O, titanium Ti, boron B, Hafnium Hf, Al aluminum, Zirconium Zr, Pb lead and Yttrium Y.

The number of chemical species is, for example, equal to 2 or 3.

Each material of an underlayer varies from the other materials of the other sub-layers by at least only one of the stoichiometry of the elements of the material and the doping rate of the material.

Otherwise formulated, for two materials of two sublayers, four cases are possible:

- the two materials are identical;

the two materials exhibit the same stoichiometry but a different doping rate;

the two materials have a different doping rate but a different stoichiometry, and

the two materials exhibit a different doping rate and a different stoichiometry. The materials of each sub-layer are chosen so that the relative capacitance variation for a predefined voltage applied to the dielectric layer 16 is less than or equal to 3.10 ³ .

By relative capacity variation in this context, it is understood the variation brought back to the value of the capacitance of the dielectric layer 16, that is to say mathematically:

AC

^VR = T

or :

• VR is the relative capacitance variation of the dielectric layer 16,

• C is the value of the capacitance of the dielectric layer 16, and

• AC is the absolute value of the temporal variation of the capacitance of the dielectric layer 16 when the predefined voltage is applied thereto.

The preceding condition therefore means that, when the preset voltage is applied to the dielectric layer 16, the relative difference in value of the capacitance C of the dielectric layer 16 is bounded by a threshold.

As can be seen in the following figures, this limitation of the value of the capacitor C is to be understood in the temporal sense, that is to say that over time, the relative distance over the value of the capacitor C of the dielectric layer 16 remains bounded by a threshold.

Such a threshold value corresponds to the relative capacitance variation making it possible to obtain the desired performances for the capacitive device 12.

Otherwise formulated, as shown in the following, this allows the dielectric layer 16 to behave as an artificial material capable of generating a homogeneous current throughout the dielectric layer 16 for the preset voltage.

Such a dielectric layer 16 thus makes it possible to avoid the accumulation of charges within the dielectric layer 16 during operation. The capacitive device 12 comprising the dielectric layer 16 has on the one hand a reduced size and guarantees a better life time for operation at the preset voltage.

To show that such a dielectric layer 16 avoids the accumulation of charges within the dielectric layer 16, the Applicant has developed a model which is described below.

The applicant has developed a model simulating the accumulation of carriers in the dielectric layer 16 in a capacitive device 12. The model therefore makes it possible to obtain, from the information on the material of the dielectric layer 16 and on the predefined voltage, the evolution of charge accumulation over time in the dielectric layer 6. More precisely, the model gives access to temporal evolution of all the physical quantities impacting the transport of charges in the dielectric layer 16: electric field, current and charge density at any point of the dielectric. From these data, it is possible to deduce the life time of the capacitive device 12 for operation at the preset voltage.

The model is a one-dimensional model taking into account tunneling and thermal effect mechanisms for four types of carriers: trapped electrons, free electrons, trapped holes and free holes. The model is based on solving the Maxwell-Gauss equations and preserving the charge throughout the thickness of the dielectric layer 16.

Examples of results obtained by the model are shown in FIGS. 5 and 6, FIG. 5 showing the spatial distribution of the charge trapped in a silicon nitride dielectric layer 16 for an applied electric field of 60 volts (V) over 255 nanometers (nm) and FIG. 6 being an enlarged view of FIG.

To validate the preceding model, it is possible to calculate the offset of the operating voltage of a capacitive radiofrequency MEMS 20 comprising such a dielectric layer 16. Measurements of evolution of the actuation voltage as a function of accumulated actuated time (total electrode contact time 14 or 18 with the dielectric layer 16) were performed on such a capacitive radiofrequency MEMS with a dielectric layer 16 made of silicon nitride. These measurements are compared with the result of the simulation in Figure 7. Figure 7 shows a good agreement between measurement and simulation, which validates the model.

The model thus makes it possible to validate the properties of a dielectric layer 16 from the point of view of the accumulation of charges at a predefined voltage.

The model can also assist in determining the undercoat materials of a dielectric layer 16 satisfying the condition that the relative capacitance variation for a predefined voltage applied to the dielectric layer 16 is less than or equal to 3.10 ³ .

Two particular examples are illustrated in the following.

In the first example, for simplicity, it is assumed that the stoichiometry of the elements remains the same and that only the doping rate can vary from one underlayer to another sublayer.

With the model, it is determined the density and the location of the charge in a dielectric layer 16 without doping in operation and when the amount of charge in the dielectric no longer changes as a function of time (stationary state). This thus makes it possible to obtain the temporal variation of the quantity of charges in the dielectric layer 16 as visible in FIG. 8 and the offset of the operating voltage. a capacitive radiofrequency MEMS 20 as visible in FIG. 9. The parameters of the simulation are the same as for FIG.

The principle of determination of the doping rate is then to dope the dielectric layer 16 in each charge accumulation location to best reproduce the stationary state before the application of a preset voltage. This reproduction at best corresponds to the respect of the condition according to which the relative capacitance variation for a predefined voltage applied to the dielectric layer 16 is less than or equal to 3.10 ³ .

Indeed, simulations carried out starting from an initial state where the dielectric layer 16 is charged show that not only does the charge change little even after 500 s under an electric field but also that the shift of the operating voltage of a MEMS 20 capacitive radio frequency also varies soon after. To illustrate this last point, FIG. 10 shows the time variation over 200 s of the shift of the operating voltage of a capacitive radiofrequency MEMS for a dielectric layer 16 made of silicon nitride having the stationary state before the application of the preset voltage, here 60 V on 255 nm.

Thus, it is possible to obtain numerous first examples with variation of the doping rate.

The material, here silicon nitride by way of example, can be doped P or N depending on the type of carriers that can be injected. The zone to be doped will be determined by calculation, and corresponds to the distribution of charges in the insulator after a sufficiently long electrical stress, which distribution is shown in FIG. 11 for the case of a single trap. This distribution varies according to the properties of the dielectric and the conditions of use of the component (applied electric field). If, for example, several levels of traps contribute to charge accumulation in the dielectric, the trapped charge distribution will consist of several peaks at the beginning of the electrical stress (see Figure 12 for two traps). The spatial distribution will then evolve with the deformation of the conduction band, the peaks can get closer and become indistinguishable or the contribution of one of the traps can become negligible.

The zone is doped P in case of accumulation of electrons, and N in case of accumulation of holes. In the case of silicon nitride, the doping P is, for example, carried out with arsenic or boron, whereas the N doping is, for example, carried out with phosphorus or fluorine. In some cases, the doping is carried out directly during the deposition by use of the adapted precursor gases. In a variant, the doping is done by implantation of ions. A deposition method such as the atomic layer deposition also called ALD referring to the term "Atomic Layer Deposition" makes it possible to synthesize a dielectric layer 16 having a suitable spatial distribution of dopants. Indeed, the control of the composition during the deposition is performed with a precision at the atomic scale.

After actuation voltage offset measurements on capacitive radio frequency MEMS and simulations, it is then possible to determine the drift value of the actuating voltage (noted V _{P |} in FIG. 13, PI referring to the term English "pull-in") and associated load distribution. If for an applied voltage of 60V and a given dielectric material, the AV offset reaches about 15V, the dielectric layer 16 is doped to allow actuation of the 45V membrane. The holding voltage of the membrane V _h must also be less than 15V in order to prevent bonding of the membrane by the action of the charges in the dielectric layer 16 (see FIG. 13 which shows the variation of the parameter S _2i corresponding to a coefficient transmission of the power by the capacitive device 12 as a function of the operating voltage V _{P |} ). With the aid of all the preceding analyzes, this results in a first case of a first example of a dielectric layer 16 whose model makes it possible to validate that the condition according to which the relative capacitance variation for a predefined voltage applied to the dielectric layer 16 is less than or equal to 3.10 ³

The dielectric has three zones: a first zone without a dopant, a second zone having a dopant distribution and a third zone without a dopant. The material is a binary or ternary material.

The first zone and the third zone have a spatial extension of 4 nm.

The distribution of dopants in the second zone is given by the following formula:

Or :

• D (x) is the spatial distribution of dopants;

G is a predefined value, typically 10 nm;

• x _oi are values ranging between 5 nm and 10 nm;

•

is a value varying between 4 nm and 6 nm, and

• A and Bi are weighting coefficients depending in particular on the predefined voltage.

The preceding formula is a formula resulting from the following physical phenomena: the thermal effects, the tunnel effect at the level of each trap. The half-Lorentzian formula ¹ serves to compensate for the thermal effects while the

sum serves to compensate for the tunnel effects at each trap (hence the dependence on i, i being the number of traps and x _oi corresponding to the position of the trap). Since these phenomena vary according to the predefined voltage, the coefficients change but this shows that the proposed structure makes it possible to verify the condition according to which the relative capacitance variation for a predefined voltage applied to the dielectric layer 16 is less than or equal to 3.10 ³ and this for several predefined voltages by modifying only the parameters y, x _oi , x _lt A and b ;.

In the second example, for simplicity, it is assumed that the doping rate remains the same and that only the stoichiometry of the elements can vary from one underlayer to another sublayer.

The model makes it possible to show that the electric field varies rather rapidly along the interfaces then more slowly at the center of the dielectric layer 16. FIG. 14 illustrates such a variation in the case of a dielectric layer 16 made of silicon nitride and enlarged in Figure 15.

The potential seen by the electrons thus has a slope break at the point where the electric field is leaking and which corresponds to the zone where the centroid of the charge is located (at about 5 nm deep in the dielectric layer 16). . The dashed line in FIG. 15 is a guide for the eye to visualize the slope failure. If a contribution corresponding to a constant electric field is subtracted from this potential, it is obtained the variation of conduction band height which would allow the appearance of a homogeneous current throughout the thickness of the dielectric layer, as visible on Figure 16.

Due to this conduction band, in a second example of a dielectric layer of 255 nm in thickness and operating at 60V, it is necessary to impose the stoichiometric gradient of each layer in three zones:

a first zone extending between 0 and 5 nm with a gradient (for example a linear gradient) of stoichiometry between SiN _{1 33} and SiN _{1 44} ;

a second zone extending between 5 nm and 250 nm with constant stoichiometry;

a third zone extending between 250 nm and 255 nm exhibiting a stoichiometric gradient from SiN _{1 44} to SiN _{1 55} .

The use of the model makes it possible to show that such a second example makes it possible to obtain a relative capacitance variation for a predefined voltage applied to the dielectric layer that is less than or equal to 3.10 ³ . The extension to other examples using the model is immediate by cleverly playing on at least one of the stoichiometry of the elements and the doping rate.

From previous examples, it follows that the following properties are interesting:

the dielectric layer has at least two sub-stacks (zones in the two preceding examples), generally three sub-stacks, the sub-layers of at least one sub-stack having the same materials.

- The dielectric layer 16 has sub-stacks among which the extreme sub-stacks of the dielectric layer 16 have a doping gradient greater than 8 × 10 ²² / m ³ which allows a variation between 0 and 1, 5.10 ¹⁴ / m ² on 2 nm.

the spatial evolution of the doping rate for the materials of at least a part of the sub-layers is a weighted sum of a Lorentzian function and a Gaussian function.

the dielectric layer has at least one sub-stack in which the change in the stoichiometric coefficient of an element as a function of the sub-layers follows a linear progression.

the dielectric layer 16 has a current density of less than 1.10 ⁴ Am

2

Moreover, it appears that the model makes it possible to envisage a method of determining the material of the dielectric layer 16, the method comprising the provision of a predefined voltage and the optimization of the materials of each underlayer to obtain that the variation relative capacity for a preset voltage applied to the dielectric layer 16 is less than or equal to 3.10 ³ .

The method is preferably implemented by computer. More precisely, it is the interaction of a computer program product with the system that makes it possible to implement a determination method.

The system is a computer.

More generally, the system is an electronic calculator adapted to manipulate and / or transform data represented as electronic or physical quantities in system registers and / or memories into other similar data corresponding to physical data in memories, registers or other types of display, transmission or storage devices. The system includes a processor including a data processing unit, memories and an information carrier reader. The system also includes a keyboard and a display unit.

The computer program product comprises a readable information medium. A readable information medium is a readable medium by the system, usually by the data processing unit. The readable information medium is a medium suitable for storing electronic instructions and capable of being coupled to a bus of a computer system.

By way of example, the readable information medium is a diskette or floppy disk ("floppy disk"), an optical disk, a CD-ROM, a magneto-optical disk, a ROM memory, a RAM memory, an EPROM memory, an EEPROM memory, a magnetic card or an optical card.

On the readable information medium is stored a computer program including program instructions.

The computer program is loadable on the data processing unit and is adapted to drive the implementation of the determination method when the computer program is implemented on the data processing unit.

Claims

1. A dielectric layer (16) for interacting with two electrodes (14, 18) to form a capacitive device (12), the dielectric layer (16) being a stack of superimposed sub-layers, each sub-layer having a thickness less than 1 nanometer, each underlayer being made of doped material or not, the material being composed of several chemical elements, each material of a sub-layer varying from other materials of other sub-layers at most only by at least one of the stoichiometry of the elements and the doping rate, the materials of each sublayer being selected so that the relative capacitance variation for a predefined voltage applied to the dielectric layer (16) is less than or equal to 3.10 ³ .

2. A dielectric layer according to claim 1, wherein the dielectric layer (16) has at least two sub-stacks, the sub-layers of at least one sub-stack having the same materials.

3.- dielectric layer according to claim 1 or 2, wherein the dielectric layer (16) has sub-stacks among which the extreme sub-stacks of the dielectric layer (16) have a doping gradient greater than 8.10 ²² / m ³ .

4. Dielectric layer according to any one of claims 1 to 3, wherein the spatial evolution of the doping rate for the materials of at least a portion of the sub-layers is a weighted sum of a Lorentzian function and a Gaussian function.

5. A dielectric layer according to any one of claims 1 to 4, wherein the dielectric layer (16) has at least one sub-stack in which the evolution of the stoichiometric coefficient of an element according to the sub-layers follows. a linear progression.

6. A capacitive device (12) comprising two electrodes (14, 18) and a dielectric layer (16) for interacting with the two electrodes (14, 18), the dielectric layer (16) being according to any one of the claims 1 to 5.

7. Capacitive device (12) according to claim 6, wherein the capacitive device (12) is a microelectromechanical system (20).

8. A method for determining the material of a dielectric layer (16) for interacting with two electrodes (14, 18) to form a capacitive device (12), the dielectric layer (16) being a stack of superposed sub-layers each sub-layer having a thickness of less than 1 nanometer, each sub-layer being made of a doped or non-doped material, the material being composed of a plurality of chemical elements, each material of a sub-layer varying with respect to the other materials of the other sub-layers at most only by at least one of the stoichiometry of the elements and the doping level, the process comprising:

the provision of a preset voltage, and

the optimization of the materials of each sub-layer to obtain that the relative capacitance variation for a predefined voltage applied to the dielectric layer

(16) is less than or equal to 3.10 ³ .

9. A computer program product comprising a readable information medium, on which is stored a computer program including program instructions, the computer program being loadable on a data processing unit and adapted to train the computer. implementation of a method according to claim 8.

10.- readable information storage medium storing a computer program comprising program instructions, the computer program being loadable on a data processing unit and adapted to cause the implementation of a method according to claim 8; when the computer program is implemented on the data processing unit.