FR3077920A1 - SPECIFIC DIELECTRIC LAYER FOR CAPACITIVE DEVICE - Google Patents

Abstract

The present invention relates to a dielectric layer for interacting with two electrodes to form a capacitive device, the dielectric layer being a stack of superimposed sub-layers, each sub-layer having a thickness of less than 1 nanometer, each sub-layer being produced in a doped or non-doped material, the material being composed of a plurality of chemical elements, each material of an underlayer varying from the other materials of the other sub-layers by at least one of the stoichiometry of the elements and the doping rate, the materials of each sublayer being chosen so that the relative capacitance variation for a predefined voltage applied to the dielectric layer is less than or equal to 3.10-3.

Description

Dielectric layer specific for capacitive device

The present invention relates to a dielectric layer. The invention also relates to a device comprising such a layer. The present invention also relates to a determination method and associated products.

The technical area is the technical area of microelectronics. In such an area, the miniaturization of components is a major issue. This is particularly the case for capacitive devices. As many types of capacitive devices exist, the choice of type depends in particular on the application envisaged, the problems posed by miniaturization are illustrated for two specific cases.

For data storage, decoupling, energy storage or electronic filtering, it is known to use a MIM capacitor 10. A MIM capacitor 10 is an example of capacitive device 12 as illustrated in FIG. 1. The acronym MIM refers to the expression “Métal-lsolant-Métal”. A MIM capacitor 10 is a planar capacitor formed by a stack of three layers forming, namely a first conductive layer 14, an insulating layer 16 and a second conductive layer 18. The first conductive layer is the first electrode 14 and the second conductive layer is the second electrode 18. The conductive layers are made of metal and the insulating layer is made of a dielectric material. The insulating layer 16 is thus also designated by the term dielectric layer 16.

In operation, a potential V is applied between the first electrode 14 and the second electrode 18 causing the capacitor to charge according to the following law:

Q = CV

Or:

• Q the load, and • C the value of the capacitance of the capacitor.

The capacity depends on the geometry of the capacitor and the properties of the insulator according to the following mathematical formula:

SC = -ε _ο ε _Γ where:

• S is the contact surface between the electrode 14 or 18 and the insulating layer;

• d is the thickness of the insulating layer 16;

• εθ is the dielectric permittivity of the vacuum, and • ε _Γ is the permittivity of the insulating layer 16.

In general for such a capacitor, it is desirable to increase the value of the capacitance and the breakdown voltage of the capacitor while reducing the dielectric losses and the leakage currents.

For this, the capacitance of the capacitor can be increased by increasing the contact surface between the electrode 14 or 18 and the insulating layer 16.

However, increasing the contact surfaces is a technique that is hardly suited in the case of microelectronics.

It is also known to reduce the thickness of the layer of dielectric material.

However, the reduction in the thickness of the insulator results in a reduction in the voltage withstand of the capacitor. In addition, under a strong electric field, charge carriers can be injected into the insulating material, thereby generating large leakage currents.

For microwave switching applications or small size sensors or actuators, the capacitive devices 12 used are MEMS microelectromechanical systems 20 (acronym for “Micro-Electro-MechanicalSystems”) notably because of their low energy consumption , their low insertion loss and their small size.

Many MEMS 20 structures exist such as series structures, of the cantilever or bridge type. A diagram of an example of MEMS 20 in bridge structure is illustrated in FIG. 2. The MEMS 20 shown is a parallel capacitive radiofrequency MEMS. The MEMS 20 comprises an upper membrane 22, a layer of dielectric material 16 and a lower membrane 24. The upper membrane 22 and the layer of dielectric material 16 delimit between them a space 26 filled with air. The upper membrane 22 forms a high electrode 18 while the lower membrane 24 is the low electrode 14. The high electrode 18 is movable in position. The dielectric layer 16 allows the insulation and reveals a capacitance.

In operation, in a first position known as the high state illustrated in FIG. 3, in the absence of application of a voltage between the two electrodes 14 or 18, the upper membrane 22 is in the high position. The radio frequency signal is then transmitted. In a second position known as the low state represented in FIG. 4, the application of a voltage between the two electrodes 14 or 18 generates an electrostatic force causing the lowering of the upper membrane 22, which results in the reduction of the space 26 filled with air and thus the increase in capacity. The capacity increases enough for the radio frequency signal to be sent to ground.

For such an application, the performance of MEMS 20 is characterized by losses, actuation voltage, switching time and tolerated power. When the upper membrane 22 is in the high state, the radiofrequency signal passes and the insertion losses must be low of the order of 0.1 decibel (dB) while, in the low state, the radiofrequency signal is blocked and the insulation must be high, the radio frequency signal is attenuated by at least 10 dB.

However, the integration of MEMS 20 is limited by their reliability. The failure can be mechanical but the lifetime is essentially limited by a charge accumulation phenomenon in the dielectric layer 16 which shifts the actuation voltage of the MEMS 20 and causes either the sticking of the membrane or the stopping of the switching operations. .

In the two illustrated cases of the MIM capacitor 10 and of a MEMS 20, the limitation in size of the capacitive device 12, and more specifically of the dielectric layer 16, results in a reduction in the lifetime of the devices, whether for a phenomenon of breakdown or offset of the actuation voltage.

There is therefore a need for a capacitive device having a dielectric layer of reduced size guaranteeing a better life time.

For this, the present description relates to a dielectric layer intended to interact with two electrodes to form a capacitive device, the dielectric layer being a stack of superimposed sublayers, each sublayer having a thickness of less than 1 nanometer, each sublayer layer being made of a doped or undoped material, the material consisting of several chemical elements, each material of an underlayer varying with respect to the other materials of the other sublayers at most only by at least one among the stoichiometry of the elements and the doping rate, the materials of each sublayer being chosen so that the relative variation in capacitance for a predefined voltage applied to the dielectric layer is less than or equal to 3.10 ′ ³ .

According to particular embodiments, the dielectric layer comprises one or more of the following characteristics, taken alone or according to all technically possible combinations:

- the dielectric layer has at least two sub-stacks, the sub-layers of at least one sub-stack having the same materials.

- The dielectric layer has under-stacks among which the extreme under-stacks of the dielectric layer have a doping gradient greater than 8.10 ²² / m ³ .

- the spatial evolution of the doping rate for the materials of at least part of the sublayers is a weighted sum of a Lorentzian function and a Gaussian function.

- The dielectric layer has at least one sub-stack in which the evolution of the stoichiometric coefficient of an element as a function of the sub-layers follows a linear progression.

The present description also relates to a capacitive device comprising two electrodes and a dielectric layer intended to interact with the two electrodes, the dielectric layer being as previously described.

According to a particular embodiment, the capacitive device is a microelectromechanical system.

The present description also relates to a method for determining the material of a dielectric layer intended to interact with two electrodes to form a capacitive device, the dielectric layer being a stack of superimposed sublayers, each sublayer having a thickness less than 1 nanometer, each sublayer being made of a doped or undoped material, the material consisting of several chemical elements, each material of an sublayer varying with respect to the other materials of the other sublayers at most only by at least 1 one of the elements stoichiometry and the doping rate. The method comprising supplying a predefined voltage and optimizing the materials of each sublayer to obtain that the relative variation in capacitance for a predefined voltage applied to the dielectric layer is less than or equal to 3.10 ' ³ C.

The present description also relates to a computer program product comprising a readable information medium, on which is stored a computer program comprising program instructions, the computer program being loadable on a data processing unit. and adapted to entail the implementation of a method as previously described.

The present description also relates to a readable information medium storing a computer program comprising program instructions, the computer program being loadable on a data processing unit and adapted to entail the implementation of a method such as previously described when the computer program is implemented on the data processing unit.

Other characteristics and advantages of the invention will appear on reading the following description of embodiments of the invention, given by way of example only and with reference to the drawings which are:

- Figure 1, a schematic view of a MIM capacity;

- Figure 2, a schematic view of a capacitive radiofrequency MEMS;

- Figure 3, a schematic view of the MEMS capacitive radio frequency in a first position;

- Figure 4, a schematic view of the MEMS capacitive radio frequency in a second position;

- Figure 5, a graph showing the spatial distribution of the charge trapped in a dielectric layer of silicon nitride for an applied electric field of 60 Volts (V) on 255 nanometers (nm);

- Figure 6, an enlarged view of Figure 5;

- Figure 7, a graph comparing experimental results of voltage offset of a capacitive radiofrequency MEMS with simulated results;

- Figure 8, a graph showing the temporal variation of the amount of charges in the dielectric layer;

- Figure 9, a graph showing the temporal variation of the offset of the actuation voltage of a capacitive radiofrequency MEMS;

- Figure 10, a graph showing the time variation over 200 s of the offset of the actuation voltage of a capacitive radiofrequency MEMS for a dielectric layer of silicon nitride having the stationary state before the application of a voltage of 60 V over 255 nm;

- Figure 11, a graph showing the spatial distribution of charges in a dielectric layer after an electrical stress of 3000 s for a single trap;

- Figure 12, a graph showing the spatial distribution of charges in a dielectric layer after an electrical stress of 3000 s for two traps;

- Figure 13, a graph showing the evolution of the actuation voltage of a capacitive radiofrequency MEMS as a function of the applied voltage;

- Figure 14, a graph showing the spatial variation of the electric field in a dielectric layer of silicon nitride;

FIG. 15, an enlarged view of FIG. 14, and

- Figure 16, a graph showing a variation of the conduction band necessary to obtain a homogeneous current in the dielectric for an applied voltage of 60 V.

It is considered a dielectric layer 16 intended to interact with two electrodes 14 or 18 to form a capacitive device 12.

The capacitive device 12 is, for example, a MIM capacitor 10 as shown in FIG. 1 or a MEMS 20 as visible in FIGS. 2 to 4.

Alternatively, the capacitive device 12 is a subset of a transistor or a memory. The dielectric layer 16 is a stack of superimposed sublayers in a stacking direction.

The number of sublayers is more than 100 layers, preferably more than 200 layers.

Each sublayer is a planar sublayer, that is to say that the sublayer extends between two plane and parallel faces.

Each sub-layer has a thickness of less than 1 nanometer. The thickness of an underlay is defined as the distance between the two faces of an underlay, the distance being measured along the stacking direction.

Each sublayer being made of a doped or undoped material.

The material consists of several chemical elements.

A chemical element is an element from Mendeleev's table.

In this case, the chemical element is chosen from the group consisting of nitrogen N, silicon Si, hydrogen H, oxygen O, titanium Ti, boron B, Hafnium Hf, aluminum Al, Zirconium Zr, lead Pb and Yttrium Y.

The number of chemical species is, for example, 2 or 3.

Each material of a sublayer varies with respect to the other materials of the other sublayers at most only by at least one of the stoichiometry of the elements of the material and the doping rate of the material.

Otherwise formulated, for two materials of two sub-layers, four cases are possible:

- the two materials are identical;

- the two materials have the same stoichiometry but a different doping rate;

the two materials have a different doping rate but a different stoichiometry, and

- the two materials have a different doping rate and a different stoichiometry.

The materials of each sublayer are chosen so that the relative variation in capacitance for a predefined voltage applied to the dielectric layer 16 is less than or equal to 3.10 ′ ³ .

By relative variation of capacitance in this context, it is understood the variation reduced to the value of the capacitance of the dielectric layer 16, that is to say mathematically:

AC where:

• VR is the relative variation of capacity of the dielectric layer 16, • C is the value of the capacity of the dielectric layer 16, and • AC is the absolute value of the temporal variation of the capacity of the dielectric layer 16 when it is applies the preset voltage.

The previous condition therefore means that, when the predefined voltage is applied to the dielectric layer 16, the relative difference in value of the capacitance C of the dielectric layer 16 is bounded by a threshold.

Such a threshold value corresponds to the relative variation in capacity making it possible to obtain the performance desired for the capacitive device 12.

Otherwise formulated, as shown in the following, this allows the dielectric layer 16 to behave like an artificial material capable of generating a homogeneous current throughout the dielectric layer 16 for the predefined voltage.

Such a dielectric layer 16 therefore makes it possible to avoid the accumulation of charges within the dielectric layer 16 in operation. The capacitive device 12 comprising the dielectric layer 16 has on the one hand a reduced size and guarantees a better life time for operation at the predefined voltage.

To show that such a dielectric layer 16 makes it possible to avoid the accumulation of charges within the dielectric layer 16, the applicant has developed a model which is described in the following.

The applicant has developed a model simulating the accumulation of carriers in the dielectric layer 16 in a capacitive device 12. The model therefore makes it possible to obtain, from information on the material of the dielectric layer 16 and on the predefined voltage, l evolution of charge accumulation over time in the dielectric layer 16. More precisely, the model gives access to the temporal evolution of all the physical quantities impacting the transport of charges in the dielectric layer 16: electric field, current and charge density at any point of the dielectric. From this data, it is possible to deduce the lifetime of the capacitive device 12 for operation at the predefined voltage.

The model is a one-dimensional model taking into account conduction mechanisms by tunnel effect and by thermal effect for four types of carriers: trapped electrons, free electrons, trapped holes and free holes. The model is based on the resolution of the Maxwell-Gauss equations and of charge conservation throughout the thickness of the dielectric layer 16.

Examples of results obtained by the model are presented in FIGS. 5 and 6, FIG. 5 showing the spatial distribution of the charge trapped in a dielectric layer 16 of silicon nitride for an applied electric field of 60 Volts (V) over 255 nanometers (nm) and FIG. 6 being an enlarged view of FIG. 5.

To validate the previous model, it is possible to calculate the offset of the actuation voltage of a capacitive radiofrequency MEMS 20 comprising such a dielectric layer 16. Measures of evolution of the actuation voltage as a function of the accumulated actuated time (total duration of electrode 14 or 18 contact with the dielectric layer 16) were produced on such a MEMS 20 capacitive radio frequency with a dielectric layer 16 made of silicon nitride. These measurements are compared with the result of the simulation in FIG. 7. FIG. 7 shows a good agreement between the measurement and the simulation, which validates the model.

The model therefore makes it possible to validate the properties of a dielectric layer 16 from the point of view of the accumulation of charges at a predefined voltage.

The model can also help to determine the materials of sublayers of a dielectric layer 16 verifying the condition according to which the relative variation of capacitance for a predefined voltage applied to the dielectric layer 16 is less than or equal to 3.10 ′ ³ .

Two specific examples are illustrated in the following.

In the first example, for simplicity, it is assumed that the stoichiometry of the elements remains identical and that only the doping rate can vary from one sublayer to another sublayer.

Thanks to the model, it is determined the density and the location of the charge in a dielectric layer 16 without doping in operation and when the amount of charges in the dielectric no longer changes as a function of time (steady state). This thus makes it possible to obtain the temporal variation of the quantity of charges in the dielectric layer 16 as visible in FIG. 8 and the offset of the actuation voltage of a capacitive radiofrequency MEMS 20 as visible in FIG. 9. The parameters of the simulation are the same as for figure 7.

The principle of determining the doping rate is then to dop the dielectric layer 16 in each place of charge accumulation in order to best reproduce the stationary state before the application of a predefined voltage. This reproduction at best corresponds to compliance with the condition that the relative variation in capacitance for a predefined voltage applied to the dielectric layer 16 is less than or equal to 3.10 ' ³ .

Indeed, simulations carried out starting from an initial state where the dielectric layer 16 is charged show that not only does the charge change little even after 500 s under electric field but also that the shift of the actuation voltage of a MEMS Capacitive radio frequency also varies soon after. To illustrate this last point, FIG. 10 shows the temporal variation over 200 s of the offset of the actuation voltage of a capacitive radiofrequency MEMS 20 for a dielectric layer 16 made of silicon nitride having the stationary state before the application of the predefined voltage, here 60 V on 255 nm.

Thus, it is possible to obtain numerous first examples of variation in the doping rate.

The material, here silicon nitride for example, can be P or N doped depending on the type of carriers that can be injected. The area to be doped will be determined by calculation, and corresponds to the distribution of charges in the insulator after a sufficiently long electrical stress, distribution which is presented in Figure 11 for the case of a single trap. This distribution varies according to the properties of the dielectric and the conditions of use of the component (applied electric field). If, for example, several levels of traps contribute to the accumulation of charges in the dielectric, the distribution of trapped charges will consist of several peaks at the start of electrical stress (see Figure 12 for two traps). The spatial distribution will then change with the deformation of the conduction band, the peaks may approach and become indistinguishable or the contribution of one of the traps may become negligible.

The zone is doped P in the event of accumulation of electrons, and N in the event of accumulation of holes. In the case of silicon nitride, the doping P is, for example, carried out with arsenic or boron while the doping N is, for example, carried out with phosphorus or fluorine. In some cases, doping is carried out directly during deposition by using suitable precursor gases. Alternatively, doping is done by implanting ions. A deposition method such as atomic layer deposition also called ALD referring to the term "Atomic Layer Deposition" makes it possible to synthesize a dielectric layer 16 having a suitable spatial distribution of dopants. Indeed, the control of the composition during the deposition is carried out with atomic scale precision.

After actuation voltage offset measurements on capacitive radiofrequency MEMS 20 and simulations, it is then possible to determine the drift value of the actuation voltage (denoted V _P | in FIG. 13, PI referring to the term "pull-in") and associated load distribution. If for an applied voltage of 60V and a given dielectric material, the AV offset reaches approximately 15V, the dielectric layer 16 is doped to allow actuation of the membrane at 45V. The membrane holding voltage V _h must also be less than 15V to avoid sticking of the membrane by the action of the charges in the dielectric layer 16 (see FIG. 13 which presents the variation of the parameter S ₂ i corresponding to a power transmission coefficient by the capacitive device 12 as a function of the actuation voltage V _P |). Using all the preceding analyzes, this results in a first case of the first example of a dielectric layer 16, the model of which makes it possible to validate that the condition according to which the relative variation in capacitance for a predefined voltage applied to the dielectric layer 16 is less than or equal to 3.10 ' ³

The dielectric has three zones: a first zone without dopant, a second zone having a distribution of dopants and a third zone without dopant. The material is a binary or ternary material.

The first zone and the third zone have a spatial extension of 4 nm.

The distribution of dopants in the second zone is given by the following formula:

Or :

• Ώ (χ) is the spatial distribution of dopants;

• y is a predefined value, typically 10 nm;

• x _Qi are values varying between 5 nm and 10 nm;

• is a value varying between 4 nm and 6 nm, and • A and Bi are weighting coefficients depending in particular on the predefined voltage.

The above formula is a formula resulting from the following physical phenomena: thermal effects, the tunnel effect at the level of each trap. The half Lorentzian formula —------- is used to compensate for the thermal effects while the ^2π Qr) + (χ-χι) ² sum is used to compensate for the tunnel effects at the level of each trap (hence the dependence on i, i being the number of traps and x _Qi corresponding to the position of the trap).

As these phenomena vary according to the predefined voltage, the coefficients change but this shows that the proposed structure makes it possible to verify the condition according to which the relative variation in capacitance for a predefined voltage applied to the dielectric layer 16 is less than or equal to 3.10 ′ ³ and this for several predefined voltages by modifying only the parameters y, x _oi , x _lt A and Bi.

In the second example, for simplicity, it is assumed that the doping rate remains identical and that only the stoichiometry of the elements can vary from one sublayer to another sublayer.

The model makes it possible to show that the electric field varies fairly quickly along the interfaces and then more slowly at the center of the dielectric layer 16. FIG. 14 illustrates such a variation in the case of a dielectric layer 16 made of silicon nitride and enlarged in Figure 15.

The potential seen by the electrons therefore presents a break in slope at the point where the electric field makes a jump and which corresponds to the zone where the barycenter of the charge is located (at about 5 nm deep in the dielectric layer 16) . The dotted line in Figure 15 is a guide for the eye to visualize the break in slope. If a contribution corresponding to a constant electric field is subtracted from this potential, the variation in height of the conduction band is obtained which would allow the appearance of a homogeneous current throughout the thickness of the dielectric layer, as visible on Figure 16.

Because of this conduction band, in a second example of a dielectric layer 255 nm thick and operating at 60V, it is necessary to impose the stoichiometric gradient of each layer according to three zones:

- A first zone extending between 0 to 5 nm with gradient (for example linear) of stoichiometry between SiN ₁₃₃ and SiN ₁₄₄₄ ;

- a second zone extending between 5 nm and 250 nm with a constant stoichiometry;

a third zone extending between 250 nm and 255 nm having a stoichiometric gradient from SiN _1i44 to SiN _1i55 .

The use of the model makes it possible to show that such a second example makes it possible to obtain a relative variation in capacitance for a predefined voltage applied to the dielectric layer which is less than or equal to 3.10 ′ ³ .

The extension to other examples using the model is immediate by cleverly playing on at least one of the elements stoichiometry and the doping rate.

From the previous examples, it follows that the following properties are interesting:

- The dielectric layer 16 has at least two sub-stacks (zones in the two previous examples), generally three sub-stacks, the sub-layers of at least one sub-stack having the same materials.

- the dielectric layer 16 has sub-stacks among which the extreme sub-stacks of the dielectric layer 16 have a doping gradient greater than 8.10 ²² / m ³ which allows a variation between 0 and 1.5.10 ¹⁴ / m ² on 2 nm.

- the spatial evolution of the doping rate for the materials of at least part of the sublayers is a weighted sum of a Lorentzian function and a Gaussian function.

- The dielectric layer 16 has at least one under-stack in which revolution of the stoichiometric coefficient of an element as a function of the under-layers follows a linear progression.

- the dielectric layer 16 has a current density less than 1.10 ' ⁴ A.rri 2

Furthermore, it appears that the model makes it possible to envisage a method for determining the material of the dielectric layer 16, the method comprising the supply of a predefined voltage and the optimization of the materials of each sublayer to obtain that the variation relative capacity for a predefined voltage applied to the dielectric layer 16 is less than or equal to 3.10 ' ³ .

The method is preferably carried out by computer. More precisely, it is the interaction of a computer program product with the system which makes it possible to implement a determination process.

The system is a computer.

More generally, the system is an electronic computer capable of manipulating and / or transforming data represented as electronic or physical quantities in system registers and / or memories into other similar data corresponding to physical data in memories, registers or other types of display, transmission or storage devices.

The system includes a processor including a data processing unit, memories and an information carrier. The system also includes a keyboard and a display unit.

The computer program product contains a readable medium.

A readable medium of information is a medium readable by the system, usually by the data processing unit. The readable information medium is a medium suitable for storing electronic instructions and capable of being coupled to a bus of a computer system.

By way of example, the readable information medium is a floppy disk or flexible disk (from the English name of "floppy disk"), an optical disk, a CD-ROM, a magneto-optical disk, a ROM memory, a RAM memory, an EPROM memory, an EEPROM memory, a magnetic card or an optical card.

On the readable information carrier is stored a computer program comprising program instructions.

The computer program is loadable on the data processing unit and is adapted to cause the implementation of the determination method when the computer program is implemented on the data processing unit.

Claims (10)

1, -Dielectric layer (16) intended to interact with two electrodes (14, 18) to form a capacitive device (12), the dielectric layer (16) being a stack of superimposed sublayers, each sublayer having a thickness less than 1 nanometer, each sublayer being made of a doped or undoped material, the material consisting of several chemical elements, each material of an sublayer varying with respect to the other materials of the other sublayers at most only by at least one of the stoichiometry of the elements and the doping rate, the materials of each sublayer being chosen so that the relative variation in capacitance for a predefined voltage applied to the dielectric layer (16) is less than or equal to 3.10 ' ³ . 2, - Dielectric layer according to claim 1, wherein the dielectric layer (16) has at least two under-stacks, the under-layers of at least one under-stack having the same materials. 3, - Dielectric layer according to claim 1 or 2, in which the dielectric layer (16) has underpacks among which the extreme underpacks of the dielectric layer (16) have a doping gradient greater than 8.10 ²² / m ³ . 4, - Dielectric layer according to any one of claims 1 to 3, in which the spatial evolution of the doping rate for the materials of at least part of the sublayers is a weighted sum of a Lorentzian function and d 'a Gaussian function. 5, - Dielectric layer according to any one of claims 1 to 4, in which the dielectric layer (16) has at least one under-stack in which revolution of the stoichiometric coefficient of an element as a function of the under-layers follows a progression linear. 6, - Capacitive device (12) comprising two electrodes (14, 18) and a dielectric layer (16) intended to interact with the two electrodes (14, 18), the dielectric layer (16) being according to any one of claims 1 to 5. 7, - Capacitive device (12) according to claim 6, wherein the capacitive device (12) is a microelectromechanical system (20). 8, - Method for determining the material of a dielectric layer (16) intended to interact with two electrodes (14, 18) to form a capacitive device (12), the dielectric layer (16) being a stack of superimposed sublayers , each sublayer having a thickness of less than 1 nanometer, each sublayer being made of a doped or undoped material, the material consisting of several chemical elements, each material of an sublayer varying with respect to the other materials of the other sublayers layers at most only by at least one of the stoichiometry of the elements and the doping rate, the method comprising: - the supply of a predefined voltage, and - Optimization of the materials of each sublayer to obtain that the relative variation in capacitance for a predefined voltage applied to the dielectric layer (16) is less than or equal to 3.10 ' ³ C. 9, - Computer program product comprising a readable information medium, on which is stored a computer program comprising program instructions, the computer program being loadable on a data processing unit and suitable for driving the implementation of a method according to claim 8. 10, - readable medium of information storing a computer program comprising program instructions, the computer program being loadable on a data processing unit and adapted to cause the implementation of a method according to claim 8 when the computer program is implemented on the data processing unit.