WO2019142581A1 - Mis type semiconductor device, method for producing same, and sputtering target which is used for production of same - Google Patents

Mis type semiconductor device, method for producing same, and sputtering target which is used for production of same Download PDF

Info

Publication number
WO2019142581A1
WO2019142581A1 PCT/JP2018/046719 JP2018046719W WO2019142581A1 WO 2019142581 A1 WO2019142581 A1 WO 2019142581A1 JP 2018046719 W JP2018046719 W JP 2018046719W WO 2019142581 A1 WO2019142581 A1 WO 2019142581A1
Authority
WO
WIPO (PCT)
Prior art keywords
fluoride
layer
semiconductor device
mis
type semiconductor
Prior art date
Application number
PCT/JP2018/046719
Other languages
French (fr)
Japanese (ja)
Inventor
貴弘 長田
知京　豊裕
Original Assignee
国立研究開発法人物質・材料研究機構
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 国立研究開発法人物質・材料研究機構 filed Critical 国立研究開発法人物質・材料研究機構
Priority to JP2019565774A priority Critical patent/JP6846834B2/en
Publication of WO2019142581A1 publication Critical patent/WO2019142581A1/en

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a MIS type semiconductor device, a method of manufacturing the same, and a sputtering target used in the manufacture thereof, and in particular, the dielectric constant of the insulating film is high, the band gap is wide, the interface state is difficult to form thereon, and the leakage current
  • the present invention relates to a MIS type semiconductor device having excellent characteristics.
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • MIS Metal-Insulator-Semiconductor
  • the gate capacitance Cox is proportional to the relative dielectric constant and inversely proportional to the thickness of the gate insulating film. Focusing on this relationship, a high dielectric constant insulating film (High-k film) using an insulating film having a dielectric constant higher than that of a silicon oxide film (SiO 2 film) conventionally used as a main gate insulating film is used. Development of the transistor which has been carried out is vigorously promoted (see Patent Document 1).
  • the physical film thickness necessary to obtain the same gate capacitance Cox can be increased, and the tunnel leak current can be suppressed.
  • the relative dielectric constant of the SiO 2 film is about 3.9. From these reasons, hafnium oxide film (HfO 2 ), zirconium oxide film (ZrO 2 ), alumina (Al 2 O 3 ) have been used as high-k films (high-k gate insulating films) under development. And their oxide films such as silicates and aluminates, and rare earth oxide films.
  • the oxide-based high-k gate insulating film tends to form an undesired oxide layer at the semiconductor interface, and the oxide layer reduces the gate capacitance Cox and reduces the current drive capability Gm and the like. there were. That is, the gate insulating film becomes a laminated film of the High-k film and its oxide layer to lower the effective dielectric constant of the gate insulating film, and the effective gate insulating film becomes thicker. There is a problem of reducing the current drive capability Gm and the like. Furthermore, there is a problem that a level tends to be generated in the oxide layer or its interface which is not desired, and the electrical characteristics are easily degraded or destabilized.
  • Patent Document 2 describes the use of fluorides of gadolinium (Gd) and lanthanum (La).
  • Non-Patent Document 1 In power semiconductors, low leakage current is an important requirement, so reduction of leakage current is strongly required.
  • An object of the present invention is to provide a MIS type semiconductor device having a relatively large gate capacitance Cox and adapted to high electric field applications, particularly power semiconductor applications, and to provide a method of manufacturing the MIS type semiconductor device.
  • the problem to be solved by the present invention is an MIS type semiconductor device having a high dielectric constant insulating film, having a small leak current, without forming an intermediate layer at the interface between the semiconductor and the insulating film. And a method of manufacturing the same.
  • (Configuration 1) A MIS type semiconductor device comprising a semiconductor layer, an insulator layer, and a conductor layer, wherein the insulator layer is sandwiched between the semiconductor layer and the conductor layer.
  • the insulator layer comprises hafnium fluoride and lanthanum fluoride,
  • the MIS type semiconductor device whose volume ratio of said hafnium fluoride to said lanthanum fluoride is 0.35 or more and 0.6 or less.
  • the insulator layer is an amorphous insulating film comprising hafnium fluoride and lanthanum fluoride
  • the MIS-type semiconductor device according to Configuration 1 wherein a volume ratio of the hafnium fluoride to the lanthanum fluoride is 0.35 or more and 0.6 or less.
  • Configuration 3 The MIS type semiconductor device according to configuration 1 or 2, wherein the hafnium fluoride is HfF 4 and the lanthanum fluoride is LaF 3 .
  • Configuration 4 6.
  • (Configuration 5) 6. The MIS type semiconductor device according to any one of constitutions 1 to 3, wherein the volume ratio of said hafnium fluoride to said lanthanum fluoride is 0.5 or more and 0.6 or less.
  • (Configuration 6) 5. The MIS-type semiconductor device according to any one of constitutions 1 to 5, wherein the semiconductor layer is made of a non-oxide semiconductor.
  • (Configuration 7) 7. The MIS type semiconductor device according to any one of constitutions 1 to 6, wherein the semiconductor layer is made of a semiconductor including any one selected from the group of GaN, Ge, Si, SiC, and diamond.
  • a method of manufacturing a MIS semiconductor device comprising: an insulator layer forming step of forming an insulator layer on a substrate having at least a semiconductor layer on the surface; and a conductor layer forming step of forming a conductor layer on the insulator layer.
  • the insulator layer comprises hafnium fluoride and lanthanum fluoride
  • a manufacturing method of MIS type semiconductor device whose volume ratio of said hafnium fluoride to said lanthanum fluoride is 0.35 or more and 0.6 or less.
  • the insulator layer is an amorphous insulating film comprising hafnium fluoride and lanthanum fluoride, 9.
  • (Configuration 15) The method for manufacturing a MIS-type semiconductor device according to any one of constitutions 8 to 14, wherein the insulator layer is formed by a vapor deposition method.
  • (Configuration 16) The method for manufacturing an MIS-type semiconductor device according to any one of constitutions 8 to 14, wherein the insulator layer is formed by a sputtering method.
  • (Configuration 17) Sputtering targets, including hafnium fluoride and lanthanum fluoride.
  • (Configuration 18) Sputtering target consisting of hafnium fluoride and lanthanum fluoride.
  • (Configuration 19) The sputtering target according to Configuration 17 or 18, wherein a volume ratio of the hafnium fluoride to the lanthanum fluoride is 0.35 or more and 0.6 or less.
  • a high dielectric constant wide band gap insulating film can be formed on a semiconductor without forming an undesired intermediate layer such as an oxide layer. Furthermore, the leakage current that is important for power semiconductors is also small. Therefore, the present invention provides a MIS type semiconductor device and a MIS type semiconductor device having a wide band gap high-k insulating film, a low level at an interface or the like, and a small leak current.
  • the MIS type semiconductor device according to the present invention is suitable not only for logic applications but also for power applications where low leakage current is required.
  • FIG. 2 is a cross-sectional view showing the MIS structure of the present invention.
  • the TEM image which shows the state of the interface of a semiconductor layer and an insulating film.
  • Sectional drawing which shows the structure of MISFET of this invention.
  • Sectional drawing which shows the structure of 2nd MISFET by this invention.
  • FIG. 19 is a main-portion cross-sectional view showing the manufacturing process of the second MISFET;
  • FIG. 8 is a relationship diagram showing the relationship of band gaps of substances.
  • the characteristic view which shows the composition ratio dependence of a valence band upper end and a band gap.
  • the characteristic view which shows the composition ratio dependence of an electric current density and an effective dielectric constant.
  • a fluoride layer (hereinafter also referred to as Hf + La fluoride layer) 2 containing hafnium fluoride and lanthanum fluoride and a conductor layer 3 are sequentially formed on a semiconductor layer 1 It has a formed structure.
  • a general-purpose semiconductor can be used as the material of the semiconductor layer 1.
  • a non-oxidizing semiconductor can be preferably used.
  • GaN 3.4 eV
  • SiC 2.86 eV
  • ZnS 3.6 eV
  • AlN relatively wide band gap
  • diamond 6.5 eV
  • Si and Ge can be particularly preferably used from the viewpoint of being used for general use
  • GaN, SiC, and diamond from the viewpoint of high withstand voltage and high power handling, which are features of the present invention.
  • GaN has a band gap of 3.4 eV, and has a doubled or more saturated electron velocity (V sat ) compared to Si and GaAs, about 10 times that of Si, and about 7.5 times that of GaAs It has an electric field strength (E c ).
  • V sat saturated electron velocity
  • E c electric field strength
  • GaN is approximately 27 times that of Si and GaAs. The size is about 15 times the size also in comparison. From these facts, GaN is a semiconductor having an overwhelming advantage, and can be particularly preferably used.
  • These semiconductors may be used alone, or the semiconductor layer 1 may be divided into regions, and any one or more of these materials may be added to each region, or any other one or more of these semiconductor materials may be combined. May be used. Since the Hf + La fluoride layer 2 has a wide band gap of 9.4 eV as described later, it has the potential to allow the combined use of various semiconductor materials.
  • a dopant is added to the semiconductor layer 1 to form a desired type semiconductor layer 1 such as n-type or p-type.
  • the dopants may be those conventionally used for the semiconductor material.
  • Ga is preferably used in order to form the n-type semiconductor layer 1 using GaN.
  • the Hf + La fluoride layer 2 contains hafnium fluoride and lanthanum fluoride, and the volume ratio of hafnium fluoride to lanthanum fluoride is 0.35 or more and 0.6 or less, preferably 0.4 or more and 0.6 or less, and further Preferably it is a layer or film which is 0.5 or more and 0.6 or less.
  • the Hf + La fluoride layer 2 is composed of hafnium fluoride and lanthanum fluoride, and the volume ratio of hafnium fluoride to lanthanum fluoride is 0.35 or more and 0.6 or less, preferably 0.4 or more and 0.6 or less. It is still more preferable that the layer or film be further preferably 0.5 or more and 0.6 or less.
  • LaF 3 is preferable as the lanthanum fluoride
  • HfF 4 is preferable as the hafnium fluoride.
  • the Hf + La fluoride layer 2 is preferably not amorphous (amorphous insulating film) from the viewpoint of obtaining stable electrical characteristics while being hardly affected by the crystal lattice matching with the semiconductor layer 1 or the like.
  • the ionic radii of LaF 3 and HfF 4 are about 0.12 nm and 0.08 nm, respectively, and there is a difference of about 50% between the ionic radii of both. In general, when the difference in ion radius is more than 15%, the amorphization tends to proceed, so the Hf + La fluoride layer 2 has a property of becoming easily amorphous.
  • the Hf + La fluoride layer 2 As described in the Example, by making the Hf + La fluoride layer 2 in such a configuration, a wide band gap, a high valence band top, a high effective dielectric constant, and a low current density (low leak current) are obtained. Can. Further, in this configuration, it is difficult to form an intermediate layer at the interface between the Hf + La fluoride layer 2 and the semiconductor layer 1, and it is difficult to generate a level in the layer and interface of the Hf + La fluoride layer 2. Therefore, it is possible to provide a MIS type semiconductor device having a relatively large gate capacitance Cox and adapted to high electric field applications, particularly power semiconductor applications.
  • the Hf + La fluoride layer 2 can be formed by vapor deposition. It is also possible to form a film by sputtering.
  • the substrate temperature it is preferable to set the substrate temperature to room temperature (23 ° C.) or more and 400 ° C. or less.
  • room temperature 23 ° C.
  • the dielectric constant tends to decrease.
  • the substrate temperature exceeds 450 ° C.
  • the electrical characteristics deteriorate
  • the temperature exceeds 500 ° C.
  • the surface roughness of the semiconductor substrate also becomes so large that it can be visually recognized, and the characteristic degradation becomes remarkable.
  • the film formation of the Hf + La fluoride layer 2 by a sputtering method because it is excellent in throughput and easy to improve in-plane uniformity.
  • the RF sputtering method is preferable because it is easy to increase the throughput.
  • noble gases such as argon (Ar) gas and krypton (Kr) gas can be preferably used as the sputtering gas.
  • a sputtering target containing hafnium and lanthanum fluoride more preferably a sputtering target consisting of hafnium and lanthanum fluoride can be preferably used.
  • the volume ratio of hafnium fluoride to lanthanum fluoride in the sputtering target is preferably 0.35 or more and 0.6 or less.
  • this sputtering target can be produced by the sintering method. Using this sputtering target, it is possible to form a desired Hf + La fluoride layer 2 with high throughput, which is easy to handle and has high in-plane uniformity.
  • NbF 5 has a sublimation temperature of about 100 ° C., and controllability at the time of forming the film is insufficient. there were.
  • the sublimation temperature of HfF 4 is about 350 ° C., there is no particular problem in the controllability of the Hf + La fluoride layer 2 formation.
  • the thickness of the Hf + La fluoride layer 2 is preferably 1 nm or more and 100 nm or less, and more preferably 5 nm or more and 10 nm or less.
  • the film thickness is less than 5 nm, a tunnel leak current starts to appear, and when it is 1 nm or less, the tunnel current becomes remarkable.
  • the film thickness exceeds 100 nm, it becomes difficult to obtain a sufficient capacitance Cox.
  • FIG. 2 is a cross-sectional TEM (Transmission Electron Microscope) photograph when a HfF 4 layer (in the case of (a)) and an Hf + La fluoride layer (in the case of (b)) are formed on a GaN substrate by vacuum evaporation.
  • the substrate temperature at the time of vacuum deposition was 300 ° C., and a TEM apparatus JEM-2100F (manufactured by JEOL) was used. From these results, it can be seen that the Hf + La fluoride layer is formed directly on the GaN semiconductor without forming an intermediate layer by oxidation or mutual diffusion, as in the case of the HfF 4 layer.
  • the conductor layer 3 is made of a conductive film such as polysilicon to which a metal or a dopant is added.
  • a metal gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), aluminum (Al), chromium (Cr), tantalum (Ta) etc.
  • gold Au
  • silver Ag
  • copper Cu
  • platinum platinum
  • Pt palladium
  • Pd tungsten
  • Ti titanium
  • Al chromium
  • an alloy such as AlCu, CuNiFe or NiCr, a silicide such as WSi or TiSi, or a metal compound such as WN, TiN, CrN or TaN can also be used.
  • an appropriate material may be selected from among such materials in consideration of conductivity, work function, processability, and the like.
  • the first MISFET (102) of the present invention is, as shown in FIG. 3 which is a cross-sectional view of the main part, a semiconductor layer 1, an Hf + La fluoride layer, and an Hf + La fluoride layer pattern 2a having a pattern for drain and source formed. , Gate 3a, source 4a and drain 5a.
  • the volume ratio of hafnium fluoride to lanthanum fluoride is 0.35 or more and 0.6 or less, preferably 0.4 or more and 0.6 or less, and more preferably 0.5 or more and 0.6 or less. It consists of the material which consists of the following.
  • LaF 3 is preferable as the lanthanum fluoride
  • HfF 4 is preferable as the hafnium fluoride.
  • the Hf + La fluoride layer pattern 2a is made of a film in an amorphous (amorphous insulating film) state from the viewpoint of being hardly affected by the crystal lattice matching with the semiconductor layer 1 and obtaining stable electrical characteristics. Is preferred.
  • the gate 3a, the source 4a and the drain 5a are made of a conductive film such as metal, alloy, metal compound, silicide, polycide or polysilicon to which a dopant is added. Specifically, the materials exemplified as the conductive layer 3 can be mentioned.
  • the temperature in the case of forming the Hf + La fluoride layer by vacuum evaporation is preferably room temperature (23 ° C.) or more and 450 ° C. or less in order to obtain good electrical characteristics. Further, after forming the Hf + La fluoride layer and before forming the conductive film constituting the gate 3a, it is preferable to perform heat treatment using nitrogen gas (N 2 gas) in order to improve the electrical characteristics of the MISFET.
  • N 2 gas nitrogen gas
  • the pressure of nitrogen gas is preferably 1 Pa or more and 2000 hPa or less, and the temperature is preferably 200 ° C. or more and 500 ° C. or less.
  • the mixing ratio of nitrogen gas and hydrogen gas is 1% to 5% by volume ratio of hydrogen gas to nitrogen gas 1
  • the pressure of mixed gas is 1 Pa to 2000 hPa
  • the temperature is 200 ° C.
  • the temperature is preferably 500 ° C. or less.
  • the heat treatment may be performed by a laser annealing, a flash lamp annealing, or the like in addition to a heating furnace with a heater, a heating furnace with a lamp, a hot plate, and the like.
  • the second MISFET (103) of the present invention is, as shown in FIG. 4 which is a cross-sectional view of the main part, a semiconductor layer 1, an Hf + La fluoride layer 12b, a gate 13b, a source 14b, a drain 15b and a patterned interlayer film. It consists of 21b.
  • the gate 13b has a buried structure.
  • the gate 13b, the source 14b, and the drain 15b are made of a conductive film such as metal, alloy, metal compound, silicide, polycide, or polysilicon to which a dopant is added, similarly to the first MISFET (102).
  • the second MISFET (103) can be manufactured by the process shown below.
  • the manufacturing method will be described with reference to FIG. 5 which illustrates the manufacturing process using the main part sectional view.
  • the interlayer film 21 is formed on the semiconductor layer 1 (see FIG. 5A).
  • the interlayer film 21 include insulating films such as SiO x formed by plasma CVD.
  • an opening for producing a gate is formed in the interlayer film 21 by lithography and dry etching to form an interlayer film pattern 21a (FIG. 5B).
  • the Hf + La fluoride layer 12a is formed on the semiconductor substrate 1 (FIG. 5 (c)).
  • the membrane is preferably deposited conformally.
  • the lanthanum fluoride layer 12a formed on the upper surface of the interlayer film pattern 21a is removed by a method such as CMP (Chemical Mechanical Polishing) or etch back, and only the opening of the interlayer film pattern 21a is formed.
  • the obtained Hf + La fluoride layer 12b is obtained (FIG. 5 (d)).
  • the conductor film 13a is deposited (FIG. 5 (e)), and the conductor film 13a formed on the upper surface of the interlayer film pattern 21a is subsequently removed by a method such as CMP or etch back.
  • a conductor film pattern in which a conductor film is embedded is formed in the groove where the Hf + La fluoride layer 12b is exposed, and the conductor film pattern is used as the gate 13b (FIG. 5 (f)). Thereafter, lithography and dry etching are used to form an interlayer film pattern 21b having openings 22 and 23 in the interlayer film pattern 21a (FIG. 5 (g)). Then, a conductor film is embedded in the openings 22 and 23, and the conductor film patterns thereof are respectively used as a source 14b and a drain 15b as a second MISFET (103) (FIG. 5 (h)).
  • the Hf + La fluoride layer 12b is processed by CMP or etch back, it is not easy to perform dry etching with less damage to the semiconductor layer. Also in a film made of fluoride (a film made of HF 4 and LaF 3 ), a MISFET with less electrical damage can be obtained.
  • the third MISFET (103) of the present invention comprises semiconductor layers 31a, 31b, 31c, Hf + La fluoride layer 32, gate 33, source 34, and drain 35, as shown in FIG. .
  • the semiconductor layers 31a, 31b and 31c are semiconductor layers made of different materials.
  • 31a is an n-type semiconductor made of InAs
  • 31b is an intrinsic semiconductor made of GaN
  • 31c is a p-type semiconductor made of GaSb It can be mentioned.
  • the Hf + La fluoride layer 32 has a wide band gap of 9.4 eV, and the upper limit of the valence band (upper end of the valence band) E VBM and the lower end of the conductor E CBM include many semiconductor materials including the above semiconductor materials.
  • the gate 33 can be formed by a processing method using a sidewall.
  • the sidewall-based processing method is a processing method using the difference between the etching rate in the longitudinal direction and the lateral direction when anisotropic dry etching is performed and the etching rate around the side wall, along the side wall (side wall). It is a processing method in which a workpiece remains.
  • the gate electrode
  • the gate can be formed in a self-aligned manner in the sidewall portion, and the dimensional accuracy important as the gate can be high.
  • the side wall is formed vertically.
  • the upper end portion (shoulder portion) of the gate 33 has a shape in which the corner is scraped.
  • Example 1 In Example 1, the composition ratio dependency of the band gap, the valence band upper end, and the leak current characteristic of the Hf + La fluoride layer was evaluated. Specifically, an Hf + La fluoride film composed of HfF 4 and LaF 3 was formed at different volume ratios x, and the band gap, valence band upper end and leak current characteristics of the film were measured. Here, this film is described as (HfF 4 ) x (LaF 3 ) 1 -x (x is a value of 0 to 1).
  • a SrTiO 3 substrate which is stable against a material composed of HfF 4 and LaF 3 and which can obtain a flat surface at the atomic layer level is used.
  • the crystal plane is (100).
  • this substrate is doped with 0.5 wt% of Nb.
  • the (HfF 4 ) x (LaF 3 ) 1-x film was formed by vacuum evaporation.
  • the film thickness was 50 nm, and the film was formed at a vacuum degree of 5 ⁇ 10 ⁇ 8 Pa and a substrate temperature of 100 ° C.
  • the surface roughness of the (HfF 4 ) x (LaF 3 ) 1-x film formed was almost the same as the surface roughness of the substrate.
  • the state of this film was measured by XRD (X-ray diffraction: D8 Discover Super Speed with GADDS, manufactured by Bruker AXS) to confirm that this film was an amorphous (amorphous) film. .
  • the valence band upper end E V B M changes around 6 eV, and in particular, when the volume ratio x of HfF 4 to LaF 3 is in the range of 0.35 to 0.6, it becomes a maximum value exceeding 6 eV.
  • the band gap E g maintains about 9.5 at a volume ratio x from 0 to 0.6, but when it exceeds 0.6, the value becomes smaller, and the volume ratio x is 0.85.
  • the band gap E g of about 8.75 and HfF 4 is almost the same. Therefore, in order to obtain a wide band gap E g , it is preferable to set the volume ratio x to 0.6 or less.
  • the band gap Eg maintains a value exceeding 9 and the energy position of the valence band upper end E VBM changes at around 6 eV, so GaN was used as the semiconductor layer In the case, it was confirmed that an energy difference of about 3 eV at the lower end of the conductor can be maintained.
  • the measurement results of the current density J and the effective dielectric constant ⁇ are shown in FIG.
  • the effective dielectric constant ⁇ monotonously decreases as the volume ratio x increases, that is, as the ratio occupied by HfF 4 increases, but has a relatively high value of about 12 or more when the volume ratio x is 0.6 or less.
  • the (HfF 4 ) x (LaF 3 ) 1-x film having the volume ratio x of 0.6 or less is HfO 2 It can be said that it has the same effective dielectric constant ⁇ as the film.
  • the current density J has a characteristic that it decreases as the volume ratio x increases from 0, and increases as the volume ratio x increases after the volume ratio x is minimized at about 0.55.
  • the volume ratio x is preferably 0.35 or more and 0.7 or less, since a leakage current of a level lower than 10 ⁇ 6 A / cm 2 is required for the MIS type semiconductor device for power applications.
  • the volume ratio x is required to be 0.35 or more and 0.6 or less, and the leakage current is more From the viewpoint of lowering the volume ratio, the volume ratio x is preferably 0.4 or more and 0.6 or less, and more preferably 0.5 or more and 0.6 or less. When the volume ratio x is 0.5 or more and 0.6 or less, the leak current can be reduced to the order of 10 ⁇ 8 A / cm 2 .
  • an insulating film having a relatively high dielectric constant and a wide band gap of about 9.4 eV can be formed without forming an undesired intermediate layer such as an oxide layer. It can be formed on a semiconductor. Furthermore, the leakage current that is important for power semiconductors is also small. Therefore, according to the present invention, a MIS type semiconductor device having a wide band gap high-k insulating film, a low level at an interface or the like, and a small leak current is provided. Since MIS type semiconductor devices capable of extracting the performance corresponding to the high electric field of semiconductors with wide band gaps such as GaN can be provided, applications to power applications where low leakage current is required as well as logic applications are expected. Ru.
  • a MISFET using this insulating film as a gate insulating film has wide band gap of the gate insulating film, and thus has versatility that can be combined with various semiconductors. From the above, the MIS type semiconductor device of the present invention may be used in many industrial fields.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

Provided is an MIS type semiconductor device which has an insulating film that has high dielectric constant and wide band gap, while being not susceptible to the formation of an intermediate layer between a semiconductor and the insulating film, and which has less interface states and less leakage current. The problem is able to be solved by an MIS type semiconductor device which comprises a semiconductor layer, an insulator layer and a conductor layer, with the insulator layer being sandwiched between the semiconductor layer and the conductor layer, and which is configured such that: the insulator layer contains a hafnium fluoride and lanthanum fluoride; and the volume ratio of the hafnium fluoride to the lanthanum fluoride is from 0.35 to 0.6 (inclusive).

Description

ＭＩＳ型半導体装置およびその製造方法、並びにその製造に用いるスパッタリングターゲットMIS-type semiconductor device, method for manufacturing the same, and sputtering target used for manufacturing the same
　本発明は、ＭＩＳ型半導体装置およびその製造方法、並びにその製造に用いるスパッタリングターゲットに係り、特に、絶縁膜の誘電率が高く、バンドギャップが広く、その上で界面準位を作りにくく、リーク電流特性に優れるＭＩＳ型半導体装置に関する。 The present invention relates to a MIS type semiconductor device, a method of manufacturing the same, and a sputtering target used in the manufacture thereof, and in particular, the dielectric constant of the insulating film is high, the band gap is wide, the interface state is difficult to form thereon, and the leakage current The present invention relates to a MIS type semiconductor device having excellent characteristics.
　ＭＩＳ（Ｍｅｔａｌ－Ｉｎｓｕｌａｔｏｒ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）型半導体装置であるＭＩＳＦＥＴ（Ｍｅｔａｌ　Ｉｎｓｕｌａｔｏｒ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）の高速化に伴い、電界一定のスケーリングのために、トランジスタの微細化が進んでいる。
　ＭＩＳＦＥＴの性能指標の一つは電流駆動能力Ｇｍである。Ｇｍは、移動度μと、ゲート幅Ｗと、ゲート電極、ゲート絶縁膜および半導体基板とで構成されるキャパシタの静電容量（ゲート容量）Ｃｏｘに比例し、ゲート長Ｌに反比例する。そこで、ゲート絶縁膜の薄膜化とゲート長Ｌの微細化によってＭＩＳＦＥＴの高速化が図られてきている。 With the speeding up of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) which is a MIS (Metal-Insulator-Semiconductor) type semiconductor device, miniaturization of the transistor is in progress for scaling of a constant electric field.
One of the performance indexes of the MISFET is the current drive capability Gm. Gm is proportional to the mobility (μ), the gate width W, and the capacitance (gate capacitance) Cox of the capacitor formed of the gate electrode, the gate insulating film, and the semiconductor substrate, and inversely proportional to the gate length L. Therefore, speeding up of the MISFET has been achieved by thinning the gate insulating film and reducing the gate length L.
　ゲート絶縁膜の物理的厚さを２ｎｍ以下まで薄膜化した場合、トンネルリーク電流が増加してゲート電圧印加時の絶縁耐性が著しく低下し、ＭＩＳＦＥＴの消費電力が増加する。
　ゲート容量Ｃｏｘは比誘電率に比例し、ゲート絶縁膜の厚さに反比例する。この関係に着目して、従来、ゲート絶縁膜として主流として使用されてきたシリコン酸化膜（ＳｉＯ２膜）よりも誘電率の高い絶縁膜を用いる高誘電率絶縁膜（Ｈｉｇｈ－ｋ膜）を用いたトランジスタの開発が精力的に進められている（特許文献１参照）。Ｈｉｇｈ－ｋ膜を用いると、同一のゲート容量Ｃｏｘを得るのに必要な物理的膜厚を厚くすることができ、トンネルリーク電流を抑制できる。なお、ＳｉＯ２膜の比誘電率は約３．９である。このようなことから、開発が進められているＨｉｇｈ－ｋ膜（Ｈｉｇｈ－ｋゲート絶縁膜）としては、ハフニウム酸化膜（ＨｆＯ２）、ジルコニウム酸化膜（ＺｒＯ２）、アルミナ（Ａｌ２Ｏ３）、それらのシリケートおよびアルミネート、並びに希土類酸化物膜等の酸化膜が挙げられる。 When the physical thickness of the gate insulating film is reduced to 2 nm or less, the tunnel leak current is increased, the insulation resistance at the time of applying the gate voltage is significantly reduced, and the power consumption of the MISFET is increased.
The gate capacitance Cox is proportional to the relative dielectric constant and inversely proportional to the thickness of the gate insulating film. Focusing on this relationship, a high dielectric constant insulating film (High-k film) using an insulating film having a dielectric constant higher than that of a silicon oxide film (SiO 2 film) conventionally used as a main gate insulating film is used. Development of the transistor which has been carried out is vigorously promoted (see Patent Document 1). When a high-k film is used, the physical film thickness necessary to obtain the same gate capacitance Cox can be increased, and the tunnel leak current can be suppressed. The relative dielectric constant of the SiO 2 film is about 3.9. From these reasons, hafnium oxide film (HfO 2 ), zirconium oxide film (ZrO 2 ), alumina (Al 2 O 3 ) have been used as high-k films (high-k gate insulating films) under development. And their oxide films such as silicates and aluminates, and rare earth oxide films.
　しかしながら、酸化膜系のＨｉｇｈ－ｋゲート絶縁膜は、半導体界面に所望ではない酸化層を形成する傾向があり、その酸化層がゲート容量Ｃｏｘを減らし、電流駆動能力Ｇｍなどを低下させるという問題があった。すなわち、ゲート絶縁膜がＨｉｇｈ－ｋ膜とその酸化層との積層膜となって実効的なゲート絶縁膜の誘電率を低下させ、また、実効的なゲート絶縁膜の膜厚が厚くなって、電流駆動能力Ｇｍなどを低下させるという問題があった。
　さらに、その所望ではない酸化層内やその界面に準位が生じやすく、電気特性の低下や不安定化が起こりやすいという問題があった。 However, the oxide-based high-k gate insulating film tends to form an undesired oxide layer at the semiconductor interface, and the oxide layer reduces the gate capacitance Cox and reduces the current drive capability Gm and the like. there were. That is, the gate insulating film becomes a laminated film of the High-k film and its oxide layer to lower the effective dielectric constant of the gate insulating film, and the effective gate insulating film becomes thicker. There is a problem of reducing the current drive capability Gm and the like.
Furthermore, there is a problem that a level tends to be generated in the oxide layer or its interface which is not desired, and the electrical characteristics are easily degraded or destabilized.
　そこで、Ｈｉｇｈ－ｋゲート絶縁膜として、酸化膜系の膜ではなくフッ化物系の膜を用いることにより、所望ではない膜、特に酸化膜の生成を抑制するという取り組みがある。その例として、ガドリニウム（Ｇｄ）およびランタン（Ｌａ）のフッ化物を用いた記載が特許文献２にある。 Therefore, there is an effort to suppress the formation of an undesired film, particularly an oxide film, by using a fluoride film instead of an oxide film as the high-k gate insulating film. As an example, Patent Document 2 describes the use of fluorides of gadolinium (Gd) and lanthanum (La).
　また、近年、電力、送電、サーバー、鉄道、ハイブリッドを含む電気自動車などの旺盛な需要に基づく要求から、高パワー用途の半導体の市場が急激に拡大している。そして、高い耐圧を得るために、ＧａＮ、ＳｉＣ、ダイヤモンドなどの半導体とワイドバンドギャップのゲート絶縁膜を組み合わせたＭＩＳ型半導体装置の開発が精力的に進められている。
　ランタンフッ化物は、ワイドバンドギャップの絶縁膜であることから、高パワーＭＩＳ型半導体装置用途の絶縁膜としても期待されている。 Also, in recent years, the market for semiconductors for high power applications is rapidly expanding due to demand based on strong demand for electric vehicles including electric power, power transmission, servers, railways and hybrids. Then, in order to obtain a high breakdown voltage, development of a MIS type semiconductor device in which a semiconductor such as GaN, SiC, or diamond is combined with a wide band gap gate insulating film is vigorously promoted.
Since lanthanum fluoride is a wide band gap insulating film, it is also expected as an insulating film for high power MIS type semiconductor device applications.
特開２０１１－５４８７２号公報JP, 2011-54872, A 特許第５１１８２７６号公報Patent No. 5118276 gazette
　しかしながら、ＬａＦ３を絶縁膜としたＭＩＳ半導体装置を作製してその電気特性を調べてみると、その絶縁膜を介して大きなリーク電流が流れるという問題があることがわかった（非特許文献１参照）。パワー半導体では、低リーク電流が重要な要求性能なので、リーク電流の低減が強く求められる。 However, when a MIS semiconductor device using LaF 3 as an insulating film is fabricated and its electrical characteristics are examined, it has been found that there is a problem that a large leak current flows through the insulating film (see Non-Patent Document 1) ). In power semiconductors, low leakage current is an important requirement, so reduction of leakage current is strongly required.
　本発明の目的は、ゲート容量Ｃｏｘが比較的大きく、高電界用途、特にパワー半導体用途に適応するＭＩＳ型半導体装置を提供すること、およびそのＭＩＳ型半導体装置の製造方法を提供することである。 An object of the present invention is to provide a MIS type semiconductor device having a relatively large gate capacitance Cox and adapted to high electric field applications, particularly power semiconductor applications, and to provide a method of manufacturing the MIS type semiconductor device.
　その目的を達成するために、本発明が解決するべき課題は、リーク電流が少なく、半導体と絶縁膜との界面に中間層を形成することなく、かつ高誘電率絶縁膜を有するＭＩＳ型半導体装置およびその製造方法を提供することである。 In order to achieve the object, the problem to be solved by the present invention is an MIS type semiconductor device having a high dielectric constant insulating film, having a small leak current, without forming an intermediate layer at the interface between the semiconductor and the insulating film. And a method of manufacturing the same.
　本発明及びその実施形態の構成を下記に示す。
（構成１）
　半導体層と絶縁体層と導電体層を有し、前記絶縁体層が前記半導体層と前記導電体層で挟まれたＭＩＳ型半導体装置であって、
　前記絶縁体層は、ハフニウムフッ化物およびランタンフッ化物を含み、
　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．３５以上０．６以下である、ＭＩＳ型半導体装置。
（構成２）
　前記絶縁体層は、ハフニウムフッ化物およびランタンフッ化物からなる非晶質絶縁膜であり、
　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．３５以上０．６以下である、構成１に記載のＭＩＳ型半導体装置。
（構成３）
　前記ハフニウムフッ化物はＨｆＦ４であり、前記ランタンフッ化物はＬａＦ３である、構成１または２に記載のＭＩＳ型半導体装置。
（構成４）
　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．４以上０．６以下である、構成１から３の何れか１に記載のＭＩＳ型半導体装置。
（構成５）
　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．５以上０．６以下である、構成１から３の何れか１に記載のＭＩＳ型半導体装置。
（構成６）
　前記半導体層は非酸化物半導体からなる、構成１から５の何れか１に記載のＭＩＳ型半導体装置。
（構成７）
　前記半導体層は、ＧａＮ、Ｇｅ、Ｓｉ、ＳｉＣ、ダイヤモンドの群から選ばれる何れか１を含む半導体からなる、構成１から６の何れか１に記載のＭＩＳ型半導体装置。
（構成８）
　半導体層を少なくとも表面に有する基板上に絶縁体層を形成する絶縁体層形成工程と、前記絶縁体層上に導電体層を形成する導電体層形成工程を含むＭＩＳ型半導体装置の製造方法において、
　前記絶縁体層は、ハフニウムフッ化物およびランタンフッ化物を含み、
　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．３５以上０．６以下である、ＭＩＳ型半導体装置の製造方法。
（構成９）
　前記絶縁体層は、ハフニウムフッ化物およびランタンフッ化物からなる非晶質絶縁膜であり、
　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．３５以上０．６以下である、構成８に記載のＭＩＳ型半導体装置の製造方法。
（構成１０）
　前記ハフニウムフッ化物はＨｆＦ４であり、前記ランタンフッ化物はＬａＦ３である、構成８または９に記載のＭＩＳ型半導体装置の製造方法。
（構成１１）
　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．４以上０．６以下である、構成８から１０の何れか１に記載のＭＩＳ型半導体装置の製造方法。
（構成１２）
　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．５以上０．６以下である、構成８から１０の何れか１に記載のＭＩＳ型半導体装置の製造方法。
（構成１３）
　前記半導体層は非酸化物半導体からなる、構成８から１２の何れか１に記載のＭＩＳ型半導体装置の製造方法。
（構成１４）
　前記半導体層は、ＧａＮ、Ｇｅ、Ｓｉ、ＳｉＣ、ダイヤモンドの群から選ばれる何れか１を含む半導体からなる、構成８から１３の何れか１に記載のＭＩＳ型半導体装置の製造方法。
（構成１５）
　前記絶縁体層は、蒸着法によって形成される、構成８から１４の何れか１に記載のＭＩＳ型半導体装置の製造方法。
（構成１６）
　前記絶縁体層は、スパッタリング法によって形成される、構成８から１４の何れか１に記載のＭＩＳ型半導体装置の製造方法。
（構成１７）
　ハフニウムフッ化物およびランタンフッ化物を含む、スパッタリングターゲット。
（構成１８）
　ハフニウムフッ化物およびランタンフッ化物からなる、スパッタリングターゲット。
（構成１９）
　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．３５以上０．６以下である、構成１７または１８に記載のスパッタリングターゲット。 The configurations of the present invention and its embodiments are shown below.
(Configuration 1)
A MIS type semiconductor device comprising a semiconductor layer, an insulator layer, and a conductor layer, wherein the insulator layer is sandwiched between the semiconductor layer and the conductor layer.
The insulator layer comprises hafnium fluoride and lanthanum fluoride,
The MIS type semiconductor device whose volume ratio of said hafnium fluoride to said lanthanum fluoride is 0.35 or more and 0.6 or less.
(Configuration 2)
The insulator layer is an amorphous insulating film comprising hafnium fluoride and lanthanum fluoride,
The MIS-type semiconductor device according to Configuration 1, wherein a volume ratio of the hafnium fluoride to the lanthanum fluoride is 0.35 or more and 0.6 or less.
(Configuration 3)
The MIS type semiconductor device according to configuration 1 or 2, wherein the hafnium fluoride is HfF 4 and the lanthanum fluoride is LaF 3 .
(Configuration 4)
6. The MIS type semiconductor device according to any one of constitutions 1 to 3, wherein the volume ratio of said hafnium fluoride to said lanthanum fluoride is 0.4 or more and 0.6 or less.
(Configuration 5)
6. The MIS type semiconductor device according to any one of constitutions 1 to 3, wherein the volume ratio of said hafnium fluoride to said lanthanum fluoride is 0.5 or more and 0.6 or less.
(Configuration 6)
5. The MIS-type semiconductor device according to any one of constitutions 1 to 5, wherein the semiconductor layer is made of a non-oxide semiconductor.
(Configuration 7)
7. The MIS type semiconductor device according to any one of constitutions 1 to 6, wherein the semiconductor layer is made of a semiconductor including any one selected from the group of GaN, Ge, Si, SiC, and diamond.
(Configuration 8)
A method of manufacturing a MIS semiconductor device, comprising: an insulator layer forming step of forming an insulator layer on a substrate having at least a semiconductor layer on the surface; and a conductor layer forming step of forming a conductor layer on the insulator layer. ,
The insulator layer comprises hafnium fluoride and lanthanum fluoride,
A manufacturing method of MIS type semiconductor device whose volume ratio of said hafnium fluoride to said lanthanum fluoride is 0.35 or more and 0.6 or less.
(Configuration 9)
The insulator layer is an amorphous insulating film comprising hafnium fluoride and lanthanum fluoride,
9. The method for manufacturing a MIS-type semiconductor device according to Configuration 8, wherein a volume ratio of the hafnium fluoride to the lanthanum fluoride is 0.35 or more and 0.6 or less.
(Configuration 10)
The method for manufacturing an MIS-type semiconductor device according to a constitution 8 or 9, wherein the hafnium fluoride is HfF 4 and the lanthanum fluoride is LaF 3 .
(Configuration 11)
8. The method for manufacturing an MIS-type semiconductor device according to any one of constitutions 8 to 10, wherein a volume ratio of the hafnium fluoride to the lanthanum fluoride is 0.4 or more and 0.6 or less.
(Configuration 12)
7. The method of manufacturing an MIS-type semiconductor device according to any one of constitutions 8 to 10, wherein a volume ratio of the hafnium fluoride to the lanthanum fluoride is 0.5 or more and 0.6 or less.
(Configuration 13)
The method of manufacturing an MIS-type semiconductor device according to any one of constitutions 8 to 12, wherein the semiconductor layer is made of a non-oxide semiconductor.
(Configuration 14)
The method of manufacturing an MIS-type semiconductor device according to any one of constitutions 8 to 13, wherein the semiconductor layer is made of a semiconductor containing any one selected from the group of GaN, Ge, Si, SiC, and diamond.
(Configuration 15)
The method for manufacturing a MIS-type semiconductor device according to any one of constitutions 8 to 14, wherein the insulator layer is formed by a vapor deposition method.
(Configuration 16)
The method for manufacturing an MIS-type semiconductor device according to any one of constitutions 8 to 14, wherein the insulator layer is formed by a sputtering method.
(Configuration 17)
Sputtering targets, including hafnium fluoride and lanthanum fluoride.
(Configuration 18)
Sputtering target consisting of hafnium fluoride and lanthanum fluoride.
(Configuration 19)
The sputtering target according to Configuration 17 or 18, wherein a volume ratio of the hafnium fluoride to the lanthanum fluoride is 0.35 or more and 0.6 or less.
　本発明によれば、高誘電率のワイドバンドギャップ絶縁膜を、酸化層などの所望ではない中間層を形成することなく、半導体上に形成できる。その上で、パワー半導体にとって重要なリーク電流も少ない。
　このため、本発明により、ワイドバンドギャップＨｉｇｈ－ｋ絶縁膜をもち、界面などに準位が少なく、かつリーク電流の少ないＭＩＳ型半導体装置およびＭＩＳ型半導体装置の製造方法が提供される。
　本発明によるＭＩＳ型半導体装置は、ロジック用途はもとより、低リーク電流が求められるパワー用途に好適である。 According to the present invention, a high dielectric constant wide band gap insulating film can be formed on a semiconductor without forming an undesired intermediate layer such as an oxide layer. Furthermore, the leakage current that is important for power semiconductors is also small.
Therefore, the present invention provides a MIS type semiconductor device and a MIS type semiconductor device having a wide band gap high-k insulating film, a low level at an interface or the like, and a small leak current.
The MIS type semiconductor device according to the present invention is suitable not only for logic applications but also for power applications where low leakage current is required.
本発明のＭＩＳ構造を示す断面図。FIG. 2 is a cross-sectional view showing the MIS structure of the present invention. 半導体層と絶縁膜の界面の状態を示すＴＥＭ像。The TEM image which shows the state of the interface of a semiconductor layer and an insulating film. 本発明のＭＩＳＦＥＴの構造を示す断面図。Sectional drawing which shows the structure of MISFET of this invention. 本発明による第２のＭＩＳＦＥＴの構造を示す断面図。Sectional drawing which shows the structure of 2nd MISFET by this invention. 第２のＭＩＳＦＥＴの製造工程を示す要部断面図。FIG. 19 is a main-portion cross-sectional view showing the manufacturing process of the second MISFET; 本発明による第３のＭＩＳＦＥＴの構造を示す断面図。Sectional drawing which shows the structure of 3rd MISFET by this invention. 物質のバンドギャップの関係を示す関係図。FIG. 8 is a relationship diagram showing the relationship of band gaps of substances. 価電子帯上端とバンドギャップの組成比依存性を示す特性図。The characteristic view which shows the composition ratio dependence of a valence band upper end and a band gap. 電流密度と実効誘電率の組成比依存性を示す特性図。The characteristic view which shows the composition ratio dependence of an electric current density and an effective dielectric constant. 硬Ｘ線光電子分光特性図。Hard X-ray photoelectron spectroscopy characteristic diagram. 図１０記載の硬Ｘ線光電子分光特性図のうち体積比率ｘ＝１の場合のもの。10 in the case of volume ratio x = 1 among the hard X-ray photoelectron spectroscopy characteristic diagrams shown in FIG. 図１０記載の硬Ｘ線光電子分光特性図のうち体積比率ｘ＝１の場合のもの（信号強度を１０倍に拡大）。Among the hard X-ray photoelectron spectroscopy characteristic diagrams shown in FIG. 10, the one in the case of volume ratio x = 1 (signal intensity is enlarged by 10 times). 図１０記載の硬Ｘ線光電子分光特性図のうち体積比率ｘ＝０．７１の場合のもの。10 in the case of volume ratio x = 0.71 among the hard X-ray photoelectron spectroscopy characteristic diagrams shown in FIG. 図１０記載の硬Ｘ線光電子分光特性図のうち体積比率ｘ＝０．７１の場合のもの（信号強度を１０倍に拡大）。Among the hard X-ray photoelectron spectroscopy characteristic diagrams shown in FIG. 10, the one for the case of the volume ratio x = 0.71 (the signal intensity is enlarged by 10 times). 図１０記載の硬Ｘ線光電子分光特性図のうち体積比率ｘ＝０．４２の場合のもの。10 in the case of volume ratio x = 0.42 among the hard X-ray photoelectron spectroscopy characteristic diagrams shown in FIG. 図１０記載の硬Ｘ線光電子分光特性図のうち体積比率ｘ＝０．４１の場合のもの（信号強度を１０倍に拡大）。Among the hard X-ray photoelectron spectroscopy characteristic diagrams shown in FIG. 10, the one for the case of the volume ratio x = 0.41 (the signal intensity is enlarged by 10 times). 図１０記載の硬Ｘ線光電子分光特性図のうち体積比率ｘ＝０．１３の場合のもの。In the hard X-ray photoelectron spectroscopy characteristic diagram shown in FIG. 図１０記載の硬Ｘ線光電子分光特性図のうち体積比率ｘ＝０．１３の場合のもの（信号強度を１０倍に拡大）。Among the hard X-ray photoelectron spectroscopy characteristic diagrams shown in FIG. 10, the one for the case of the volume ratio x = 0.13 (the signal intensity is enlarged by 10 times).
　以下、本発明を実施するための形態を、図面を参照しながら説明する。
　本発明のＭＩＳ構造１０１は、図１に示すように、半導体層１上にハフニウムフッ化物およびランタンフッ化物を含むフッ化物層（以下、Ｈｆ＋Ｌａフッ化物層とも称す）２および導電体層３が順次形成された構造になっている。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the MIS structure 101 of the present invention, as shown in FIG. 1, a fluoride layer (hereinafter also referred to as Hf + La fluoride layer) 2 containing hafnium fluoride and lanthanum fluoride and a conductor layer 3 are sequentially formed on a semiconductor layer 1 It has a formed structure.
　半導体層１の材料としては、Ｈｆ＋Ｌａフッ化物層２が広いバンドギャップを有するので、汎用な半導体を用いることができる。その上で、半導体層１とＨｆ＋Ｌａフッ化物層２との界面に所望ではない酸化物中間層を生成しにくいという特性を活かす観点からは、非酸化性の半導体を好んで用いることができる。
　具体的には、半導体として広く用いられているＳｉ、ＧａＡｓ、Ｇｅなどに加え、バンドギャップの比較的広いＧａＮ（３．４ｅＶ）、ＳｉＣ（２．８６ｅＶ）、ＺｎＳ（３．６ｅＶ）、ＡｌＮ（６．３ｅＶ）、ダイヤモンド（６．５ｅＶ）を挙げることができる。この中で、Ｓｉ、Ｇｅは汎用に用いられている観点から、また、ＧａＮ、ＳｉＣ、ダイヤモンドは、本発明の特徴である高耐圧、高パワー対応という観点から、特に好ましく用いることができる。 As the material of the semiconductor layer 1, since the Hf + La fluoride layer 2 has a wide band gap, a general-purpose semiconductor can be used. In addition, from the viewpoint of making it difficult to form an undesired oxide intermediate layer at the interface between the semiconductor layer 1 and the Hf + La fluoride layer 2, a non-oxidizing semiconductor can be preferably used.
Specifically, in addition to Si, GaAs, Ge, etc. widely used as semiconductors, GaN (3.4 eV), SiC (2.86 eV), ZnS (3.6 eV), AlN (relatively wide band gap), etc. 6.3 eV), diamond (6.5 eV) can be mentioned. Among these, Si and Ge can be particularly preferably used from the viewpoint of being used for general use, and GaN, SiC, and diamond from the viewpoint of high withstand voltage and high power handling, which are features of the present invention.
　その中でもＧａＮは、バンドギャップが３．４ｅＶであり、ＳｉやＧａＡｓと比較して２倍以上の飽和電子速度（Ｖｓａｔ）と、Ｓｉの約１０倍、ＧａＡｓの約７．５倍の絶縁破壊電界強度（Ｅｃ）を有する。半導体を用いた高周波・高出力増幅器の性能を比較する指標としてよく用いられるＶｓａｔ・Ｅｃ／２πで表されるＪｏｈｎｓｏｎ指数で比較すると、ＧａＮは、Ｓｉと比較して約２７倍、ＧａＡｓと比較しても約１５倍の大きさであり、これらのことからＧａＮは圧倒的な優位性を有する半導体であり、特に好ましく用いることができる。 Among them, GaN has a band gap of 3.4 eV, and has a doubled or more saturated electron velocity (V sat ) compared to Si and GaAs, about 10 times that of Si, and about 7.5 times that of GaAs It has an electric field strength (E c ). In comparison with the Johnson index represented by V sat · E c / 2π, which is often used as an index for comparing the performance of semiconductor-based high frequency and high power amplifiers, GaN is approximately 27 times that of Si and GaAs. The size is about 15 times the size also in comparison. From these facts, GaN is a semiconductor having an overwhelming advantage, and can be particularly preferably used.
　これらの半導体は、単独でもよいし、半導体層１を領域ごとに区分して、各領域にこれらの何れか１以上の材料、またはこれらの何れか１以上に他の半導体材料が組み合わさったものを用いてもよい。Ｈｆ＋Ｌａフッ化物層２は、後述のように、バンドギャップが９．４ｅＶと広いので、様々な半導体材料の組み合わせ使用を可能にするポテンシャルをもつ。 These semiconductors may be used alone, or the semiconductor layer 1 may be divided into regions, and any one or more of these materials may be added to each region, or any other one or more of these semiconductor materials may be combined. May be used. Since the Hf + La fluoride layer 2 has a wide band gap of 9.4 eV as described later, it has the potential to allow the combined use of various semiconductor materials.
　半導体層１にはドーパントを添加して、ｎ型、ｐ型など所望の型の半導体層１とする。ドーパントはその半導体材料に対して通常用いられているものでよい。例えば、ＧａＮを用いてｎ型の半導体層１を形成するには、Ｇａが好んで用いられる。 A dopant is added to the semiconductor layer 1 to form a desired type semiconductor layer 1 such as n-type or p-type. The dopants may be those conventionally used for the semiconductor material. For example, in order to form the n-type semiconductor layer 1 using GaN, Ga is preferably used.
　Ｈｆ＋Ｌａフッ化物層２は、ハフニウムフッ化物とランタンフッ化物を含み、ランタンフッ化物に対するハフニウムフッ化物の体積比率が、０．３５以上０．６以下、好ましくは０．４以上０．６以下、さらに好ましくは０．５以上０．６以下である層または膜である。
　ここで、Ｈｆ＋Ｌａフッ化物層２は、ハフニウムフッ化物とランタンフッ化物からなり、ランタンフッ化物に対するハフニウムフッ化物の体積比率が、０．３５以上０．６以下、好ましくは０．４以上０．６以下、さらに好ましくは０．５以上０．６以下である層または膜であることがさらにより好ましい。
　また、ランタンフッ化物としてはＬａＦ３が好ましく、ハフニウムフッ化物としてはＨｆＦ４が好ましい。 The Hf + La fluoride layer 2 contains hafnium fluoride and lanthanum fluoride, and the volume ratio of hafnium fluoride to lanthanum fluoride is 0.35 or more and 0.6 or less, preferably 0.4 or more and 0.6 or less, and further Preferably it is a layer or film which is 0.5 or more and 0.6 or less.
Here, the Hf + La fluoride layer 2 is composed of hafnium fluoride and lanthanum fluoride, and the volume ratio of hafnium fluoride to lanthanum fluoride is 0.35 or more and 0.6 or less, preferably 0.4 or more and 0.6 or less. It is still more preferable that the layer or film be further preferably 0.5 or more and 0.6 or less.
In addition, LaF 3 is preferable as the lanthanum fluoride, and HfF 4 is preferable as the hafnium fluoride.
　また、Ｈｆ＋Ｌａフッ化物層２は、半導体層１との結晶格子整合性などの影響を受けにくく、安定した電気特性を得るという観点からアモルファス（非晶質絶縁膜）であることが好ましい。 Further, the Hf + La fluoride layer 2 is preferably not amorphous (amorphous insulating film) from the viewpoint of obtaining stable electrical characteristics while being hardly affected by the crystal lattice matching with the semiconductor layer 1 or the like.
　ＬａＦ３およびＨｆＦ４のイオン半径は、各々約０．１２ｎｍ、０．０８ｎｍであり、両者のイオン半径には約５０％の差がある。一般に、イオン半径差が１５％より大きいと非晶質化が進みやすいので、Ｈｆ＋Ｌａフッ化物層２は、アモルファスになりやすい性質を有している。 The ionic radii of LaF 3 and HfF 4 are about 0.12 nm and 0.08 nm, respectively, and there is a difference of about 50% between the ionic radii of both. In general, when the difference in ion radius is more than 15%, the amorphization tends to proceed, so the Hf + La fluoride layer 2 has a property of becoming easily amorphous.
　実施例のところで述べるように、Ｈｆ＋Ｌａフッ化物層２をこのような構成にすることにより、広いバンドギャップ、高い価電子帯上端、高い実効誘電率、そして低い電流密度（低いリーク電流）を得ることができる。また、この構成では、Ｈｆ＋Ｌａフッ化物層２と半導体層１との界面に中間層を作りにくく、Ｈｆ＋Ｌａフッ化物層２の層内および界面に準位を生じにくい。このため、ゲート容量Ｃｏｘが比較的大きく、高電界用途、特にパワー半導体用途に適応するＭＩＳ型半導体装置を提供することが可能になる。 As described in the Example, by making the Hf + La fluoride layer 2 in such a configuration, a wide band gap, a high valence band top, a high effective dielectric constant, and a low current density (low leak current) are obtained. Can. Further, in this configuration, it is difficult to form an intermediate layer at the interface between the Hf + La fluoride layer 2 and the semiconductor layer 1, and it is difficult to generate a level in the layer and interface of the Hf + La fluoride layer 2. Therefore, it is possible to provide a MIS type semiconductor device having a relatively large gate capacitance Cox and adapted to high electric field applications, particularly power semiconductor applications.
　Ｈｆ＋Ｌａフッ化物層２は蒸着法により成膜することができる。また、スパッタリング法によって成膜することも可能である。 The Hf + La fluoride layer 2 can be formed by vapor deposition. It is also possible to form a film by sputtering.
　Ｈｆ＋Ｌａフッ化物層２を真空蒸着法により成膜する場合は、基板温度を室温（２３℃）以上４００℃以下とすることが好ましい。基板温度が室温を下回ると誘電率が低下する傾向にある。また、基板温度が４５０℃を超えると電気特性が劣化し、５００℃を超えるような温度になると半導体基板の表面ラフネスも肉眼でわかるほど大きくなって特性劣化が顕著になる。 In the case of forming the Hf + La fluoride layer 2 by vacuum evaporation, it is preferable to set the substrate temperature to room temperature (23 ° C.) or more and 400 ° C. or less. When the substrate temperature is below room temperature, the dielectric constant tends to decrease. Also, when the substrate temperature exceeds 450 ° C., the electrical characteristics deteriorate, and when the temperature exceeds 500 ° C., the surface roughness of the semiconductor substrate also becomes so large that it can be visually recognized, and the characteristic degradation becomes remarkable.
　Ｈｆ＋Ｌａフッ化物層２の成膜をスパッタリング法で行うと、スループットに優れ、また面内均一性を高めやすいことから好ましい。特に、ＲＦスパッタリング法はスループットを高めやすいので好ましい。ここで、スパッタリングガスとしてはアルゴン（Ａｒ）ガス、クリプトン（Ｋｒ）ガスなどの貴ガスを好んで用いることができる。 It is preferable to perform the film formation of the Hf + La fluoride layer 2 by a sputtering method because it is excellent in throughput and easy to improve in-plane uniformity. In particular, the RF sputtering method is preferable because it is easy to increase the throughput. Here, noble gases such as argon (Ar) gas and krypton (Kr) gas can be preferably used as the sputtering gas.
　この際のスパッタリングターゲットとしては、ハフニウムおよびランタンフッ化物を含むスパッタリングターゲット、さらに好ましくはハフニウムおよびランタンフッ化物からなるスパッタリングターゲットを好んで用いることができる。
　そして、そのスパッタリングターゲットにおけるランタンフッ化物に対するハフニウムフッ化物の体積比率は、０．３５以上０．６以下が好ましい。
　なお、このスパッタリングターゲットは焼結法によって作製することができる。
　このスパッタリングターゲットを用いると、取扱いが容易で、高い面内均一性をもつ所望のＨｆ＋Ｌａフッ化物層２を高いスループットで形成することが可能になる。 As a sputtering target at this time, a sputtering target containing hafnium and lanthanum fluoride, more preferably a sputtering target consisting of hafnium and lanthanum fluoride can be preferably used.
The volume ratio of hafnium fluoride to lanthanum fluoride in the sputtering target is preferably 0.35 or more and 0.6 or less.
In addition, this sputtering target can be produced by the sintering method.
Using this sputtering target, it is possible to form a desired Hf + La fluoride layer 2 with high throughput, which is easy to handle and has high in-plane uniformity.
　なお、Ｈｆに替えてＮｂ（ニオブ）としたＮｂＦ５とＬａＦ３からなる絶縁膜も検討したが、ＮｂＦ５は昇華温度が約１００℃であり、膜を形成するときの制御性は不十分であった。一方、ＨｆＦ４の昇華温度は約３５０℃であることから、Ｈｆ＋Ｌａフッ化物層２形成の制御性には特段の問題はない。 In addition, although the insulating film which consists of NbF 5 and LaF 3 which were replaced with Hf and made Nb (niobium) was examined, NbF 5 has a sublimation temperature of about 100 ° C., and controllability at the time of forming the film is insufficient. there were. On the other hand, since the sublimation temperature of HfF 4 is about 350 ° C., there is no particular problem in the controllability of the Hf + La fluoride layer 2 formation.
　Ｈｆ＋Ｌａフッ化物層２の厚さは、１ｎｍ以上１００ｎｍ以下が好ましく、５ｎｍ以上１０ｎｍ以下がより好ましい。膜厚が５ｎｍを下回るとトンネルリーク電流が現れ始め、１ｎｍ以下でトンネル電流は顕著になる。膜厚が１００ｎｍを上回ると十分な静電容量Ｃｏｘを得るのが困難になる。 The thickness of the Hf + La fluoride layer 2 is preferably 1 nm or more and 100 nm or less, and more preferably 5 nm or more and 10 nm or less. When the film thickness is less than 5 nm, a tunnel leak current starts to appear, and when it is 1 nm or less, the tunnel current becomes remarkable. When the film thickness exceeds 100 nm, it becomes difficult to obtain a sufficient capacitance Cox.
　本発明の特徴の１つは、バッファー層を設けることなく半導体層１を構成する物質のＨｆ＋Ｌａフッ化物層２への拡散抑制、界面準位生成抑制（界面制御）が可能なことである。また、半導体層１とＨｆ＋Ｌａフッ化物層２が接する界面にこれら以外からなる層が形成されないことである。
　図２は、ＧａＮ基板上にＨｆＦ４層（（ａ）の場合）およびＨｆ＋Ｌａフッ化物層（（ｂ）の場合）を真空蒸着法で形成したときの断面ＴＥＭ（Ｔｒａｎｓｍｉｓｓｉｏｎ　Ｅｌｅｃｔｒｏｎ　Ｍｉｃｒｏｓｃｏｐｅ）写真である。真空蒸着時の基板温度は３００℃とし、ＴＥＭ装置としてはＪＥＭ－２１００Ｆ（ＪＥＯＬ製）を用いた。この結果から、ＧａＮ半導体上にＨｆ＋Ｌａフッ化物層が、ＨｆＦ４層と同様に、酸化や相互拡散などによる中間層を形成することなく直に形成されていることが分かる。 One of the features of the present invention is that it is possible to suppress the diffusion of the substance constituting the semiconductor layer 1 to the Hf + La fluoride layer 2 and to suppress the generation of interface state (interface control) without providing a buffer layer. In addition, no other layer is formed at the interface where the semiconductor layer 1 and the Hf + La fluoride layer 2 are in contact with each other.
FIG. 2 is a cross-sectional TEM (Transmission Electron Microscope) photograph when a HfF 4 layer (in the case of (a)) and an Hf + La fluoride layer (in the case of (b)) are formed on a GaN substrate by vacuum evaporation. The substrate temperature at the time of vacuum deposition was 300 ° C., and a TEM apparatus JEM-2100F (manufactured by JEOL) was used. From these results, it can be seen that the Hf + La fluoride layer is formed directly on the GaN semiconductor without forming an intermediate layer by oxidation or mutual diffusion, as in the case of the HfF 4 layer.
　導電体層３は、金属あるいはドーパントが添加されたポリシリコンなどの導電膜からなる。金属としては、金（Ａｕ）、銀（Ａｇ）、銅（Ｃｕ）、白金（Ｐｔ）、パラジウム（Ｐｄ）、タングステン（Ｗ）、チタン（Ｔｉ）、アルミニウム（Ａｌ）、クロム（Ｃｒ）、タンタル（Ｔａ）などを挙げることができる。また、ＡｌＣｕ、ＣｕＮｉＦｅ、ＮｉＣｒなどの合金、ＷＳｉ、ＴｉＳｉなどのシリサイド、ＷＮ、ＴｉＮ、ＣｒＮ、ＴａＮなどの金属化合物も用いることができる。導電体層３は、このような材料の中から導電率、仕事関数、加工性などを適宜勘案して適当な材料を選択すればよい。なお、集積回路として本発明のＭＩＳ半導体装置を用いる場合は、インテグレーションとしての各種熱処理が加わることから、それらの熱処理も勘案した材料の拡散を考慮の上、材料を選択する。 The conductor layer 3 is made of a conductive film such as polysilicon to which a metal or a dopant is added. As metal, gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), aluminum (Al), chromium (Cr), tantalum (Ta) etc. can be mentioned. Further, an alloy such as AlCu, CuNiFe or NiCr, a silicide such as WSi or TiSi, or a metal compound such as WN, TiN, CrN or TaN can also be used. For the conductive layer 3, an appropriate material may be selected from among such materials in consideration of conductivity, work function, processability, and the like. When the MIS semiconductor device of the present invention is used as an integrated circuit, various heat treatments as integration are added, so materials are selected in consideration of the diffusion of the material in consideration of the heat treatment.
　次に、本発明のＭＩＳＦＥＴについて説明する。 Next, the MISFET of the present invention will be described.
　本発明の第１のＭＩＳＦＥＴ（１０２）は、要部断面図である図３に示すように、半導体層１、Ｈｆ＋Ｌａフッ化物層にドレインおよびソース用のパターンが形成されたＨｆ＋Ｌａフッ化物層パターン２ａ、ゲート３ａ、ソース４ａおよびドレイン５ａからなる。 The first MISFET (102) of the present invention is, as shown in FIG. 3 which is a cross-sectional view of the main part, a semiconductor layer 1, an Hf + La fluoride layer, and an Hf + La fluoride layer pattern 2a having a pattern for drain and source formed. , Gate 3a, source 4a and drain 5a.
　Ｈｆ＋Ｌａフッ化物層パターン２ａは、ランタンフッ化物に対するハフニウムフッ化物の体積比率が、０．３５以上０．６以下、好ましくは０．４以上０．６以下、さらに好ましくは０．５以上０．６以下からなる材料で構成される。
　ここで、ランタンフッ化物としてはＬａＦ３が好ましく、ハフニウムフッ化物としてはＨｆＦ４が好ましい。
　また、Ｈｆ＋Ｌａフッ化物層パターン２ａは、半導体層１との結晶格子整合性などの影響を受けにくく、安定した電気特性を得るという観点から、アモルファス（非晶質絶縁膜）状態の膜からなることが好ましい。 In the Hf + La fluoride layer pattern 2a, the volume ratio of hafnium fluoride to lanthanum fluoride is 0.35 or more and 0.6 or less, preferably 0.4 or more and 0.6 or less, and more preferably 0.5 or more and 0.6 or less. It consists of the material which consists of the following.
Here, LaF 3 is preferable as the lanthanum fluoride, and HfF 4 is preferable as the hafnium fluoride.
Further, the Hf + La fluoride layer pattern 2a is made of a film in an amorphous (amorphous insulating film) state from the viewpoint of being hardly affected by the crystal lattice matching with the semiconductor layer 1 and obtaining stable electrical characteristics. Is preferred.
　ゲート３ａ、ソース４ａおよびドレイン５ａは、金属、合金、金属化合物、シリサイド、ポリサイドまたはドーパントが添加されたポリシリコンなどの導電膜からなる。具体的には、上記導電体層３として例示した材料を挙げることができる。 The gate 3a, the source 4a and the drain 5a are made of a conductive film such as metal, alloy, metal compound, silicide, polycide or polysilicon to which a dopant is added. Specifically, the materials exemplified as the conductive layer 3 can be mentioned.
　Ｈｆ＋Ｌａフッ化物層を真空蒸着法で形成する場合の温度は、良好な電気特性を得る上で、室温（２３℃）以上４５０℃以下が好ましい。
　また、Ｈｆ＋Ｌａフッ化物層を形成後でゲート３ａを構成する導電膜を形成する前に、窒素ガス（Ｎ２ガス）を用いた熱処理が行われることがＭＩＳＦＥＴの電気特性を改善する上で好ましい。その熱処理の条件としては、窒素ガスの圧力が１Ｐａ以上２０００ｈＰａ以下、温度が２００℃以上５００℃以下が好ましい。
　さらに、ゲート３ａを構成する導電膜を形成後に、窒素ガスと水素ガス（Ｈ２ガス）の混合ガスを用いた熱処理が行われることがＭＩＳＦＥＴの電気特性を改善する上で好ましい。その熱処理の条件としては、窒素ガスと水素ガスの混合比率が窒素ガス１に対して水素ガスが体積比で１％以上５％以下、混合ガスの圧力が１Ｐａ以上２０００ｈＰａ以下、そして温度が２００℃以上５００℃以下が好ましい。
　なお、熱処理は、ヒーターによる加熱炉、ランプによる加熱炉、ホットプレートなどのほか、レーザーアニール、フラッシュランプアニールなどによって行ってもよい。 The temperature in the case of forming the Hf + La fluoride layer by vacuum evaporation is preferably room temperature (23 ° C.) or more and 450 ° C. or less in order to obtain good electrical characteristics.
Further, after forming the Hf + La fluoride layer and before forming the conductive film constituting the gate 3a, it is preferable to perform heat treatment using nitrogen gas (N 2 gas) in order to improve the electrical characteristics of the MISFET. As the conditions for the heat treatment, the pressure of nitrogen gas is preferably 1 Pa or more and 2000 hPa or less, and the temperature is preferably 200 ° C. or more and 500 ° C. or less.
Furthermore, it is preferable to perform heat treatment using a mixed gas of nitrogen gas and hydrogen gas (H 2 gas) after forming the conductive film constituting the gate 3 a in order to improve the electrical characteristics of the MISFET. As the conditions for the heat treatment, the mixing ratio of nitrogen gas and hydrogen gas is 1% to 5% by volume ratio of hydrogen gas to nitrogen gas 1, the pressure of mixed gas is 1 Pa to 2000 hPa, and the temperature is 200 ° C. The temperature is preferably 500 ° C. or less.
The heat treatment may be performed by a laser annealing, a flash lamp annealing, or the like in addition to a heating furnace with a heater, a heating furnace with a lamp, a hot plate, and the like.
　本発明の第２のＭＩＳＦＥＴ（１０３）は、要部断面図である図４に示すように、半導体層１、Ｈｆ＋Ｌａフッ化物層１２ｂ、ゲート１３ｂ、ソース１４ｂ、ドレイン１５ｂおよびパターン化された層間膜２１ｂからなる。この構造では、ゲート１３ｂは埋め込み構造をとる。ここで、ゲート１３ｂ、ソース１４ｂおよびドレイン１５ｂは、第１のＭＩＳＦＥＴ（１０２）と同様に、金属、合金、金属化合物、シリサイド、ポリサイドまたはドーパントが添加されたポリシリコンなどの導電膜からなる。 The second MISFET (103) of the present invention is, as shown in FIG. 4 which is a cross-sectional view of the main part, a semiconductor layer 1, an Hf + La fluoride layer 12b, a gate 13b, a source 14b, a drain 15b and a patterned interlayer film. It consists of 21b. In this structure, the gate 13b has a buried structure. Here, the gate 13b, the source 14b, and the drain 15b are made of a conductive film such as metal, alloy, metal compound, silicide, polycide, or polysilicon to which a dopant is added, similarly to the first MISFET (102).
　第２のＭＩＳＦＥＴ（１０３）は、下記に示す工程により製造することができる。要部断面図を用いてその製造工程を説明した図５を参照しながら、その製造方法を説明する。
　まず、半導体層１の上に層間膜２１を形成する（図５（ａ）参照）。層間膜２１としては、例えばプラズマＣＶＤ法によるＳｉＯｘなどの絶縁膜を挙げることができる。
　次に、層間膜２１にゲートを作製するための開口をリソグラフィとドライエッチングにより形成し、層間膜パターン２１ａとする（図５（ｂ））。
　その後、半導体基板１上にＨｆ＋Ｌａフッ化物層１２ａを成膜形成する（図５（ｃ））。この膜はコンフォーマルに被着されるのが好ましい。
　次に、ＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）やエッチバックなどの方法により、層間膜パターン２１ａの上面上に形成されているランタンフッ化物層１２ａを除去して、層間膜パターン２１ａの開口部にのみ形成されているＨｆ＋Ｌａフッ化物層１２ｂを得る（図５（ｄ））。
　しかる後、導電体膜１３ａを被着（図５（ｅ））し、引き続いてＣＭＰやエッチバックなどの方法により層間膜パターン２１ａの上面上に形成されている導電体膜１３ａを除去して、Ｈｆ＋Ｌａフッ化物層１２ｂが露出している溝部に導電体膜が埋め込まれた導電体膜パターンを形成し、その導電体膜パターンをゲート１３ｂとする（図５（ｆ））。
　その後、リソグラフィとドライエッチングを用いて、層間膜パターン２１ａに開口部２２および２３を有する層間膜パターン２１ｂを形成する（図５（ｇ））。
　そして、開口部２２および２３に導電体膜を埋め込んで、その導電体膜パターンをそれぞれソース１４ｂとドレイン１５ｂとして第２のＭＩＳＦＥＴ（１０３）とする（図５（ｈ））。 The second MISFET (103) can be manufactured by the process shown below. The manufacturing method will be described with reference to FIG. 5 which illustrates the manufacturing process using the main part sectional view.
First, the interlayer film 21 is formed on the semiconductor layer 1 (see FIG. 5A). Examples of the interlayer film 21 include insulating films such as SiO x formed by plasma CVD.
Next, an opening for producing a gate is formed in the interlayer film 21 by lithography and dry etching to form an interlayer film pattern 21a (FIG. 5B).
Thereafter, the Hf + La fluoride layer 12a is formed on the semiconductor substrate 1 (FIG. 5 (c)). The membrane is preferably deposited conformally.
Next, the lanthanum fluoride layer 12a formed on the upper surface of the interlayer film pattern 21a is removed by a method such as CMP (Chemical Mechanical Polishing) or etch back, and only the opening of the interlayer film pattern 21a is formed. The obtained Hf + La fluoride layer 12b is obtained (FIG. 5 (d)).
Thereafter, the conductor film 13a is deposited (FIG. 5 (e)), and the conductor film 13a formed on the upper surface of the interlayer film pattern 21a is subsequently removed by a method such as CMP or etch back. A conductor film pattern in which a conductor film is embedded is formed in the groove where the Hf + La fluoride layer 12b is exposed, and the conductor film pattern is used as the gate 13b (FIG. 5 (f)).
Thereafter, lithography and dry etching are used to form an interlayer film pattern 21b having openings 22 and 23 in the interlayer film pattern 21a (FIG. 5 (g)).
Then, a conductor film is embedded in the openings 22 and 23, and the conductor film patterns thereof are respectively used as a source 14b and a drain 15b as a second MISFET (103) (FIG. 5 (h)).
　第２のＭＩＳＦＥＴの製造方法によれば、Ｈｆ＋Ｌａフッ化物層１２ｂの加工をＣＭＰやエッチバックで行っているので、半導体層へのダメージが少ないドライエッチングを行うことが容易ではないハフニウムフッ化物とランタンフッ化物よりなる膜（ＨＦ４とＬａＦ３からなる膜）においても電気的ダメージの少ないＭＩＳＦＥＴを得ることができる。 According to the second method of manufacturing the MISFET, since the Hf + La fluoride layer 12b is processed by CMP or etch back, it is not easy to perform dry etching with less damage to the semiconductor layer. Also in a film made of fluoride (a film made of HF 4 and LaF 3 ), a MISFET with less electrical damage can be obtained.
　本発明の第３のＭＩＳＦＥＴ（１０３）は、要部断面図である図６に示すように、半導体層３１ａ、３１ｂ、３１ｃ、Ｈｆ＋Ｌａフッ化物層３２、ゲート３３、ソース３４、およびドレイン３５からなる。ここで、半導体層３１ａ、３１ｂ、３１ｃは異種の材料からなる半導体層であり、例えば、３１ａはＩｎＡｓからなるｎ型半導体、３１ｂはＧａＮからなるイントリンシック半導体、３１ｃはＧａＳｂからなるｐ型半導体を挙げることができる。
　Ｈｆ＋Ｌａフッ化物層３２はバンドギャップが９．４ｅＶと広く、しかもその価電子帯上限（価電子帯上端）ＥＶＢＭと伝導体下端ＥＣＢＭの中に、上記の半導体材料を含め多くの半導体材料のＥＶＢＭとＥＣＢＭが納まるバンドアライメントを有する（図７参照）。このため、このようなバンドギャップの異なる複数からなる半導体に対してもＭＩＳ構造半導体装置のゲート絶縁膜として機能する。なお、ＧａＳｂ、ＧａＮ、ＩｎＡｓのバンドギャップは、それぞれ、０．７ｅＶ、３．４ｅＶおよび０．３６ｅＶであり、図７中のＥＣＮＬは電荷中性準位を表す。 The third MISFET (103) of the present invention comprises semiconductor layers 31a, 31b, 31c, Hf + La fluoride layer 32, gate 33, source 34, and drain 35, as shown in FIG. . Here, the semiconductor layers 31a, 31b and 31c are semiconductor layers made of different materials. For example, 31a is an n-type semiconductor made of InAs, 31b is an intrinsic semiconductor made of GaN, 31c is a p-type semiconductor made of GaSb It can be mentioned.
The Hf + La fluoride layer 32 has a wide band gap of 9.4 eV, and the upper limit of the valence band (upper end of the valence band) E VBM and the lower end of the conductor E CBM include many semiconductor materials including the above semiconductor materials. It has a band alignment in which E VBM and E CBM can be accommodated (see FIG. 7). Therefore, even a semiconductor composed of a plurality of different band gaps functions as a gate insulating film of the MIS structure semiconductor device. The band gaps of GaSb, GaN, and InAs are 0.7 eV, 3.4 eV, and 0.36 eV, respectively, and E CNL in FIG. 7 represents a charge neutral level.
　ゲート３３はサイドウォールを利用した加工法で形成することができる。サイドウォール利用加工法とは、異方性ドライエッチングを行ったときの縦方向と横方向のエッチング速度差および側壁周辺でのエッチング速度差を利用した加工法で、側壁（サイドウォール）に沿って被加工物が残る加工法である。この加工法により、サイドウォール部にゲート（電極）を自己整合的に形成でき、ゲートとして重要な寸法精度も高いものとなる。ここで、形成されるゲートの寸法精度を高めるためには、このサイドウォールは垂直に形成されていることが好ましい。なお、サイドウォール利用加工法を適用するとゲート３３の上端部（肩の部分）は角が削れた形状になる。 The gate 33 can be formed by a processing method using a sidewall. The sidewall-based processing method is a processing method using the difference between the etching rate in the longitudinal direction and the lateral direction when anisotropic dry etching is performed and the etching rate around the side wall, along the side wall (side wall). It is a processing method in which a workpiece remains. By this processing method, the gate (electrode) can be formed in a self-aligned manner in the sidewall portion, and the dimensional accuracy important as the gate can be high. Here, in order to improve the dimensional accuracy of the gate to be formed, it is preferable that the side wall is formed vertically. When the sidewall utilizing processing method is applied, the upper end portion (shoulder portion) of the gate 33 has a shape in which the corner is scraped.
　以下、本発明のＭＩＳ半導体装置の特性を、キャパシタ特性によって調べた実施例について説明する。当然ながら、本発明はこのような特定の形式に限定されるものではなく、本発明の技術的範囲は特許請求の範囲により規定されるものである。 Hereinafter, an embodiment in which the characteristics of the MIS semiconductor device of the present invention are examined by the capacitor characteristics will be described. Of course, the present invention is not limited to such a specific format, and the technical scope of the present invention is defined by the claims.
（実施例１）
　実施例１では、Ｈｆ＋Ｌａフッ化物層のバンドギャップ、価電子帯上端およびリーク電流特性の組成比依存性について評価した。
　具体的には、ＨｆＦ４とＬａＦ３からなるＨｆ＋Ｌａフッ化物膜をその体積比率ｘを変えて形成し、その膜のバンドギャップ、価電子帯上端およびリーク電流特性を測定した。ここで、この膜を（ＨｆＦ４）ｘ（ＬａＦ３）１－ｘ（ｘは０から１の値）と記す。 Example 1
In Example 1, the composition ratio dependency of the band gap, the valence band upper end, and the leak current characteristic of the Hf + La fluoride layer was evaluated.
Specifically, an Hf + La fluoride film composed of HfF 4 and LaF 3 was formed at different volume ratios x, and the band gap, valence band upper end and leak current characteristics of the film were measured. Here, this film is described as (HfF 4 ) x (LaF 3 ) 1 -x (x is a value of 0 to 1).
　この評価においては、基板の影響を極力少なくすることを目的として、ＨｆＦ４とＬａＦ３からなる材料に対して安定で原子層レベルの平坦な表面が得られるＳｒＴｉＯ３基板を用いた。結晶面は（１００）である。ここで、導電性基板にする目的で、この基板には０．５ｗｔ％のＮｂをドープしてある。 In this evaluation, in order to reduce the influence of the substrate as much as possible, a SrTiO 3 substrate which is stable against a material composed of HfF 4 and LaF 3 and which can obtain a flat surface at the atomic layer level is used. The crystal plane is (100). Here, in order to form a conductive substrate, this substrate is doped with 0.5 wt% of Nb.
　（ＨｆＦ４）ｘ（ＬａＦ３）１－ｘ膜は真空蒸着により形成した。その膜厚は５０ｎｍであり、真空度５×１０－８Ｐａ、基板温度１００℃で成膜した。形成された（ＨｆＦ４）ｘ（ＬａＦ３）１－ｘ膜の表面粗さは基板の表面粗さとほぼ同じであった。また、この膜の状態をＸＲＤ（Ｘ－ｒａｙ　ｄｉｆｆｒａｃｔｉｏｎ：Ｘ線回折、Ｄ８　Ｄｉｓｃｏｖｅｒ　Ｓｕｐｅｒ　Ｓｐｅｅｄ　ｗｉｔｈ　ＧＡＤＤＳ、ブルカーＡＸＳ製）で測定して、この膜がアモルファス（非晶質）膜であることを確認した。 The (HfF 4 ) x (LaF 3 ) 1-x film was formed by vacuum evaporation. The film thickness was 50 nm, and the film was formed at a vacuum degree of 5 × 10 −8 Pa and a substrate temperature of 100 ° C. The surface roughness of the (HfF 4 ) x (LaF 3 ) 1-x film formed was almost the same as the surface roughness of the substrate. In addition, the state of this film was measured by XRD (X-ray diffraction: D8 Discover Super Speed with GADDS, manufactured by Bruker AXS) to confirm that this film was an amorphous (amorphous) film. .
　（ＨｆＦ４）ｘ（ＬａＦ３）１－ｘ膜の価電子帯上端ＥＶＢＭとその膜のバンドギャップＥｇをＳＰｒｉｎｇ－８においてＨＡＸＰＳ（Ｈａｒｄ　Ｘ－ｒａｙ　Ｐｈｏｔｏｅｒｅｃｔｒｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ：硬Ｘ線電子分光法）を用いて調べた。その結果を図８に示す。ここで、同図中のバーはエラーバーを示す。 Valence band top E VBM of (HfF 4 ) x (LaF 3 ) 1-x films and the band gap E g of the films at HA SPX-8 by HAXPS (Hard X-ray Photoelectron spectroscopy) It examined using. The results are shown in FIG. Here, the bars in the figure indicate error bars.
　価電子帯上端ＥＶＢＭは、６ｅＶ前後で推移し、特にＬａＦ３に対するＨｆＦ４の体積比率ｘが０．３５から０．６の範囲では６ｅＶを超えて極大値となる。一方、バンドギャップＥｇは、体積比率ｘが０以上０．６までは約９．５を維持しているが、０．６を超えると値がその小さくなり、体積比率ｘが０．８５で約８．７５とＨｆＦ４のバンドギャップＥｇとほぼ同じになる。したがって、広いバンドギャップＥｇを得るためには体積比率ｘを０．６以下とするのが好ましい。 The valence band upper end E V B M changes around 6 eV, and in particular, when the volume ratio x of HfF 4 to LaF 3 is in the range of 0.35 to 0.6, it becomes a maximum value exceeding 6 eV. On the other hand, the band gap E g maintains about 9.5 at a volume ratio x from 0 to 0.6, but when it exceeds 0.6, the value becomes smaller, and the volume ratio x is 0.85. The band gap E g of about 8.75 and HfF 4 is almost the same. Therefore, in order to obtain a wide band gap E g , it is preferable to set the volume ratio x to 0.6 or less.
　また、体積比率ｘが０．６以下では、バンドギャップＥｇが９を超える値を維持するとともに、価電子帯上端ＥＶＢＭのエネルギー位置も６ｅＶ前後で推移することから、半導体層としてＧａＮを用いた場合は、３ｅＶ程度の導電体下端のエネルギー差を維持できることが確認された。 In addition, when the volume ratio x is 0.6 or less, the band gap Eg maintains a value exceeding 9 and the energy position of the valence band upper end E VBM changes at around 6 eV, so GaN was used as the semiconductor layer In the case, it was confirmed that an energy difference of about 3 eV at the lower end of the conductor can be maintained.
　電流密度Ｊと実効誘電率εの測定結果を図９に示す。
　実効誘電率εは、体積比率ｘが大きくなるほど、すなわちＨｆＦ４の占める比率が増えるほど単調に小さくなるが、体積比率ｘが０．６以下では約１２以上と比較的高い値となっている。ちなみに、Ｈｉｇｈ－ｋ膜として使用されているＨｆＯ２膜の実効誘電率εは１３－１８なので、体積比率ｘが０．６以下の（ＨｆＦ４）ｘ（ＬａＦ３）１－ｘ膜はＨｆＯ２膜と同程度の実効誘電率εを有しているといえる。 The measurement results of the current density J and the effective dielectric constant ε are shown in FIG.
The effective dielectric constant ε monotonously decreases as the volume ratio x increases, that is, as the ratio occupied by HfF 4 increases, but has a relatively high value of about 12 or more when the volume ratio x is 0.6 or less. Incidentally, since the effective dielectric constant ε of the HfO 2 film used as the High-k film is 13-18, the (HfF 4 ) x (LaF 3 ) 1-x film having the volume ratio x of 0.6 or less is HfO 2 It can be said that it has the same effective dielectric constant ε as the film.
　電流密度Ｊは、体積比率ｘが０より増えるにともなって下がり、体積比率ｘが約０．５５で極小となった後、体積比率ｘの増加とともに増えるという特性を有する。
　１０－６Ａ／ｃｍ２より低いレベルのリーク電流がパワー用途のＭＩＳ型半導体装置に求められるので、その観点からは、体積比率ｘは０．３５以上０．７以下が好ましい。
　さらに、ＨｆＯ２膜並みの実効誘電率εと、パワー用途の電流密度（リーク電流）Ｊの両立という観点に立つと、体積比率ｘは０．３５以上０．６以下が求められ、よりリーク電流を下げるという観点からは、体積比率ｘは、０．４以上０．６以下が好ましく、０．５以上０．６以下がより好ましい。体積比率ｘが０．５以上０．６以下の場合には、リーク電流を１０－８Ａ／ｃｍ２のオーダーに収めることが可能になる。 The current density J has a characteristic that it decreases as the volume ratio x increases from 0, and increases as the volume ratio x increases after the volume ratio x is minimized at about 0.55.
From the viewpoint of this, the volume ratio x is preferably 0.35 or more and 0.7 or less, since a leakage current of a level lower than 10 −6 A / cm 2 is required for the MIS type semiconductor device for power applications.
Furthermore, from the viewpoint of achieving both the effective dielectric constant ε as HfO 2 film and the current density (leakage current) J for power application, the volume ratio x is required to be 0.35 or more and 0.6 or less, and the leakage current is more From the viewpoint of lowering the volume ratio, the volume ratio x is preferably 0.4 or more and 0.6 or less, and more preferably 0.5 or more and 0.6 or less. When the volume ratio x is 0.5 or more and 0.6 or less, the leak current can be reduced to the order of 10 −8 A / cm 2 .
　（ＨｆＦ４）ｘ（ＬａＦ３）１－ｘ膜をＳＰｒｉｎｇ－８でＨＡＸＰＳ分析行った結果を図１０に示す。同図には、結合エネルギーが９ｅＶ以下の状態をわかりやすくするために、その領域に関して信号強度を１０倍にした結果も合わせて載せている。
　図１０に記載の複数の硬Ｘ線光電子分光特性図が、それぞれどの体積比率ｘに対応するかを一層明確にするため、図１１から１８に、各硬Ｘ線光電子分光特性図を単独で示した。
　体積比率ｘが０．７１の場合には、結合エネルギーが２から５ｅＶの領域にギャップ内準位の増加が認められる。
　体積比率ｘが０．６より大きなハフニウムフッ化物がリッチな領域では、バンドギャップは減少していたこと（図８）を合わせて鑑みると、体積比率ｘが０．６より大きい領域では、バンドを形成する電子構造がＨｆＦ４の構造が支配的になる過程で欠陥構造が生成されていると考えられる。 The results of HAXPS analysis of the (HfF 4 ) x (LaF 3 ) 1-x film at SPring-8 are shown in FIG. In the same figure, in order to make it easy to understand the state where the binding energy is 9 eV or less, the result of making the signal intensity 10 times for that region is also included.
In order to further clarify which volume ratio x the plurality of hard X-ray photoelectron spectroscopy characteristic diagrams shown in FIG. 10 correspond to, each hard X-ray photoelectron spectroscopy characteristic diagram is shown alone in FIGS. The
When the volume ratio x is 0.71, an increase in the level in the gap is observed in the region of 2 to 5 eV of binding energy.
In the region rich in hafnium fluoride in which the volume ratio x is larger than 0.6, the band gap is decreased (Fig. 8). It is considered that a defect structure is generated while the electronic structure to be formed is dominated by the HfF 4 structure.
　以上説明したように、本発明によれば、誘電率が比較的高く、かつ約９．４ｅＶというワイドバンドギャップをもった絶縁膜を、酸化層などの所望ではない中間層を形成することなく、半導体上に形成できる。その上で、パワー半導体にとって重要なリーク電流も少ない。
　したがって、本発明により、ワイドバンドギャップＨｉｇｈ－ｋ絶縁膜をもち、界面などに準位が少なく、かつリーク電流の少ないＭＩＳ型半導体装置が提供される。
　ＧａＮ等の広いバンドギャップをもつ半導体のもつ高電界対応の性能を引き出すことができるＭＩＳ型半導体装置が提供されるので、ロジック用途はもとより、低リーク電流が求められるパワー用途への適用が期待される。
　また、この絶縁膜をゲート絶縁膜として用いたＭＩＳＦＥＴは、ゲート絶縁膜のバンドギャップが広いので、様々な半導体と組み合わせることができる汎用性を有する。
　以上のことから、本発明のＭＩＳ型半導体装置は多くの産業分野で利用される可能性がある。 As described above, according to the present invention, an insulating film having a relatively high dielectric constant and a wide band gap of about 9.4 eV can be formed without forming an undesired intermediate layer such as an oxide layer. It can be formed on a semiconductor. Furthermore, the leakage current that is important for power semiconductors is also small.
Therefore, according to the present invention, a MIS type semiconductor device having a wide band gap high-k insulating film, a low level at an interface or the like, and a small leak current is provided.
Since MIS type semiconductor devices capable of extracting the performance corresponding to the high electric field of semiconductors with wide band gaps such as GaN can be provided, applications to power applications where low leakage current is required as well as logic applications are expected. Ru.
Further, a MISFET using this insulating film as a gate insulating film has wide band gap of the gate insulating film, and thus has versatility that can be combined with various semiconductors.
From the above, the MIS type semiconductor device of the present invention may be used in many industrial fields.
１：半導体層
２：Ｈｆ＋Ｌａフッ化物層
２ａ：Ｈｆ＋Ｌａフッ化物層パターン
３：導電体層
３ａ： ゲート
４ａ：ソース
５ａ：ドレイン
１２ａ：Ｈｆ＋Ｌａフッ化物層
１２ｂ：Ｈｆ＋Ｌａフッ化物層
１３ａ：導電体膜
１３ｂ： ゲート
１４ｂ：ソース
１５ｂ：ドレイン
２１：層間膜
２１ａ：層間膜パターン
２１ｂ：パターン化された層間膜
２２：開口部
２３：開口部
３１ａ：半導体（ＩｎＡｓ）
３１ｂ：半導体（ＧａＮ）
３１ｃ：半導体（ＧａＳｂ）
３２：Ｈｆ＋Ｌａフッ化物層
３３： ゲート
３４：ソース
３５：ドレイン
１０１：ＭＩＳ構造
１０２：ＭＩＳＦＥＴ
１０３：ＭＩＳＦＥＴ
１０４：ＭＩＳＦＥＴ
  1: Semiconductor layer 2: Hf + La fluoride layer 2a: Hf + La fluoride layer pattern 3: conductor layer 3a: gate 4a: source 5a: drain 12a: Hf + La fluoride layer 12b: Hf + La fluoride layer 13a: conductor film 13b: Gate 14b: Source 15b: Drain 21: Interlayer film 21a: Interlayer film pattern 21b: Patterned interlayer film 22: Opening 23: Opening 31a: Semiconductor (InAs)
31b: Semiconductor (GaN)
31c: Semiconductor (GaSb)
32: Hf + La fluoride layer 33: gate 34: source 35: drain 101: MIS structure 102: MISFET
103: MISFET
104: MISFET

Claims (19)

  1. 　半導体層と絶縁体層と導電体層を有し、前記絶縁体層が前記半導体層と前記導電体層で挟まれたＭＩＳ型半導体装置であって、
    　前記絶縁体層は、ハフニウムフッ化物およびランタンフッ化物を含み、
    　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．３５以上０．６以下である、ＭＩＳ型半導体装置。     A MIS type semiconductor device comprising a semiconductor layer, an insulator layer, and a conductor layer, wherein the insulator layer is sandwiched between the semiconductor layer and the conductor layer.
    The insulator layer comprises hafnium fluoride and lanthanum fluoride,
    The MIS type semiconductor device whose volume ratio of said hafnium fluoride to said lanthanum fluoride is 0.35 or more and 0.6 or less.
  2. 　前記絶縁体層は、ハフニウムフッ化物およびランタンフッ化物からなる非晶質絶縁膜であり、
    　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．３５以上０．６以下である、請求項１に記載のＭＩＳ型半導体装置。     The insulator layer is an amorphous insulating film comprising hafnium fluoride and lanthanum fluoride,
    The MIS type semiconductor device according to claim 1, wherein a volume ratio of said hafnium fluoride to said lanthanum fluoride is 0.35 or more and 0.6 or less.
  3. 　前記ハフニウムフッ化物はＨｆＦ４であり、前記ランタンフッ化物はＬａＦ３である、請求項１または２に記載のＭＩＳ型半導体装置。 The MIS type semiconductor device according to claim 1, wherein the hafnium fluoride is HfF 4 and the lanthanum fluoride is LaF 3 .
  4. 　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．４以上０．６以下である、請求項１から３の何れか１に記載のＭＩＳ型半導体装置。 The MIS type semiconductor device according to any one of claims 1 to 3, wherein a volume ratio of said hafnium fluoride to said lanthanum fluoride is 0.4 or more and 0.6 or less.
  5. 　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．５以上０．６以下である、請求項１から３の何れか１に記載のＭＩＳ型半導体装置。 The MIS type semiconductor device according to any one of claims 1 to 3, wherein a volume ratio of the hafnium fluoride to the lanthanum fluoride is 0.5 or more and 0.6 or less.
  6. 　前記半導体層は非酸化物半導体からなる、請求項１から５の何れか１に記載のＭＩＳ型半導体装置。 The MIS semiconductor device according to any one of claims 1 to 5, wherein the semiconductor layer is made of a non-oxide semiconductor.
  7. 　前記半導体層は、ＧａＮ、Ｇｅ、Ｓｉ、ＳｉＣ、ダイヤモンドの群から選ばれる何れか１を含む半導体からなる、請求項１から６の何れか１に記載のＭＩＳ型半導体装置。 The MIS semiconductor device according to any one of claims 1 to 6, wherein the semiconductor layer is made of a semiconductor including any one selected from the group of GaN, Ge, Si, SiC, and diamond.
  8. 　半導体層を少なくとも表面に有する基板上に絶縁体層を形成する絶縁体層形成工程と、前記絶縁体層上に導電体層を形成する導電体層形成工程を含むＭＩＳ型半導体装置の製造方法において、
    　前記絶縁体層は、ハフニウムフッ化物およびランタンフッ化物を含み、
    　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．３５以上０．６以下である、ＭＩＳ型半導体装置の製造方法。     A method of manufacturing a MIS semiconductor device, comprising: an insulator layer forming step of forming an insulator layer on a substrate having at least a semiconductor layer on the surface; and a conductor layer forming step of forming a conductor layer on the insulator layer. ,
    The insulator layer comprises hafnium fluoride and lanthanum fluoride,
    A manufacturing method of MIS type semiconductor device whose volume ratio of said hafnium fluoride to said lanthanum fluoride is 0.35 or more and 0.6 or less.
  9. 　前記絶縁体層は、ハフニウムフッ化物およびランタンフッ化物からなる非晶質絶縁膜であり、
    　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．３５以上０．６以下である、請求項８に記載のＭＩＳ型半導体装置の製造方法。     The insulator layer is an amorphous insulating film comprising hafnium fluoride and lanthanum fluoride,
    9. The method of manufacturing an MIS-type semiconductor device according to claim 8, wherein a volume ratio of said hafnium fluoride to said lanthanum fluoride is 0.35 or more and 0.6 or less.
  10. 　前記ハフニウムフッ化物はＨｆＦ４であり、前記ランタンフッ化物はＬａＦ３である、請求項８または９に記載のＭＩＳ型半導体装置の製造方法。 The method for manufacturing an MIS-type semiconductor device according to claim 8, wherein the hafnium fluoride is HfF 4 and the lanthanum fluoride is LaF 3 .
  11. 　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．４以上０．６以下である、請求項８から１０の何れか１に記載のＭＩＳ型半導体装置の製造方法。 The method for manufacturing an MIS-type semiconductor device according to any one of claims 8 to 10, wherein a volume ratio of the hafnium fluoride to the lanthanum fluoride is 0.4 or more and 0.6 or less.
  12. 　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．５以上０．６以下である、請求項８から１０の何れか１に記載のＭＩＳ型半導体装置の製造方法。 The method for manufacturing an MIS-type semiconductor device according to any one of claims 8 to 10, wherein a volume ratio of the hafnium fluoride to the lanthanum fluoride is 0.5 or more and 0.6 or less.
  13. 　前記半導体層は非酸化物半導体からなる、請求項８から１２の何れか１に記載のＭＩＳ型半導体装置の製造方法。 The method for manufacturing an MIS-type semiconductor device according to any one of claims 8 to 12, wherein the semiconductor layer is made of a non-oxide semiconductor.
  14. 　前記半導体層は、ＧａＮ、Ｇｅ、Ｓｉ、ＳｉＣ、ダイヤモンドの群から選ばれる何れか１を含む半導体からなる、請求項８から１３の何れか１に記載のＭＩＳ型半導体装置の製造方法。 The method for manufacturing an MIS-type semiconductor device according to any one of claims 8 to 13, wherein the semiconductor layer is made of a semiconductor including any one selected from the group of GaN, Ge, Si, SiC, and diamond.
  15. 　前記絶縁体層は、蒸着法によって形成される、請求項８から１４の何れか１に記載のＭＩＳ型半導体装置の製造方法。 The method according to any one of claims 8 to 14, wherein the insulator layer is formed by vapor deposition.
  16. 　前記絶縁体層は、スパッタリング法によって形成される、請求項８から１４の何れか１に記載のＭＩＳ型半導体装置の製造方法。 The method for manufacturing a MIS-type semiconductor device according to any one of claims 8 to 14, wherein the insulator layer is formed by sputtering.
  17. 　ハフニウムフッ化物およびランタンフッ化物を含む、スパッタリングターゲット。 Sputtering targets, including hafnium fluoride and lanthanum fluoride.
  18. 　ハフニウムフッ化物およびランタンフッ化物からなる、スパッタリングターゲット。 Sputtering target consisting of hafnium fluoride and lanthanum fluoride.
  19. 　前記ランタンフッ化物に対する前記ハフニウムフッ化物の体積比率が０．３５以上０．６以下である、請求項１７または１８に記載のスパッタリングターゲット。
          The sputtering target according to claim 17 or 18, wherein a volume ratio of the hafnium fluoride to the lanthanum fluoride is 0.35 or more and 0.6 or less.
PCT/JP2018/046719 2018-01-22 2018-12-19 Mis type semiconductor device, method for producing same, and sputtering target which is used for production of same WO2019142581A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2019565774A JP6846834B2 (en) 2018-01-22 2018-12-19 MIS type semiconductor device, its manufacturing method, and the sputtering target used for its manufacturing

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-007977 2018-01-22
JP2018007977 2018-01-22

Publications (1)

Publication Number Publication Date
WO2019142581A1 true WO2019142581A1 (en) 2019-07-25

Family

ID=67302141

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/046719 WO2019142581A1 (en) 2018-01-22 2018-12-19 Mis type semiconductor device, method for producing same, and sputtering target which is used for production of same

Country Status (2)

Country Link
JP (1) JP6846834B2 (en)
WO (1) WO2019142581A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112558374A (en) * 2019-09-26 2021-03-26 Tdk株式会社 Optical modulator

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003078135A (en) * 2001-09-05 2003-03-14 Nikko Materials Co Ltd Gate insulation film for semiconductor device and method for manufacturing the same
US20050139965A1 (en) * 2003-12-29 2005-06-30 Lee Kee-Jeung Capacitor with hafnium, lanthanum and oxygen mixed dielectric and method for fabricating the same
WO2011042955A1 (en) * 2009-10-06 2011-04-14 ルネサスエレクトロニクス株式会社 Semiconductor device and method of producing same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003078135A (en) * 2001-09-05 2003-03-14 Nikko Materials Co Ltd Gate insulation film for semiconductor device and method for manufacturing the same
US20050139965A1 (en) * 2003-12-29 2005-06-30 Lee Kee-Jeung Capacitor with hafnium, lanthanum and oxygen mixed dielectric and method for fabricating the same
WO2011042955A1 (en) * 2009-10-06 2011-04-14 ルネサスエレクトロニクス株式会社 Semiconductor device and method of producing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112558374A (en) * 2019-09-26 2021-03-26 Tdk株式会社 Optical modulator

Also Published As

Publication number Publication date
JP6846834B2 (en) 2021-03-24
JPWO2019142581A1 (en) 2020-11-19

Similar Documents

Publication Publication Date Title
US20210175342A1 (en) Semiconductor device and manufacturing method thereof
KR102168345B1 (en) Semiconductor device and manufacturing method thereof
CN109427877A (en) Semiconductor devices and its manufacturing method
US10256321B2 (en) Semiconductor device including enhanced low-k spacer
CN108962736A (en) The forming method of semiconductor element
US20100006955A1 (en) Method for manufacturing semiconductor device and semiconductor device
US11217694B2 (en) Field-effect transistor and method for manufacturing the same
US11196001B2 (en) 3D ReRAM formed by metal-assisted chemical etching with replacement wordline and wordline separation
WO2019142581A1 (en) Mis type semiconductor device, method for producing same, and sputtering target which is used for production of same
TW201036071A (en) Metal gate transistor with barrier layer
JP4177803B2 (en) Manufacturing method of semiconductor device
JP6955748B2 (en) MIS type semiconductor device and its manufacturing method
Ding et al. Metal-insulator-metal capacitors using atomic-layer-deposited Al2O3∕ HfO2∕ Al2O3 sandwiched dielectrics for wireless communications
JP6941346B2 (en) MIS type semiconductor device and its manufacturing method
JP2002134737A (en) Field effect transistor and its manufacturing method
TWI624023B (en) Semiconductor structure and method of manufacturing the same
TWI600164B (en) Microelectronic structure and method for forming the same
US20100120211A1 (en) Methods of manufacturing Semiconductor Devices Including PMOS and NMOS Transistors Having Different Gate Structures
TW202347792A (en) Semiconductor structure and method of forming the same
JP2013135135A (en) Semiconductor device
JP2012060055A (en) Gate electrode and method of manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18901326

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2019565774

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18901326

Country of ref document: EP

Kind code of ref document: A1