JP2002134737A - Field effect transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor that has approximately 2 nm or smaller SiO2 conversion film thickness, uses a gate insulating film having small gate and leakage current and a high dielectric constant, and has high current drive force with a low operating voltage. SOLUTION: This field effect transistor has an Si substrate 101, source and drain regions 102 that are provided in the Si substrate 101, a gate insulating film that is provided on a channel region 103, between the source and drain regions 102 in the Si substrate 101 and has a lamination film constituted by an n layer including at least a silicon carbide film 104 and an oxide high dielectric film 105 with five or higher relative dielectric constant, and a gate electrode 106 that is provided on the gate insulating film. In the field effect transistor, the SiO2 conversion film thickness in the relative dielectric constant of the gate insulating film is to be set to 2 nm or smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor, and more particularly to a field effect transistor using a gate insulating film having a high dielectric constant.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and low-voltage operation of field effect transistors, thinning of a gate insulating film is required. However, when the gate insulating film is made thinner, a tunnel current flows, and a gate leak current increases exponentially.

[0003] In future generations in which the minimum processing dimension will be about 0.1 µm, if SiO ₂ or SiON, which is currently used as a material for the gate insulating film, is used, the thickness of the gate insulating film will be about 2 nm or less. Will be required,
The gate leakage current is too large, making it difficult to use. Therefore, it is considered that a high dielectric constant material instead of SiO ₂ is required as the gate insulating film.

[0004] Such high-permittivity materials, particularly those currently considered as high-permittivity materials having a relative permittivity of about 5 or more, desirably 10 or more, are substantially limited to metal oxides. For example, ZrO ₂ , HfO ₂ , Al ₂ O ₃ , Ta ₂
O _{5 and the} like. These high dielectric constant materials can have a large film thickness because of their high dielectric constant, and are effective in reducing leakage current. Accordingly, the converted film thickness of the high dielectric constant material with respect to SiO ₂ obtained from the ratio of the relative dielectric constant of the high dielectric constant material and SiO ₂ (the relative dielectric constant of SiO ₂ is 3.9) is about 2 nm or less. And a gate insulating film with small leakage current can be formed. Here, when the gate insulating film is composed of n layers, the actual film thickness of each layer is t _i (1 ≦ i ≦ n), and the relative dielectric constant of each layer is ε _i (1
When ≦ i ≦ n), the equivalent SiO ₂ film thickness obtained from the ratio of the relative permittivity of the SiO ₂ film to the gate insulating film is represented by the following (Equation 3). Note that 3.9 in the following (Equation 3) indicates the relative dielectric constant of SiO ₂ .

[0005]

(Equation 3)

However, since these high dielectric films are oxides, it is necessary to prevent oxygen defects from being introduced in order to form them with good crystallinity on a Si substrate. Then, in order to prevent the introduction of oxygen vacancies and form a gate insulating film composed of these oxide high dielectric films, it is necessary to form the gate insulating film at a high temperature in an oxygen atmosphere.

When an oxide high dielectric film is formed in an oxygen atmosphere at a high temperature, SiO ₂ is inevitably generated on the surface of the Si substrate, that is, between the Si substrate and the oxide high dielectric film. The thickness often reaches about 2 nm or more. That is, (1) the SiO ₂ equivalent film thickness is set to about 2 nm or less;
(2) Despite the use of an oxide high-dielectric film to achieve the two objectives of suppressing gate leakage current, a Si substrate is used to form this oxide high-dielectric film. on the surface, will be equivalent SiO ₂ thickness over SiO ₂ of interest from being generated, not a fundamental solution.

FIG. 3 shows a MOS capacitor using an oxide high dielectric film as a gate insulating film. This MOS capacitor is, as shown in FIG.
After removing the natural oxide film on the Si surface using hydrofluoric acid using the substrate 301, SrT is used as a high dielectric constant gate insulating film.
Approximately 10 nm thick S was formed by sputtering using iO _3.
An rTiO ₃ film 302 is formed. At this time, an argon gas containing about 20% oxygen is used as a sputtering atmosphere, and a film is formed at a plurality of kinds of temperatures from room temperature to about 600 ° C. After that, the gate electrode 303 is formed by the same method and material as usual, and the MOS capacitor is completed.

[0009] The Si substrate 301 of this MOS capacitor,
A voltage was applied between the gate electrodes 303, and electric characteristics were measured. In addition, the cross section was observed with a transmission electron microscope (TEM),
The thickness of the formed SrTiO ₃ film 302 and the thickness of the SiO ₂ film generated by oxidizing the Si substrate 301 during its formation were measured. Table 1 shows the results of forming the SrTiO ₃ film 302 at each film forming temperature.

[0010]

[Table 1]

As can be seen from Table 1, the film formation temperature is about 2
Below 00 ° C., the thickness of the SiO ₂ film formed at the interface with the Si substrate 301 is small, but the dielectric constant of the SrTiO ₃ film 302 is low, so that the SiO ₂ equivalent film thickness is large and the leak current is too large. . This is probably because the film forming temperature is too low and the crystallinity is not sufficient.

When the film forming temperature is as high as about 400 ° C. or higher, the dielectric constant of the SrTiO ₃ film 302 is high and the leak current is small, but the thick SiO 2 film is formed at the interface with the Si substrate 301.
_{When two} films are formed and the SiO ₂ film and the SrTiO ₃ film 302 are totaled, the equivalent SiO ₂ film thickness is still too large. Therefore, they cannot satisfy both (1) and (2) described above in any case.

In order to prevent oxidation of the Si substrate,
Many attempts have been made to introduce a nitride film, but the oxidation resistance of the Si nitride film is still insufficient, and when forming an oxide high dielectric film on the Si nitride film, the Si nitride film is similarly oxidized. S
Since it is iO ₂ , it is not a fundamental solution to the problem.

[0014]

As described above [0004], with the miniaturization of field effect transistors, although thinner gate insulating film is demanded, SiO ₂ equivalent thickness is about 2nm or less, gate A gate insulating film with a small leak current has not been obtained.

Therefore, the present invention has been made in view of this problem,
₂ equivalent thickness is about 2nm or less, using the gate insulating film of a small high dielectric constant of the gate leakage current, and an object thereof is to create a field effect transistor having a high current driving power at a low operating voltage.

[0016]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a Si substrate, a source / drain region provided in the Si substrate, and a channel region provided between the source / drain region in the Si substrate. Film and relative permittivity is 5
A gate insulating film having a stacked film composed of an n-layer including an oxide high dielectric film, and a gate electrode provided on the gate insulating film, wherein the actual thickness of each layer of the gate insulating film is t _i (1 ≦ i ≦ n), and the relative permittivity of each layer is ε _i (1
When ≦ i ≦ n, the field effect transistor is characterized in that the SiO ₂ equivalent film thickness of the gate insulating film represented by the above (Equation 3) is 2 nm or less.

Here, the silicon carbide film may be an amorphous film.

Further, the silicon carbide film may be grown epitaxially on the Si substrate.

Further, the relative permittivity of the oxide high dielectric film is 1
It may be 0 or more.

The present invention also provides a step of forming a source / drain region in a Si substrate, a step of forming a silicon carbide film on a channel region between the source / drain regions in the Si substrate, and a step of forming a silicon carbide film on the silicon carbide film. A step of forming an oxide high dielectric film having a relative dielectric constant of 5 or more, a step of oxidizing a stacked film including the silicon carbide film and the oxide high dielectric film, and a step of forming a gate electrode on the stacked film. Forming an n-layer (n is 2
A laminated film composed of the above), the actual thickness of each layer t _i
(1 ≦ i ≦ n) and the relative dielectric constant of each layer is ε _i (1 ≦ i ≦ n)
, The SiO _{2 of the} laminated film represented by the above (Equation 3)
Provided is a method for manufacturing a field-effect transistor, wherein the reduced film thickness is 2 nm or less.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The conditions required for a gate insulating film formed on a channel region formed on a Si substrate are as follows. (1) It has good oxidation resistance and protects the Si channel region serving as an underlayer from oxidation. (2) An insulator or a wide gap semiconductor. (3) The dielectric constant is high and the dielectric constant is 5 or more, preferably 10 or more. (4) An interface state is not formed at the interface with the channel region of Si as an underlayer, and the defect density is low.

In order to satisfy the above conditions, various materials were examined. As a result, in the present invention, it is optimal to include a stacked film of a silicon carbide film and an oxide high dielectric film as a gate insulating film. Was found. That is, a silicon carbide film having high oxidation resistance is provided on the Si channel region to prevent oxidation of the channel region, and at least an oxide high dielectric film having a high dielectric constant is laminated thereon.

It is known that a silicon carbide film has three types of crystal systems, hexagonal, cubic, and amorphous, depending on the preparation conditions. These physical properties are listed and shown in (Table 2).

[0024]

[Table 2]

As shown in Table 2, the most significant feature of silicon carbide is that it is extremely excellent in oxidation resistance. Among non-oxide compounds other than metals, that is, one of the most excellent compounds among compounds that can be used as a gate insulating film without oxidizing a Si channel region. As shown in (Table 2), the oxidation rate is about several tenths or less as compared with that of Si. Therefore, the surface of silicon carbide is not substantially oxidized or is extremely thin having a thickness of about several atomic layers or less. It is only to the extent that an oxide layer is formed. When silicon carbide is oxidized, carbon is released in the form of CO, and the remaining Si is oxidized to form SiO 2.
_Since this becomes ₂ , this oxide layer portion can also be used as a preferable gate insulating film. Therefore, with respect to the oxidation resistance and the protection of the channel region in (1), it can be said that a favorable effect can be obtained by using the silicon carbide film immediately above the channel region.

Next, regarding the problem (2) of insulating properties, silicon carbide has a band gap of about 2 to 3 eV, which is larger than the band gap of Si. Therefore, silicon carbide can be treated as an insulator in this case. In addition, since the oxide high-dielectric film is also a wide-gap semiconductor or an insulator, by laminating these, a favorable effect can also be obtained with respect to the insulating property (2).

Also, the problem of the relative dielectric constant of (3) is about 10 as shown in Table 2 for silicon carbide, and the relative dielectric constant of the oxide high dielectric film is also reduced in the present invention. Since about 5 or more are used, it can be said that favorable effects can be obtained.

Among them, as the oxide high dielectric film having a relative dielectric constant of about 10 or more, any metal oxide having a large dielectric constant can be used. For example, ZrO
₂ , HfO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ and other simple oxides of metals, composite metal oxides having a perovskite structure such as SrTiO ₃ and SrZrO ₃ , ZrSiO ₄ , HfS
Composite metal oxides with Si, such as iO ₄ and La ₂ SiO _5, can also be preferably used.

Further, regarding the point (4) in which no interface state is formed at the Si interface, the silicon carbide film formed immediately above the Si channel region has a small coordination number, so that the interface state becomes low. Therefore, it can be said that a favorable effect can be obtained. Alternatively, the silicon carbide film may be oxidized after forming the oxide high-dielectric film on the silicon carbide film. In this case, since the SiO ₂ film just above the channel region is a preferable interface, the interface state is higher. It is possible to suppress generation of places.

[0030]

EXAMPLES Hereinafter, embodiments of the present invention will be described in detail, but the present invention is not limited to these embodiments. (First Embodiment) A first embodiment of the present invention will be described. FIG. 1 shows a cross-sectional view of the field-effect transistor of the present embodiment. The field effect transistor according to the present embodiment includes a Si substrate 101 having a first conductivity type and a source / drain region 1 provided in the Si substrate 101 and having a second conductivity type.
02, a channel region 103 provided in the Si substrate 101 and connected to the source / drain region 102, a silicon carbide film 104 provided on the channel region 103, an SrTiO ₃ film 105 provided on the silicon carbide film 104, SrTi
It has a gate electrode 106 provided on the O ₃ film 105, an interlayer insulating film 107 provided on the gate electrode 106, and a sidewall 108 provided on a side surface of a region where the silicon carbide film 104 to the interlayer insulating film 107 are stacked.

Next, a method of manufacturing the field-effect transistor according to the present embodiment will be described with reference to FIG.

First, a Si substrate 101 having a first conductivity type
After removing the natural oxide film on the surface of the Si substrate 101 with hydrofluoric acid, the Si substrate 101 is placed in an ultra-high vacuum chamber.
And heated to about 1000 ° C., using acetylene (C, an unsaturated hydrocarbon) as a carrier gas using hydrogen.
₂ H ₂ ) is introduced into the chamber and allowed to flow for about 10 minutes. At this time, it was confirmed that the silicon carbide film 104 made of cubic silicon carbide was epitaxially grown on the Si substrate 101 by a reflection high-energy electron beam diffractometer (RHEED) attached to an ultra-high vacuum chamber.

Next, an SrTiO ₃ film 105 is formed as a gate insulating film made of an oxide high dielectric film to a thickness of about 10 nm by a sputtering method. At this time, an argon gas containing about 20% of oxygen is used as a sputtering atmosphere, and a film is formed at a substrate temperature of about 600 ° C.

Next, a gate electrode 106 is formed by sputtering using platinum, and an interlayer insulating film 107 is formed on the gate electrode 106 by using SiN or the like.

Next, the silicon carbide film 104, the SrTiO ₃ film 105, the gate electrode 106, and the interlayer insulating film 107 are patterned into a predetermined shape. Then, the Si
A film made of O ₂ is formed on the entire surface and is etched to form a sidewall 108 on a side portion from the silicon carbide film 104 patterned into a predetermined shape to the interlayer insulating film 107.

The source / drain region 102 is
In order to obtain the conductivity type, B, P, As, or the like is doped into a predetermined region of the Si substrate 101 using the gate electrode 106 as a mask.

Here, the electrical characteristics of the MOS capacitor are measured, and a TEM observation of the cross section is performed.

As a result, the surface of the Si substrate 101 has a thickness of about 0.1 mm.
Silicon carbide film 1 made of cubic silicon carbide having a thickness of 5 nm
04 was epitaxially grown, and an SrTiO ₃ film 105 having a thickness of about 10 nm was observed to grow thereon. Note that, on the Si substrate 101 or the silicon carbide film 10
On No. 4, no amorphous layer in which Si was oxidized to SiO ₂ was observed.

The electrical characteristics of the silicon carbide film 10
4 and the SrTiO ₃ film 105 resulted in a total SiO ₂ equivalent film thickness of about 0.7 nm, a very low value was obtained, and a small leak current of about 10 ⁻³ A / cm ² was obtained.
Therefore, it was found that the specifications for the gate insulating film of the generation in which the SiO ₂ equivalent film thickness was about 2 nm or less, the leakage current was small, and the minimum processing dimension was about 0.1 μm were satisfied.

This is because the silicon carbide film 104 having good oxidation resistance
Is formed immediately above the channel region 103, and the channel region 10 is formed.
3 is protected from oxidation, so that no SiO ₂ film is formed. Further, since the SrTiO ₃ film 105 having a high dielectric constant is formed thereon, the equivalent SiO ₂ film thickness can be reduced.

Further, since the silicon carbide film 104 is epitaxially grown directly on the channel region 103 made of Si, and the SrTiO ₃ film 105 is grown on the silicon carbide film 104, the characteristics of these films become uniform. Is higher, and the leakage current is smaller, which is more preferable.

Further, when the electric characteristics of the field effect transistor were measured, a well-saturated drain current was obtained at a gate voltage of about 1 V. In addition, the S factor, which is a voltage necessary to change the current by one digit in the subthreshold region, which reflects the amount of interface states between the channel region 103 and the gate insulating film, that is, the silicon carbide film 104, is as low as about 85 mV. It can be said that the interface state is small. From these, it was confirmed that a high-performance field-effect transistor having a small leakage current and corresponding to a low voltage was formed. (Second Embodiment) Next, a second embodiment of the present invention will be described. The field effect transistor of the present embodiment will be described with reference to FIG.

The structure of the field-effect transistor of this embodiment is almost the same as that of the first embodiment. The point that silicon carbide film 104 is an amorphous film
This is different from the first embodiment.

Next, a method of manufacturing the field-effect transistor according to this embodiment will be described with reference to FIG.

First, a Si substrate 101 having a first conductivity type
After removing the natural oxide film on the surface of the Si substrate 101 with hydrofluoric acid, the Si substrate 101 is placed in an ultra-high vacuum chamber.
And heated to about 650 ° C., C ₂ H ₂ is introduced into the ultra-high vacuum chamber using hydrogen as a carrier gas, and simultaneously, Si is vapor-deposited on the surface of the Si substrate 101 by an electron beam vapor deposition apparatus. . At this time, the growth of the amorphous layer was confirmed by RHEED attached to the ultrahigh vacuum chamber.

Next, an SrTiO ₃ film 105, a gate electrode 106, an interlayer insulating film 107, a side wall 108, and a source / drain region 102 are formed by using the same material and method as in the first embodiment.

Here, the electrical characteristics of the MOS capacitor are measured, and a TEM observation of the cross section is performed.

As a result, about 0.1 μm
The growth of a flat amorphous layer having a thickness of 6 nm was confirmed. As a result of composition analysis by energy dispersive X-ray composition analysis (EDX), it was confirmed that the amorphous layer was not SiO ₂ but silicon carbide having a substantially stoichiometric composition. Then, it was observed that a polycrystalline SrTiO ₃ film 105 was grown on this amorphous silicon carbide film 104 with a thickness of about 10 nm. The Si substrate 10
No amorphous layer in which Si was oxidized to become SiO ₂ was found on 1 or on the silicon carbide film 104.

The electrical characteristics of the silicon carbide film 10
4 and the SrTiO ₃ film 105 had a total SiO ₂ equivalent film thickness of about 1.1 nm, a very low value was obtained, and a small leak current of about 10 ⁻⁴ A / cm ² was obtained.
Therefore, as in the first embodiment, this embodiment also satisfies the specifications for a generation of a gate insulating film having a SiO ₂ equivalent film thickness of about 2 nm or less, a small leak current, and a minimum processing dimension of about 0.1 μm. I found out.

This is because the silicon carbide film 104 having good oxidation resistance
Is formed immediately above the channel region 103, and the channel region 10 is formed.
3 is protected from oxidation, so that no SiO ₂ film is formed. Further, since the SrTiO ₃ film 105 having a high dielectric constant is formed thereon, the equivalent SiO ₂ film thickness can be reduced.

The silicon carbide film 104 formed directly on the channel region 103 made of Si is preferable because it is an amorphous layer and has no grain boundaries and can form a film having uniform characteristics. .

Further, when the electric characteristics of the field-effect transistor were measured, a well-saturated drain current was obtained at a gate voltage of about 1 V. Further, the S factor, which is a voltage necessary for changing the current by one digit in the subthreshold region, which reflects the amount of interface states between the channel region 103 and the gate insulating film, that is, the silicon carbide film 104, is as low as about 82 mV. It can be said that the interface state is small. From these, it was confirmed that a high-performance field-effect transistor having a small leakage current and corresponding to a low voltage was formed. (Third Embodiment) Next, a third embodiment of the present invention will be described. FIG. 2 is a cross-sectional view of the field-effect transistor according to the present embodiment, and a description will be given with reference to FIG.

Structure of the Field Effect Transistor of the Present Embodiment
Is substantially the same as the field-effect transistor of the second embodiment.
And a silicon carbide film on the channel region 103 instead of S
iO _TwoThe point that the film 201 is provided is different from the second embodiment.
You. In the present embodiment, an amorphous
Silicon carbide film and SrTiO_ThreeFilm 105 was laminated
Thereafter, the silicon carbide film is oxidized to form SiO 2_TwoWhat is used as the film 201
It is.

Next, a method of manufacturing the field-effect transistor of this embodiment will be described with reference to FIG.

First, a Si substrate 101 having the first conductivity type
After removing the natural oxide film on the surface of the Si substrate 101 with hydrofluoric acid, the Si substrate 101 is placed in an ultra-high vacuum chamber.
And heated to about 650 ° C., C ₂ H ₂ is introduced into the ultra-high vacuum chamber using hydrogen as a carrier gas, and simultaneously, Si is vapor-deposited on the surface of the Si substrate 101 by an electron beam vapor deposition apparatus. . At this time, the growth of the amorphous layer was confirmed by RHEED attached to the ultrahigh vacuum chamber. Then, SrTi
The O ₃ film 105 is formed using the same material and method as in the second embodiment.

Next, the amorphous layer and the SrTiO ₃ film 105 formed on the Si substrate 101 are put into an oxidation furnace,
The amorphous layer under the SrTiO ₃ film 105 is oxidized.
At the outlet of the oxidation furnace, while monitoring the CO gas and CO ₂ gas, the Si substrate 101 is heated to about 1000 ° C. and oxygen is flowed. After the CO gas and CO ₂ gas are no longer detected at the outlet of the oxidation furnace, oxidation is performed. The process ends.

Next, the gate electrode 106 and the interlayer insulating film 10
7, the side wall 108 and the source / drain region 102
It is formed using the same material and method as in the embodiment.

Here, the electrical characteristics of the MOS capacitor are measured, and the cross section is observed with a TEM.

As a result, about 0.
The growth of a flat amorphous layer having a thickness of 8 nm was confirmed. As a result of composition analysis by EDX, it was confirmed that this amorphous layer had a composition of almost SiO ₂ . It was observed that a polycrystalline SrTiO ₃ film 105 was grown on this amorphous SiO ₂ film 201 to a thickness of about 10 nm.

The electrical characteristics of the SiO ₂ film 20
The total SiO ₂ equivalent film thickness of 1 and the SrTiO ₃ film 105 was about 1.3 nm, a very low value was obtained, and the leak current was also a small value of about 10 ⁻⁶ A / cm ² .
Therefore, as in the second embodiment, this embodiment also satisfies the specifications for a gate insulating film of a generation in which the equivalent SiO ₂ film thickness is about 2 nm or less, the leak current is small, and the minimum processing dimension is about 0.1 μm. I found out.

In this embodiment, an amorphous silicon carbide film is formed on the channel region 103, a high dielectric constant SrTiO ₃ film 105 is formed thereon, and then the amorphous silicon carbide film is oxidized to form SiO _2. It is a film 201.
By forming the gate insulating film in this manner, the silicon carbide film functions as an oxidation preventing film for the channel region 103, and then is oxidized to form the SiO ₂ film 201, which is excellent as an interface with the channel region 103. A film can be provided directly above the channel region 103. Therefore, generation of interface states can be minimized.

Further, if the silicon carbide film is formed thin, it is possible to form the SiO ₂ film 201 having a correspondingly small thickness. Further, a high dielectric constant SrTiO ₃ film 105 is formed thereon.
In order to form the gate insulating film, SiO
_{(2) The} equivalent film thickness can be reduced.

Further, when the electric characteristics of the field effect transistor were measured, a well-saturated drain current was obtained at a gate voltage of about 1 V. In addition, the S factor, which is a voltage necessary to change the current by one digit in the subthreshold region, which reflects the amount of interface state between the channel region 103 and the gate insulating film, that is, the SiO ₂ film 201, is as low as about 75 mV. It can be said that the interface state is small. From these, it was confirmed that a high-performance field-effect transistor having a small leakage current and corresponding to a low voltage was formed.

[0064]

As described in detail above, according to the present invention,
A field effect transistor having a low operating voltage and a high current drivability can be provided by using a high dielectric constant gate insulating film having a SiO ₂ equivalent film thickness of about 2 nm or less and a small gate leak current.

[Brief description of the drawings]

FIG. 1 is a sectional view of a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a field-effect transistor according to a third embodiment of the present invention.

FIG. 3 is a cross-sectional view of a MOS capacitor for explaining a conventional gate insulating film.

[Explanation of symbols]

101 and 301 ... Si substrate 102 ... source-drain regions 103 ... channel region 104 ... silicon carbide film 105,302 ... SrTiO ₃ film 106,303 ... gate electrode 107 ... interlayer insulating film 108 ... side wall 201 ... SiO ₂ film

Continuing from the front page (72) Inventor Takashi Yonohe 1F, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in the Toshiba R & D Center 5F040 DA19 DC01 EC04 ED01 ED03 EL06 FA05 FC05

Claims (5)

[Claims] 1. A silicon substrate, a source / drain region provided in the Si substrate, and a channel region provided between the source / drain regions in the Si substrate, wherein at least a silicon carbide film and a relative permittivity are provided. A gate insulating film having a stacked film composed of an n-layer including an oxide high dielectric film of 5 or more, and a gate electrode provided on the gate insulating film; Film thickness t _i
(1 ≦ i ≦ n) and the relative dielectric constant of each layer is ε _i (1 ≦ i ≦ n)
Wherein the SiO ₂ equivalent film thickness of the gate insulating film represented by the following (formula 1) is 2 nm or less. (Equation 1) 2. The field effect transistor according to claim 1, wherein said silicon carbide film is an amorphous film. 3. The field effect transistor according to claim 1, wherein said silicon carbide film is epitaxially grown on said Si substrate. 4. A high dielectric constant oxide film having a relative dielectric constant of 10
2. The field effect transistor according to claim 1, wherein: 5. A step of forming a source / drain region in a Si substrate, a step of forming a silicon carbide film on a channel region between the source / drain regions in the Si substrate, and a step of forming a silicon carbide film on the silicon carbide film. A step of forming an oxide high dielectric film having a relative dielectric constant of 5 or more, a step of oxidizing a stacked film including the silicon carbide film and the oxide high dielectric film, and A step of forming a gate electrode, wherein the actual thickness of each layer of the laminated film composed of n layers (n is 2 or more) is t _i (1 ≦ i ≦ n), and the relative dielectric constant of each layer is When ε _i (1 ≦ i ≦ n), a method of manufacturing a field-effect transistor, wherein the SiO ₂ equivalent film thickness of the laminated film represented by the following (Formula 2) is 2 nm or less. (Equation 2)