WO2019140994A1 - Capacitor, manufacturing method of capacitor, and semiconductor equipment - Google Patents

Capacitor, manufacturing method of capacitor, and semiconductor equipment Download PDF

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Publication number
WO2019140994A1
WO2019140994A1 PCT/CN2018/115359 CN2018115359W WO2019140994A1 WO 2019140994 A1 WO2019140994 A1 WO 2019140994A1 CN 2018115359 W CN2018115359 W CN 2018115359W WO 2019140994 A1 WO2019140994 A1 WO 2019140994A1
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Prior art keywords
capacitor
lower electrode
layer
upper electrode
dielectric layer
Prior art date
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PCT/CN2018/115359
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French (fr)
Chinese (zh)
Inventor
杨玉杰
丁培军
夏威
郑金果
王宽冒
杨敬山
蒋秉轩
谢谦
Original Assignee
北京北方华创微电子装备有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority claimed from CN201820074900.4U external-priority patent/CN215451402U/en
Priority claimed from CN201810044659.5A external-priority patent/CN108281414A/en
Application filed by 北京北方华创微电子装备有限公司 filed Critical 北京北方华创微电子装备有限公司
Priority to KR1020207020219A priority Critical patent/KR20200092403A/en
Priority to JP2020560527A priority patent/JP7057445B2/en
Priority to SG11202006651RA priority patent/SG11202006651RA/en
Priority to KR1020237035460A priority patent/KR20230148398A/en
Publication of WO2019140994A1 publication Critical patent/WO2019140994A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67167—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
    • H—ELECTRICITY
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    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67742—Mechanical parts of transfer devices
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    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements

Definitions

  • the invention belongs to the field of semiconductor manufacturing, and in particular relates to a capacitor, a method for manufacturing the capacitor and a semiconductor device.
  • micro-capacitors are generally referred to as microcapacitors.
  • the existing microcapacitor generally comprises an upper metal electrode, a lower metal electrode and a dielectric layer therebetween, wherein the upper metal electrode comprises a W film layer and a TiN film layer which are sequentially stacked in a direction close to the lower metal electrode;
  • the lower metal electrode includes a TiN film layer, a W film layer, and a TiN film layer which are sequentially stacked in a direction close to the upper metal electrode;
  • the dielectric layer is an Al 2 O 3 film layer.
  • both the TiN film layer and the W film layer are prepared by a CVD (Chemical Vapor Deposition, hereinafter referred to as CVD) device, and the dielectric layer is prepared by an ALD (Atomic Layer Deposition, hereinafter referred to as ALD) device.
  • CVD Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • the present invention is directed to solving the above technical problems existing in the prior art, and provides a capacitor, a capacitor manufacturing method, and a semiconductor device, which have a simple structure, thereby simplifying a manufacturing process, and reducing exposure of a substrate during transmission.
  • the number of times in the air can reduce the contamination of the film surface to some extent.
  • the present invention provides a capacitor including an upper electrode, a lower electrode, and a dielectric layer, the dielectric layer being disposed between the upper electrode and the lower electrode, the upper electrode and the lower electrode
  • a capacitor including an upper electrode, a lower electrode, and a dielectric layer, the dielectric layer being disposed between the upper electrode and the lower electrode, the upper electrode and the lower electrode
  • the material of the metal layer comprises Al, Au, Ti or Cu.
  • the upper electrode and the lower electrode are both prepared by a physical vapor deposition process.
  • the thickness of the upper electrode and the lower electrode ranges from 50 to 500 nm.
  • the thickness of the upper electrode and the lower electrode ranges from 100 to 300 nm.
  • the dielectric layer comprises an Al 2 O 3 layer, a TiO 2 layer or an Hf O 4 layer.
  • the thickness of the dielectric layer ranges from 5 to 15 nm.
  • the capacitor is a high-density capacitor.
  • the present invention further provides a semiconductor device for preparing the above capacitor provided by the present invention, the semiconductor device comprising: a physical vapor deposition chamber, an atomic layer deposition chamber, and a transmission platform;
  • the physical vapor deposition chamber is used to prepare an upper electrode and a lower electrode of the capacitor
  • the atomic layer deposition chamber is used to prepare a dielectric layer of the capacitor
  • the transport platform is coupled to the physical vapor deposition chamber and the atomic layer deposition chamber, respectively, for transporting a substrate.
  • degassing chamber for degassing and annealing the substrate; the degassing chamber being coupled to the transport platform.
  • pre-cleaning chamber for removing impurities on the surface of the substrate; the pre-cleaning chamber being connected to the transport platform.
  • the number of the physical vapor deposition chambers is plural, and the plurality of physical vapor deposition chambers are respectively used for depositing thin films of a plurality of materials.
  • the target base distance is greater than 90 mm.
  • the target base distance ranges from 200 to 410 mm.
  • the present invention also provides a capacitor manufacturing method, including the following steps:
  • the upper electrode and the lower electrode each comprise a metal layer, and the metal layer of the upper electrode and the metal layer of the lower electrode are made of the same material.
  • the metal layer comprises Al, Au, Ti or Cu.
  • the process pressure ranges from 0 to 2 mTorr, and the sputtering power ranges from 30-38kW, the bias power range is 400-1000W.
  • the dielectric layer comprises an Al 2 O 3 layer, a TiO 2 layer or an Hf O 4 layer.
  • the process temperature ranges from 300 to 400 °C.
  • a degassing process for degassing the surface to be deposited of the substrate is further included.
  • an annealing process is further included.
  • the capacitor In the capacitor, the capacitor manufacturing method and the semiconductor device, the capacitor includes an upper electrode, a lower electrode, and a dielectric layer disposed therebetween, wherein the upper electrode and the lower electrode each comprise a metal layer, and The metal layer of the upper electrode is the same material as the metal layer of the lower electrode.
  • the capacitor has a simple structure, which simplifies the manufacturing process and reduces the number of times the substrate is exposed to the air during transport, thereby reducing the contamination of the film surface to some extent.
  • FIG. 1 is a schematic structural diagram of a capacitor according to a first embodiment of the present invention
  • FIG. 2a is a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention.
  • 2b is a schematic structural diagram of a semiconductor device according to a modified embodiment of the second embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a first chamber in a second embodiment of the present invention.
  • FIG. 4 is a flowchart of a method for fabricating a capacitor according to a third embodiment of the present invention.
  • a first embodiment of the present invention provides a capacitor including a substrate 20 , an upper electrode 21 , a lower electrode 22 , and a dielectric layer 23 disposed between the upper electrode 21 and the lower electrode 22 , and
  • the upper electrode 21 and the lower electrode 22 each include a metal layer, and the metal layer of the upper electrode 21 and the metal layer of the lower electrode 22 are made of the same material.
  • the above capacitor is a three-layer structure composed of a metal layer/dielectric layer/metal layer, which is similar to a “sandwich” structure, which is simple in structure, thereby simplifying the manufacturing process and reducing the exposure of the substrate to the air during transmission. The number of times can reduce the contamination of the film surface to some extent.
  • the capacitor is a trench capacitor, and the capacitor further includes a substrate 20, which may be made of SiO2 or other materials.
  • the substrate 20 has a trench 201.
  • the upper electrode 21, the lower electrode 22, and the dielectric layer 23 are formed on the surface of the substrate 20 on which the above-described trench 201 is located, and cover the surface.
  • the surface referred to herein includes both the surface on which the above-described groove 201 of the substrate 20 is located and the inner surface of the groove 201 which is exposed to the air. Also, after the upper electrode 21, the lower electrode 22, and the dielectric layer 23 are formed, the trench 201 is completely filled.
  • the capacitor is a high-density capacitor.
  • the so-called high-density capacitor refers to a capacitor formed by depositing a metal layer and a dielectric layer in a high-density trench.
  • the material of the metal layer includes Al, Au, Ti, Cu, or the like.
  • both the upper electrode 21 and the lower electrode 22 are prepared by a physical vapor deposition (PVD) process.
  • PVD physical vapor deposition
  • a metal layer is usually prepared by a chemical vapor deposition (CVD) process, and the present invention can greatly reduce the resistivity of the metal layer and increase the density of the metal layer by preparing a metal layer by using a PVD process.
  • surface flatness for example, the resistivity of the Al layer prepared by the PVD process is nearly 100 times lower than that of the W layer prepared by the CVD process, and the thickness of the Al layer on the inner sidewall of the trench 201 is compared to W The layer is much thinned.
  • the thickness of the dielectric layer 23 is constant, the thinner the thickness of the metal layer is, the larger the area of the metal layer is, so that the capacitance value of the capacitor is larger, thereby improving the electrode characteristics of the capacitor.
  • the thickness of the upper electrode 21 and the lower electrode 22 ranges from 50 to 500 nm, preferably from 100 to 300 nm. Within this thickness range, both the quality of the capacitor and the capacitance of the capacitor can be increased.
  • the dielectric layer 23 includes a film layer having a large dielectric constant such as an Al 2 O 3 layer, a TiO 2 layer, or an HfO 4 layer.
  • the thickness of the dielectric layer 23 ranges from 5 to 15 nm.
  • the thickness of the dielectric layer 23 can be adjusted with reference to its breakdown voltage. For example, if the breakdown voltage of the capacitor is 2.5V, the thickness of the dielectric layer 23 can be controlled to be between 9-10 nm.
  • a second embodiment of the present invention provides a semiconductor device that can be used to prepare a capacitor.
  • the semiconductor device includes: a physical vapor deposition (PVD) chamber, an atomic layer deposition (Atomic Layer Deposition, hereinafter referred to as ALD) chamber, and a transmission platform.
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • the PVD chamber is used to prepare the upper and lower electrodes of the capacitor
  • the ALD chamber is used to prepare a dielectric layer of the capacitor
  • the transfer platform is respectively connected to the PVD chamber and the ALD chamber for transporting the substrate.
  • the transport platform mainly includes a transfer chamber and a loading/unloading station, wherein the transfer chamber is a vacuum chamber, and a robot is disposed in the transfer chamber.
  • a PVD chamber and an ALD chamber surround and are in communication with the transfer chamber to form a cluster device system.
  • the substrate is taken out from the loading table by the robot, and the substrate is transferred to the PVD chamber and the ALD chamber in a process sequence, and after the completion of the preparation of the capacitor, the processing is completed.
  • the substrate is transmitted to the unloading station.
  • the semiconductor device provided by the embodiment of the invention uses the PVD chamber to prepare the upper electrode and the lower electrode of the capacitor, which greatly reduces the resistivity of the upper electrode and the lower electrode and improves the upper electrode and the lower electrode compared with the chemical vapor deposition process. Densification and surface flatness, so that the metal electrode performance of the upper and lower electrodes can be improved, thereby improving the performance of the capacitor; meanwhile, the semiconductor device provided by the embodiment of the invention has the PVD chamber and the ALD chamber and the same transmission platform. Integrated to form a single cluster device system, which not only reduces equipment costs, but also avoids exposure of the substrate to air during transport, thereby avoiding contamination of the film surface. In addition, the process cost of the PVD chamber and the ALD chamber is low, which is advantageous for the control of industrialization costs.
  • the semiconductor device includes a PVD chamber 31, an ALD chamber 33, a degassing chamber 35, a pre-cleaning chamber 36, and a transport platform, wherein the transport platform includes a transfer chamber 34, which is a vacuum chamber A chamber is provided and a robot is disposed in the transfer chamber 34.
  • the PVD chamber 31, the ALD chamber 33, the degassing chamber 35, and the pre-cleaning chamber 36 surround the transfer chamber 34 and communicate with the transfer chamber 34 to form a cluster device system.
  • the PVD chamber 31 is used to implement a PVD process to prepare the upper and lower electrodes of the capacitor.
  • the upper electrode and the lower electrode respectively comprise a metal layer, and the metal layer of the upper electrode and the metal layer of the lower electrode are the same material.
  • the material of the metal layer includes Al, Au, Ti, Cu, or the like.
  • a target 41 is disposed at the top of the PVD chamber 31, and a susceptor 42 for carrying the workpiece to be processed is disposed under the target 41. Further, the sputtering surface of the sputtering target 41 is disposed opposite to the bearing surface of the susceptor 42, and the distance H between the sputtering surface of the sputtering target 41 and the bearing surface of the susceptor 42 is referred to as a target base distance.
  • the target base distance is greater than 90 mm, so that the chamber can meet the requirements of implementing a long-range sputtering process, thereby facilitating the improvement of film uniformity.
  • the target base distance ranges from 200 to 410 mm, and within this range, the production efficiency can be ensured while satisfying the requirements of the long-range sputtering process.
  • the ALD chamber 33 is used to perform an atomic layer deposition process to prepare a capacitive dielectric layer.
  • the dielectric layer comprises a film layer having a large dielectric constant such as an Al 2 O 3 layer, a TiO 2 layer or an Hf O 4 layer.
  • the degassing chamber 35 is used to degas and anneal the workpiece.
  • the pre-cleaning chamber 36 is for cleaning the surface of the workpiece to remove impurities on the surface of the workpiece.
  • the PVD chamber 31 is one, but the present invention is not limited thereto. In practical applications, the number of PVD chambers 31 may also be plural, and a plurality of PVD chambers 31 are disposed around the transfer chamber 34 to form a cluster device system with the other chambers.
  • the substrate is transferred into the PVD chamber 31 to prepare the lower electrode, the substrate is transferred into the ALD chamber 33 to prepare a dielectric layer, and finally the substrate is again The upper electrode is prepared by being transferred into the PVD chamber 31.
  • the semiconductor device when the semiconductor device is provided with two PVD chambers (31, 32), after the substrate is transferred into the first PVD chamber 31 to prepare the lower electrode, the substrate is transferred into the ALD chamber 33. A dielectric layer is prepared and finally transferred to a second PVD chamber 32 to prepare an upper electrode.
  • the semiconductor device in which one PVD chamber 31 is provided, it is not necessary to return the substrate to the PVD chamber, which is more advantageous for the flow operation, thereby improving the processing efficiency of the semiconductor device.
  • a third embodiment of the present invention provides a capacitor manufacturing method, including the following steps:
  • An upper electrode is formed on the surface of the dielectric layer facing away from the lower electrode by a physical vapor deposition process.
  • the resistivity of the upper and lower electrodes can be greatly reduced, and the compactness and surface flatness of the upper and lower electrodes can be improved, thereby improving the performance of the metal electrodes of the upper and lower electrodes. To improve the performance of the capacitor.
  • a capacitor manufacturing method is used to fabricate the capacitor shown in FIG. 1 by using the semiconductor device provided by the second embodiment of the present invention.
  • the capacitor manufacturing method includes:
  • step S1 a degassing process is performed, that is, the surface to be deposited of the substrate 20 is subjected to a degassing treatment.
  • step S1 the substrate 20 is first transferred to the degassing chamber 35 for degassing treatment to remove impurities on the surface of the substrate 20.
  • the pressure of the degassing chamber 35 is controlled to be 0-10 Torr, and the temperature is controlled at 0 to 400 °C.
  • the pressure of the degassing chamber 35 is controlled at 1-7 Torr and the temperature is controlled at 300-400 °C.
  • the substrate 20 can be made of SiO2 or other materials. Also, the substrate 20 has a trench 201.
  • the surface to be deposited of the substrate 20 described above includes both the surface of the substrate 20 on which the trench 201 is located, and the inner surface of the trench 201 which is exposed to air.
  • step S2 the lower electrode 22 is formed on the surface to be deposited of the substrate 20 by a physical vapor deposition process.
  • step S3 a dielectric layer 23 is formed on the surface of the lower electrode 22 facing away from the substrate 20 by an atomic layer deposition process.
  • step S4 the upper electrode 21 is formed on the surface of the dielectric layer 23 facing away from the lower electrode 22 by a physical vapor deposition process.
  • the upper electrode 21, the lower electrode 22, and the dielectric layer 23 cover the surface to be deposited of the substrate 20, and the trench 201 is completely filled.
  • the upper electrode 21 and the lower electrode 22 each include a metal layer, and the metal layers of the upper electrode 21 and the metal layer of the lower electrode 22 are made of the same material.
  • the capacitor is a three-layer structure composed of a metal layer/dielectric layer/metal layer, similar to a “sandwich” structure, which is simple in structure, thereby simplifying the manufacturing process and reducing the exposure of the substrate to the air during transport. The number of times can thus reduce the contamination of the film surface to some extent.
  • the material of the metal layer includes Al, Au, Ti, Cu, or the like.
  • the dielectric layer 23 includes a film layer having a large dielectric constant such as an Al 2 O 3 layer, a TiO 2 layer, or an HfO 4 layer.
  • the top portion in the PVD chamber 31 for preparing the upper electrode 21 and the lower electrode 22 is provided with a target 41, and a susceptor 42 for carrying a workpiece to be processed is disposed below the target 41.
  • the target base distance is greater than 90 mm, preferably 200-410 mm.
  • a process gas is introduced into the PVD chamber 31, and the chamber pressure is 0-5 mTorr, preferably 0-2 mTorr.
  • the sputtering power applied to the target 41 is 0-40 kW, preferably 30-38 kW.
  • the bias power applied to the susceptor is 0-2000 W, preferably 400-1000 W.
  • the thickness of the upper electrode 21 and the lower electrode 22 ranges from 50 to 500 nm, preferably from 100 to 300 nm. Within this thickness range, both the quality of the capacitor and the capacitance of the capacitor can be increased.
  • the thickness of the dielectric layer 23 ranges from 5 to 15 nm.
  • the thickness of the dielectric layer 23 can be adjusted with reference to its breakdown voltage. For example, if the breakdown voltage of the capacitor is 2.5V, the thickness of the dielectric layer 23 can be controlled to be between 9-10 nm.
  • step S3 when the atomic layer deposition process is performed, the temperature is controlled at 150-400 ° C, preferably 300-400 ° C, to be able to anneal the lower electrode 22 while preparing the dielectric layer 23, thereby optimizing the lower electrode.
  • the crystallization of 22 improves the performance of the lower electrode 22.
  • step S5 the upper electrode 21, the lower electrode 22, and the dielectric layer 23 are annealed.
  • the annealing treatment may be performed in the degassing chamber 35, or may be performed in other chambers having an annealing function.
  • the chamber pressure is controlled to be 0 to 10 Torr, preferably 1 to 7 Torr.
  • the temperature is controlled at 0 to 400 ° C, preferably 300 to 400 ° C.
  • the target base distance is preferably 290 mm
  • the chamber pressure is 0.1-1 mTorr, which is applied to the target 41.
  • the sputtering power was 30-35 kW
  • the bias power applied to the susceptor 42 was 500-800 W
  • the thicknesses of the prepared upper electrode 21 and lower electrode 22 were both 100-200 nm.

Abstract

A capacitor and a manufacturing method thereof, and semiconductor equipment. The capacitor comprises an upper electrode (21), a lower electrode (22), and a dielectric layer (23) provided between the upper electrode (21) and the lower electrode (22). Each of the upper electrode (21) and the lower electrode (22) comprises a metal layer. The metal layers of the upper electrode (21) and the lower electrode (22) are made of the same material. The capacitor has a simple structure, such that a manufacturing process can be simplified. Moreover, the number of times a substrate is exposed to the air in a transport process can be reduced, thereby reducing contamination of a film surface to a certain extent.

Description

电容、电容制作方法及半导体设备Capacitor, capacitor manufacturing method and semiconductor device 技术领域Technical field
本发明属于半导体制造领域，具体涉及一种电容、该电容的制作方法及半导体设备。The invention belongs to the field of semiconductor manufacturing, and in particular relates to a capacitor, a method for manufacturing the capacitor and a semiconductor device.
背景技术Background technique
电容器作为电路中最基本的元件之一，对整个电子设备起着至关重要的作用。随着半导体技术的发展，薄膜沉积技术使电子元器件进入纳米级工艺制程，成为了电容器走向微型化、集成化的主要手段，一般将制备成的微型化的电容器称为微型电容。As one of the most basic components in a circuit, a capacitor plays a vital role in the entire electronic device. With the development of semiconductor technology, thin film deposition technology has enabled electronic components to enter the nano-scale process, becoming the main means for miniaturization and integration of capacitors. Micro-capacitors are generally referred to as microcapacitors.
目前，现有的微型电容一般包括上金属电极、下金属电极以及位于二者之间的电介质层，其中，上金属电极包括朝靠近下金属电极的方向依次层叠的W膜层和TiN膜层；下金属电极包括朝靠近上金属电极的方向依次层叠的TiN膜层、W膜层和TiN膜层；电介质层为Al2O3膜层。At present, the existing microcapacitor generally comprises an upper metal electrode, a lower metal electrode and a dielectric layer therebetween, wherein the upper metal electrode comprises a W film layer and a TiN film layer which are sequentially stacked in a direction close to the lower metal electrode; The lower metal electrode includes a TiN film layer, a W film layer, and a TiN film layer which are sequentially stacked in a direction close to the upper metal electrode; the dielectric layer is an Al 2 O 3 film layer.
上述电容在实际应用中存在以下问题，即：The above capacitors have the following problems in practical applications, namely:
由于上述电容的层数较多，结构复杂，导致制作工艺流程复杂，需要六步沉积工艺才能完成。而且，在这六步沉积工艺中，TiN膜层和W膜层均采用CVD(Chemical Vapor Deposition，以下简称CVD)设备制备，而电介质层采用ALD(Atomic Layer Deposition，以下简称ALD)设备制备，这些设备相互独立，不能集成在一个真空传输系统内，在每个独立设备完成一工艺之后，需要将基片传递至下一工艺对应的独立设备。由于两个独立设备之间的基片传递会使基片暴露在空气中，上述电容的整个制备流程中基片会暴露在空气中五次，这不可避免地对沉积薄膜的表面造成污染。Due to the large number of layers of the above capacitors and the complicated structure, the manufacturing process is complicated, and a six-step deposition process is required to complete. Moreover, in the six-step deposition process, both the TiN film layer and the W film layer are prepared by a CVD (Chemical Vapor Deposition, hereinafter referred to as CVD) device, and the dielectric layer is prepared by an ALD (Atomic Layer Deposition, hereinafter referred to as ALD) device. The devices are independent of each other and cannot be integrated into a vacuum transmission system. After each individual device completes a process, the substrate needs to be transferred to a separate device corresponding to the next process. Since substrate transfer between two separate devices exposes the substrate to air, the substrate is exposed to air five times throughout the preparation process of the above capacitors, which inevitably contaminates the surface of the deposited film.
发明内容Summary of the invention
本发明旨在解决现有技术中存在的上述技术问题，提供了一种电容、电容制作方法及半导体设备，其结构简单，从而可以简化制作工艺流程，而且可以减少基片在传输过程中暴露在空气中的次数，从而可以在一定程度上减少薄膜表面的污染。The present invention is directed to solving the above technical problems existing in the prior art, and provides a capacitor, a capacitor manufacturing method, and a semiconductor device, which have a simple structure, thereby simplifying a manufacturing process, and reducing exposure of a substrate during transmission. The number of times in the air can reduce the contamination of the film surface to some extent.
解决上述技术问题，本发明提供了一种电容，包括上电极、下电极和电介质层，所述电介质层设置于所述上电极和所述下电极之间，所述上电极和所述下电极均包括一层金属层，且所述上电极的金属层与所述下电极的金属层的材质相同。To solve the above technical problems, the present invention provides a capacitor including an upper electrode, a lower electrode, and a dielectric layer, the dielectric layer being disposed between the upper electrode and the lower electrode, the upper electrode and the lower electrode Each includes a metal layer, and the metal layer of the upper electrode is the same material as the metal layer of the lower electrode.
优选地，所述金属层的材质包括Al、Au、Ti或者Cu。Preferably, the material of the metal layer comprises Al, Au, Ti or Cu.
优选地，所述上电极和所述下电极均采用物理气相沉积工艺制备。Preferably, the upper electrode and the lower electrode are both prepared by a physical vapor deposition process.
优选地，所述上电极和所述下电极的厚度的取值范围均为50-500nm。Preferably, the thickness of the upper electrode and the lower electrode ranges from 50 to 500 nm.
优选地，所述上电极和所述下电极的厚度的取值范围均为100-300nm。Preferably, the thickness of the upper electrode and the lower electrode ranges from 100 to 300 nm.
优选地，所述电介质层包括Al2O3层、TiO2层或者HfO4层。Preferably, the dielectric layer comprises an Al 2 O 3 layer, a TiO 2 layer or an Hf O 4 layer.
优选地，所述电介质层的厚度的取值范围为5-15nm。Preferably, the thickness of the dielectric layer ranges from 5 to 15 nm.
其中，所述电容为高密电容。Wherein, the capacitor is a high-density capacitor.
作为另一个技术方案，本发明还提供一种半导体设备，用于制备本发明提供的上述电容，所述半导体设备包括：物理气相沉积腔室、原子层沉积腔室和传输平台；As another technical solution, the present invention further provides a semiconductor device for preparing the above capacitor provided by the present invention, the semiconductor device comprising: a physical vapor deposition chamber, an atomic layer deposition chamber, and a transmission platform;
所述物理气相沉积腔室用于制备电容的上电极和下电极；The physical vapor deposition chamber is used to prepare an upper electrode and a lower electrode of the capacitor;
所述原子层沉积腔室用于制备所述电容的电介质层；The atomic layer deposition chamber is used to prepare a dielectric layer of the capacitor;
所述传输平台分别与所述物理气相沉积腔室和所述原子层沉积腔室连接，用于传输基片。The transport platform is coupled to the physical vapor deposition chamber and the atomic layer deposition chamber, respectively, for transporting a substrate.
其中，还包括去气腔室，所述去气腔室用于对基片进行除气和退火；所述去气腔室与所述传输平台连接。There is further included a degassing chamber for degassing and annealing the substrate; the degassing chamber being coupled to the transport platform.
其中，还包括预清洗腔室，所述预清洗腔室用于去除基片表面上的杂质；所述预清洗腔室与所述传输平台连接。There is further included a pre-cleaning chamber for removing impurities on the surface of the substrate; the pre-cleaning chamber being connected to the transport platform.
优选地，所述物理气相沉积腔室的数量为多个，多个所述物理气相沉积腔室分别用于沉积多种材料的薄膜。Preferably, the number of the physical vapor deposition chambers is plural, and the plurality of physical vapor deposition chambers are respectively used for depositing thin films of a plurality of materials.
优选地，在所述物理气相沉积腔室中，靶基距大于90mm。Preferably, in the physical vapor deposition chamber, the target base distance is greater than 90 mm.
优选地，所述靶基距的取值范围为200-410mm。Preferably, the target base distance ranges from 200 to 410 mm.
作为另一个技术方案，本发明还提供一种电容制作方法，包括以下步骤：As another technical solution, the present invention also provides a capacitor manufacturing method, including the following steps:
通过物理气相沉积工艺在基底的待沉积表面形成下电极；Forming a lower electrode on a surface to be deposited of the substrate by a physical vapor deposition process;
通过原子层沉积工艺在所述下电极的背离所述基底的表面形成电介质层；Forming a dielectric layer on a surface of the lower electrode facing away from the substrate by an atomic layer deposition process;
通过物理气相沉积工艺在所述电介质层的背离所述下电极的表面形成上电极；Forming an upper electrode on a surface of the dielectric layer facing away from the lower electrode by a physical vapor deposition process;
其中，所述上电极和所述下电极均包括一层金属层，且所述上电极的金属层与所述下电极的金属层的材质相同。The upper electrode and the lower electrode each comprise a metal layer, and the metal layer of the upper electrode and the metal layer of the lower electrode are made of the same material.
优选地，所述金属层包括Al、Au、Ti或者Cu。Preferably, the metal layer comprises Al, Au, Ti or Cu.
优选地，在所述通过物理气相沉积工艺在所述电介质层的背离所述下电极的表面形成上电极的步骤中，工艺压力的取值范围为0-2mTorr，溅射功率的取值范围为30-38kW，偏压功率的取值范围为400-1000W。Preferably, in the step of forming an upper electrode on a surface of the dielectric layer facing away from the lower electrode by a physical vapor deposition process, the process pressure ranges from 0 to 2 mTorr, and the sputtering power ranges from 30-38kW, the bias power range is 400-1000W.
优选地，所述电介质层包括Al2O3层、TiO2层或者HfO4层。Preferably, the dielectric layer comprises an Al 2 O 3 layer, a TiO 2 layer or an Hf O 4 layer.
优选地，在所述通过原子层沉积工艺在所述下电极的背离所述基底的表面形成电介质层的步骤中，工艺温度的取值范围为300-400℃。Preferably, in the step of forming a dielectric layer on the surface of the lower electrode facing away from the substrate by an atomic layer deposition process, the process temperature ranges from 300 to 400 °C.
优选地，在所述通过物理气相沉积工艺在基底的待沉积表面形成下电极的步骤之前，还包括，去气工艺，用于对所述基底的待沉积表面进行去气处理。Preferably, before the step of forming a lower electrode on the surface to be deposited of the substrate by the physical vapor deposition process, a degassing process for degassing the surface to be deposited of the substrate is further included.
优选地，在所述通过物理气相沉积工艺在所述电介质层的背离所述下电 极的表面形成上电极的步骤之后，还包括退火工艺。Preferably, after the step of forming an upper electrode on a surface of the dielectric layer facing away from the lower electrode by a physical vapor deposition process, an annealing process is further included.
本发明具有以下有益效果：The invention has the following beneficial effects:
本发明提供的电容、电容制作方法及半导体设备的技术方案中，电容包括上电极、下电极以及设置于二者之间的电介质层，其中，上电极和下电极均包括一层金属层，且上电极的金属层与下电极的金属层的材质相同。该电容的结构简单，从而可以简化制作工艺流程，而且可以减少基片在传输过程中暴露在空气中的次数，从而可以在一定程度上减少薄膜表面的污染。In the capacitor, the capacitor manufacturing method and the semiconductor device, the capacitor includes an upper electrode, a lower electrode, and a dielectric layer disposed therebetween, wherein the upper electrode and the lower electrode each comprise a metal layer, and The metal layer of the upper electrode is the same material as the metal layer of the lower electrode. The capacitor has a simple structure, which simplifies the manufacturing process and reduces the number of times the substrate is exposed to the air during transport, thereby reducing the contamination of the film surface to some extent.
附图说明DRAWINGS
图1为本发明第一实施例提供的电容的结构示意图；1 is a schematic structural diagram of a capacitor according to a first embodiment of the present invention;
图2a为本发明第二实施例提供的半导体设备的结构示意图；2a is a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention;
图2b为本发明第二实施例的变型实施例提供的半导体设备的结构示意图；2b is a schematic structural diagram of a semiconductor device according to a modified embodiment of the second embodiment of the present invention;
图3为本发明第二实施例中第一腔室的结构示意图；3 is a schematic structural view of a first chamber in a second embodiment of the present invention;
图4为本发明第三实施例提供的电容制作方法的流程图。FIG. 4 is a flowchart of a method for fabricating a capacitor according to a third embodiment of the present invention.
附图编号：Drawing number:
20-基底，201-沟槽，21-上电极，22-下电极，23-电介质层，31、32-PVD腔室，33-ALD腔室，34-传输腔室，41-溅射靶，42-基座。20-substrate, 201-trench, 21-upper electrode, 22-lower electrode, 23-dielectric layer, 31, 32-PVD chamber, 33-ALD chamber, 34-transfer chamber, 41-sputter target, 42-base.
具体实施方式Detailed ways
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的电容、电容制作方法及半导体设备进行详细描述。In order to enable those skilled in the art to better understand the technical solutions of the present invention, the capacitor, the capacitor manufacturing method and the semiconductor device provided by the present invention are described in detail below with reference to the accompanying drawings.
请参阅图1，本发明第一实施例提供一种电容，其包括基底20、上电极21、下电极22和电介质层23，该电介质层23设置于上电极21和下电极22之间，而且上电极21和下电极22均包括一层金属层，且上电极21的金属层 和下电极22的金属层的材质相同。Referring to FIG. 1 , a first embodiment of the present invention provides a capacitor including a substrate 20 , an upper electrode 21 , a lower electrode 22 , and a dielectric layer 23 disposed between the upper electrode 21 and the lower electrode 22 , and The upper electrode 21 and the lower electrode 22 each include a metal layer, and the metal layer of the upper electrode 21 and the metal layer of the lower electrode 22 are made of the same material.
上述电容是由金属层/电介质层/金属层组成的三层结构，类似于“三明治”结构，该结构简单，从而可以简化制作工艺流程，而且可以减少基片在传输过程中暴露在空气中的次数，从而可以在一定程度上减少薄膜表面的污染。The above capacitor is a three-layer structure composed of a metal layer/dielectric layer/metal layer, which is similar to a “sandwich” structure, which is simple in structure, thereby simplifying the manufacturing process and reducing the exposure of the substrate to the air during transmission. The number of times can reduce the contamination of the film surface to some extent.
在本实施例中，上述电容为沟槽电容，该电容还包括基底20，其可以采用SiO2或其它材质制作。并且，该基底20具有沟槽201。上电极21、下电极22和电介质层23形成于基底20的上述沟槽201所在的表面，且覆盖该表面。这里所指的表面既包括基底20的上述沟槽201所在的表面，又包括可暴露于空气的槽201的内表面。并且，在上电极21、下电极22和电介质层23形成之后，沟槽201被完全填充。In this embodiment, the capacitor is a trench capacitor, and the capacitor further includes a substrate 20, which may be made of SiO2 or other materials. Also, the substrate 20 has a trench 201. The upper electrode 21, the lower electrode 22, and the dielectric layer 23 are formed on the surface of the substrate 20 on which the above-described trench 201 is located, and cover the surface. The surface referred to herein includes both the surface on which the above-described groove 201 of the substrate 20 is located and the inner surface of the groove 201 which is exposed to the air. Also, after the upper electrode 21, the lower electrode 22, and the dielectric layer 23 are formed, the trench 201 is completely filled.
可选的，上述电容为高密电容。所谓高密电容，是指在高密度的沟槽中沉积金属层及电介质层形成的电容。Optionally, the capacitor is a high-density capacitor. The so-called high-density capacitor refers to a capacitor formed by depositing a metal layer and a dielectric layer in a high-density trench.
可选的，上述金属层的材质包括Al、Au、Ti或者Cu等等。Optionally, the material of the metal layer includes Al, Au, Ti, Cu, or the like.
在本实施例中，上电极21和下电极22均采用物理气相沉积(Physical Vapor Deposition，以下简称PVD)工艺制备。在现有技术中，通常采用化学气相沉积(Chemical Vapor Deposition，以下简称CVD)工艺制备金属层，而本申请通过采用PVD工艺制备金属层，可以大大降低金属层的电阻率，提高金属层的致密性和表面平整度，例如，采用PVD工艺制备的Al层的电阻率比采用CVD工艺制备的W层的电阻率低近百倍，而且Al层在上述沟槽201的内侧壁的厚度相比于W层减薄很多，当电介质层23的厚度恒定时，金属层的厚度越薄，则金属层的面积越大，从而使电容的电容值更大，进而提高了电容的电极特性。In the present embodiment, both the upper electrode 21 and the lower electrode 22 are prepared by a physical vapor deposition (PVD) process. In the prior art, a metal layer is usually prepared by a chemical vapor deposition (CVD) process, and the present invention can greatly reduce the resistivity of the metal layer and increase the density of the metal layer by preparing a metal layer by using a PVD process. And surface flatness, for example, the resistivity of the Al layer prepared by the PVD process is nearly 100 times lower than that of the W layer prepared by the CVD process, and the thickness of the Al layer on the inner sidewall of the trench 201 is compared to W The layer is much thinned. When the thickness of the dielectric layer 23 is constant, the thinner the thickness of the metal layer is, the larger the area of the metal layer is, so that the capacitance value of the capacitor is larger, thereby improving the electrode characteristics of the capacitor.
可选的，上电极21和下电极22的厚度的取值范围均为50-500nm，优选为100-300nm。在该厚度范围内，既可保证电容的质量，又可增加电容的电 容值。Optionally, the thickness of the upper electrode 21 and the lower electrode 22 ranges from 50 to 500 nm, preferably from 100 to 300 nm. Within this thickness range, both the quality of the capacitor and the capacitance of the capacitor can be increased.
可选的，电介质层23包括Al2O3层、TiO2层或者HfO4层等的介电常数较大的膜层。Optionally, the dielectric layer 23 includes a film layer having a large dielectric constant such as an Al 2 O 3 layer, a TiO 2 layer, or an HfO 4 layer.
可选的，电介质层23的厚度的取值范围为5-15nm。在实际应用中，电介质层23的厚度可以参考其击穿电压进行调整。例如：若电容的击穿电压为2.5V，则可以将电介质层23的厚度控制在9-10nm之间。Optionally, the thickness of the dielectric layer 23 ranges from 5 to 15 nm. In practical applications, the thickness of the dielectric layer 23 can be adjusted with reference to its breakdown voltage. For example, if the breakdown voltage of the capacitor is 2.5V, the thickness of the dielectric layer 23 can be controlled to be between 9-10 nm.
本发明第二实施例提供一种半导体设备，其可以用于制备电容。该半导体设备包括：物理气相沉积(Physical Vapor Deposition，以下简称PVD)腔室、原子层沉积(Atomic Layer Deposition，以下简称ALD)腔室和传输平台。其中，PVD腔室用于制备电容的上电极和下电极；ALD腔室用于制备电容的电介质层；传输平台分别与PVD腔室和ALD腔室连接，用于传输基片。具体地，传输平台主要包括传输腔室和装/卸载台，其中，传输腔室为真空腔室，且在该传输腔室中设置有机械手。PVD腔室和ALD腔室围绕在传输腔室的周围，且与该传输腔室连通，从而构成一集簇设备系统。A second embodiment of the present invention provides a semiconductor device that can be used to prepare a capacitor. The semiconductor device includes: a physical vapor deposition (PVD) chamber, an atomic layer deposition (Atomic Layer Deposition, hereinafter referred to as ALD) chamber, and a transmission platform. Wherein, the PVD chamber is used to prepare the upper and lower electrodes of the capacitor; the ALD chamber is used to prepare a dielectric layer of the capacitor; and the transfer platform is respectively connected to the PVD chamber and the ALD chamber for transporting the substrate. Specifically, the transport platform mainly includes a transfer chamber and a loading/unloading station, wherein the transfer chamber is a vacuum chamber, and a robot is disposed in the transfer chamber. A PVD chamber and an ALD chamber surround and are in communication with the transfer chamber to form a cluster device system.
在将基片装载至传输平台的装载台之后，由机械手自装载台取出基片，并将基片按工艺顺序传输至PVD腔室和ALD腔室，在完成电容的制备之后，再将加工完成的基片传出至卸载台。After the substrate is loaded onto the loading platform of the transfer platform, the substrate is taken out from the loading table by the robot, and the substrate is transferred to the PVD chamber and the ALD chamber in a process sequence, and after the completion of the preparation of the capacitor, the processing is completed. The substrate is transmitted to the unloading station.
本发明实施例提供的半导体设备，其采用PVD腔室制备电容的上电极和下电极，这与采用化学气相沉积工艺相比，大大降低上电极和下电极的电阻率，提高上电极和下电极的致密性和表面平整度，从而可以提高上电板和下电极的金属电极性能，进而提高电容的性能；同时，本发明实施例提供的半导体设备将PVD腔室和ALD腔室与同一传输平台集成在一起，构成单一集簇设备系统，这不仅降低了设备成本，而且可以避免基片在传输过程中暴露在空气中，从而可以避免薄膜表面被污染。另外，PVD腔室和ALD腔室的工艺成本较低，有利于工业化成本的控制。The semiconductor device provided by the embodiment of the invention uses the PVD chamber to prepare the upper electrode and the lower electrode of the capacitor, which greatly reduces the resistivity of the upper electrode and the lower electrode and improves the upper electrode and the lower electrode compared with the chemical vapor deposition process. Densification and surface flatness, so that the metal electrode performance of the upper and lower electrodes can be improved, thereby improving the performance of the capacitor; meanwhile, the semiconductor device provided by the embodiment of the invention has the PVD chamber and the ALD chamber and the same transmission platform. Integrated to form a single cluster device system, which not only reduces equipment costs, but also avoids exposure of the substrate to air during transport, thereby avoiding contamination of the film surface. In addition, the process cost of the PVD chamber and the ALD chamber is low, which is advantageous for the control of industrialization costs.
下面对本发明实施例提供的半导体设备的具体实施方式进行详细描述。具体地，请参阅图2a，半导体设备包括PVD腔室31、ALD腔室33、去气腔室35、预清洗腔室36和传输平台，其中，传输平台包括传输腔室34，其为真空腔室，且在该传输腔室34中设置有机械手。PVD腔室31、ALD腔室33、去气腔室35和预清洗腔室36围绕在传输腔室34的周围，且与该传输腔室34连通，从而构成一集簇设备系统。The specific embodiments of the semiconductor device provided by the embodiments of the present invention are described in detail below. Specifically, referring to FIG. 2a, the semiconductor device includes a PVD chamber 31, an ALD chamber 33, a degassing chamber 35, a pre-cleaning chamber 36, and a transport platform, wherein the transport platform includes a transfer chamber 34, which is a vacuum chamber A chamber is provided and a robot is disposed in the transfer chamber 34. The PVD chamber 31, the ALD chamber 33, the degassing chamber 35, and the pre-cleaning chamber 36 surround the transfer chamber 34 and communicate with the transfer chamber 34 to form a cluster device system.
其中，PVD腔室31用于实施PVD工艺，以制备电容的上电极和下电极。可选的，上电极和下电极分别包括一层金属层，且上电极的金属层和下电极的金属层的材质相同。可选的，上述金属层的材质包括Al、Au、Ti或者Cu等等。Wherein, the PVD chamber 31 is used to implement a PVD process to prepare the upper and lower electrodes of the capacitor. Optionally, the upper electrode and the lower electrode respectively comprise a metal layer, and the metal layer of the upper electrode and the metal layer of the lower electrode are the same material. Optionally, the material of the metal layer includes Al, Au, Ti, Cu, or the like.
请参阅图3，在PVD腔室31内的顶部设置有靶材41，且在该靶材41的下方设置有用于承载被加工工件的基座42。并且，溅射靶41的溅射面与基座42的承载面相对设置，且溅射靶41的溅射面与基座42的承载面之间的距离H称为靶基距。可选的，靶基距大于90mm，以使腔室能够满足实施长程溅射工艺的要求，从而有利于提高薄膜均匀性。优选地，靶基距的取值范围为200-410mm，在该范围内，可以在使腔室满足实施长程溅射工艺的要求的同时，保证生产效率。Referring to FIG. 3, a target 41 is disposed at the top of the PVD chamber 31, and a susceptor 42 for carrying the workpiece to be processed is disposed under the target 41. Further, the sputtering surface of the sputtering target 41 is disposed opposite to the bearing surface of the susceptor 42, and the distance H between the sputtering surface of the sputtering target 41 and the bearing surface of the susceptor 42 is referred to as a target base distance. Optionally, the target base distance is greater than 90 mm, so that the chamber can meet the requirements of implementing a long-range sputtering process, thereby facilitating the improvement of film uniformity. Preferably, the target base distance ranges from 200 to 410 mm, and within this range, the production efficiency can be ensured while satisfying the requirements of the long-range sputtering process.
ALD腔室33用于实施原子层沉积工艺，以制备电容的电介质层。可选的，电介质层包括Al2O3层、TiO2层或者HfO4层等的介电常数较大的膜层。The ALD chamber 33 is used to perform an atomic layer deposition process to prepare a capacitive dielectric layer. Optionally, the dielectric layer comprises a film layer having a large dielectric constant such as an Al 2 O 3 layer, a TiO 2 layer or an Hf O 4 layer.
去气腔室35用于对被加工件进行除气和退火。The degassing chamber 35 is used to degas and anneal the workpiece.
预清洗腔室36用于清洗被加工件的表面，以去除被加工件表面上的杂质。The pre-cleaning chamber 36 is for cleaning the surface of the workpiece to remove impurities on the surface of the workpiece.
需要说明的是，在本实施例中，PVD腔室31为一个，但本发明并不局限于此。在实际应用中，PVD腔室31的数量还可以为多个，多个PVD腔室31设置在传输腔室34的周围，与其他腔室构成构成一集簇设备系统。It should be noted that in the present embodiment, the PVD chamber 31 is one, but the present invention is not limited thereto. In practical applications, the number of PVD chambers 31 may also be plural, and a plurality of PVD chambers 31 are disposed around the transfer chamber 34 to form a cluster device system with the other chambers.
如图2a所示，当半导体设备设置一个PVD腔室31时，在将基底传输至PVD腔室31内制备下电极之后，再将基底传输至ALD腔室33内制备电介质层，最后再次将基底传输至PVD腔室31内制备上电极。As shown in FIG. 2a, when the semiconductor device is provided with one PVD chamber 31, after the substrate is transferred into the PVD chamber 31 to prepare the lower electrode, the substrate is transferred into the ALD chamber 33 to prepare a dielectric layer, and finally the substrate is again The upper electrode is prepared by being transferred into the PVD chamber 31.
如图2b所示，当半导体设备设置两个PVD腔室(31，32)时，在将基底传输至第一个PVD腔室31内制备下电极之后，再将基底传输至ALD腔室33内制备电介质层，最后将基底传输至第二个PVD腔室32制备上电极。这与上述半导体设备设置一个PVD腔室31相比，无需使基底返回PVD腔室，更有利于流水作业，从而提高半导体设备的加工效率。As shown in FIG. 2b, when the semiconductor device is provided with two PVD chambers (31, 32), after the substrate is transferred into the first PVD chamber 31 to prepare the lower electrode, the substrate is transferred into the ALD chamber 33. A dielectric layer is prepared and finally transferred to a second PVD chamber 32 to prepare an upper electrode. Compared with the above-mentioned semiconductor device in which one PVD chamber 31 is provided, it is not necessary to return the substrate to the PVD chamber, which is more advantageous for the flow operation, thereby improving the processing efficiency of the semiconductor device.
本发明第三实施例提供一种电容制作方法，其包括以下步骤：A third embodiment of the present invention provides a capacitor manufacturing method, including the following steps:
通过物理气相沉积工艺在基底的待沉积表面形成下电极；Forming a lower electrode on a surface to be deposited of the substrate by a physical vapor deposition process;
通过原子层沉积工艺在下电极的背离基底的表面形成电介质层；Forming a dielectric layer on the surface of the lower electrode facing away from the substrate by an atomic layer deposition process;
通过物理气相沉积工艺在电介质层的背离下电极的表面形成上电极。An upper electrode is formed on the surface of the dielectric layer facing away from the lower electrode by a physical vapor deposition process.
通过采用PVD工艺制备上电极和下电极，可以大大降低上电极和下电极的电阻率，提高上电极和下电极的致密性和表面平整度，从而可以提高上电板和下电极的金属电极性能，进而提高电容的性能。By using the PVD process to prepare the upper and lower electrodes, the resistivity of the upper and lower electrodes can be greatly reduced, and the compactness and surface flatness of the upper and lower electrodes can be improved, thereby improving the performance of the metal electrodes of the upper and lower electrodes. To improve the performance of the capacitor.
请一并参阅图1至图4，本发明第三实施例提供的电容制作方法，其采用本发明第二实施例提供的半导体设备制作图1示出的电容。具体地，电容制作方法包括：Referring to FIG. 1 to FIG. 4, a capacitor manufacturing method according to a third embodiment of the present invention is used to fabricate the capacitor shown in FIG. 1 by using the semiconductor device provided by the second embodiment of the present invention. Specifically, the capacitor manufacturing method includes:
步骤S1，进行去气工艺，即，对基底20的待沉积表面进行去气处理。In step S1, a degassing process is performed, that is, the surface to be deposited of the substrate 20 is subjected to a degassing treatment.
在步骤S1中，首先将基底20传输至去气腔室35内进行去气处理，以去除基底20表面上的杂质。在进行去气工艺的过程中，将去气腔室35的压力控制在0-10Torr，温度控制在0-400℃。优选的，去气腔室35的压力控制在1-7Torr，温度控制在300-400℃。In step S1, the substrate 20 is first transferred to the degassing chamber 35 for degassing treatment to remove impurities on the surface of the substrate 20. During the degassing process, the pressure of the degassing chamber 35 is controlled to be 0-10 Torr, and the temperature is controlled at 0 to 400 °C. Preferably, the pressure of the degassing chamber 35 is controlled at 1-7 Torr and the temperature is controlled at 300-400 °C.
基底20可以采用SiO2或其它材质制作。并且，该基底20具有沟槽201。上述基底20的待沉积表面既包括基底20的上述沟槽201所在的表面，又包 括可暴露于空气的槽201的内表面。The substrate 20 can be made of SiO2 or other materials. Also, the substrate 20 has a trench 201. The surface to be deposited of the substrate 20 described above includes both the surface of the substrate 20 on which the trench 201 is located, and the inner surface of the trench 201 which is exposed to air.
步骤S2，通过物理气相沉积工艺在基底20的待沉积表面形成下电极22。In step S2, the lower electrode 22 is formed on the surface to be deposited of the substrate 20 by a physical vapor deposition process.
步骤S3，通过原子层沉积工艺在下电极22的背离基底20的表面形成电介质层23。In step S3, a dielectric layer 23 is formed on the surface of the lower electrode 22 facing away from the substrate 20 by an atomic layer deposition process.
步骤S4，通过物理气相沉积工艺在电介质层23的背离下电极22的表面形成上电极21。In step S4, the upper electrode 21 is formed on the surface of the dielectric layer 23 facing away from the lower electrode 22 by a physical vapor deposition process.
在上述步骤S2至步骤S4中，上电极21、下电极22和电介质层23覆盖基底20的待沉积表面，且使沟槽201被完全填充。In the above steps S2 to S4, the upper electrode 21, the lower electrode 22, and the dielectric layer 23 cover the surface to be deposited of the substrate 20, and the trench 201 is completely filled.
在上述步骤S2和步骤S4中，上电极21和下电极22均包括一层金属层，且上电极21的金属层和下电极22的金属层的材质相同。这样，电容是由金属层/电介质层/金属层组成的三层结构，类似于“三明治”结构，该结构简单，从而可以简化制作工艺流程，而且可以减少基片在传输过程中暴露在空气中的次数，从而可以在一定程度上减少薄膜表面的污染。In the above steps S2 and S4, the upper electrode 21 and the lower electrode 22 each include a metal layer, and the metal layers of the upper electrode 21 and the metal layer of the lower electrode 22 are made of the same material. Thus, the capacitor is a three-layer structure composed of a metal layer/dielectric layer/metal layer, similar to a “sandwich” structure, which is simple in structure, thereby simplifying the manufacturing process and reducing the exposure of the substrate to the air during transport. The number of times can thus reduce the contamination of the film surface to some extent.
可选的，上述金属层的材质包括Al、Au、Ti或者Cu等等。Optionally, the material of the metal layer includes Al, Au, Ti, Cu, or the like.
可选的，电介质层23包括Al2O3层、TiO2层或者HfO4层等的介电常数较大的膜层。Optionally, the dielectric layer 23 includes a film layer having a large dielectric constant such as an Al 2 O 3 layer, a TiO 2 layer, or an HfO 4 layer.
在本实施例中，用于制备上电极21和下电极22的PVD腔室31内的顶部设置有靶材41，且在该靶材41的下方设置有用于承载被加工工件的基座42。并且，靶基距大于90mm，优选为200-410mm。在进行PVD工艺的过程中，向PVD腔室31内通入工艺气体，且腔室压力为0-5mTorr，优选为0-2mTorr。施加在靶材41上的溅射功率为0-40kW，优选为30-38kW。施加在基座上的偏压功率为0-2000W，优选为400-1000W。In the present embodiment, the top portion in the PVD chamber 31 for preparing the upper electrode 21 and the lower electrode 22 is provided with a target 41, and a susceptor 42 for carrying a workpiece to be processed is disposed below the target 41. Also, the target base distance is greater than 90 mm, preferably 200-410 mm. During the PVD process, a process gas is introduced into the PVD chamber 31, and the chamber pressure is 0-5 mTorr, preferably 0-2 mTorr. The sputtering power applied to the target 41 is 0-40 kW, preferably 30-38 kW. The bias power applied to the susceptor is 0-2000 W, preferably 400-1000 W.
可选的，上电极21和下电极22的厚度的取值范围均为50-500nm，优选为100-300nm。在该厚度范围内，既可保证电容的质量，又可增加电容的电容值。Optionally, the thickness of the upper electrode 21 and the lower electrode 22 ranges from 50 to 500 nm, preferably from 100 to 300 nm. Within this thickness range, both the quality of the capacitor and the capacitance of the capacitor can be increased.
可选的，电介质层23的厚度的取值范围为5-15nm。在实际应用中，电介质层23的厚度可以参考其击穿电压进行调整。例如：若电容的击穿电压为2.5V，则可以将电介质层23的厚度控制在9-10nm之间。Optionally, the thickness of the dielectric layer 23 ranges from 5 to 15 nm. In practical applications, the thickness of the dielectric layer 23 can be adjusted with reference to its breakdown voltage. For example, if the breakdown voltage of the capacitor is 2.5V, the thickness of the dielectric layer 23 can be controlled to be between 9-10 nm.
在步骤S3中，在实施原子层沉积工艺时，将温度控制在150-400℃，优为300-400℃，以能够在制备电介质层23的同时对下电极22进行退火处理，从而优化下电极22的结晶，提高下电极22的性能。In step S3, when the atomic layer deposition process is performed, the temperature is controlled at 150-400 ° C, preferably 300-400 ° C, to be able to anneal the lower electrode 22 while preparing the dielectric layer 23, thereby optimizing the lower electrode. The crystallization of 22 improves the performance of the lower electrode 22.
步骤S5，对上电极21、下电极22和电介质层23进行退火处理。In step S5, the upper electrode 21, the lower electrode 22, and the dielectric layer 23 are annealed.
由于在制备上电极21、下电极22和电介质层23的过程中容易产生应力，因此，制备完成之后，需要对上电极21、下电极22和电介质层23进行退火处理。退火处理可以在去气腔室35内进行，或者也可以在其他具有退火功能的腔室内进行。在进行退火处理时，将腔室压力控制在0-10Torr，优选为1-7Torr。温度控制在0-400℃，优选为300-400℃。Since stress is easily generated in the process of preparing the upper electrode 21, the lower electrode 22, and the dielectric layer 23, after the preparation is completed, the upper electrode 21, the lower electrode 22, and the dielectric layer 23 need to be annealed. The annealing treatment may be performed in the degassing chamber 35, or may be performed in other chambers having an annealing function. When the annealing treatment is performed, the chamber pressure is controlled to be 0 to 10 Torr, preferably 1 to 7 Torr. The temperature is controlled at 0 to 400 ° C, preferably 300 to 400 ° C.
在本实施例中，若沟槽201的深宽比为4∶1，在制作上电极21和下电极22时，优选靶基距为290mm，腔室压力为0.1-1mTorr，施加在靶材41上的溅射功率为30-35kW，施加在基座42上的偏压功率为500-800W，制备的上电极21和下电极22的厚度均为100-200nm。In the present embodiment, if the aspect ratio of the trench 201 is 4:1, when the upper electrode 21 and the lower electrode 22 are formed, the target base distance is preferably 290 mm, and the chamber pressure is 0.1-1 mTorr, which is applied to the target 41. The sputtering power was 30-35 kW, the bias power applied to the susceptor 42 was 500-800 W, and the thicknesses of the prepared upper electrode 21 and lower electrode 22 were both 100-200 nm.
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。It is to be understood that the above embodiments are merely exemplary embodiments employed to explain the principles of the invention, but the invention is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the invention. These modifications and improvements are also considered to be within the scope of the invention.

Claims (21)

  1. 一种电容，包括上电极、下电极和电介质层，所述电介质层设置于所述上电极和所述下电极之间，其特征在于，所述上电极和所述下电极均包括一层金属层，且所述上电极的金属层与所述下电极的金属层的材质相同。A capacitor comprising an upper electrode, a lower electrode and a dielectric layer, the dielectric layer being disposed between the upper electrode and the lower electrode, wherein the upper electrode and the lower electrode each comprise a layer of metal a layer, and the metal layer of the upper electrode is the same material as the metal layer of the lower electrode.
  2. 根据权利要求1所述的电容，其特征在于，所述金属层的材质包括Al、Au、Ti或者Cu。The capacitor according to claim 1, wherein the material of the metal layer comprises Al, Au, Ti or Cu.
  3. 根据权利要求1或2所述的电容，其特征在于，所述上电极和所述下电极均采用物理气相沉积工艺制备。The capacitor according to claim 1 or 2, wherein the upper electrode and the lower electrode are both prepared by a physical vapor deposition process.
  4. 根据权利要求2所述的电容，其特征在于，所述上电极和所述下电极的厚度的取值范围均为50-500nm。The capacitor according to claim 2, wherein the thickness of the upper electrode and the lower electrode ranges from 50 to 500 nm.
  5. 根据权利要求4所述的电容，其特征在于，所述上电极和所述下电极的厚度的取值范围均为100-300nm。The capacitor according to claim 4, wherein the thickness of the upper electrode and the lower electrode ranges from 100 to 300 nm.
  6. 根据权利要求1所述的电容，其特征在于，所述电介质层包括Al2O3层、TiO2层或者HfO4层。The capacitor of claim 1 wherein said dielectric layer comprises an Al2O3 layer, a TiO2 layer or an HfO4 layer.
  7. 根据权利要求6所述的电容，其特征在于，所述电介质层的厚度的取值范围为5-15nm。The capacitor according to claim 6, wherein the thickness of the dielectric layer ranges from 5 to 15 nm.
  8. 根据权利要求1所述的电容，其特征在于，所述电容为高密电容。The capacitor of claim 1 wherein said capacitor is a high density capacitor.
  9. 一种半导体设备，其特征在于，用于制备如权利要求1-8任意所述的 电容，所述半导体设备包括：物理气相沉积腔室、原子层沉积腔室和传输平台；A semiconductor device, characterized by comprising the capacitor of any of claims 1-8, the semiconductor device comprising: a physical vapor deposition chamber, an atomic layer deposition chamber, and a transport platform;
    所述物理气相沉积腔室用于制备电容的上电极和下电极；The physical vapor deposition chamber is used to prepare an upper electrode and a lower electrode of the capacitor;
    所述原子层沉积腔室用于制备所述电容的电介质层；The atomic layer deposition chamber is used to prepare a dielectric layer of the capacitor;
    所述传输平台分别与所述物理气相沉积腔室和所述原子层沉积腔室连接，用于传输基片。The transport platform is coupled to the physical vapor deposition chamber and the atomic layer deposition chamber, respectively, for transporting a substrate.
  10. 根据权利要求9所述的半导体设备，其特征在于，还包括去气腔室，所述去气腔室用于对基片进行除气和退火；所述去气腔室与所述传输平台连接。The semiconductor device according to claim 9, further comprising a degassing chamber for degassing and annealing the substrate; said degassing chamber being coupled to said transfer platform .
  11. 根据权利要求9所述的半导体设备，其特征在于，还包括预清洗腔室，所述预清洗腔室用于去除基片表面上的杂质；所述预清洗腔室与所述传输平台连接。The semiconductor device of claim 9 further comprising a pre-cleaning chamber for removing impurities on the surface of the substrate; said pre-cleaning chamber being coupled to said transport platform.
  12. 根据权利要求9所述的半导体设备，其特征在于，所述物理气相沉积腔室的数量为多个，多个所述物理气相沉积腔室分别用于沉积多种材料的薄膜。The semiconductor device according to claim 9, wherein the number of the physical vapor deposition chambers is plural, and the plurality of physical vapor deposition chambers are respectively used to deposit thin films of a plurality of materials.
  13. 根据权利要求9所述的半导体设备，其特征在于，在所述物理气相沉积腔室中，靶基距大于90mm。The semiconductor device according to claim 9, wherein in the physical vapor deposition chamber, the target base distance is greater than 90 mm.
  14. 根据权利要求13所述的半导体设备，其特征在于，所述靶基距的取值范围为200-410mm。The semiconductor device according to claim 13, wherein said target base distance ranges from 200 to 410 mm.
  15. 一种电容制作方法，其特征在于，包括以下步骤：A capacitor manufacturing method, comprising the steps of:
    通过物理气相沉积工艺在基底的待沉积表面形成下电极；Forming a lower electrode on a surface to be deposited of the substrate by a physical vapor deposition process;
    通过原子层沉积工艺在所述下电极的背离所述基底的表面形成电介质层；Forming a dielectric layer on a surface of the lower electrode facing away from the substrate by an atomic layer deposition process;
    通过物理气相沉积工艺在所述电介质层的背离所述下电极的表面形成上电极；Forming an upper electrode on a surface of the dielectric layer facing away from the lower electrode by a physical vapor deposition process;
    其中，所述上电极和所述下电极均包括一层金属层，且所述上电极的金属层与所述下电极的金属层的材质相同。The upper electrode and the lower electrode each comprise a metal layer, and the metal layer of the upper electrode and the metal layer of the lower electrode are made of the same material.
  16. 根据权利要求15所述电容制作方法，其特征在于，所述金属层包括Al、Au、Ti或者Cu。The method of fabricating a capacitor according to claim 15, wherein the metal layer comprises Al, Au, Ti or Cu.
  17. 根据权利要求15所述电容制作方法，其特征在于，在所述通过物理气相沉积工艺在所述电介质层的背离所述下电极的表面形成上电极的步骤中，工艺压力的取值范围为0-2mTorr，溅射功率的取值范围为30-38kW，偏压功率的取值范围为400-1000W。The capacitor manufacturing method according to claim 15, wherein in the step of forming an upper electrode on a surface of the dielectric layer facing away from the lower electrode by a physical vapor deposition process, the process pressure has a value range of 0 -2mTorr, the sputtering power ranges from 30 to 38 kW, and the bias power ranges from 400 to 1000 W.
  18. 根据权利要求15所述电容制作方法，其特征在于，所述电介质层包括Al2O3层、TiO2层或者HfO4层。The capacitor manufacturing method according to claim 15, wherein the dielectric layer comprises an Al2O3 layer, a TiO2 layer or an HfO4 layer.
  19. 根据权利要求15所述电容制作方法，其特征在于，在所述通过原子层沉积工艺在所述下电极的背离所述基底的表面形成电介质层的步骤中，工艺温度的取值范围为300-400℃。The capacitor manufacturing method according to claim 15, wherein in the step of forming a dielectric layer on a surface of the lower electrode facing away from the substrate by an atomic layer deposition process, the process temperature ranges from 300 to - 400 ° C.
  20. 根据权利要求15所述电容制作方法，其特征在于，在所述通过物理气相沉积工艺在基底的待沉积表面形成下电极的步骤之前，还包括，去气工艺，用于对所述基底的待沉积表面进行去气处理。The capacitor manufacturing method according to claim 15, wherein before the step of forming a lower electrode on a surface to be deposited of the substrate by a physical vapor deposition process, a degassing process is further provided for the substrate The deposition surface is degassed.
  21. 根据权利要求15所述电容制作方法，其特征在于，在所述通过物 理气相沉积工艺在所述电介质层的背离所述下电极的表面形成上电极的步骤之后，还包括退火工艺。The method of fabricating a capacitor according to claim 15, wherein after said step of forming an upper electrode on a surface of said dielectric layer facing away from said lower electrode by a physical vapor deposition process, an annealing process is further included.
PCT/CN2018/115359 2018-01-17 2018-11-14 Capacitor, manufacturing method of capacitor, and semiconductor equipment WO2019140994A1 (en)

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