TW201932629A - Semiconductor equipment - Google Patents

Abstract

Semiconductor equipment comprises a physical vapor deposition chamber, an atomic layer deposition chamber and a transport platform. The physical vapor deposition chamber is used to manufacture an upper electrode and a lower electrode of a capacitor. The atomic layer deposition chamber is used to manufacture a dielectric layer of the capacitor. The transport platform is respectively connected to the physical vapor deposition chamber and the atomic layer deposition chamber for transport of a substrate. The semiconductor equipment can protect a substrate from exposure to the air in a transport process, improve performance of a manufactured capacitor, and reduce equipment costs.

Description

Semiconductor equipment

The invention belongs to the technical field of semiconductor processing equipment, and particularly relates to a semiconductor equipment.

As one of the most basic components in a circuit, a capacitor plays a vital role in the entire electronic equipment. With the development of semiconductor technology, thin film deposition technology has made electronic components into nano-scale processes, which has become the main means for capacitors to miniaturize and integrate. Generally, the prepared miniaturized capacitors are called micro capacitors.

Miniature capacitors generally include planar capacitors and trench capacitors. Figure 1a shows a planar capacitor; Figure 1b shows a trench. It can be seen from FIGS. 1a and 1b that the planar capacitor and the trench capacitor are mainly composed of an upper electrode 10, a lower electrode 20, and a dielectric layer 30 located between the upper electrode 10 and the lower electrode 20. FIG. 1c is a specific structural diagram of a trench capacitor. As shown in FIG. 1c, the upper electrode 10 of the trench capacitor includes a W film layer and a TiN film layer which are sequentially stacked in a direction close to the lower electrode 20; 20 includes a TiN film layer, a W film layer, and a TiN film layer sequentially stacked in a direction close to the upper electrode 10; the dielectric layer 30 is an Al ₂ O ₃ film layer.

The method for preparing the trench capacitor shown in FIG. 1c is: CVD TiN → CVD W → CVD TiN → ALD Al ₂ O ₃ → CVD TiN → CVD W, where CVD TiN and CVD W refer to chemical vapor deposition ( Chemical Vapor Deposition (hereinafter referred to as CVD) process for preparing TiN film layer and W film layer needs to be performed in a CVD chamber; ALD Al ₂ O ₃ refers to the preparation of Al ₂ O ₃ by an atomic layer deposition (ALD) process The film layer needs to be performed in an ALD chamber.

At present, CVD W, CVD TiN, and ALD Al ₂ O ₃ are independent devices on the market and cannot be integrated into the same transmission platform. This will have the following problems:

First, the cost of preparing capacitors by using CVD and ALD multiple independent devices is high.

Second, after each independent device completes a process, the wafer needs to be transferred to the independent device corresponding to the next process. Since the wafer transfer between two independent devices will expose the wafer to the air, the wafer will be exposed to the air five times during the entire preparation process of the above trench capacitor, which inevitably causes pollution to the surface of the deposited film.

Third, the resistivity of the electrode obtained by the CVD process deposition is large, which affects the capacitance performance.

The invention aims to solve at least one of the technical problems existing in the prior art, and proposes a semiconductor device, which can not only avoid the wafer from being exposed to the air during the transfer process, but also can improve the performance of the prepared capacitor and reduce the equipment cost.

To solve one of the above problems, the present invention provides a semiconductor device including: a physical vapor deposition chamber, an atomic layer deposition chamber, and a transmission platform;

The physical vapor deposition chamber is used to prepare an upper electrode and a lower electrode of a capacitor;

The atomic layer deposition chamber is used for preparing the dielectric layer of the capacitor;

The transfer platform is respectively connected to the physical vapor deposition chamber and the atomic layer deposition chamber, and is used for transferring wafers.

Optionally, it further includes a degassing chamber, which is used for degassing and annealing the wafer; the degassing chamber is connected to the transfer platform.

Optionally, a pre-cleaning chamber is further included, the pre-cleaning chamber is used for removing impurities on the surface of the wafer; the pre-cleaning chamber is connected to the transfer platform.

Optionally, the number of the physical vapor deposition chambers is plural, and the plurality of physical vapor deposition chambers are respectively used for depositing thin films of multiple materials.

Optionally, the upper electrode and the lower electrode of the capacitor each include at least one W film layer and at least one TiN film layer; the number of the physical vapor deposition chambers is two; and the two physical vapor deposition chambers are used for deposition, respectively. W film layer and TiN film layer.

Optionally, the upper electrode of the capacitor includes a W film layer and a TiN film layer sequentially stacked in a direction close to the lower electrode;

The lower electrode includes a W film layer and a TiN film layer sequentially stacked in a direction close to the upper electrode.

Optionally, the upper electrode of the capacitor includes a W film layer and a TiN film layer sequentially stacked in a direction close to the lower electrode;

The lower electrode includes a TiN film layer, a W film layer, and a TiN film layer sequentially stacked in a direction close to the upper electrode;

The dielectric layer is an Al ₂ O ₃ thin film.

Optionally, the dielectric layer includes an Al ₂ O ₃ film layer; the atomic layer deposition chamber is used to deposit an Al ₂ O ₃ film.

Optionally, the capacitor is a planar capacitor.

Optionally, the capacitor is a trench capacitor.

The present invention has the following beneficial effects: The semiconductor device provided by the present invention uses a physical vapor deposition chamber to prepare the upper electrode and the lower electrode of the capacitor. Compared with the chemical vapor deposition, the formed film has better density, and The resistivity is low, thereby improving the performance of the metal electrodes of the power board and the lower electrode, thereby improving the performance of the capacitor; at the same time, the semiconductor device provided by the present invention combines the physical vapor deposition chamber and the atomic layer deposition chamber with the same transmission platform Integrated together to form a single cluster equipment system, which not only reduces equipment costs, but also prevents wafers from being exposed to the air during the transfer process, thereby preventing the film surface from being contaminated.

In order to enable those skilled in the art to better understand the technical solutions of the present invention, the semiconductor device provided by the present invention will be described in detail below with reference to the accompanying drawings. Example 1

The semiconductor device provided by the embodiment of the present invention can be used to prepare a capacitor. FIG. 2 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. Please refer to FIG. 2. The semiconductor device includes: a physical vapor deposition (Physical Vapor Deposition (PVD)) chamber 40, and an atomic layer deposition (Atomic Layer Deposition (hereinafter referred to as ALD) chamber 50 and transmission platform 60. The PVD chamber 40 is used to prepare the upper and lower electrodes of the capacitor; the ALD chamber 50 is used to prepare the dielectric layer of the capacitor; the transfer platform 60 is connected to the PVD chamber 40 and the ALD chamber 50, respectively, for transferring wafers. Specifically, the transfer platform 60 mainly includes a transfer chamber and a loading / unloading station, wherein the transfer chamber is a vacuum chamber, and a robot arm is provided in the transfer chamber. The PVD chamber 40 and the ALD chamber 50 surround the transmission chamber and communicate with the transmission chamber, thereby forming a cluster equipment system.

After loading the wafer to the loading stage of the transfer platform 60, the robot removes the wafer from the loading stage, and transfers the wafer to the PVD chamber 40 and the ALD chamber 50 according to the process sequence. After the capacitor is prepared, the wafer is processed. The completed wafer is transferred to the unloading station.

The semiconductor device provided by the embodiment of the present invention uses a PVD chamber to prepare the upper electrode and the lower electrode of a capacitor. Compared with chemical vapor deposition, the formed film has better density and lower resistivity, thereby improving the film thickness. The performance of the metal electrode of the power board and the lower electrode, thereby improving the performance of the capacitor; at the same time, the semiconductor device provided by the present invention integrates the PVD chamber and the ALD chamber with the same transmission platform to form a single cluster equipment system. The equipment cost is reduced, and the wafer can be prevented from being exposed to the air during the transfer process, thereby preventing the surface of the film from being contaminated.

Optionally, the number of PVD chambers is plural, and the plural PVD chambers are respectively used for depositing thin films of multiple materials. In this way, a single cluster equipment system can complete the thin film deposition of multiple materials without using a plurality of independent equipment, which can reduce equipment costs while avoiding wafers being exposed to the air during transfer.

For example, the capacitor may be a planar capacitor or a trench capacitor. In addition, the upper electrode and the lower electrode of the capacitor may each include at least one W film layer and at least one TiN film layer. In this case, the number of PVD chambers may be two; the two PVD chambers are respectively used to deposit a W film layer and a TiN film layer. Optionally, the dielectric layer includes an Al ₂ O ₃ film layer; the ALD chamber is used to deposit an Al ₂ O ₃ film.

In this embodiment, FIG. 3a illustrates a planar capacitor, and FIG. 3b illustrates a trench capacitor. Both types of capacitors include an upper electrode 10, a lower electrode 20, and a dielectric layer 30 therebetween. . Wherein, the upper electrode 10 includes a W film layer and a TiN film layer which are sequentially stacked toward the lower electrode 20; the lower electrode 20 includes a W film layer and a TiN film layer which are sequentially stacked toward the upper electrode 10; the dielectric layer 30 is Al ₂ O ₃ film layer.

The two methods for preparing the above capacitors are: PVD W → PVD TiN → ALD Al ₂ O ₃ → PVD TiN → PVD W. Among them, PVD TiN and PVD W refer to the preparation of a TiN film layer and a W film layer by a physical vapor deposition process, which are performed in two PVD chambers, respectively. ALD Al ₂ O ₃ refers to the preparation of an Al ₂ O ₃ film layer by an atomic layer deposition process, which needs to be performed in an ALD chamber.

It should be noted that, in practical applications, the upper electrode and the lower electrode of the capacitor may also adopt other structures. For example, as shown in FIG. 1c, the upper electrode 10 of the capacitor includes a W film that is sequentially stacked in a direction close to the lower electrode 20. And a TiN film layer; the lower electrode 20 includes a TiN film layer, a W film layer, and a TiN film layer sequentially stacked in a direction close to the upper electrode 10. Of course, the number of film layers and the types of materials used for the upper and lower electrodes of the capacitor can be specifically set as required. In addition, the number of PVD chambers and the number of ALD chambers should correspond to the sum of the types of film materials used for the upper and lower electrodes.

Optionally, the PVD chamber is a magnetron sputtering chamber. FIG. 4 is a schematic diagram of a typical magnetron sputtering chamber. As shown in FIG. 4, the magnetron sputtering chamber includes a cavity 8 and a process kit, and a substrate is provided inside the cavity 8. A base 9 is used to carry a wafer; a target 3 is provided on the top of the cavity 8. The process kit includes a shielding member 2, a shielding ring 11, and a deposition ring 14, wherein the shielding member 2 surrounds the inside of the sidewall of the cavity 8 for protecting the sidewall of the cavity 8. The deposition ring 14 is disposed around the edge region of the base 9, and the shielding ring 11 is disposed on the shield 2 and the deposition ring 14 to block the gap between the two to prevent the plasma from entering the lower portion of the base 15. In addition, a magnetron 6 is provided above the target 3, and the magnetron 6 is rotated around the central axis by the drive of the motor 5. In addition, a cooling chamber 7 for containing deionized water is provided above the target 3 to cool the target; a magnetron 6 is located in the cooling chamber 7. In addition, a vacuum system 13 is provided at the bottom of the cavity 8 for evacuating the cavity.

As shown in FIG. 2, the semiconductor device provided by the embodiment of the present invention further includes a degas chamber 70, which is used for degassing and annealing the wafer. In addition, the degassing chamber 70 is connected to the transmission platform 60 and forms a cluster equipment system with other chambers.

Specifically, FIG. 5 is a schematic structural diagram of a degassing chamber. Please refer to FIG. 5. The degassing chamber 70 includes a cavity. A quartz window 71 is provided in the cavity, and the quartz window 71 isolates the cavity. A vacuum cavity 72 and an atmospheric cavity 73 are formed, wherein a susceptor 74 for carrying the wafer 76 is provided in the vacuum cavity 72; and a heating wire assembly 75 is provided in the susceptor 74 for uniformly heating the wafer 76. effect. A heating bulb 77 is provided in the atmospheric cavity 73, and the heating bulb 77 radiates heat to the wafer 76 through the quartz window 71. The heating bulb 77 is mounted on the mounting plate 79 through the lamp base 78, and a reflecting plate 792 is stacked on the surface of the mounting plate 79 facing the heating bulb 77, and the lower surface of the reflecting plate 792 is smoothed to make it more The heat from the heating bulb 77 is well reflected in the direction of the quartz window 71, so that the heating efficiency can be improved. In addition, a cooling water pipe 791 is provided on the mounting plate 79. Used to cool the reflector 792. A shield 793 is provided around the inner side of the side wall of the chamber, and a cooling water pipe 794 is provided in the shield 793 to cool the side wall of the chamber to avoid overheating of the side wall of the chamber.

By heating the wafer 76 with the heating bulb 77 and the heating wire assembly 75 at the same time, not only the heating efficiency can be improved, but also because the heating wire assembly 75 can heat the wafer 76 uniformly, the wafer 76 can be quickly and uniformly heated.

As shown in FIG. 2, the semiconductor device provided by the embodiment of the present invention further includes a PreClean chamber 80 for removing impurities on the surface of the wafer. In addition, the pre-cleaning chamber 80 is connected to the transfer platform 60 and forms a cluster equipment system with other chambers.

Specifically, FIG. 6 is a structural schematic diagram of the pre-cleaning chamber. Please refer to FIG. 6. The pre-cleaning chamber 80 includes a chamber cover 801, an insulation chamber wall 802, and a ring-shaped metal part 803. The base 804 carrying the wafer; and a solenoid coil 805 is wound on the outside of the insulation chamber wall 802, and a shielding cover 806 is provided around the solenoid coil 805 to avoid the occurrence of the solenoid coil 805 The magnetic induction lines radiate to the outside world. In addition, the solenoid coil 805 is connected to the first radio frequency power supply 807 through a matcher, and the first radio frequency power supply 807 is used to apply radio frequency power to the solenoid coil 805 to ionize the gas in the chamber to generate plasma; The radio frequency power supply 808 is connected to the base 804 through a matcher, and is used to generate a negative bias voltage on the wafer and attract plasma to bombard the wafer to remove impurities on the wafer surface and pre-process the wafer surface.

It should be noted that FIG. 4 to FIG. 6 respectively show typical PVD chambers, degassing chambers 70 and pre-cleaning chambers 80 commonly used at present, but the present invention is not limited to this, and in practical applications The PVD chamber, the degassing chamber 70, and the pre-cleaning chamber 80 of other structures can also be used. In addition, the ALD chamber adopts a chamber structure commonly used in the prior art, which is not described in detail here.

It can be understood that the above embodiments are merely exemplary embodiments used to explain the principle of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various variations and improvements can be made without departing from the spirit and essence of the present invention, and these variations and improvements are also considered as the protection scope of the present invention.

2‧‧‧shield

3‧‧‧ target

5‧‧‧motor

6‧‧‧Magnetron

7‧‧‧ cooling chamber

8‧‧‧ Cavity

9‧‧‧ base

10‧‧‧up electrode

11‧‧‧shield ring

13‧‧‧vacuum system

14‧‧‧ sedimentary ring

20‧‧‧ lower electrode

30‧‧‧ Dielectric layer

40‧‧‧Physical Vapor Deposition (PVD) chamber

50‧‧‧ Atomic Layer Deposition (ALD) chamber

60‧‧‧Transmission Platform

70‧‧‧Degas chamber

71‧‧‧Quartz window

72‧‧‧vacuum chamber

73‧‧‧ Atmosphere

74, 804‧‧‧ base

75‧‧‧Heating wire assembly

76‧‧‧Chip

77‧‧‧ heating bulb

78‧‧‧ bulb base

79‧‧‧Mounting plate

80‧‧‧PreClean chamber

791‧‧‧ cooling water pipeline

792‧‧‧Reflector

793‧‧‧shield

801‧‧‧ chamber cover

802‧‧‧ insulated chamber wall

803‧‧‧Ring metal parts

805‧‧‧solenoid coil

806‧‧‧Mask

807‧‧‧First RF Power Supply

808‧‧‧Second RF Power Supply

Fig. 1a is a schematic structural diagram of a planar capacitor; Fig. 1b is a schematic structural diagram of a trench capacitor; Fig. 1c is a schematic structural diagram of a specific trench capacitor; and Fig. 2 is a simplified structural diagram of a semiconductor device according to an embodiment of the present invention. Figure 3a is a schematic diagram of a planar capacitor in an embodiment of the present invention; Figure 3b is a schematic diagram of a trench capacitor in an embodiment of the present invention; Figure 4 is a schematic diagram of a typical magnetron sputtering chamber; Figure 5 is a schematic diagram of a degassing chamber; Figure 6 is a schematic diagram of a pre-cleaning chamber.

Claims (10)

A semiconductor device, comprising: a physical vapor deposition chamber, an atomic layer deposition chamber, and a transmission platform; the physical vapor deposition chamber is used to prepare an upper electrode and a lower electrode of a capacitor; the atom The layer deposition chamber is used to prepare a dielectric layer of the capacitor; the transfer platform is connected to the physical vapor deposition chamber and the atomic layer deposition chamber, respectively, for transferring wafers. The semiconductor device according to item 1 of the patent application scope further includes a degassing chamber for degassing and annealing the wafer; the degassing chamber is connected to the transfer platform. The semiconductor device according to item 1 of the patent application scope further includes a pre-cleaning chamber for removing impurities on the surface of the wafer; the pre-cleaning chamber is connected to the transfer platform. The semiconductor device according to item 1 of the scope of patent application, wherein the number of the physical vapor deposition chambers is plural, and the plurality of physical vapor deposition chambers are respectively used for depositing thin films of multiple materials. The semiconductor device according to item 4 of the scope of patent application, wherein the upper electrode and the lower electrode of the capacitor each include at least one W film layer and at least one TiN film layer; the number of the physical vapor deposition chambers is two; two The physical vapor deposition chamber is used to deposit a W film layer and a TiN film layer, respectively. The semiconductor device according to item 5 of the scope of patent application, wherein the upper electrode of the capacitor includes a W film layer and a TiN film layer sequentially stacked in a direction close to the lower electrode; the lower electrode includes a direction close to the upper electrode A W film layer and a TiN film layer are sequentially stacked. The semiconductor device according to item 5 of the scope of patent application, wherein the upper electrode of the capacitor includes a W film layer and a TiN film layer sequentially stacked in a direction close to the lower electrode; the lower electrode includes a direction close to the upper electrode The TiN film layer, the W film layer, and the TiN film layer are sequentially stacked; the dielectric layer is an Al ₂ O ₃ thin film. The semiconductor device according to any one of claims 1 to 7, wherein the dielectric layer includes an Al ₂ O ₃ film layer; and the atomic layer deposition chamber is used to deposit an Al ₂ O ₃ film. The semiconductor device according to item 1 of the scope of patent application, wherein the capacitor is a planar capacitor. The semiconductor device according to item 1 of the scope of patent application, wherein the capacitor is a trench capacitor.