WO2019139584A1 - Dispositif de mémoire de transition ferroélectrique à grilles multiples / métal-isolant - Google Patents

Dispositif de mémoire de transition ferroélectrique à grilles multiples / métal-isolant Download PDF

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Publication number
WO2019139584A1
WO2019139584A1 PCT/US2018/013243 US2018013243W WO2019139584A1 WO 2019139584 A1 WO2019139584 A1 WO 2019139584A1 US 2018013243 W US2018013243 W US 2018013243W WO 2019139584 A1 WO2019139584 A1 WO 2019139584A1
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WIPO (PCT)
Prior art keywords
ferroelectric gate
layer
gate
ferroelectric
insulator
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Application number
PCT/US2018/013243
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English (en)
Inventor
Brian Doyle
Prashant Majhi
Ravi Pillarisetty
Elijah Karpov
Abhishek Sharma
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Intel Corporation
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Priority to PCT/US2018/013243 priority Critical patent/WO2019139584A1/fr
Publication of WO2019139584A1 publication Critical patent/WO2019139584A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N99/00—Subject matter not provided for in other groups of this subclass
    • H10N99/03—Devices using Mott metal-insulator transition, e.g. field-effect transistor-like devices

Definitions

  • Embodiments of the present description generally relate to the field of integrated circuit memory devices, and, more specifically, to a ferroelectric memory device utilizing an insulator-metal transition material for a channel region, and methods of manufacturing the same.
  • the integrated circuit industry is continually striving to produce ever faster and smaller integrated circuit memory devices for use in various server and mobile electronic products, including, but not limited to, computer server products and portable products, such as wearable integrated circuit systems, portable computers, electronic tablets, cellular phones, digital cameras, and the like.
  • computer server products and portable products such as wearable integrated circuit systems, portable computers, electronic tablets, cellular phones, digital cameras, and the like.
  • data center and server markets are continually seeking larger capacity, more compact, and faster memory solutions.
  • One way to achieve these goals is by the utilization of unique materials for transistor components within the memory devices, which may be an improvement over traditional silicon semiconductor channel based memory devices having a standard gate dielectric layer and metal gate configuration for the transistor gate.
  • FIGs. 1-3 illustrate side schematic views of the operation of a multi-gate
  • ferroelectric/insulator-metal transition memory device according to one embodiment of the present description.
  • FIG. 4 illustrates a side schematic view of a multi-gate ferroelectric/insulator-metal transition memory device, according to another embodiment of the present description.
  • FIG. 5 is a flow chart of a process of fabricating a mulit-gate ferroelectric/insulator- metal transition memory device, according to an embodiment of the present description.
  • FIG. 6 illustrates top plan views of a wafer and dice that may include any of the multi gate ferroelectric/insulator-metal transition memory devices of any of the embodiments disclosed herein.
  • FIG. 7 illustrates a cross-sectional side view of an integrated circuit device that may include any of the multi-gate ferroelectric/insulator-metal transition memory devices of any of the embodiments disclosed herein.
  • FIG. 8 illustrates a cross-sectional side view of an integrated circuit device assembly that may include any of the multi-gate ferroelectric/insulator-metal transition memory devices of any of the embodiments disclosed herein.
  • FIG. 9 illustrates an electronic system, according to one embodiment of the present description.
  • the terms“over”,“to”,“between” and“on” as used herein may refer to a relative position of one layer with respect to other layers.
  • One layer“over” or“on” another layer or bonded“to” another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • One layer“between” layers may be directly in contact with the layers or may have one or more intervening layers.
  • Embodiments of the present description relate to integrated circuit memory devices fabricated with an insulator-metal transition layer as a channel region and multiple ferroelectric gates for switching the insulator-metal transition between an insulative state and a conductive state, and vice versa.
  • a source structure and a drain structure may be formed on a first surface of the insulator-metal transition layer
  • a first ferroelectric gate may be formed on the first surface of the insulator-metal transition layer between the source structure and the drain structure
  • a second ferroelectric gate may be formed on a second surface of the insulator-metal transition layer.
  • a memory device such as memory cell 100, may be formed by forming an insulator-metal transition layer 110 having a first surface 112 and an opposing second surface 114.
  • a source structure 122 and a drain structure 124 may be formed on the first surface 112 of the insulator-metal transition layer 110.
  • the insulator-metal transition layer 110 may act as a channel region between the source structure 122 and the drain structure 124.
  • a first ferroelectric gate 130 may be formed on the first surface 112 of the insulator-metal transition layer 110 between the source structure 122 and the drain structure 124.
  • a second ferroelectric gate 140 may be formed on the second surface 114 of the insulator-metal transition layer 110.
  • the first ferroelectric gate 130 may be formed opposite the second ferroelectric gate 140.
  • the first ferroelectric gate 130 and the second ferroelectric gate 140 may substantially share a common centerline CL substantially perpendicular to the first surface 112 and the second surface 114 of the insulator-metal transition layer 110.
  • the first ferroelectric gate 130 may comprise a gate electrode 134 and a ferroelectric gate layer 136, wherein the ferroelectric gate layer 136 is positioned between the gate electrode 134 and the first surface 112 of the insulator-metal transition layer 110.
  • the ferroelectric gate layer 136 takes the place of a gate dielectric layer.
  • the ferroelectric gate layer 136 may act as a binary switch, wherein the polarity of the ferroelectric gate layer 136 switches in the presence of an electric field that can be generated by the gate electrode 134.
  • the second ferroelectric gate 140 may also comprise a gate electrode 144 and a ferroelectric gate layer 146, wherein the ferroelectric gate layer 136 is positioned between the gate electrode 144 and second surface 114 of the insulator-metal transition layer 110, wherein the ferroelectric gate layer 146 of the second ferroelectric gate 140 operates in the manner of the ferroelectric gate layer 136 of the first ferroelectric gate 130.
  • the ferroelectric gate layer 136 of the first ferroelectric gate 130 and the ferroelectric gate layer 146 of the second ferroelectric gate 140 may comprise any appropriate ferroelectric material, including, but not limited to, lead zirconate titanate, lead titanate, barium titanate, and hafnium oxide, any of which may be doped or undoped.
  • the ferroelectric gate layer 136 of the first ferroelectric gate 130 and/or the ferroelectric gate layer 146 of the second ferroelectric gate 140 comprises hafnium and oxygen, such as hafnium oxide.
  • the hafnium oxide can be doped, for example by silicon, zirconium, lanthanum, aluminum, and the like, and may have dopant concentrations between about 3 and 30% by weight.
  • the gate electrode 134 of the first ferroelectric gate 130 and the gate electrode 144 of the second ferroelectric gate 140 may be any appropriate conductive or semiconductive material, including, but not limited to, polysilicon, metals (such as tungsten, copper, aluminum, gold, silver, and alloys thereof), metal containing materials, and the like.
  • the insulator-metal transition layer 110 may be any appropriate material that transitions from a metal to an insulator or vice versa when exposed to a polarization charge.
  • the insulator-metal transition 110 may be a bipolar Schottky diode material, including, but not limited to titanium dioxide.
  • the insulator-metal transition 110 may be a bipolar tunneling diode material, including, but not limited to silicon nitride (e.g. S13N4).
  • the insulator-metal transition 110 may be a varistor, such as a layered structure comprising a pair of tantalum oxide layers separated by a titanium dioxide layer.
  • the insulator- metal transition 110 may be a compositional insulator- metal transition material, including, but not limited to, a silver/hafnium oxide composition.
  • the insulator-metal transition 110 may be a Peierls insulator-metal transition material, including but not limited to, niobium oxide. In yet another embodiment, the insulator-metal transition 110 may be a Mott insulator-metal transition material, including but not limited to, vanadium dioxide and titanium(III) oxide. In yet a further embodiment, the insulator-metal transition 110 may be an Anderson insulator-metal transition material, including but not limited to, multicomponent chalcogenides.
  • the insulator-metal transition layer 110 may being insulative (denoted as INS).
  • INS insulative
  • a voltage may be applied to the gate electrode 144 of the second ferroelectric gate 140, which switches a polarization of the ferroelectric gate layer 146 of the second ferroelectric gate 140 from -5Q2 at the second surface 114 for the insulator-metal transition layer 110 to +5Q2.
  • This change in polarization in the ferroelectric gate layer 146 of the second ferroelectric gate 140 may begin to transition the insulator-metal transition layer 110 from insulative (denoted as INS) to conductive (denoted as CON).
  • insulator- metal transition layers 110 may need high charge densities to transition between insulative and conductive.
  • the first ferroelectric gate 130 may be used to increase the polarization charge to cause the insulator-metal transition layer 110 from insulative to conductive (and vice versa) more easily.
  • a voltage may be applied to the gate electrode 134 of the first ferroelectric gate 130, which switches a polarization of the ferroelectric gate layer 136 of the first ferroelectric gate 130 from -5Qi at the first surface 112 for the insulator-metal transition layer 110 to +5Qi.
  • This change in polarization in the ferroelectric gate layer 136 of the first ferroelectric gate 130 may completely transition the insulator-metal transition layer 110 to conductive (denoted as CON).
  • the use of at least two ferroelectric gates may allow for a greater polarization charge (i.e. 5Qi + 5Q2) compared to the use of a single ferroelectric gate, and may also allow for easier programming and more precise tuning of the switching voltage of the insulator-metal transition layer 110.
  • the memory cell 100 can be independently programmed: the memory cell 100 will not switch without both ferroelectric gates (e.g. the first ferroelectric gate 130 and the second ferroelectric gate 140) being on or off.
  • a more precise tuning may be achieved by fabricating the first ferroelectric gate 130 to have a different switching voltage from the switching voltage of the second ferroelectric gate 140. This may be achieved in several ways, including, but not limited to, fabricating the ferroelectric gate layer 136 of the first ferroelectric gate 130 from a different material from the ferroelectric gate layer 146 of the second ferroelectric gate 140, fabricating the ferroelectric gate layer 136 of the first ferroelectric gate 130 to have a different thickness from the ferroelectric gate layer 146 of the second ferroelectric gate 140 (shown in FIG. 3 as Tl > T2), fabricating the gate electrode 134 of the first ferroelectric gate 130 to have a different work function from the gate electrode 144 of the second ferroelectric gate 140, or any combination thereof.
  • the first ferroelectric gate 130 may be aligned to be opposite the second ferroelectric gate 140 on opposing sides of the insulator- metal transition layer 110. This configuration may concentrate the polarization changes in a position between the source structure 122 and the drain structure 124.
  • embodiments of the present description are not so limited, as the memory cell 100 may have more than two ferroelectric gates in any appropriate configuration or alignment.
  • an additional ferroelectric gate l40a may be formed on the second surface 114 of the insulator-metal transition layer 110.
  • FIG. 5 is a flow chart of a process 200 of fabricating a memory cell according to the various embodiments of the present description.
  • an insulator-metal transition layer may be formed having a first surface and an opposing second surface.
  • a source structure may be formed on the first surface of the insulator-metal transition layer, as set forth in block 204.
  • a drain structure may be formed on the first surface of the insulator-metal transition layer.
  • a first ferroelectric gate may be formed on the first surface of the insulator-metal transition layer between the source structure and the drain structure, as set forth in block 208.
  • a second ferroelectric gate may be formed on the second surface of the insulator-metal transition layer.
  • FIG. 6 depicts top views of a wafer 400 and dice 410 that may be formed from the wafer 400.
  • the dice 410 may include the memory cell 100 disclosed herein.
  • the wafer 400 may include semiconductor material and may include one or more dice 410 having integrated circuit elements (e.g., memory cell 100) formed on or above a surface of the wafer 400.
  • Each of the dice 410 may be a repeating unit of a semiconductor product that includes any suitable device. After the fabrication of the semiconductor product is complete, the wafer 400 may undergo a singulation process in which the dice 410 are separated from one another to provide discrete "chips" of the semiconductor product.
  • a die 410 may include one or more memory cells 100 and/or supporting circuitry to route electrical signals to the memory cells 100, as well as any other integrated circuit components.
  • the wafer 400 or the die 410 may include other memory devices, logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 410.
  • a memory device formed by multiple memory arrays e.g., multiple sets of memory cells 100
  • FIG. 7 is a cross-sectional side view of an integrated circuit device 500 that may include any of the memory cells 100 disclosed herein.
  • the integrated circuit device 500 may be formed on a substrate 502 (e.g., the wafer 400 of FIG. 6) and may be included in a die (e.g., the die 410 of FIG. 6).
  • the substrate 502 may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both).
  • the substrate 502 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure.
  • SOI silicon-on-insulator
  • the substrate 502 may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the substrate 502. Although a few examples of materials from which the substrate 502 may be formed are described here, any material that may serve as a foundation for an integrated circuit device 500 may be used.
  • the substrate 502 may be part of a singulated die (e.g., the dice 410 of FIG. 6) or a wafer (e.g., the wafer 400 of FIG. 6).
  • the integrated circuit device 500 may include one or more device layers 504 disposed on the substrate 502.
  • the device layer 504 may include features of one or more
  • transistors 540 e.g., metal oxide semiconductor field-effect transistors (MOSFETs) formed on the substrate 502.
  • the device layer 504 may include, for example, one or more source and/or drain (S/D) regions 520, a gate 522 to control current flow in the transistors 540 between the S/D regions 520, and one or more S/D contacts 524 to route electrical signals to/from the S/D regions 520.
  • the transistors 540 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 540 are not limited to the type and configuration depicted in FIG.
  • Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap around or all-around gate transistors, such as nanoribbon and nano wire transistors.
  • Each transistor 540 may include a gate 522 formed of at least two layers, a gate dielectric and a gate electrode.
  • the gate dielectric may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
  • the gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 540 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor.
  • the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning).
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
  • the gate electrode when viewed as a cross-section of the transistor 540 along the source-channel-drain direction, may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack.
  • the sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • the S/D regions 520 may be formed within the substrate 502 adjacent to the gate 522 of each transistor 540.
  • the S/D regions 520 may be formed using an implantation/diffusion process or an etching/deposition process, for example.
  • dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 502 to form the S/D regions 520.
  • An annealing process that activates the dopants and causes them to diffuse farther into the substrate 502 may follow the ion-implantation process.
  • the substrate 502 may first be etched to form recesses at the locations of the S/D regions 520.
  • the S/D regions 520 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the S/D regions 520 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy.
  • one or more layers of metal and/or metal alloys may be used to form the S/D regions 520.
  • Electrical signals such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 540) of the device layer 504 through one or more interconnect layers disposed on the device layer 504 (illustrated in FIG. 7 as interconnect layers 506-510).
  • interconnect layers 506-510 electrically conductive features of the device layer 504 (e.g., the gate 522 and the S/D contacts 524) may be electrically coupled with the interconnect structures 528 of the interconnect layers 506-510.
  • the one or more interconnect layers 506- 510 may form a metallization stack (also referred to as an "ILD stack") 519 of the integrated circuit device 500.
  • one or more memory cells 100 may be disposed in one or more of the interconnect layers 506-510, in accordance with any of the techniques disclosed herein.
  • FIG. 7 illustrates a single memory array 150, comprising a plurality of memory cells 100, in the interconnect layer 508 for illustration purposes, but any number and structure of memory cells 100 may be included in any one or more of the layers in a metallization stack 519.
  • a memory cell 100 (not shown) or the memory array 150 included in the metallization stack 519, in combination with computing logic (e.g., some or all of the transistors 540) in the integrated circuit device 500, may be referred to as an "embedded" memory array, as discussed above.
  • the integrated circuit device 500 may be referred to as a "standalone" memory device.
  • One or more memory cells 100 or the memory array 150 in the metallization stack 519 may be coupled to any suitable ones of the devices in the device layer 504, and/or to one or more of the conductive contacts 536 (discussed below).
  • the interconnect structures 528 may be arranged within the interconnect layers 506- 510 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 528 depicted in FIG. 7). Although a particular number of interconnect layers 506-510 is depicted in FIG. 7, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.
  • the interconnect structures 528 may include lines 528a and/or vias 528b filled with an electrically conductive material such as a metal.
  • the lines 528a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 502 upon which the device layer 504 is formed.
  • the lines 528a may route electrical signals in a direction in and out of the page from the perspective of FIG. 7.
  • the vias 528b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 502 upon which the device layer 504 is formed.
  • the vias 528b may electrically couple lines 528a of different interconnect layers 506-510 together.
  • the interconnect layers 506-510 may include a dielectric material 526 disposed between the interconnect structures 528, as shown in FIG. 7.
  • the dielectric material 526 disposed between the interconnect structures 528 in different ones of the interconnect layers 506-510 may have different compositions; in other embodiments, the composition of the dielectric material 526 between different interconnect layers 506-510 may be the same.
  • a first interconnect layer 506 (referred to as Metal 1 or "Ml") may be formed directly on the device layer 504.
  • the first interconnect layer 506 may include lines 528a and/or vias 528b, as shown.
  • the lines 528a of the first interconnect layer 506 may be coupled with contacts (e.g., the S/D contacts 524) of the device layer 504.
  • a second interconnect layer 508 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 506.
  • the second interconnect layer 508 may include vias 528b to couple the lines 528a of the second interconnect layer 508 with the lines 528a of the first interconnect layer 506.
  • the lines 528a and the vias 528b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 508) for the sake of clarity, the lines 528a and the vias 528b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual Damascene process) in some embodiments.
  • a third interconnect layer 510 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 508 according to similar techniques and configurations described in connection with the second interconnect layer 508 or the first interconnect layer 506.
  • the interconnect layers that are "higher up” in the metallization stack 519 in the integrated circuit device 500 may be thicker.
  • the integrated circuit device 500 may include a solder resist material 534 (e.g., polyimide or similar material) and one or more conductive contacts 536 formed on the interconnect layers 506-510.
  • a solder resist material 534 e.g., polyimide or similar material
  • conductive contacts 536 are illustrated as taking the form of bond pads.
  • the conductive contacts 536 may be electrically coupled with the interconnect structures 528 and configured to route the electrical signals of the
  • solder bonds may be formed on the one or more conductive contacts 536 to mechanically and/or electrically couple a chip including the integrated circuit device 500 with another component (e.g., a circuit board).
  • the integrated circuit device 500 may include additional or alternate structures to route the electrical signals from the interconnect layers 506-510; for example, the conductive contacts 536 may include other analogous features (e.g., posts) that route the electrical signals to external components.
  • the conductive contacts 536 may include other analogous features (e.g., posts) that route the electrical signals to external components.
  • FIG. 8 is a cross-sectional side view of a device assembly 600 that may include any of the memory cells 100 disclosed herein in one or more packages.
  • a "package" may refer to an electronic component that includes one or more integrated circuit devices (e.g., the integrated circuit devices 500 discussed above with reference to FIG. 7) that are structured for coupling to other components; for example, a package may include a die coupled to a package substrate that provides electrical routing and mechanical stability to the die.
  • the device assembly 600 includes a number of components disposed on a circuit board 602.
  • the device assembly 600 may include components disposed on a first surface 640 of the circuit board 602 and an opposing second surface 642 of the circuit board 602; generally, components may be disposed on one or both surfaces 640 and 642.
  • the circuit board 602 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 602.
  • the circuit board 602 may be a package substrate or flexible board.
  • the device assembly 600 illustrated in FIG. 8 includes a package-on-interposer structure 636 coupled to the first surface 640 of the circuit board 602 by coupling
  • the coupling components 616 may electrically and mechanically couple the package-on-interposer structure 636 to the circuit board 602 and may include solder balls, male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
  • the package-on-interposer structure 636 may include a package 620 coupled to an interposer 604 by coupling components 618.
  • the coupling components 618 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 616. Although a single package 620 is shown in FIG. 8, multiple packages may be coupled to the interposer 604; indeed, additional interposers may be coupled to the interposer 604.
  • the interposer 604 may provide an intervening substrate used to bridge the circuit board 602 and the package 620.
  • the package 620 may include one or more memory cells 100. Generally, the interposer 604 may spread a connection to a wider pitch or reroute a connection to a different connection.
  • the interposer 604 may couple the package 620 (e.g., a die) to a ball grid array (BGA) of the coupling components 616 for coupling to the circuit board 602.
  • the package 620 and the circuit board 602 are attached to opposing sides of the interposer 604; in other embodiments, the package 620 and the circuit board 602 may be attached to a same side of the interposer 604. In some embodiments, three or more components may be
  • interconnected by way of the interposer 604.
  • the interposer 604 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 604 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer 604 may include metal interconnects 608 and vias 610, including, but not limited to, through-silicon vias (TSVs) 606.
  • TSVs through-silicon vias
  • the interposer 604 may further include embedded devices 614, including both passive and active devices.
  • Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices (e.g., the memory cells 100). More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 604.
  • RF radio frequency
  • MEMS microelectromechanical systems
  • the package-on-interposer structure 636 may take the form of any of the package-on-interposer structures known in the art.
  • the device assembly 600 may include a package 624 coupled to the first surface 640 of the circuit board 602 by coupling components 622.
  • the coupling components 622 may take the form of any of the embodiments discussed above with reference to the coupling components 616
  • the package 624 may take the form of any of the embodiments discussed above with reference to the package 620.
  • the package 624 may include one or more memory cells 100, for example.
  • the device assembly 600 illustrated in FIG. 8 includes a package-on-package structure 634 coupled to the second face 642 of the circuit board 602 by coupling
  • the package-on-package structure 634 may include a package 626 and a package 632 coupled together by coupling components 630 such that the package 626 is disposed between the circuit board 602 and the package 632.
  • the coupling components 628 and 630 may take the form of any of the embodiments of the coupling components 616 discussed above, and the packages 626 and 632 may take the form of any of the embodiments of the package 620 discussed above.
  • Each of the packages 626 and 632 may include one or more memory cells 100.
  • FIG. 9 illustrates an electronic system or computing device 700 in accordance with one implementation of the present description.
  • the computing device 700 may house a board 702.
  • the board 702 may include a number of integrated circuit components attached thereto, including but not limited to a processor 704, at least one communication chip 706 A, 706B, volatile memory 708, (e.g., DRAM), non-volatile memory 710 (e.g., ROM), flash memory 712, a graphics processor or CPU 714, a digital signal processor (not shown), a crypto processor (not shown), a chipset 716, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a camera, and a mass storage device (not shown) (such as hard disk drive
  • the communication chip enables wireless communications for the transfer of data to and from the computing device.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device may include a plurality of communication chips.
  • a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others
  • the term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • any of the integrated circuit components within the computing device 700 may include memory cells 100, or an array thereof, which comprises an insulator-metal transition layer having a first surface and an opposing second surface, a source structure on the first surface of the insulator-metal transition layer, a drain structure on the first surface of the insulator-metal transition layer, a first ferroelectric gate on the first surface of the insulator- metal transition layer between the source structure and the drain structure, and a second ferroelectric gate on the second surface of the insulator-metal transition layer.
  • the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device may be any other electronic device that processes data.
  • Example 1 is a memory cell comprising an insulator-metal transition layer having a first surface and an opposing second surface, a source structure on the first surface of the insulator-metal transition layer, a drain structure on the first surface of the insulator-metal transition layer, a first ferroelectric gate on the first surface of the insulator-metal transition layer between the source structure and the drain structure, and a second ferroelectric gate on the second surface of the insulator-metal transition layer.
  • Example 2 the subject matter of Example 1 can optionally include the first ferroelectric gate being positioned opposite the second ferroelectric gate.
  • Example 3 the subject matter of either Example 1 or 2 can optionally include the insulator-metal transition layer being selected from the group consisting of titanium dioxide, titanium(III) oxide, vanadium dioxide, tantalum oxide, niobium oxide, silicon nitride, silver/hafhium oxide compositions, and chalcogenides.
  • the insulator-metal transition layer being selected from the group consisting of titanium dioxide, titanium(III) oxide, vanadium dioxide, tantalum oxide, niobium oxide, silicon nitride, silver/hafhium oxide compositions, and chalcogenides.
  • Example 4 the subject matter of either Example 1 or 2 can optionally include the first ferroelectric gate comprises a gate electrode and a ferroelectric gate layer, wherein the ferroelectric gate layer is positioned between the gate electrode and the insulator-metal transition layer and wherein the second ferroelectric gate comprises a gate electrode and a ferroelectric gate layer, wherein the ferroelectric gate layer is positioned between the gate electrode and the insulator-metal transition layer.
  • Example 5 the subject matter of Example 4 can optionally include at least one of the ferroelectric gate layer of the first ferroelectric gate and the ferroelectric gate layer of the second ferroelectric gate comprising hafnium and oxygen.
  • Example 6 the subject matter of Example 4 can optionally include the ferroelectric gate layer of the first ferroelectric gate comprising a different material from the ferroelectric gate layer of the second ferroelectric gate.
  • Example 7 the subject matter of Example 4 can optionally include the ferroelectric gate layer of the first ferroelectric gate has a thickness different material from a thickness of the ferroelectric gate layer of the second ferroelectric gate.
  • Example 8 the subject matter of Example 4 can optionally include the gate electrode of the first ferroelectric gate has a different work function from a work function of the gate electrode of the second ferroelectric gate.
  • Example 9 the subject matter of either Example 1 or 2 can optionally include at least one additional ferroelectric gate on the insulator-metal transition layer.
  • Example 10 is an integrated circuit device comprising at least one logic transistors and at least one memory cell electrically connected to the at least one logic transistor, wherein the at least one memory cell comprises an insulator-metal transition layer having a first surface and an opposing second surface, a source structure on the first surface of the insulator-metal transition layer, a drain structure on the first surface of the insulator-metal transition layer, a first ferroelectric gate on the first surface of the insulator-metal transition layer between the source structure and the drain structure, and a second ferroelectric gate on the second surface of the insulator-metal transition layer.
  • the subject matter of Example 10 can optionally include the first ferroelectric gate being positioned opposite the second ferroelectric gate.
  • Example 12 the subject matter of either Example 10 or 11 can optionally include the insulator-metal transition layer being selected from the group comprising titanium dioxide, titanium(III) oxide, vanadium dioxide, tantalum oxide, niobium oxide, silicon nitride, silver/hafhium oxide compositions, and chalcogenides.
  • the insulator-metal transition layer being selected from the group comprising titanium dioxide, titanium(III) oxide, vanadium dioxide, tantalum oxide, niobium oxide, silicon nitride, silver/hafhium oxide compositions, and chalcogenides.
  • Example 13 the subject matter of either Example 10 or 11 can optionally include the first ferroelectric gate comprises a gate electrode and a ferroelectric gate layer, wherein the ferroelectric gate layer is positioned between the gate electrode and the insulator-metal transition layer and wherein the second ferroelectric gate comprises a gate electrode and a ferroelectric gate layer, wherein the ferroelectric gate layer is positioned between the gate electrode and the insulator-metal transition layer.
  • Example 14 the subject matter of Example 13 can optionally include at least one of the ferroelectric gate layer of the first ferroelectric gate and the ferroelectric gate layer of the second ferroelectric gate comprising hafnium and oxygen.
  • Example 15 the subject matter of Example 13 can optionally include the ferroelectric gate layer of the first ferroelectric gate comprising a different material from the ferroelectric gate layer of the second ferroelectric gate.
  • Example 16 the subject matter of Example 13 can optionally include the ferroelectric gate layer of the first ferroelectric gate has a thickness different material from a thickness of the ferroelectric gate layer of the second ferroelectric gate.
  • Example 17 the subject matter of Example 13 can optionally include the gate electrode of the first ferroelectric gate has a different work function from a work function of the gate electrode of the second ferroelectric gate.
  • Example 18 the subject matter of either Example 10 or 11 can optionally include at least one additional ferroelectric gate on the insulator-metal transition layer.
  • Example 19 is an electronic system comprising a board and an integrated circuit component attached to the board, wherein the integrated circuit component includes at least one memory cell comprising an insulator-metal transition layer having a first surface and an opposing second surface, a source structure on the first surface of the insulator-metal transition layer, a drain structure on the first surface of the insulator-metal transition layer, a first ferroelectric gate on the first surface of the insulator-metal transition layer between the source structure and the drain structure, and a second ferroelectric gate on the second surface of the insulator-metal transition layer.
  • the integrated circuit component includes at least one memory cell comprising an insulator-metal transition layer having a first surface and an opposing second surface, a source structure on the first surface of the insulator-metal transition layer, a drain structure on the first surface of the insulator-metal transition layer, a first ferroelectric gate on the first surface of the insulator-metal transition layer between the source structure and the drain structure, and a second
  • Example 20 the subject matter of Example 19 can optionally include the first ferroelectric gate being positioned opposite the second ferroelectric gate.
  • Example 21 the subject matter of either Example 19 or 20 can optionally include the insulator-metal transition layer being selected from the group comprising titanium dioxide, titanium(III) oxide, vanadium dioxide, tantalum oxide, niobium oxide, silicon nitride, silver/hafhium oxide compositions, and chalcogenides.
  • the insulator-metal transition layer being selected from the group comprising titanium dioxide, titanium(III) oxide, vanadium dioxide, tantalum oxide, niobium oxide, silicon nitride, silver/hafhium oxide compositions, and chalcogenides.
  • Example 22 the subject matter of either Example 19 or 20 can optionally include the first ferroelectric gate comprises a gate electrode and a ferroelectric gate layer, wherein the ferroelectric gate layer is positioned between the gate electrode and the insulator-metal transition layer and wherein the second ferroelectric gate comprises a gate electrode and a ferroelectric gate layer, wherein the ferroelectric gate layer is positioned between the gate electrode and the insulator-metal transition layer.
  • Example 23 the subject matter of Example 22 can optionally include at least one of the ferroelectric gate layer of the first ferroelectric gate and the ferroelectric gate layer of the second ferroelectric gate comprising hafnium and oxygen.
  • Example 24 the subject matter of Example 22 can optionally include the ferroelectric gate layer of the first ferroelectric gate comprising a different material from the ferroelectric gate layer of the second ferroelectric gate.
  • Example 25 the subject matter of Example 22 can optionally include the ferroelectric gate layer of the first ferroelectric gate has a thickness different material from a thickness of the ferroelectric gate layer of the second ferroelectric gate.
  • Example 26 the subject matter of Example 22 can optionally include the gate electrode of the first ferroelectric gate has a different work function from a work function of the gate electrode of the second ferroelectric gate.
  • Example 27 the subject matter of either Example 19 or 20 can optionally include at least one additional ferroelectric gate on the insulator-metal transition layer.
  • Example 28 is a method of forming a memory cell, comprising forming an insulator-metal transition layer having a first surface and an opposing second surface, forming a source structure on the first surface of the insulator-metal transition layer, forming a drain structure on the first surface of the insulator-metal transition layer, forming a first ferroelectric gate on the first surface of the insulator-metal transition layer between the source structure and the drain structure, and forming a second ferroelectric gate on the second surface of the insulator-metal transition layer.
  • Example 29 the subject matter of Example 28 can optionally forming the second ferroelectric gate further comprising positioning the second ferroelectric gate opposite the first ferroelectric gate.
  • Example 30 the subject matter of either Example 28 or 29 can optionally include forming the insulator-metal transition layer comprising forming the insulator-metal transition layer from a material selected from the group comprising titanium dioxide, titanium(III) oxide, vanadium dioxide, tantalum oxide, niobium oxide, silicon nitride, silver/hafnium oxide compositions, and chalcogenides.
  • Example 31 the subject matter of either Example 28 or 29 can optionally include forming the first ferroelectric gate comprises forming a gate electrode and forming a ferroelectric gate layer, wherein the ferroelectric gate layer is positioned between the gate electrode and the insulator-metal transition layer and wherein the second ferroelectric gate comprises a gate electrode and a ferroelectric gate layer, wherein the ferroelectric gate layer is positioned between the gate electrode and the insulator-metal transition layer.
  • Example 32 the subject matter of Example 31 can optionally include at least one of forming the ferroelectric gate layer of the first ferroelectric gate and forming the ferroelectric gate layer of the second ferroelectric gate comprising a ferroelectric gate layer from hafnium and oxygen.
  • Example 33 the subject matter of Example 31 can optionally include forming the ferroelectric gate layer of the first ferroelectric gate comprising forming the ferroelectric gate layer of the first ferroelectric gate from a different material from the ferroelectric gate layer of the second ferroelectric gate.
  • Example 34 the subject matter of Example 31 can optionally include forming the ferroelectric gate layer of the first ferroelectric gate comprising forming the ferroelectric gate layer of the first ferroelectric gate having a thickness different material from a thickness of the ferroelectric gate layer of the second ferroelectric gate.
  • Example 35 the subject matter of Example 31 can optionally include forming the gate electrode of the first ferroelectric gate comprising forming the gate electronic of the first ferroelectric gate having a different work function from a work function of the gate electrode of the second ferroelectric gate.
  • Example 36 the subject matter of either Example 28 or 29 can optionally include forming at least one additional ferroelectric gate on the insulator-metal transition layer.

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Abstract

L'invention concerne un dispositif de mémoire à circuit intégré qui peut être fabriqué avec une couche de transition métal-isolant en tant que région de canal et de multiples grilles ferroélectriques pour commuter la transition métal-isolant entre un état isolant et un état conducteur, et vice versa. Dans un mode de réalisation, une structure de source et une structure de drain peuvent être formées sur une première surface de la couche de transition métal-isolant, une première grille ferroélectrique peut être formée sur la première surface de la couche de transition métal-isolant entre la structure de source et la structure de drain, et une seconde grille ferroélectrique peut être formée sur une seconde surface de la couche de transition métal-isolant.
PCT/US2018/013243 2018-01-11 2018-01-11 Dispositif de mémoire de transition ferroélectrique à grilles multiples / métal-isolant WO2019139584A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0732751A1 (fr) * 1995-03-13 1996-09-18 Kabushiki Kaisha Toshiba Dispositif semi-conducteur de mémoire avec une couche de transistion métal-isolant
US20030054615A1 (en) * 2001-09-17 2003-03-20 Hyun-Tak Kim Switching field effect transistor using abrupt metal-insulator transition
US20060255392A1 (en) * 2005-05-12 2006-11-16 Samsung Electronics Co., Ltd. Transistor including metal-insulator transition material and method of manufacturing the same
US20110019488A1 (en) * 2008-01-04 2011-01-27 Centre National De La Recherche Scientifique Double-gate floating-body memory device
JP2011199278A (ja) * 2010-03-23 2011-10-06 Internatl Business Mach Corp <Ibm> 高密度メモリ素子

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0732751A1 (fr) * 1995-03-13 1996-09-18 Kabushiki Kaisha Toshiba Dispositif semi-conducteur de mémoire avec une couche de transistion métal-isolant
US20030054615A1 (en) * 2001-09-17 2003-03-20 Hyun-Tak Kim Switching field effect transistor using abrupt metal-insulator transition
US20060255392A1 (en) * 2005-05-12 2006-11-16 Samsung Electronics Co., Ltd. Transistor including metal-insulator transition material and method of manufacturing the same
US20110019488A1 (en) * 2008-01-04 2011-01-27 Centre National De La Recherche Scientifique Double-gate floating-body memory device
JP2011199278A (ja) * 2010-03-23 2011-10-06 Internatl Business Mach Corp <Ibm> 高密度メモリ素子

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