WO2019132925A1 - Système frontal rf doté d'un résonateur à ondes acoustiques co-intégré - Google Patents

Système frontal rf doté d'un résonateur à ondes acoustiques co-intégré Download PDF

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Publication number
WO2019132925A1
WO2019132925A1 PCT/US2017/068752 US2017068752W WO2019132925A1 WO 2019132925 A1 WO2019132925 A1 WO 2019132925A1 US 2017068752 W US2017068752 W US 2017068752W WO 2019132925 A1 WO2019132925 A1 WO 2019132925A1
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WO
WIPO (PCT)
Prior art keywords
interconnect structure
cap
metal
inductor
system die
Prior art date
Application number
PCT/US2017/068752
Other languages
English (en)
Inventor
Vijay K. Nair
Telesphor Kamgaing
Feras EID
Georgios C. DOGIAMIS
Johanna M. SWAN
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/068752 priority Critical patent/WO2019132925A1/fr
Publication of WO2019132925A1 publication Critical patent/WO2019132925A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0542—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a lateral arrangement
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
    • H03H9/0557—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement the other elements being buried in the substrate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H03H9/1014—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
    • H03H9/1071—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the SAW device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material
    • H03H9/542—Filters comprising resonators of piezoelectric or electrostrictive material including passive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021—Constructional details
    • H03H2001/0085—Multilayer, e.g. LTCC, HTCC, green sheets

Definitions

  • Embodiments of the present disclosure relate to RF front end systems, and more particularly, to an RF front end system with an integrated and hermetically sealed acoustic wave resonator (AWR).
  • AWR hermetically sealed acoustic wave resonator
  • Front end modules for smartphones and other hand held devices require radio frequency (RF) filters with very high frequency selectivity and tunability.
  • the filters need to be integrated with active circuits like power amplifiers, low noise amplifiers, switches etc. in very compact form factor to minimize parasitic effects on the circuit performance.
  • the state of the art today is to build filters and RF active circuits in different substrates and assemble them together in a package or on a printed circuit board (PCB).
  • PCB printed circuit board
  • Fig. 1 A is an illustration of a system or system-on-a-chip die, in accordance with an embodiment of the present disclosure.
  • Fig. 1B is a plan view illustration of a portion of a system die, in accordance with an embodiment of the present disclosure.
  • Fig. 1C illustrates a packaged system in accordance with an embodiment of the present disclosure.
  • Fig. 2A illustrates a system die in accordance with an embodiment of the present disclosure.
  • Fig. 2B is an illustration of a system die in accordance with an embodiment of the present disclosure.
  • Fig. 2C is an illustration of a packaged system wherein a system die is attached to a package substrate in accordance with an embodiment of the present disclosure.
  • Fig. 3A illustrates a system die in accordance with an embodiment of the present disclosure.
  • Fig. 3B is an illustration of a system die in accordance with an embodiment of the present disclosure.
  • Fig. 3C is an illustration of a packaged system wherein a system die is attached to a package substrate in accordance with an embodiment of the present disclosure.
  • Fig. 3D is an illustration of a packaged system wherein a system die is attached to a package substrate in accordance with an embodiment of the present disclosure.
  • Fig. 4 is a schematic illustration of a RF front end system or module in accordance with an embodiment of the present disclosure.
  • Fig. 5 is a schematic illustration of an RF hybrid circuit or filter in accordance with an embodiment of the present disclosure.
  • Fig. 6A and Fig. 6B illustrate various capacitors which may be integrated or embedded into a package substrate, in accordance with embodiments of the present disclosure.
  • Figs. 7A-7F illustrate various inductors which may be embedded into a package substrate in accordance with embodiments of the present disclosure.
  • Fig. 8 is a schematic block diagram illustrating a computer system that utilizes a system die or a packaged system, or a combination thereof, as described herein, in accordance with an embodiment of the present disclosure.
  • RF front end systems and more particularly an RF front end system with an integrated and hermetically sealed acoustic wave resonator (AWR) are described.
  • AWR hermetically sealed acoustic wave resonator
  • Embodiments of the present disclosure relate to RF front end systems and more particularly to a fully integrated RF front end system or module which includes an integrated and hermetically sealed acoustic wave resonator (AWR) or resonator and passive components, such as inductors and capacitors.
  • AWR acoustic wave resonator
  • an RF front end system includes front end active circuits, such as amplifiers, matching networks and switches, passive devices, such as resistors, capacitors and inductors, and one or more acoustic wave resonators (AWR) all integrated together on a same substrate or die.
  • the passive devices and one or more acoustic wave resonators may be integrated together on a same substrate or die to create a hybrid filter, such as a hybrid LC/AWR (lumped components/acoustic wave resonator) filter.
  • the hybrid circuit may contain a transformer.
  • a hybrid filter or bank of filters may have multiple resonators and multiple passive components to provide different frequency band operations as required by, for example, a 5G communication system.
  • the hybrid filter may be integrated with front end RF active circuits, such as power amplifiers, low noise amplifiers and switches to create an RF front end system or module fully integrated on a single substrate.
  • the integrated RF system may enable transmission and reception of radio frequency (RF) signals in a network, such as a 5G network.
  • a die containing the system may contain a cap or lid which may hermetically and/or acoustically seal the AWR from environmental interference and contamination, such as moisture contamination.
  • the cap may include a metal plate to provide an electromagnetic interference (EMI) shield to protect the resonator and any other components on the die from electromagnetic interference.
  • the die may be coupled to a package substrate, and the package substrate may have high quality factor passive components, such as inductors, capacitors, and transformers embedded therein.
  • Fig. 1 A is an illustration of a system die, in accordance with an embodiment of the present disclosure.
  • System die 100 includes a substrate 102, such as a semiconductor substrate, an interconnect structure 104, an acoustic wave resonator (or resonator) 106, a cap or lid 108, an active circuit area 110, and one or more passive components, such as capacitor 114 and inductor 112
  • substrate 102 may be a semiconductor substrate, such as but not limited to a silicon substrate, a silicon carbide substrate, or a group III-V semiconductor substrate, such as but not limited to gallium nitride (GaN), gallium arsenide (GaAs), and indium phosphide (InP).
  • substrate 102 is a monocry stalline silicon substrate.
  • substrate 102 is a gallium nitride substrate.
  • Interconnect structure 104 may be disposed on a front side 116 of substrate 102.
  • interconnect structure 104 is a multilayer interconnect structure including multiple metallization layers 118 separated by dielectric layers 120.
  • Conductive vias 122 may electrically connect one level of metal 118 to another level of metal 118.
  • Each of the metal layers 118 may contain a plurality of metal interconnects used to route signals and power to various devices and components on system die 100.
  • the metal layers 118 may be formed from any suitable metal or stack of metals, such as but not limited to copper, aluminum, gold, cobalt, titanium nitride, and tantalum nitride.
  • Dielectric layers 120 may be formed from any suitable dielectric or stack of dielectrics, such as but not limited to silicon oxide, carbon doped silicon oxide, silicon oxynitride, polyimide, BCB, and silicon nitride. Although only two metal layers 118 and one dielectric layer 120 are illustrated in Fig. lA, it is to be appreciated that interconnect structure 104 may contain many more metal layers 118 and dielectric layers 120, such as between 6-14 metal layers with corresponding dielectric layers, depending upon the complexity and number of elements or devices to be coupled together. Metal layers 118 and vias 120 may be fabricated by any well known process, such as but not limited to damascene and dual damascene processes.
  • resonator 106 may be disposed in interconnect structure 104 as illustrated in Fig. 1A.
  • a resonator 106 may be any well known resonator, such as but not limited to a bulk acoustic wave resonator (BAW), a thin film bulk acoustic wave resonator (FBAR), a solidly mounted resonator (SMR), a contour-mode resonator (CMR), a composite longitudinal mode resonator (CLMR) or a surface acoustic wave (SAW) device.
  • BAW bulk acoustic wave resonator
  • FBAR thin film bulk acoustic wave resonator
  • SMR solidly mounted resonator
  • CMR contour-mode resonator
  • CLMR composite longitudinal mode resonator
  • SAW surface acoustic wave
  • resonator 106 is a thin film bulk resonator having a piezoelectric material 124 sandwiched between a first electrode 126 and a second electrode 128.
  • the piezoelectric material 124 may be any suitable piezoelectric material, such as but not limited to aluminum nitride, zinc oxide, lead zirconium titanate (PZT), and sodium potassium niobate (KNN), or the like.
  • the piezoelectric material 124 may have a thickness ranging from several micrometers down to a hundredths of a micrometer.
  • resonator 106 has a resonance frequency or may resonate at a frequency between 10 MHz to 10 GHz.
  • the resonator 106 has a cantilever portion 130 and an anchored portion 132.
  • cantilever portion 130 extends over a cavity 134 disposed in interconnect structure 104 in order to enable the cantilever portion 130 to translate between 0.1- 3 microns.
  • resonator 106 may have an x-y size between 50 micron by 50 microns to 500 microns by 500 microns.
  • cap 108 is attached to interconnect structure 104 by a seal frame 136.
  • Seal frame 136 completely surrounds resonator 106 and creates a hermetic seal between interconnect structure 104 and cap 108.
  • Seal frame 136 forms a hermetic and acoustically sealed air cavity 131 around resonator 106 which protects resonator 106 from environmental conditions and interference.
  • Seal frame 136 may be made from metal, such as but not limited to gold, copper, tin and indium.
  • seal frame 136 may be made from an insulating material, such as but not limited to a glass frit, a ceramic, a polymer, a liquid crystal polymer, and an inorganic dielectric.
  • seal frame 136 may have a thickness between 0.5-10 microns.
  • seal frame 136 includes a metal ring or frame disposed on the outer surface of interconnect structure 104 and a metal ring or frame on cap 108.
  • the metal rings or frames may be directly bonded together by, for example, diffusion bonding, or may be bonded together by intermediate solder layer, such as an eutectic solder, e.g., tin bismuth.
  • cap 108 may be formed from a semiconductor, such as silicon, a ceramic, a glass, or an epoxy.
  • cap 108 may include a metal plate or shield 137.
  • Metal plate or shield 137 may be formed by electroplating or other metallization techniques, such as sputtering or lamination. Shield 137 may act as an electromagnetic interference (EMI) shield and protect resonator 106 from electromagnetic interference. In an embodiment, plate or shield 137 is electrically coupled to interconnect structure 104 by a metal seal frame 136.
  • EMI electromagnetic interference
  • system die 100 may contain two or more resonators 106. In one embodiment, two or more resonators may be located in the cavity 131 created by cap 108. In another embodiment, die 100 may contain two or more resonators 106 and two or more caps 108 and seal frames 136 so that one resonator 106 may be located in one cavity, and a second resonator 106 may be located in a second different cavity.
  • inductor 112 is disposed in interconnect structure 104.
  • inductor 112 surrounds resonator 106 as illustrated in the plan view of Fig. 1B. In other embodiments, inductor 112 may not surround resonator 106 but may be located adjacent to resonator 106. In an embodiment, one of the ends or terminals of inductor 112 may be electrically coupled to one of the electrodes 126 or 128 of resonator 106, as illustrated in Figs. 1 A and 1B.
  • inductor 112 may have one end or terminal coupled to one electrode 126 or 128 of resonator 106 and may have a second end or terminal coupled to the other electrode 126 or 128 of inductor 112 so that inductor 112 and resonator 106 are coupled in parallel as illustrated in Figs. 1A and 1B.
  • Inductor 112 may contain a partial or fraction of a loop, a single loop or multiple loops as illustrated in Fig. 1B.
  • inductor 112 is a planar inductor and may have loops fabricated in a single metal layer 118 of interconnect structure 104, such as a top metal layer 118, for example.
  • inductor 112 may have a loop or loops fabricated in two or more metal layers 118 of interconnect structure 104, where the metal layers 118 are electrically connected by a plurality of conductive vias, such as rectangular or circular vias, in order to achieve a higher trace thickness for inductor 112 and thereby create a higher quality factor (e.g., high Q) inductor.
  • a higher quality factor e.g., high Q
  • the metal layers 118 of the inductor may be connected by a trench via or a slot via which extends the entire length or substantially the entire length, such as, for example 90%, of the length of the conductors of the inductor 112 disposed in metal layers 118.
  • system die 100 may contain two or more inductors 112, and in embodiments each inductor 112 may be coupled to a same resonator 106 or to different resonators 106.
  • active device area 110 contains active devices such as but not limited to transistors and/or diodes.
  • the active devices may be electrically coupled together by interconnect structure 104 to form RF front end circuits, such as but not limited to switches, power amplifiers, low noise amplifiers, and matching networks.
  • Fig. 1A and Fig. 1B illustrate a transistor 140, such as a field effect transistor (FET) having a source 142 and a drain 144 separated by a gate 146. Although only a single transistor 140 is illustrated in Figs. 1A and 1B, it is to be appreciated that active device area 110 may contain many more active devices.
  • transistor 140 may be part of a power amplifier or switch.
  • transistor 140 is coupled to inductor 112 by, for example, the drain terminal 144 to provide, for example, frequency selection.
  • active device area 110 is part of semiconductor substrate 102 and is of the same semiconductor material, such as silicon or GaN, as substrate 102. In an embodiment, active device area 110 is a different semiconductor material than semiconductor material of substrate 102. For example, active device area 110 may be made of a semiconductor material beher suited for the fabrication of RF active circuits than is a semiconductor material of substrate 102. In an embodiment, active device area 110 is gallium nitride and contains RF active circuits, such as amplifiers and switches, and substrate 102 is silicon and contains CMOS circuitry and transistors (not shown) such as nonplanar finFETs. In an embodiment, the finFETs formed in the silicon substrate may be coupled together by interconnect structure 104 to create a processor, such as an applications processor. The finFets may also be interconnected to form driver circuits for the RF circuits.
  • capacitor 114 may be disposed in interconnect structure 104.
  • Capacitor 114 may be any suitable capacitor, such as but not limited to a parallel plate capacitor, a metal insulator metal (MIM) capacitor, an interdigitated capacitor, and/or a cup or trench capacitor.
  • Capacitors may include a capacitor dielectric which may be an organic or inorganic material such as silica-filled epoxy, silicon oxide, silicon nitride, barium titanate, titanium oxide or lead zirconium titanate.
  • system die 100 includes a plurality of through substrate vias (TSVs) 150 which extends through substrate 102 as illustrated in Fig. 1A.
  • TSVs 150 extend from front side 116 of substrate 102 to a backside 117 of substrate 102.
  • TSVs 150 electrically couple contact pads 152 on backside 117 of substrate 102 to metal layers 118, such as a lower metal layer, of interconnect structure 104. In an embodiment, the TSVs 150 may couple to diffusion regions formed in substrate 102. TSVs 150 enable electrical connections to be made to active and passive devices disposed in or on system die 100 to other components external to system die 100. In an embodiment, when, for example, substrate 102 is fabricated from a low resistance semiconductor, such as a low resistance silicon, it may be necessary to line the TSVs 150 with an insulator 154, such as an oxide, in order to electrically isolate the TSVs.
  • insulator 154 such as an oxide
  • TSVs 150 may be formed by forming a via opening by, for example, drilling, such as laser drilling, or etching and then filling the opening with a conductive material, such as copper or tungsten.
  • backside 117 of substrate 102 may contain one or more redistribution layers in order to route contact pads 152 to TSVs 150 which are not located above the corresponding contact pad 152.
  • one or more backside capacitors may be fabricated in the redistribution layer or layers. In this way, the backside capacitors may be located closer to passive devices disposed or embedded in a package substrate as discussed below.
  • Fig. 1C illustrates a packaged system 190 in accordance with an embodiment of the present disclosure.
  • Packaged system 190 includes a system die, such as system die 100, electrically coupled to a package substrate 160 as illustrated in Fig. 1C.
  • System die 100 may be coupled to package substrate 160 by, for example, a plurality of solder balls or bumps 162.
  • package substrate 160 has a die side 164 and a land side or second level interconnect (SLI) side 166.
  • a plurality of contact pads 168 are disposed on die side 164.
  • solder balls 162 electrically couple contact pads 152 on system die 100 to corresponding contact pads 168 on package substrate 160 as illustrated in Fig. 1C.
  • Land side 166 of package substrate 160 includes a plurality of contact pads or land pads 170.
  • a plurality of second level contacts, such as solder balls or bumps 172 may be disposed on pads 170 to enable package system 190 to be electrically coupled to other components, such as a mother board or main board.
  • contact pads 168 have a tighter pitch and are smaller than the pitch and size of contacts pads 170, as is depicted.
  • Package substrate 160 may be any suitable package substrate.
  • package substrate 160 is an organic multilayer printed circuit board including a dielectric material such as but not limited to silicon filled epoxy, FR4, or polyimide.
  • package substrate is an inorganic package substrate such as a ceramic substrate, such as a low temperature co-fired ceramic substrate or a high temperature co-fired ceramic substrate, a glass substrate (e.g., silicon oxide), or a semiconductor substrate (e.g., silicon).
  • package substrate 160 is a multilayer package substrate which includes a plurality of metallization layers 174 each comprising a plurality of electrical traces 177 or power planes 178. Each metallization layer 174 may be separated from adjacent metal layers 174 by one or more dielectric layers 176. Conductive vias 179 may be disposed in the dielectric layers 176 to enable electrical connections from one metallization layer to another.
  • package substrate 160 includes one or more inductors 180 embedded therein as illustrated in Fig. 1C.
  • Inductor 180 may be a partial loop inductor, a single loop inductor, or a multi loop inductor fabricated in a single level or multiple levels of package substrate 160 as described in more detail with respect to Figs. 7A-7F.
  • inductor 180 may consist of one or more turns of conductive material, such as copper, separated by a dielectric such as a polymer, a ceramic, a glass, or air. In one embodiment, the one or more turns of conductive material are separated by the material of a package substrate.
  • inductor 180 is electrically coupled by an electrical connection to resonator 106 of system die 100 as illustrated in Fig. 1C.
  • package substrate 160 may include one or more capacitors 182 embedded therein.
  • Capacitor 182 may be a parallel plate capacitor or interdigitated capacitor and may be fabricated in a single layer 174 or multiple layers of package substrate 160 as described in more detail with respect to Figs. 6A and 6B.
  • capacitor 182 may be electrically coupled by an electrical connection to resonator 106 of system die 100 and/or to inductor 112 of system die 100.
  • capacitor 182 may be electrically coupled by an electrical connection to inductor 180.
  • inductor 180 may be part of a network of inductors including a transformer equivalent circuit, such as a Pi-network or T-network.
  • packaged system 190 may contain passive devices, acoustic wave resonators and couplings thereto to create a hybrid filter 500 described below.
  • package substrate 160 includes one or more transformers 184 embedded therein.
  • transformer 184 includes a first winding 186 and a second winding 188 wherein the first winding 186 and the second winding 188 are inductively coupled.
  • first winding 186 is vertically above second winding 188 as illustrated in Fig. 1C.
  • first winding 186 and second winding 188 are substantially aligned with one another.
  • first winding 186 has a central axis which is slightly offset from a central axis of second winding 188 in order to control the coupling coefficient of transformer 184.
  • first winding 186 is a planar winding fabricated in a single layer 174 of package substrate 160
  • second winding 188 is a planar winding fabricated in a single different metal layer 174 of package substrate 160.
  • first winding 186 is separated from second winding 188 by a vertical distance of between 15 microns to 60 microns.
  • first winding 186 and second winding 188 may each be fabricated in multiple metal layers 174 of package substrate 160 in order to create high quality factor (high Q) inductors for transformer 184.
  • first winding 186 may be electrically coupled to capacitor 182 embedded within package substrate 160.
  • second winding 188 is electrically coupled to another capacitor 182 embedded in package substrate 160.
  • transformer 184 may be a vertical transformer where first winding 186 and second winding 188 are fabricated in multiple metal layers 174 of package substrate 160. In an embodiment, first winding 186 and second winding 188 may be interleaved with one another. In an embodiment, the vertical transformer has an implementation with angle offset with mutual coupling adjustment.
  • package substrate 160 may include discrete inductors and/or discrete capacitors and/or integrated passive devices (IPD) and/or baluns attached to the die side 164 of package substrate 160 (not shown).
  • IPD integrated passive devices
  • package substrate 160 may include one or more antennas (not shown).
  • Fig. 2A illustrates a system die 200 in accordance with an embodiment of the present disclosure.
  • System die 200 is similar to system die 100 except cap 108 is replaced with a cap 210.
  • Cap 210 is disposed over resonator 106 as well as over inductor 112.
  • cap 210 is also disposed over capacitor 114.
  • Cap 210 may be attached by a seal frame 214 to create a hermetically sealed cavity 216.
  • resonator 106 and inductor 112 are located within cavity 216.
  • capacitor 114 is also located beneath cap 210. In this way, the resonator 106 and associated passive components are all enclosed in a single hermetically sealed cavity 216 as illustrated in Fig. 2A.
  • resonator 106 is situated inside the coil of inductor 112 and has one electrode coupled to one end of inductor 112 and a second electrode coupled to a second end of inductor 112 to form a very tightly coupled hybrid filter in the smallest form factor and thereby realize a highly efficient filter bank.
  • cap 210 may include a metal plate or metal shield 212 disposed on the side of the cap nearest interconnect structure 104, as illustrated in Fig. 2A.
  • metal plate 212 may be electrically coupled to interconnect structure 104 by a metal seal frame 214.
  • metal plate 212 is coupled to ground to provide an EMI shield.
  • Fig. 2B is an illustration of a system die 250 in accordance with an embodiment of the present disclosure.
  • System die 250 is similar to system die 200, except that cap 210 and may be replaced with cap 260.
  • cap 260 is disposed over resonator 106 and inductor 112 and, in embodiments, over capacitor 114.
  • Cap 260 has a metal plate or shield 262 located on a side of cap 260 distal from the interconnect structure 104 and inductor 112 as illustrated in Fig. 2B.
  • a plurality of through cap vias 264 may be formed in cap 260 to allow electrical coupling of shield 262 to interconnect structure 104 by a metal seal frame 214.
  • the through cap vias 264 may be individual discrete vias or continuous trench vias.
  • metal plate or shield 262 is coupled to ground to provide an EMI shield.
  • Through cap vias 264 may be formed by forming a plurality of via openings through cap 260 by, for example, drilling, such as laser drilling, or etching, and then filling the opening with a conductive material, such as copper.
  • a plurality of contact pads 266 may be formed on the side of cap 260 closest to interconnect structure 104 to provide for attachment and electrical coupling between metal seal frame 214 and through cap vias 264 as illustrated in Fig. 2B.
  • the contact pads 266 may be discrete or continuous.
  • Fig. 2C is an illustration of a packaged system 270 wherein a system die, such as system die 200 or 250, is attached to a package substrate, such as package substrate 160.
  • Fig. 3A illustrates a system die 300 in accordance with an embodiment of the present disclosure.
  • System die 300 is similar to system die 100 except cap 108 is replaced with a cap 310.
  • Cap 310 is disposed over resonator 106 as well as over inductor 112 as well as over device active area 110.
  • cap 310 is also disposed over capacitor 114.
  • Cap 310 may be attached by a seal frame 314 to create a hermetically sealed cavity 316.
  • Sealed cavity 316 may be a single continuous cavity or may be a partitioned cavity, creating three or more hermetically isolated cavities with one cavity over inductor 112, a second cavity over resonator 106, and a third cavity over active device area 110.
  • the three hermetically isolated cavities may be associated with a corresponding metal seal ring or frame, where the metal seal rings or frames may be separate and distinct from one another or in other
  • resonator 106 and inductor 112 and active device area 110 are located within cavity 316.
  • capacitor 114 is also located beneath cap 310. In this way, the resonator 106 and associated passive components as well as front end active circuits are all enclosed in a single hermetically sealed cavity 316 as illustrated in Fig. 3A.
  • resonator 106 is situated inside the coil of inductor 112 and has one electrode coupled to one end of inductor 112 and a second electrode coupled to a second end of inductor 112 to form a very tightly coupled hybrid filter in the smallest form factor and thereby realize a highly efficient filter bank.
  • active circuits of active device area 110 are coupled to resonator 106 to create a hermetically sealed RF front end module integrated on a single die.
  • cap 310 may include a metal plate or metal shield 312 disposed on the side of the cap nearest interconnect structure 104, as illustrated in Fig. 3 A.
  • metal plate 312 may be electrically coupled to interconnect structure 104 by a metal seal frame 314.
  • metal plate 312 is coupled to ground to provide an EMI shield.
  • Fig. 3B is an illustration of a system die 350 in accordance with an embodiment of the present disclosure.
  • System die 350 is similar to system die 300, except that cap 310 and may be replaced with cap 360.
  • cap 360 is disposed over resonator 106 and inductor 112 and active device area 110 and, in embodiments, over capacitor 114.
  • Cap 360 has a metal plate or shield 362 located on a side of cap 360 distal from the interconnect structure 104 and inductor 112 and active device area 110 as illustrated in Fig. 3B.
  • a plurality of through cap vias 364 may be formed in cap 360 to allow electrical coupling of shield 362 to interconnect structure 104 by a metal seal frame 314.
  • the cap vias 364 may be individual discrete vias or continuous trench vias.
  • metal plate or shield 362 is coupled to ground to provide an EMI shield.
  • Through cap vias 364 may be formed by forming a plurality of via openings through cap 360 by, for example, drilling, such as laser drilling, or etching, and then filling the opening with a conductive material, such as copper.
  • a plurality of contact pads 366 may be formed on the side of cap 360 closest to interconnect structure 104 to provide for attachment and electrical coupling between metal seal frame 314 and through cap vias 364 as illustrated in Fig. 3B.
  • the contact pads 366 may be discrete or continuous.
  • Fig. 3C is an illustration of a packaged system 370 wherein a system die 355, which may be similar to system die 300 or 350 except that resonator 106 is isolated from inductor 112, is attached to a package substrate, such as package substrate 160.
  • the packaged system 370 provides hermetic and EMI shielding of the passive structures, such as inductor 112 and capacitor 114, resonator 106, and RF front end active device area 110 in one faraday cage using cap 360.
  • Passive devices embedded in package substrate 160 such as capacitor 182, inductor 180 and transformer 184 may also be included in the faraday cage.
  • the faraday cage is created by the ground plane 178, stacked vias 190, TSVs 150, seal ring 314, through cap vias 364, solder ball or interconnect bump 162 and shield plate 362. In an embodiment, the faraday cage is coupled to ground.
  • Fig. 3D is an illustration of a packaged system 390 wherein a system die, such as system die 300 or 350, is attached to a package substrate, such as package substrate 160.
  • the packaged system 390 provides hermetic and EMI shielding of the passive structures, such as inductor 112 and capacitor 114, resonator 106, and RF front end active device area 110 in one faraday cage using cap 360.
  • Passive devices embedded in package substrate 160 such as capacitor 182, inductor 180 and transformer 184 may also be included in the faraday cage.
  • the faraday cage is created by the ground plane 178, stacked vias 190, TSVs 150, seal ring 314, through cap vias 364, solder balls or interconnect bumps 162 and shield plate 362.
  • the faraday cage is coupled to ground.
  • Fig. 4 is a schematic illustration of an RF front end system or module 400.
  • RF module 400 includes passive devices 410 and active devices 420.
  • Passive devices 410 may include an acoustic wave resonator 430 and an inductor 440 coupled together in parallel.
  • the active devices 420 may include transistors 450, amplifiers 460 and switches 480.
  • passive devices 410 may be coupled together to form a hybrid filter or bank of hybrid filters.
  • the hybrid filter is a hybrid filter such as described below in association with Fig. 5.
  • the passive devices 410 and active devices 420 are integrated together on a single system die, such as a system die described above.
  • the passive devices 410 and active devices 420 are integrated together in a packaged system including a system die coupled to a package substrate, as described above.
  • Embodiments of the present disclosure relate to hybrid filters and more particularly to filters having acoustic wave resonators (AWRs) and transformers and packages therefor.
  • AWRs acoustic wave resonators
  • Embodiments of the present disclosure relate to a radio frequency (RF) hybrid filter having a plurality of acoustic wave resonators (AWR) and a transformer based resonator.
  • the basic principle of the embodiments of the present disclosure consist of utilizing at least one RF transformer as the core of an LC resonator and one or more acoustic wave resonators to improve the out of band rejection of the resulting hybrid filter.
  • the use of a transformer reduces the number of components in the filter. Additionally, the broadband nature of a transformer results in low parasitics and therefore enables filters operating at high frequencies.
  • the filter can be further implemented by using an equivalent circuit of a transformer, such as a T-network or a Pi- network.
  • the hybrid circuit includes multiple parallel acoustic wave resonators to enhance the signal rejection in the guard band and at the band edge.
  • the hybrid filter of the present disclosure may exhibit wide band width and sharp roll off.
  • the hybrid filter of the present disclosure may be used in next generation mobile and wireless communication devices and infrastructures which require the handling of data at high rates, such as 5G networks.
  • the filters of the present disclosure may exhibit excellent roll off and out of band rejection to enable multi-radio coexistence.
  • the hybrid filter is a hybrid LC/AWR (lumped component/acoustic wave resonator) filter comprising RF passive elements, such as inductors, transformers and capacitors, and acoustic wave resonators fabricated using a piezoelectric material, such as a thin film bulk acoustic resonator (FBAR to TFBAR).
  • a first winding of a transformer may be coupled to a first port and to a first acoustic wave resonator and a second acoustic wave resonator may be coupled to a second winding of the transformer and to a second port.
  • a first capacitor may be coupled in parallel with the first winding of the inductor and a second capacitor may be coupled in parallel with a second winding of the transformer.
  • a lumped element resonator comprising an inductor coupled in parallel with a capacitor may be disposed between the coupling of the first acoustic wave resonator and the first winding of the transformer.
  • Fig. 5 is a schematic illustration of an RF hybrid circuit or filter 500 in accordance with an embodiment of the present disclosure.
  • Hybrid filter 500 includes a first acoustic wave resonator (AWR) 510, a lumped component resonator 524, a transformer (XFMR) 512 and a second acoustic wave resonator (AWR) 514.
  • first AWR 510 has a first electrode coupled to a first port or an input port 502 and has a second electrode coupled to ground.
  • an inductor 520 has a first terminal coupled to the first electrode of AWR 510 and to the input port 502 and a second terminal coupled to a first node 530.
  • a capacitor 522 is coupled in parallel with inductor 520.
  • the capacitor 522 and the inductor 520 create a lump element resonator 524 which forms a transmission zero either below or above the pass band region.
  • a first coil or winding 534 of transformer 512 has a first terminal coupled to node 530 and a second terminal couple to ground.
  • a second coil or winding 536 of transformer 512 has a first terminal coupled to a node 540 and a second terminal coupled to ground as illustrated in Fig. 5.
  • a capacitor 550 has a first electrode or plate coupled to node 530 and in an embodiment a second electrode or plate coupled to ground. In an embodiment the second electrode of capacitor 550 is directly connected to the second terminal of first winding 534 of transformer 512.
  • a capacitor 560 has a first electrode or plate coupled to node 540 and in an embodiment has a second electrode or plate coupled to ground.
  • the second electrode of capacitor 560 is directly connected to the second terminal of the second winding 536 of transformer 512.
  • each of the second terminals of capacitor 550 and capacitor 560 are illustrated as being coupled to ground, they may each be, in an embodiment, connected to a same or different DC voltage in order to provide tuning capabilities.
  • the poles of the filter are defined by capacitors 550 and 560 and transformer 512.
  • filter 500 has two poles and therefore may be considered a second order filter. In another embodiment filter 500 has more than two poles and be considered a higher order filter.
  • Second AWR 514 has a first electrode coupled to node 540 and a second electrode coupled to a second port or output port 504.
  • hybrid filter 500 of Fig. 5 includes two acoustic wave resonators, AWR 510 and AWR 514.
  • the acoustic wave resonators act as a transmission zero around the edge of the passband and therefore enable filter 500 to achieve strong rejection in the adjacent guard band.
  • filter 500 may include one or more matching inductors.
  • filter 500 includes an inductor 570 having a first terminal coupled to input port 502 and a second terminal coupled to ground.
  • filter 500 may include an inductor 580 disposed between second AWR 514 and node 540.
  • inductor 580 has a first terminal coupled to node 540 and a second terminal to the first electrode of AWR 514, as illustrated in Fig. 5.
  • inductor 570 and inductor 580 are matching inductors and act as transmission zeroes (responsible for signal attenuation) at low and high frequencies, respectively.
  • filter 500 may include a capacitor 590 having a first electrode or plate coupled to node 530 and a second electrode or plate coupled to node 540, as illustrated in Fig. 5.
  • Capacitor 590 may form another transmission zero with transformer 512.
  • individual ones of the inductors 520, 570, and 580 may be implemented as a series combination of two or more smaller inductors to improve the frequency range of operation, the in-band and out of band performance at a cost of inductance density and/or quality factor.
  • individual ones of the capacitors 522, 550, 560 and 590 may be implemented as a parallel combination of two or more smaller capacitors.
  • the inductors may have an inductance in the range of 0.1 to 15 nanoHenrys (nH).
  • the capacitors may have a capacitance in the range of 0.1 to 15 picofarads (pF).
  • First winding 534 and second winding 536 of transformer 512 may be inductively coupled together. That is, first winding 534 and second winding 536 may be sufficiently close together to provide mutual inductive coupling. In an embodiment, first winding 534 and second winding 536 have a low inductive mutual coupling coefficient of between 0.01 to 0.5. In an embodiment, first winding 534 and second winding 536 are sufficiently sized to create an inductance ratio between 1 :2-2: 1. In an embodiment first winding 534 and second winding 536 have an inductance ratio of approximately 1: 1. First winding 534 may be considered the primary coil of transformer (XFMR) 512 and second winding 536 may be considered the secondary winding of transformer 512.
  • XFMR primary coil of transformer
  • second winding 536 may be considered the secondary winding of transformer 512.
  • hybrid filter 500 is an RF band pass filter. Filter 500 may reject signals at both low and high frequencies. The signal transmission between input port 502 and output port 504 is maximum in the desired passband region.
  • an RF analog input signal having a frequency between 800 MHz to 8 GHz is applied to input port 502.
  • an analog signal between 3.3 to 4.2 GHz is provided to input port 502.
  • an input signal between 4.4 to 4.9 GHz is provided to input port 502.
  • the input signal passes through filter 500 and a filtered analog output signal is provided on output port 504.
  • transformer 512 may be replaced with a transformer equivalent circuit such as a T-network of inductors or a Pi-network of inductors.
  • Fig. 6A and Fig. 6B illustrate various capacitors which may be integrated or embedded into a package substrate, in accordance with embodiments of the present disclosure.
  • capacitors are thin film resonators consisting of metal electrodes and a loss tangent dielectric material between the electrodes. The quality of the capacitors increases with decreasing loss tangent.
  • the capacitor dielectric material may have a high dielectric constant to reduce the footprint of the capacitor.
  • Fig. 6A is a cross sectional illustration of a multilayer package substrate 600, such as a multilayer organic package substrate or a low temperature co- fired substrate.
  • Substrate 600 includes a first side 602 and a second side 604 opposite the first side 602.
  • a plurality of contact pads 606 may be disposed on first side 602 and a plurality of contact pads 608 may be disposed on second side 604.
  • Multilayer substrate 600 includes a plurality of metal layers 610, such as copper layers. Each of the metal layers 610 includes a plurality of metal traces or conductors 612.
  • a plurality of dielectric layers 620 such as silicon dioxide or silicon oxide layers, silicon filled epoxy, FR4, or polyimide, are disposed between metal layers 610 to electrically isolate the metal layers 610 from one another. Dielectric layers 620 may also be disposed between traces 612 of metal layers 610.
  • a plurality of conductive vias 622 such as copper vias, may be disposed in dielectric layers 620 to enable electrical connections between adjacent metal layers 610.
  • package substrate 600 may include a parallel plate capacitor 630 which includes a first electrode or plate 632 formed in one metal layer 610 and a second electrode or plate 634 formed in a second vertically adjacent metal layer 610.
  • a parallel plate capacitor 630 which includes a first electrode or plate 632 formed in one metal layer 610 and a second electrode or plate 634 formed in a second vertically adjacent metal layer 610.
  • a portion of the dielectric layers 620 between first electrode or plate 632 and second electrode or plate 634 forms the capacitor dielectric layer of capacitor 630.
  • package substrate 600 may include one or more parallel plate capacitors 640 which includes a first electrode or plate 642 formed in one metal layer 610 and a second electrode or plate 644 disposed in a second vertically adjacent metal layer 610.
  • Capacitor 640 may include a capacitor dielectric 646 formed of a dielectric material which is different than the dielectric material 620 used to isolate the metal layers 610 of package substrate 600.
  • dielectric 646 is a high dielectric constant material, such as a metal oxide dielectric material, e.g., aluminum oxide, zirconium oxide, hafnium oxide, barium strontium titanate (BST) or lead zirconium titanate (PZT).
  • dielectric 646 is a low loss tangent dielectric material. In this way, a high performance capacitor may be fabricated.
  • package substrate 600 may include one or more parallel plate capacitors 650.
  • Capacitor 650 includes a first electrode or plate 652, a second electrode or plate 654 and an intervening capacitor dielectric 656 disposed there between.
  • capacitor 650 is disposed in a single metal layer 610 of substrate 600 as illustrated in Fig. 6A.
  • capacitor dielectric 656 may be formed from a dielectric material having a high dielectric constant, such as a high k dielectric and which is different than the dielectric material 620 used to form package substrate 600.
  • dielectric 656 is a high dielectric constant material, such as a metal oxide dielectric material, e.g., aluminum oxide, zirconium oxide, hafnium oxide, BST or PZT. In an embodiment, dielectric 656 is a low loss tangent dielectric material. In this way, a high performance capacitor may be fabricated.
  • a metal oxide dielectric material e.g., aluminum oxide, zirconium oxide, hafnium oxide, BST or PZT.
  • dielectric 656 is a low loss tangent dielectric material. In this way, a high performance capacitor may be fabricated.
  • package substrate 600 may include one or more capacitors 660 as illustrated in Fig. 6A.
  • Capacitor 660 includes a top electrode 662 and a bottom electrode 664.
  • Top electrode 662 includes a via portion 666.
  • Via portion 666 is separated from bottom electrode 664 by a capacitor dielectric 668.
  • Capacitor dielectric 668 may be deposited in a via opening prior to filling the via with a conductive material, such as copper.
  • capacitor dielectric 668 is a high k dielectric layer, such as a metal oxide, such as hafnium oxide or aluminum oxide.
  • capacitor dielectric 668 is a low loss dielectric material.
  • capacitor dielectric 668 is a different dielectric material than dielectric material 620.
  • capacitor dielectric 668 is a high dielectric constant material, such as a metal oxide dielectric material, e.g., aluminum oxide, zirconium oxide, hafnium oxide, BST or PZT. In an embodiment, capacitor dielectric 668 is a low loss tangent dielectric material. In this way, a high performance capacitor may be fabricated.
  • a metal oxide dielectric material e.g., aluminum oxide, zirconium oxide, hafnium oxide, BST or PZT.
  • capacitor dielectric 668 is a low loss tangent dielectric material. In this way, a high performance capacitor may be fabricated.
  • Fig. 6B illustrates a plan view of a capacitor 670 which may be embedded in package substrate 600 in accordance with embodiments of the present disclosure.
  • Capacitor 670 includes a first electrode 672 and a second electrode 674.
  • First electrode 672 includes a plurality of fingers 675 extending from a back bone 676 which are interleaved or interdigitated with a plurality of fingers 677 extending from a back bone 678 of second electrode 674 as illustrated in Fig. 6B.
  • first electrode 672 and second electrode 674 are disposed in a same metal layer 610 or plane of package substrate 600.
  • Dielectric layer 620 disposed between the back bone and fingers of the electrodes may act as a capacitor dielectric.
  • dielectric material 620 disposed between the electrodes may be replaced with a different dielectric material, such as a high k dielectric material and/or a low loss tangent dielectric material, if desired.
  • Figs. 7A-7F illustrate various inductors which may be embedded into a package substrate in accordance with embodiments of the present disclosure.
  • Fig. 7A is a cross-sectional illustration of package substrate 600 which in an embodiment may include one or more inductors formed from one or more metal layers 610 of package substrate 600.
  • package substrate 600 may include one or more inductors 710.
  • inductor 710 has a loop disposed in a single metal layer 610 of package substrate 600.
  • Inductor 710 may have a partial or fractional loop, as illustrated in Fig. 7B, a full loop, as illustrated in Fig. 7C, or multiple loops, such as two or more loops as illustrated in Fig. 7D.
  • package substrate 600 may include one or more inductors 720.
  • Inductor 720 may include one or more loops including a first metal portion 722 disposed in a first metal layer 610 of package substrate 600 and a second metal portion 724 disposed in a second metal layer 610 vertically adjacent to the first metal layer 610.
  • the first metal portion 722 is electrically coupled to the second metal portion 724 by a plurality of metal vias 726, as illustrated in Fig. 7A.
  • an inductor 720 may have a loop with a metal thickness greater than the metal thickness of a single metal layer 610 of package substrate 600 and thereby yield a high Q inductor.
  • an inductor having a Q factor of 100 or better at the frequency of operation may be achieved.
  • Fig. 7E is a plan view of inductor 720 showing a top portion 722 of a loop and the underlying vias 726 electrically connected thereto.
  • Dielectric material 620 may be disposed between conductive vias 726 and between the first metal portion 722 and a second metal portion 724.
  • inductor 720 may include a third metal portion disposed in a third metal layer 610 and be electrically connected to second metal portion 724 by a second plurality of conductive vias.
  • the plurality of conductive vias 726 and 622 may be formed by laser drilling a plurality of via openings in the dielectric layer 610 and then filling the vias with a conductive material, such as copper, when forming the metal layer 610 above. Laser drilling provides a cost effective method of creating vias 726 and 622.
  • package substrate 600 may include one or more inductors 730 as illustrated in Fig. 7A.
  • Inductor 730 includes a first metal portion 732 disposed in a first metal layer 610 and a second metal portion 734 disposed in a second metal layer 610 vertically adjacent to the first metal layer 610.
  • a slot via or trench via 736 may be used to connect first metal portion 732 with second metal portion 734.
  • Trench via 734 may have a length
  • trench via 736 has a width which is less than the width of metal portions 732 and 734.
  • Trench vias 736 may be formed by lithographically patterning a trench opening in dielectric layer 620 by, for example,
  • dielectric layer 620 may be a photo definable dielectric and may be directly photo defined to form a trench opening therein. The trench opening may be subsequently filled when forming metal layer 610 which includes metal portion 732.
  • Inductor 730 may be able to exhibit a higher Q factor than inductor 722 because inductor 730 has a trench via which substantially or completely connects the metal portion 732 with the metal portion 734 while inductor 720 is coupled by vias and has dielectric 620 between metal portions 722 and 724, as illustrated in Fig. 7E.
  • inductors such as inductors 710, 720 and 730 may be stand alone inductors or may be combined with other inductors to fabricate windings of a transformer or a transformer-equivalent circuit.
  • Fig. 8 is a schematic block diagram illustrating a computer system that utilizes a system die or a packaged system, or a combination thereof, as described herein, in accordance with an embodiment of the present disclosure.
  • Fig. 8 illustrates an example of a computing device 800.
  • Computing device 800 houses motherboard 802.
  • Motherboard 802 may include a number of components, including but not limited to processor 804, device package 810, and at least one communication chip 806.
  • Processor 804 is physically and electrically coupled to motherboard 802.
  • at least one communication chip 806 is also physically and electrically coupled to motherboard 802.
  • at least one communication chip 806 is part of processor 804.
  • computing device 800 may include other components that may or may not be physically and electrically coupled to motherboard 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display
  • At least one communication chip 806 enables wireless communications for the transfer of data to and from computing device 800.
  • the term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • At least one communication chip 806 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • Computing device 800 may include a plurality of communication chips 806. For instance, a first communication chip 806 may be dedicated to shorter range wireless
  • Wi-Fi and Bluetooth and a second communication chip 806 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • Processor 804 of computing device 800 includes an integrated circuit die packaged within processor 804.
  • Device package 810 may be, but is not limited to, a packaging substrate and/or a printed circuit board. Note that device package 810 may be a single component, a subset of components, and/or an entire system.
  • the integrated circuit die may be packaged with one or more devices on device package 810 that include a thermally stable RFIC and antenna for use with wireless communications.
  • the term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • At least one communication chip 806 also includes an integrated circuit die packaged within the communication chip 806.
  • the integrated circuit die of the communication chip may be packaged with one or more devices on the device package 810, as described herein.
  • a system die includes a semiconductor substrate having a first side and a second side opposite the first side.
  • An interconnect structure is on the first side of the semiconductor substrate, the interconnect structure comprising a plurality of metal layers and a plurality of dielectric layers.
  • An acoustic wave resonator is in the interconnect structure.
  • An inductor in the interconnect structure.
  • An active device area is in the first side of the semiconductor substrate.
  • a cap is attached to the interconnect structure by a seal frame, the cap over the acoustic wave resonator and hermetically sealing the acoustic wave resonator.
  • Example embodiment 2 The system die of example embodiment 1 wherein the cap is disposed over the inductor.
  • Example embodiment 3 The system die of example embodiment 1 or 2 wherein the cap is disposed over the active device area.
  • Example embodiment 4 The system die of example embodiment 1, 2 or 3 wherein the seal frame is a metal seal frame.
  • Example embodiment 5 The system die of example embodiment 1, 2, 3 or 4 wherein the cap comprises a material selected from the group consisting of glass, quartz, ceramic, epoxy and silicon.
  • Example embodiment 6 The system die of example embodiment 1, 2, 3, 4 or 5 wherein the cap further comprising an electromagnetic interference (EMI) shield.
  • EMI electromagnetic interference
  • Example embodiment 7 The system die of example embodiment 6 wherein the EMI shield is on a side of the cap nearest the interconnect structure.
  • Example embodiment 8 The system die of example embodiment 6 wherein the EMI shield is on a side of the cap distal from the interconnect structure and the cap further comprises a through cap via extending from a side nearest the interconnect structure to the EMI shield.
  • Example embodiment 9 The system die of example embodiment 8 wherein the seal frame is a metal seal frame and wherein the through cap via is electrically coupled to the metal seal frame.
  • Example embodiment 10 The system die of example embodiment 1, 2, 3, 4, 5, 6, 7, 8 or 9 wherein the inductor surrounds the acoustic wave resonator.
  • Example embodiment 11 The system die of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10 wherein the inductor is disposed in at least two metal layers of the plurality of metal layers of the interconnect structure.
  • Example embodiment 12 The system die of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10 wherein the inductor is in a single metal layer of the plurality of metal layers of the interconnect structure.
  • Example embodiment 13 The system die of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12 further comprising a transistor formed in the active device area of the
  • Example embodiment 14 The system die of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 or 13 further comprising at least one of a switch or an amplifier.
  • Example embodiment 15 The system die of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14 wherein the semiconductor substrate is selected from the group consisting of a silicon substrate, a group III-V substrate, and a silicon-on-insulator substrate.
  • Example embodiment 16 The system die of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 or 15 further comprising a plurality of through substrate vias (TSVs) extending from the first side of the substrate to the second side of the substrate.
  • TSVs through substrate vias
  • Example embodiment 17 The system die of example embodiment 16 further comprising a plurality of bumps on a second side of the semiconductor substrate, the plurality of through substrate vias (TSVs) coupling the plurality of bumps to the interconnect structure.
  • Example embodiment 18 The system die of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 or 17 wherein the acoustic wave resonator is selected from the group consisting of a BAW, a FBAR, a SMR, a CMR, a CLMR, and a SAW device.
  • Example embodiment 19 The system die of example embodiment 18 wherein the acoustic wave resonator comprises: a first electrode; and a piezoelectric layer having a first side disposed on the first electrode; and a second electrode disposed on a second side of the piezoelectric layer wherein the second side is opposite the first side.
  • Example embodiment 20 The system die of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 or 19 further comprising a cavity in the interconnect structure beneath the acoustic wave resonator.
  • a system die includes a semiconductor substrate having a first side and a second side opposite the first side.
  • An interconnect structure is on the first side of the semiconductor substrate, the interconnect structure comprising a plurality of metal layers and a plurality of dielectric layers.
  • An acoustic wave resonator is in the interconnect structure.
  • An inductor is in the interconnect structure.
  • An active device area is in the first side of the semiconductor substrate.
  • a second metal seal frame surrounds the inductor.
  • a third metal seal frame surrounds the active device area.
  • a cap is attached to the first metal seal frame, the second metal seal frame and the third metal seal frame wherein the cap further comprises a metal plate.
  • Example embodiment 22 The system die of example embodiment 21 wherein the metal plate is disposed on a side of the cap nearest the interconnect structure, and wherein the metal plate is attached to the first metal seal frame, the second metal seal frame, and the third metal seal frame.
  • Example embodiment 23 The system die of example embodiment 21 wherein the metal plate is disposed on a side of the cap distal from the interconnect structure, wherein a first through cap via couples the first metal seal frame to the metal plate, wherein a second through cap via couples the second metal seal frame to the metal plate and wherein a third through cap via couples the third metal seal frame to the metal plate.
  • Example embodiment 24 A packaged system includes a semiconductor substrate having a first side and a second side opposite the first side.
  • An interconnect structure is on the first side of the semiconductor substrate, the interconnect structure comprising a plurality of metal layers and a plurality of dielectric layers.
  • An acoustic wave resonator is in the interconnect structure.
  • An inductor is in the interconnect structure; an active device area in the first side of the semiconductor substrate.
  • a cap is attached to the interconnect structure by a seal frame, the cap over the acoustic wave resonator and hermetically sealing the acoustic wave resonator.
  • a package substrate has a first side coupled to the semiconductor substrate by a plurality of bumps.
  • Example embodiment 25 The packaged system of example embodiment 24 further comprising a plurality of solder balls on a second side of the package substrate, the second side opposite the first side.
  • Example embodiment 26 The packaged system of example embodiment 24 or 25 wherein the package substrate is a substrate selected from the group consisting of a multilayer organic package substrate and inorganic package substrate.
  • Example embodiment 27 The packaged system of example embodiment 24, 25 or 26 further comprising a high Q inductor embedded in the package substrate.
  • Example embodiment 28 The packaged system of example embodiment 24, 25, 26 or 27 further comprising a plurality of capacitors embedded in the package substrate.
  • Example embodiment 29 The packaged system of example embodiment 24, 25, 26, 27 or 28 further comprising a transformer embedded in the package substrate.
  • Example embodiment 30 The packaged system of example embodiment 24, 25, 26, 27, 28 or 29 further comprising a plurality of through substrate vias in the semiconductor substrate, the through substrate vias electrically coupling the plurality of bumps to the interconnect structure.

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  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

L'invention concerne des systèmes frontaux RF, et plus particulièrement un système frontal RF doté d'un résonateur à ondes acoustiques (AWR) intégré et hermétiquement scellé. Dans un exemple, une puce système comprend un substrat semi-conducteur ayant un premier côté et un second côté en regard du premier côté. Une structure d'interconnexion est sur le premier côté du substrat semi-conducteur, la structure d'interconnexion comprenant une pluralité de couches métalliques et une pluralité de couches diélectriques. Un résonateur à ondes acoustiques se situe dans la structure d'interconnexion. Une bobine d'induction se situe dans la structure d'interconnexion. Une zone de dispositif actif se trouve dans le premier côté du substrat semi-conducteur. Un capuchon est fixé à la structure d'interconnexion par un cadre d'étanchéité, le capuchon étant disposé sur le résonateur à ondes acoustiques et scellant hermétiquement le résonateur à ondes acoustiques.
PCT/US2017/068752 2017-12-28 2017-12-28 Système frontal rf doté d'un résonateur à ondes acoustiques co-intégré WO2019132925A1 (fr)

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US20220094337A1 (en) * 2018-12-26 2022-03-24 Ningbo Semiconductor International Corporation (Shanghai Branch) Integration Method and Integration Structure for Control Circuit and Acoustic Wave Filter
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