WO2019132882A1

WO2019132882A1 - Functional vias in backend for reconfigurable interconnect

Info

Publication number: WO2019132882A1
Application number: PCT/US2017/068546
Authority: WO
Inventors: Elijah V. KARPOV; Christopher J. Jezewski; Prashant Majhi; Ravi Pillarisetty; Fatih Hamzaoglu
Original assignee: Intel Corporation
Priority date: 2017-12-27
Filing date: 2017-12-27
Publication date: 2019-07-04

Abstract

Techniques for providing a low RC reconfigurable interconnect structure, which operates as a programmable connection for routing signals between metal lines in a semiconductor backend interconnect layer, so as to not consume device layer area. A reconfigurable interconnect structure may comprise two types of vias, which may be utilized in the same interconnect layer to enable reconfigurable routing. A reconfigurable interconnect structure may further comprise a first type of via, which may be a standard via. The reconfigurable routing structure may further comprise a second type of via herein referred to as a "programmable via" that may be programmed by the standard via so as to provide reconfigurable routing.

Description

FUNCTIONAL VIAS IN BACKEND FOR RECONFIGURABLE

INTERCONNECT

Inventors:

Elijah V. Karpov

Christopher J. Jezewski

Prashant Majhi

Ravi Pillarisetty

Fatih Hamzaoglu

BACKGROUND

[0001] Current semiconductor signal routing techniques generally utilize metal oxide semiconductor field effect transistors (MOSFETs) in the silicon device layer or so-called front- end, whereby the MOSFETs operate as silicon based switches. In some cases, an array of such switches is used such as the case with a field programmable gate array (FPGA), although other device layer configurations can be used. Signals that are switched or routed at the device layer are then passed to the overlying interconnect layers or so-called backend, for further routing. There are a number of non-trivial issues associated with such routing techniques.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] FIG. 1 shows a standard signal interconnect mechanism.

[0003] FIG. 2a shows a combination of reconfigurable interconnect structures arranged so that an associated path with respect to each respective structure may be enabled or disabled independently, according to one embodiment of the present disclosure.

[0004] FIG. 2b is a block diagram of a reconfigurable interconnect structure according to another embodiment of the present disclosure. [0005] FIG. 2c is a block diagram of a reconfigurable interconnect structure according to another embodiment of the present disclosure.

[0006] FIG. 3 shows an example structure of an interconnect switching structure according to one embodiment of the present invention.

[0007] FIG. 4a depicts a programming of a reconfigurable interconnect structure into a conducting state, according to one embodiment of the present disclosure.

[0008] FIG. 4b depicts a programming of a reconfigurable interconnect structure into a non conducting state, according to one embodiment of the present disclosure.

[0009] FIG. 5 depicts an operation of an interconnect structure according to one embodiment of the present disclosure.

[0010] FIG. 6a depicts a fabrication process for generating a reconfigurable interconnect structure utilizing a mask deposition technique, according to one embodiment of the present disclosure.

[0011] FIG. 6b depicts a fabrication process for generating a reconfigurable interconnect structure utilizing a masked etch technique, according to one embodiment of the present disclosure.

[0012] FIG. 7 shows a specific example embodiment wherein a reconfigurable interconnect structure is utilized according to one embodiment of the present disclosure.

[0013] FIG. 8 illustrates a computing system implemented with integrated circuit structures that employs the routing techniques disclosed herein, in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] As previously explained, there are a number of non-trivial issues associated with standard routing techniques. For example, standard routing techniques generally employ a device layer based switching approach, which is disadvantageous because it consumes significant area in silicon. In addition, as the number of interconnect layers above the device layer increases, the performance of MOS-based switches decreases due to large RC time constants introduced because of the significant traversal path for signals. In particular, a significant delay is introduced because the signal being routed must travel all the way down through the interconnect structure to the silicon based switches at the device layer, and then back up through the interconnect structure for each routing configuration in use. The significant traversal path invokes an associated increased resistance and capacitance, leading to signal propagation delays due to the increased RC time constant. Thus, there exists a need for reconfigurable interconnect that involves relatively low RC, allowing for fast and flexible switching and routing.

[0015] To this end, the present disclosure relates to techniques for providing a low RC reconfigurable interconnect structure that does not consume front-end area, whether it be silicon or other semiconductor(s). According to one embodiment of the present disclosure, a reconfigurable interconnect structure is introduced that operates as a programmable connection for routing signals between metal lines. The reconfigurable interconnect structure can be provided, for example, in a semiconductor backend process where one or more interconnect layers are formed. Because the reconfigurable interconnect structure is fabricated in the backend, it does not consume any device layer area. Further, it invokes smaller RC associated costs because the signals are not routed all the way down to the device layer. [0016] According to one embodiment of the present disclosure, a reconfigurable interconnect structure may comprise two types of vias, which may be utilized in the same interconnect layer to enable reconfigurable routing. In one such example case, a reconfigurable interconnect structure includes a first type of via, which may be a standard via and is referred to herein as a “programming via” as it is utilized to establish the reconfigurable interconnect structure in either a conducting state or a non-conducting state thereby enabling or disabling a conduction path. The reconfigurable routing structure further includes a second type of via herein referred to as a“programmable via” that may be programmed by the programming via so as to provide reconfigurable routing. The programmable vias may employ a dielectric layer or other non- metal layer that may be selectively induced to enter a persistent conducting state or a non conducting state through the application of a respective positive or negative bias. Because the reconfigurable interconnect structure resides in a given interconnect layer, the requirement of routing signals all the way down to the device layer is obviated and a low RC signal routing system may be realized.

[0017] According to some embodiments of the present disclosure, a standard via is modified so as operate in a“closed” or“open” configuration, thereby becoming a programmable via. Employment of such a reconfigurable interconnect structure allows for the“in” and“out” interconnect paths (relative to the device layer) to be connected or disconnected (i.e., routed) in an interconnect layer instead of in the device layer, thereby reducing delay due to the routing of signals all the way down into the device layer as well as conserving device layer area and process complexity.

[0018] FIG. 1 shows a standard signal interconnect mechanism. As shown in FIG. 1, NMOS FET (“Field Effect Transistor”) may comprise p substrate, source and drain regions (n+) and gate, source and drain contacts (gate, source, drain). A signal path 208 may be enabled or disabled (i.e., rendered conductive or non-conductive) by activating FET 102 by applying by applying a bias voltage to gate, thereby inducing a channel in p substrate establishing a conductive path between source and drain contacts. Standard vias 104(a)- 104(b) may be respectively coupled to source and drain contacts. The combination of standard vias 104(a)- 104(b) and switchable FET of the device layer provide a standard routing structure through which path 208 may be enabled or disabled. Further, an assemblage of such structures may be used to provide an arbitrarily complex routing structure. However, as shown in FIG. 1, using such structures, signals must traverse standard vias l04(a)-l04(b) of the backend interconnect layers (e.g., metal layers Ml through M9, for instance) and propagate all the way down into the silicon device layer. Such a signal path necessarily introduces significant RC costs resulting in propagation delay.

[0019] FIG. 2a is a block diagram of a reconfigurable interconnect structure and an example application of a reconfigurable interconnect structure as a multiplexer, according to one embodiment of the present disclosure. As shown in FIG. 2a, reconfigurable interconnect structure 200 comprises programming via 204, and first and second programmable vias 202(a)- 202(b). Each programmable via 202(a)-202(b) may further include respective interconnect switching structure 2l0(a)-2l0(b). As will be described in detail below, according to one embodiment of the present disclosure, interconnect switching structures 210(a) may comprise additional layer/s within the same via stack which can be programmed, i.e. made high or low resistance.

[0020] As described below, programmable vias 202(a)-202(b) may be programmed to be in one of a conducting state or a non-conducting state by utilizing the switchable nature of interconnect switching structures 2l0(a)-2l0(b). As shown in FIG. 2a, when programmable vias 202(a)-202(b) are in a conducting state, a conductive path 208 exists between programmable vias 202(a)-202(b). Conversely, when programmable vias 202(a)-202(b) are in a non-conducting state, no conducting path 208 exists between programmable vias 202(a)- 202(b). An operation of interconnect switching structure 2l0(a)-2l0(b) to provide for the switching of programmable vias 202(a)-202(b) to be in one of a conducting or non-conducting state is described below with respect to FIG. 3.

[0021] As can be further seen, FIG. 2a also shows a combination of reconfigurable interconnect structures 200(1 )-200(N) arranged so that an associated path with respect to each respective structure 200(l)-200(N) may be enabled or disabled independently. As shown in FIG. 2a, reconfigurable interconnect structures 200(l)-200(N) may be coupled to conductive layer 206. Each interconnect switching structure 2l0(l)(a)-2l0(l)(b) - 2lO(N)(a)-2lO(N)(b) may operate in a conductive or non-conductive state thereby enabling or disabling respective conductive paths 208(l)-208(N). Conductive layer 206 may be any suitable metal or other sufficiently conductive (e.g., copper, aluminum, tungsten, gold, silver, titanium, or a metal- containing alloy). As will be further appreciated, one of more reconfigurable interconnect structures 200 may be implemented in any one of the layers of the backend interconnect structure, which may include any number of layers (such as layers Ml through M9).

[0022] Reconfigurable interconnect structure 200 may span multiple layers of the backend interconnect or a single layer. According to one embodiment of the present disclosure, programming via 204 may be a standard via with any number of conducting and non-diffusion layers. An example structure for a programmable via (202(a)-202(b)) is described below with respect to FIG. 3.

[0023] FIG. 2b is a block diagram of a reconfigurable interconnect structure according to another example embodiment of the present disclosure. As shown in FIG. 2b, reconfigurable interconnect structure 200 may comprise a programming via 204 and an arbitrary number of programmable vias 202(a)-202(n). Path 208 may be enabled as conducting or non-conducting for each of a set of programmable vias 202(a)-202(b) by using programming via 204 to set the conducting/non-conducting state of respective interconnect switching structures 210(a)-2l0(n). Just as with the example embodiment of FIG. 2a, the reconfigurable interconnect structure 200 shown in FIG. 2b may be implemented in any one of the layers of the backend interconnect structure.

[0024] FIG. 2c is a block diagram of a reconfigurable interconnect structure according to another example embodiment of the present disclosure. As shown in FIG. 2c, reconfigurable interconnect structure 200 comprise programming via 204, programmable via 202, and standard via 104. Path 208 may be enabled as conducting or non-conducting between programmable via 202 and standard via 104 by setting the conducting/non-conducting state of interconnect switching structure 210. Just as with the example embodiment of FIG. 2a, the reconfigurable interconnect structure 200 shown in FIG. 2b may be implemented in any one of the layers of the backend interconnect structure.

[0025] FIG. 3 shows an example structure of an interconnect switching structure according to one embodiment of the present invention. As can be seen in this example case, interconnect switching structure 210(a) may comprise additional layer/s within the same via stack, which can be programmed, i.e. made high or low resistance such that a respective non-conductive or conductive state may be established. In particular, according to some embodiments one of the additional layers may be a highly resistive non-metal layer, with resistance -0.01 to 1 gigaohms. Examples of such non-metals are: aSi (Amorphous Silicon), backend porous dielectrics (CDO - “Carbon Doped Oxide”), low temperature ALD (“Atomic Layer Deposition”) oxides such as AI2O3 (aluminum oxide). The adjacent layer can be, for example, Ag (Silver) or Cu (Copper) or Al (Aluminum). Ag or Cu or Al also can be added in <20% atomic percent in the non-metal layer.

[0026] As shown in FIG. 3, interconnect switching structures 2l0(a)-2l0(b) may comprise Cu layers 306(a)-306(b), tantalum (“Ta”) layers 304(a)-304(b), and non-metal layer 302, according to some embodiments. Non-metal layer 302 may comprise amorphous silicon (“aSi”), amorphous germanium (“aGe”), NPZ, ALD aluminum oxide (“AI2O3). Other embodiments may include metals other than copper such as aluminum or other suitable conductive metal, as well as barrier materials other than tantalum such as tantalum nitride, as will be appreciated. According to other embodiments, non-metal layer 302 may be a chalcogenide-based alloy and include Te, Se, or S possessing phase change properties. Non- metal layer 302 may also or alternatively comprise organic materials. Rather than utilizing AI2O3 and S1O2 transition metal oxides such as hafnium oxide (Hf0₂), titanium oxide (T1O2), tantalum pentoxide (Ta₂0₅), Zrilh), and niobium pentoxide (Nt^Os), to name a few examples. According to some embodiments of the present disclosure, these materials may be deposited using ALD.

[0027] Copper layers 306(a)-306(b) may operate as a conductive layer. Tantalum layers 304(a)-304(b) may operate as a diffusion barrier, to prevent the copper (or other metal) from diffusing into the insulator or so-called inter-layer dielectric (ILD) material (e.g., silicon dioxide or other suitable insulator which would generally surround the various features of the reconfigurable interconnect structures 200 of a given interconnect layer, as will be appreciated). Interconnect switching structures 2l0(a)-2l0(b) may be rendered conductive or non-conductive respectively by applying a positive or negative bias voltage. Non-metal layer 302 may be selectively induced to enter a conductive or non-conductive state by application of a respective positive or negative bias.

[0028] FIG. 4a depicts a programming of a reconfigurable interconnect structure into a conducting state according to one embodiment of the present disclosure. As shown in FIG. 4a, positive bias voltage Von is applied to programming via 204, which causes programmable vias 202(a)-202(b) to enter a conducting state thereby enabling conductive path 208.

[0029] FIG. 4b depicts a programming of a reconfigurable interconnect structure into a non conducting state according to one embodiment of the present disclosure. As shown in FIG. 4b, negative bias voltage Von is applied to programming via 204, which causes programmable vias 202(a)-202(b) to enter a non-conducting state thereby disabling conductive path 208.

[0030] FIG. 5 depicts an operation of an interconnect structure according to one embodiment of the present disclosure. As discussed with respect to FIG. 5, interconnect switching structure 210 may comprise aSi, aGe, porous silicon oxide, AI2O3, with adjacent layers of Ag or Cu or Aluminum, according to some embodiments.

[0031] As shown in FIG. 5, interconnect switching structure 210 may operate in either a non volatile conducting or non-conducting state. Interconnect switching structure 210 may operate as a non-volatile memory. That is, interconnect switching structure 210 may retain its conductive or non-conductive state after a bias voltage is removed. In more detail, and as shown in FIG. 5, interconnect switching structure 210 may further comprise bottom inert electrode 508, dielectric layer 504, which may comprise a solid electrolyte, and oxidizable metal layer 502, which may operate as a top electrode. Filament 506 may form or dissolve in dielectric layer 504 upon application of a positive or negative bias voltage as described below. As previously described, dielectric layer 504 may further comprise aSi, aGe, porous silicon oxide, AI2O3.

[0032] An operation of interconnect switching structure 210 will now be described. Interconnect switching structure 210 may comprise a two terminal resistive memory (i.e., 502, 508) that relies on redox reactions to form and dissolve conductive filament 506. The state of the device is determined by the resistance across the two terminals (502,508). The existence of filament 506 between the terminals (502, 508) produces a low resistance state while the absence of a filament results in a high resistance state. Interconnect switching structure 210 may comprise two solid metal electrodes (502, 508), one relatively inert (508)

(e.g., tungsten or nickel) the other electrochemically active (502) (e.g., silver or copper), with a thin film of solid electrolyte between them (504). [0033] According to one embodiment of the present disclosure, the resistance state of interconnect switching structure 210 may be controlled by the formation (programming) or dissolution (erasing) of a metallic conductive filament (506) between terminals 502 and 508 of cell 500. Filament 506 may be a fractal tree like structure.

Filament Formation

[0034] Interconnect switching structure 210 may form of a metallic conductive filament 506 to transition to a low resistance state. According to one embodiment of the present disclosure, filament 506 may be created by applying a positive voltage bias (Von) to an anode contact 502 (active metal) while grounding the cathode contact 508 (inert metal). The positive bias may then oxidize the active metal 502 according to the relationship:

M M+ + e-

[0035] The applied bias may then generate an electric field between the two metal contacts (502, 508). The ionized (oxidized) metal ions may migrate along the electric field toward the cathode contact 508. At the cathode contact 508, the metal ions may be reduced:

M+ + e- M

[0036] As the active metal deposits on the cathode 508, the electric field increases between the anode 502 and the deposit. The evolution of a local electric field (E) between the growing filament and the anode 502 may be expressed as:

where d is the distance between the anode and the top of the growing filament. Filament 506 may grow to connect to anode 502 within a few nanoseconds. Metal ions will continue to be reduced at filament 506 until the voltage is removed, broadening conductive filament 506 and decreasing the resistance of the connection over time. Once the voltage is removed, conductive filament will 506 remain (persist), leaving interconnect switching structure 210 in a low resistance state.

Filament Dissolution

[0037] According to one embodiment of the present disclosure, interconnect switching structure 210 may be "erased" into a high resistance state by applying a negative voltage bias to anode 502. The process used to create conductive filament 506 may be reversed and the metal ions migrate along the reversed electric field to reduce at the anode contact 502. With filament 506 removed, interconnect switching structure 210 is analogous to parallel plate capacitor with a high resistance of several MW to GQ between the contacts.

[0038] FIGs. 6a depicts a fabrication process for generating a reconfigurable interconnect structure utilizing a mask deposition technique according to one embodiment of the present disclosure. The fabrication method may utilize a resist technology that is applied to one hole/via while the second via is generated using a deposition process. According to one embodiment of the present disclosure, a via may be fabricated in a dielectric layer of a backend interconnect layer. As can be seen in 702 and 704, a resist mask layer 722 is deposited on dielectric layer 724. In 704, and two holes 732(a) and 732(b) are generated in in resist mask layer 722. Then, in 706 two holes may be etched into dielectric layer 724 to accommodate a programmable via 202 and a programming via 204 (i.e., 726(a) and 726(b)).

[0039] According to one embodiment of the present disclosure, using mask resist 722, one of the holes (726(b)) is then protected, as shown in 708, while programming via 204 is fabricated in the other hole. In 710 programmable via 204 is protected by masking resist 722, while programmable via 202 is formed in the other hole. In 712, resistive mask 722 is removed. [0040] FIG. 6b depicts a fabrication process for generating a generating a reconfigurable interconnect structure utilizing a masked etch technique according to one embodiment of the present disclosure. In this second fabrication method, the copper and functional via are generated simultaneously. Thus, as shown in FIG. 6b, interconnect switching structure 210 may be fabricated as a single layer on copper layer 712. In 714, hole 726 is created in dielectric layer 724 such that hole 726 does not permeate interconnect switching structure layer 210. In 716 the remaining layers are fabricated to form programmable via 202 and programming via 204

[0041] FIG. 7 shows a specific example embodiment wherein a reconfigurable interconnect structure is utilized according to one embodiment of the present disclosure. As can be seen in this example configuration, programming vias 202(a)-202(b) (V7" and V7) are formed in metal layer M8. Programming via 204 is formed in metal layer M8 (i.e., via V7'). In a more general sense, and as will be appreciated, one or more reconfigurable interconnect structures 200 can be implemented in any number of locations within a given interconnect structure, according to some embodiments.

[0042] FIG. 8 illustrates a computing system implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure. Computing system 1000 may employ a number of reconfigurable interconnect structures 200. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc. [0043] Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices configured in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

[0044] The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0045] The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices configured as variously described herein. The term“processor” may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0046] The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices configured as variously described herein. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

[0047] In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. Note that reference to a computing system is intended to include computing devices, apparatuses, and other structures configured for computing or processing information.

Further Example Embodiments

[0048] The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

[0049] Example l is a reconfigurable interconnect structure for routing signals comprising a first programmable via, including a first non-volatile element that is selectively operable in one of a conducting and non-conducting state, a second programmable via, including a second non volatile element that is selectively operable in one of a conducting and non-conducting state, and, a programming via, wherein said programming via is electrically coupled to said first and second programmable vias at a contact, wherein upon application of a positive bias to said programming via a conducting path is established between said first and second programmable vias.

[0050] Example 2 includes the subject matter of Example 1, wherein said first and second programmable vias comprise a respective interconnect switching structure that may operate in one of a conducting non-volatile state or a non-conducting non-volatile state.

[0051] Example 3 includes the subject matter of Example 2, wherein said conducting and non-conducting non-volatile states may be established by respectively applying a positive bias voltage and a negative bias voltage to said respective interconnect switching structure.

[0052] Example 4 includes the subject matter of Example 2 or 3, wherein each interconnect switching structure assume a resistance of between 0.01 gigaohms to 1 gigaohms, in the non conducting non-volatile state.

[0053] Example 5 includes the subject matter of any of Examples 2-4, wherein each interconnect switching structure further comprises a non-metal layer. [0054] Example 6 includes the subject matter of Example 5, wherein said non-metal layer may comprises one of amorphous silicon, porous dielectric, carbon doped oxide (CDO), and aluminum oxide (AI2O3), or some combination of these.

[0055] Example 7 includes the subject matter of any of Examples 2-6, wherein each interconnect switching structure further comprises a metal layer. In some such cases, said metal layer is one of silver, copper, and aluminum.

[0056] Example 8 includes the subject matter of Example 5, wherein said non-metal layer further includes one of silver, copper, and aluminum in less than 20% atomic percent.

[0057] Example 9 includes the subject matter of any of Examples 1-8, wherein each of said first and second non-volatile elements is an interconnect switching structure comprising one of aSi, aGe, porous silicon oxide, and AI2O3, as well as one or more adjacent layers of Ag or Cu or aluminum.

[0058] Example 10 is a signal router for routing signals in an integrated circuit, the signal router comprising at least one reconfigurable interconnect structure, wherein each of said at least one reconfigurable interconnect structure comprises a first programmable via (including a first non-volatile element that is selectively operable in one of a conducting and non conducting state), a second programmable via (including a second non-volatile element that is selectively operable in one of a conducting and non-conducting state), and a programming via, wherein said programming via is electrically coupled to said first and second programmable vias at a contact, and wherein upon application of a positive bias to said programming via a conducting path is established between said first and second programmable vias.

[0059] Example 11 includes the subject matter of Example 10, wherein said first and second programmable vias comprise a respective interconnect switching structure that may operate in one of a conducting or non-conducting non-volatile state. [0060] Example 12 includes the subject matter of Example 11, wherein said conducting and non-conducting non-volatile states may be established by respectively applying a positive bias voltage and a negative bias voltage to said respective interconnect switching structure.

[0061] Example 13 includes the subject matter of Example 11 or 12, wherein each interconnect switching structure may assume a resistance of between 0.01 gigaohms to 1 gigaohms.

[0062] Example 14 includes the subject matter of any of Examples 11-13, wherein each interconnect switching structure further comprises a non-metal layer.

[0063] Example 15 includes the subject matter of Example 14, wherein said non-metal layer comprises one of amorphous silicon, a porous dielectric, carbon doped oxide (CDO), and aluminum oxide (AI2O3), or some combination of these.

[0064] Example 16 includes the subject matter of Example 14 or 15, wherein each interconnect switching structure may further comprise an adjacent layer (adjacent to the non- metal layer), wherein said adjacent layer is one of Ag, Cu, or Al.

[0065] Example 17 is a computing system comprising a communication chip, a memory, and, a processor, wherein at least one of said communication chip or processor further comprises at least one reconfigurable interconnect structure for routing signals, wherein each of said at least one reconfigurable interconnect structure includes a first programmable via (which includes a first non-volatile element that is selectively operable in one of a conducting and non-conducting state), a second programmable via (which includes a second non-volatile element that is selectively operable in one of a conducting and non-conducting state), and a programming via, wherein said programming via is electrically coupled to said first and second programmable vias at a contact, and wherein upon application of a positive bias to said programming via a conducting path is established between said first and second programmable vi as. [0066] Example 18 includes the subject matter of Example 17, wherein said first and second programmable vias further comprise a respective interconnect switching structure that may operate in one of a conducting or non-conducting non-volatile state.

[0067] Example 19 includes the subject matter of Example 18, wherein said conducting and non-conducting non-volatile states may be established by respectively applying a positive bias voltage and a negative bias voltage to said respective interconnect switching structure.

[0068] Example 20 includes the subject matter of any of Examples 17-19, wherein each interconnect switching structure may assume a resistance of between 0.01 gigaohms to 1 gigaohms.

[0069] The foregoing description of example embodiments of the disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the disclosure be limited not by this detailed description, but rather by the claims appended hereto.

Claims

CLAIMS What is claimed is:

1. A reconfigurable interconnect structure for routing signals, comprising: a first programmable via, including a first non-volatile element that is selectively operable in one of a conducting and non-conducting state; a second programmable via, including a second non-volatile element that is selectively operable in one of a conducting and non-conducting state; and, a programming via, wherein said programming via is electrically coupled to said first and second programmable vias at a contact, wherein upon application of a positive bias to said programming via a conducting path is established between said first and second programmable vias.

2. The reconfigurable interconnect structure according to claim 1, wherein said first and second programmable vias comprise a respective interconnect switching structure that may operate in one of a conducting non-volatile state or a non conducting non-volatile state.

3. The reconfigurable interconnect structure according to claim 2, wherein said conducting and non-conducting non-volatile states may be established by respectively applying a positive bias voltage and a negative bias voltage to said respective interconnect switching structure.

4. The reconfigurable interconnect structure according to claim 2, wherein each interconnect switching structure assumes a resistance of between 0.01 gigaohms to 1 gigaohms.

5. The reconfigurable interconnect structure according to any of claims 2 through 4, wherein each interconnect switching structure comprises a non-metal layer.

6. The reconfigurable interconnect structure according to claim 5, wherein said non- metal layer comprises one of amorphous silicon, porous dielectric, carbon doped oxide (CDO), and aluminum oxide (AI2O3).

7. The reconfigurable interconnect structure according to claim 5, wherein each interconnect switching structure further comprises a metal layer, wherein said metal layer is one of silver, copper, and aluminum.

8. The reconfigurable interconnect structure according to claim 5, wherein said non- metal layer further includes one of silver, copper, and aluminum in less than 20% atomic percent.

9. The reconfigurable interconnect structure according to claim 1 , wherein each of said first and second non-volatile elements is an interconnect switching structure comprising one of aSi, aGe, porous silicon oxide, and AI2O3, as well as one or more adjacent layers of Ag or Cu or Al.

10. A signal router for routing signals in an integrated circuit, the signal router comprising: at least one reconfigurable interconnect structure for routing signals, wherein each of said at least one reconfigurable interconnect structure further includes a first programmable via, including a first non-volatile element that is selectively operable in one of a conducting and non-conducting state; a second programmable via, including a second non-volatile element that is selectively operable in one of a conducting and non-conducting state; and, a programming via, wherein said programming via is electrically coupled to said first and second programmable vias at a contact, wherein upon application of a positive bias to said programming via a conducting path is established between said first and second programmable vias.

11. The signal router according to claim 10, wherein said first and second programmable vias further comprise a respective interconnect switching structure that may operate in one of a conducting or non-conducting non-volatile state.

12. The signal router according to claim 11, wherein said conducting and non conducting non-volatile states may be established by respectively applying a positive bias voltage and a negative bias voltage to said respective interconnect switching structure.

13. The signal router according to claim 11, wherein each interconnect switching structure may assume a resistance of between 0.01 gigaohms to 1 gigaohms.

14. The signal router according to any of claims 11 through 13, wherein each interconnect switching structure further comprises a non-metal layer.

15. The signal router according to claim 14, wherein said non-metal layer comprises one of amorphous silicon, porous dielectric, carbon doped oxide (CDO), and aluminum oxide (AI2O3).

16. The signal router according to claim 15, wherein each interconnect switching structure further comprises an additional layer adjacent to said non-metal layer, wherein said additional layer comprises one of Ag, Cu, or Al.

17. A computing system further comprising: a communication chip; a memory; and, a processor; wherein at least one of said processor and communication chip comprises at least one reconfigurable interconnect structure for routing signals, wherein each of said at least one reconfigurable interconnect structure further includes a first programmable via, including a first non-volatile element that is selectively operable in one of a conducting and non-conducting state; a second programmable via, including a second non-volatile element that is selectively operable in one of a conducting and non-conducting state; and, a programming via, wherein said programming via is electrically coupled to said first and second programmable vias at a contact, wherein upon application of a positive bias to said programming via a conducting path is established between said first and second programmable vias.

18. The computing system according to claim 17, wherein said first and second programmable vias further comprise a respective interconnect switching structure that may operate in one of a conducting or non-conducting non-volatile state.

19. The computing system according to claim 18, wherein said conducting and non conducting non-volatile states may be established by respectively applying a positive bias voltage and a negative bias voltage to said respective interconnect switching structure.

20. The computing system according to claim 19, wherein each interconnect switching structure may assume a resistance of between 0.01 gigaohms to 1 gigaohms.