WO2019129019A1 - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

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Publication number
WO2019129019A1
WO2019129019A1 PCT/CN2018/123706 CN2018123706W WO2019129019A1 WO 2019129019 A1 WO2019129019 A1 WO 2019129019A1 CN 2018123706 W CN2018123706 W CN 2018123706W WO 2019129019 A1 WO2019129019 A1 WO 2019129019A1
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Prior art keywords
boundary
light shielding
shielding layer
layer
polysilicon
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PCT/CN2018/123706
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French (fr)
Chinese (zh)
Inventor
安喜锋
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武汉华星光电技术有限公司
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Publication of WO2019129019A1 publication Critical patent/WO2019129019A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate and a display panel.
  • FIG. 1 is a schematic structural view of an array substrate.
  • FIG. 2 is a cross-sectional view of a portion 1-1 of the array substrate.
  • the polysilicon layer 14 is prepared by a single crystal silicon layer by an excimer laser annealing process.
  • the excimer laser annealing process causes the polysilicon layer 14 to produce a block-shaped ingot 141. Between the ingots 141 is a raised grain boundary 142. Since the scanning direction of the excimer laser annealing process is vertical or horizontal, the direction of the grain boundary 142 is also generated along the scanning direction.
  • a light shielding layer 12 is provided on the base substrate 11. Since the thickness of each region of the buffer layer 13 is the same, the climbing portion of the light shielding layer 12 is inevitably transmitted to the buffer layer, so that the polysilicon layer 14 encounters the grain boundary 142 at the climbing position above the light shielding layer 12, so that the polysilicon at the climbing slope is caused. The resistance of the layer 14 is large, and eventually a thin film transistor device of good quality cannot be formed, thereby forming a dark spot on the display panel.
  • the grain boundary in the polysilicon layer is parallel to the boundary of the light shielding layer, resulting in a problem that the resistance of the thin film transistor device is excessive.
  • an array substrate including:
  • a light shielding layer disposed on a surface of the base substrate
  • a buffer layer disposed above the base substrate and the light shielding layer
  • the thin film transistor disposed on the buffer layer, the thin film transistor including a polysilicon layer;
  • the polysilicon layer is composed of ingots, and there are convex grain boundaries between the adjacent crystal blocks, the grain boundaries are perpendicular to the boundary of the polysilicon layer, and the straight line where the grain boundaries are located
  • the straight line where the boundary of the shading layer is located is a straight line.
  • the thin film transistor is a U-type thin film transistor.
  • the thickness of each region of the buffer layer is the same.
  • the structure of the light shielding layer is one of a rectangular parallelepiped structure and a prismatic structure.
  • the polysilicon layer includes a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
  • the first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer intersects a boundary of the light shielding layer and is not perpendicular.
  • the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer, and a projection of the first grain boundary on the light shielding layer and the light shielding layer The boundaries intersect.
  • the light shielding layer includes a first boundary, a second boundary, a third boundary, and a fourth boundary;
  • the first boundary and the second boundary are oppositely disposed, and the third boundary and the fourth boundary are oppositely disposed.
  • the first boundary and the second boundary are linear, and the third boundary and the fourth boundary are non-linear.
  • the polysilicon layer includes a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
  • the first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer is parallel to a first boundary of the light shielding layer.
  • the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer, a projection of the first grain boundary on the light shielding layer, and the third The boundary intersects the fourth boundary.
  • a display panel the display panel color film substrate and the array substrate, the array substrate comprising:
  • a light shielding layer disposed on a surface of the base substrate
  • a buffer layer disposed above the base substrate and the light shielding layer
  • the thin film transistor disposed on the buffer layer, the thin film transistor including a polysilicon layer;
  • the polysilicon layer is composed of ingots, and there are convex grain boundaries between the adjacent crystal blocks, the grain boundaries are perpendicular to the boundary of the polysilicon layer, and the straight line where the grain boundaries are located
  • the straight line where the boundary of the shading layer is located is a straight line.
  • the thin film transistor is a U-type thin film transistor.
  • the thickness of each region of the buffer layer is the same.
  • the structure of the light shielding layer is one of a rectangular parallelepiped structure and a prismatic structure.
  • the polysilicon layer includes a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
  • the first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer intersects a boundary of the light shielding layer and is not perpendicular.
  • the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer, and a projection of the first grain boundary on the light shielding layer and the light shielding layer The boundaries intersect.
  • the light shielding layer includes a first boundary, a second boundary, a third boundary, and a fourth boundary;
  • the first boundary and the second boundary are oppositely disposed, and the third boundary and the fourth boundary are oppositely disposed.
  • the first boundary and the second boundary are linear, and the third boundary and the fourth boundary are non-linear.
  • the polysilicon layer includes a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
  • the first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer is parallel to a first boundary of the light shielding layer.
  • the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer, and a projection of the first grain boundary on the light shielding layer and the third The boundary intersects the fourth boundary.
  • the present application can prevent the boundary between the grain boundary of the polysilicon layer and the boundary of the light shielding layer when the polysilicon layer crosses the light shielding layer, thereby avoiding a large channel between the crystal blocks and causing excessive resistance of the thin film transistor device.
  • the problem is thus improved the conductivity of the thin film transistor in the array substrate.
  • 1 is a schematic structural view of a conventional array substrate
  • FIG. 2 is a cross-sectional structural view showing a cross section of the array substrate 1-1 of FIG. 1;
  • FIG. 3 is a schematic structural view of an array substrate in a first embodiment of the present application.
  • Figure 4 is a cross-sectional view taken along line 2-2 of the first embodiment of the present application.
  • FIG. 5 is a schematic structural view of a light shielding layer in a second embodiment of the present application.
  • Figure 6 is a plan view of an array substrate in a third embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of an array substrate according to a first embodiment of the present application.
  • FIG. 4 is a cross-sectional view taken along line 2-2 of the first embodiment of the present application.
  • the application provides an array substrate 2, comprising:
  • a light shielding layer 22 disposed on a surface of the base substrate 21;
  • a buffer layer 23 disposed above the base substrate 21 and the light shielding layer 22;
  • the thin film transistor disposed on the buffer layer 23, the thin film transistor comprising a polysilicon layer 24;
  • the polysilicon layer 24 is composed of ingots 241, and there are convex grain boundaries 242 between the adjacent crystal blocks 241, and the grain boundaries 242 are perpendicular to the boundary of the polysilicon layer 24, the crystal The straight line where the boundary of the boundary 242 and the boundary of the light shielding layer 22 are different from each other.
  • the polysilicon layer 24 includes a planar portion and a hill climbing portion.
  • the ingots 241 are closely adhered to each other such that the polysilicon layer 24 has no channel, and the polysilicon layer 24 has a small resistance; the polysilicon layer is climbed.
  • the polysilicon layer 24 appears at the grain boundary 242 above the light shielding layer 22, causing an abnormal increase in polysilicon in the region.
  • by setting a straight line where the boundary between the grain boundary 242 and the light shielding layer 22 is a different line straight line it is possible to prevent the channel at the grain boundary 242 from being excessively large and the resistance of the polysilicon layer to increase.
  • the thin film transistor 2 is a U-type thin film transistor.
  • the regions on the buffer layer have the same thickness.
  • the present application determines the line between the line where the grain boundary 242 is located and the boundary of the light shielding layer 22 by changing the angle of the boundary between the polysilicon layer 24 and the light shielding layer 22 when the polysilicon layer 24 is crossed.
  • the out-of-plane line it is also possible to prevent the horizontal grain boundary 242 from being non-parallel to the boundary of the light-shielding layer 22 to avoid the channel being excessively large at the grain boundary.
  • the structure of the light shielding layer 22 is one of a rectangular parallelepiped structure and a prismatic structure, and the effect of reducing the resistance of the polysilicon layer 24 can be achieved without special limitation.
  • the polysilicon layer 24 includes a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
  • the first polysilicon region is a linear structure, and the projection of the first polysilicon region on the light shielding layer 22 intersects with the boundary of the light shielding layer 22 and is not perpendicular.
  • the projection here refers to vertical illumination of parallel light directly above the polysilicon layer 24, and the pattern formed on the plane of the light shielding layer 22 is the polysilicon layer 22 The projection on the light shielding layer 22.
  • the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer 22, a projection of the first grain boundary on the light shielding layer 22 and the light shielding The boundaries of layer 22 intersect.
  • FIG. 5 is a schematic structural diagram of a light shielding layer according to a second embodiment of the present application.
  • FIG. 6 is a top view of the array substrate in the third embodiment of the present application.
  • the present application realizes the boundary between the straight line where the grain boundary 342 is located and the light shielding layer 32 by changing the structure of the polysilicon layer 34 and changing the shape of the light shielding property.
  • the line in which it is located is the purpose of a different line.
  • the light shielding layer 22 includes a first boundary, a second boundary, a third boundary, and a fourth boundary;
  • the first boundary and the second boundary are oppositely disposed, and the third boundary and the fourth boundary are oppositely disposed.
  • first boundary and the second boundary are linear, and the third boundary and the fourth boundary are non-linear.
  • the polysilicon layer 24 includes a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer 22;
  • the first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer 22 is parallel to a first boundary of the light shielding layer 22 .
  • the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer 22, and a projection of the first grain boundary on the light shielding layer 22 and the first The three boundaries intersect with the fourth boundary.
  • the first embodiment, the second embodiment, and the third embodiment are both for the purpose of realizing that the straight line where the boundary between the grain boundary 242 and the light shielding layer 22 is a straight line; It is to be noted that the first embodiment is carried out by a change in the structure of the polysilicon layer 24, and the second embodiment is realized by a change in the structure of the light shielding layer 22.
  • the present application can prevent the boundary between the grain boundary of the polysilicon layer and the boundary of the light shielding layer when the polysilicon layer crosses the light shielding layer, thereby avoiding a large channel between the crystal blocks and causing excessive resistance of the thin film transistor device.
  • the problem is thus improved the conductivity of the thin film transistor in the array substrate.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

Provided are an array substrate and a display panel. The array substrate sequentially comprises a base substrate, a light shielding layer, a buffer layer, and a polysilicon layer. Wherein, the polysilicon layer is composed of crystal blocks, raised grain boundaries are presented between the adjacent crystal blocks, the grain boundaries are perpendicular to the boundaries of the polysilicon layer, and the straight line where the grain boundaries are located and the straight line where the boundaries of the light shielding layer are located are non-coplanar straight lines.

Description

阵列基板及显示面板Array substrate and display panel 技术领域Technical field
本申请涉及显示技术领域，具体涉及一种阵列基板及显示面板。The present application relates to the field of display technologies, and in particular, to an array substrate and a display panel.
背景技术Background technique
请参阅图1，图1为阵列基板的结构示意图；请参阅图2，图2为阵列基板中1-1部分的剖面图。Please refer to FIG. 1. FIG. 1 is a schematic structural view of an array substrate. Referring to FIG. 2, FIG. 2 is a cross-sectional view of a portion 1-1 of the array substrate.
在传统的阵列基板1的制作过程中，多晶硅层14由单晶硅层经过准分子激光退火工艺制备而成。准分子激光退火工艺会导致多晶硅层14产生方块状的晶块141。所述晶块141之间为凸起的晶界142。由于准分子激光退火工艺的扫描方向为垂直或者水平方向，因此晶界142的方向也会沿着扫描方向产生。In the fabrication process of the conventional array substrate 1, the polysilicon layer 14 is prepared by a single crystal silicon layer by an excimer laser annealing process. The excimer laser annealing process causes the polysilicon layer 14 to produce a block-shaped ingot 141. Between the ingots 141 is a raised grain boundary 142. Since the scanning direction of the excimer laser annealing process is vertical or horizontal, the direction of the grain boundary 142 is also generated along the scanning direction.
在阵列基板1的传统设计中，在衬底基板11上设置有遮光层12。由于所述缓冲层13各区域的厚度相同，遮光层12的爬坡处必然会传递到缓冲层，使得多晶硅层14在遮光层12上方的爬坡处遇到晶界142，致使爬坡处多晶硅层14的电阻较大，最终无法形成品质良好的薄膜晶体管器件，进而在显示面板上形成暗点。In the conventional design of the array substrate 1, a light shielding layer 12 is provided on the base substrate 11. Since the thickness of each region of the buffer layer 13 is the same, the climbing portion of the light shielding layer 12 is inevitably transmitted to the buffer layer, so that the polysilicon layer 14 encounters the grain boundary 142 at the climbing position above the light shielding layer 12, so that the polysilicon at the climbing slope is caused. The resistance of the layer 14 is large, and eventually a thin film transistor device of good quality cannot be formed, thereby forming a dark spot on the display panel.
因此目前亟需一种阵列基板能够解决上述问题。Therefore, there is an urgent need for an array substrate to solve the above problems.
技术问题technical problem
阵列基板中多晶硅层在跨过遮光层时，多晶硅层中的晶界与遮光层边界平行，导致薄膜晶体管器件电阻过大的问题。When the polysilicon layer in the array substrate crosses the light shielding layer, the grain boundary in the polysilicon layer is parallel to the boundary of the light shielding layer, resulting in a problem that the resistance of the thin film transistor device is excessive.
技术解决方案Technical solution
为实现上述目的，本申请提供的技术方案如下：To achieve the above objective, the technical solution provided by the present application is as follows:
根据本申请的一个方面，提供了一种阵列基板，包括：According to an aspect of the present application, an array substrate is provided, including:
衬底基板；Substrate substrate;
设置在所述衬底基板表面的遮光层；a light shielding layer disposed on a surface of the base substrate;
设置在所述衬底基板和所述遮光层上方的缓冲层；a buffer layer disposed above the base substrate and the light shielding layer;
设置在所述缓冲层上的薄膜晶体管，所述薄膜晶体管包括多晶硅层；a thin film transistor disposed on the buffer layer, the thin film transistor including a polysilicon layer;
其中，所述多晶硅层由晶块组成，相邻的所述晶块之间存在凸起的晶界，所述晶界与所述多晶硅层的边界相垂直，所述晶界所在的直线与所述遮光层边界所在的直线为异面直线。Wherein the polysilicon layer is composed of ingots, and there are convex grain boundaries between the adjacent crystal blocks, the grain boundaries are perpendicular to the boundary of the polysilicon layer, and the straight line where the grain boundaries are located The straight line where the boundary of the shading layer is located is a straight line.
在本申请的阵列基板中，所述薄膜晶体管为U型薄膜晶体管。In the array substrate of the present application, the thin film transistor is a U-type thin film transistor.
在本申请的阵列基板中，所述缓冲层各区域的厚度相同。In the array substrate of the present application, the thickness of each region of the buffer layer is the same.
在本申请的阵列基板中，所述遮光层的结构为长方体结构和棱台结构的其中一种。In the array substrate of the present application, the structure of the light shielding layer is one of a rectangular parallelepiped structure and a prismatic structure.
在本申请的阵列基板中，所述多晶硅层包括第一多晶硅区域和第二多晶硅区域，所述第一多晶硅区域位于所述遮光层的正上方；In the array substrate of the present application, the polysilicon layer includes a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
其中，所述第一多晶硅区域为直线型结构，所述第一多晶硅区域位于所述遮光层上的投影与所述遮光层的边界相交且不垂直。The first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer intersects a boundary of the light shielding layer and is not perpendicular.
在本申请的阵列基板中，所述第一多晶硅区域包括与所述遮光层边界相对应的第一晶界，所述第一晶界位于所述遮光层上的投影与所述遮光层的边界相交。In the array substrate of the present application, the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer, and a projection of the first grain boundary on the light shielding layer and the light shielding layer The boundaries intersect.
在本申请的阵列基板中，所述遮光层包括第一边界、第二边界、第三边界和第四边界；In the array substrate of the present application, the light shielding layer includes a first boundary, a second boundary, a third boundary, and a fourth boundary;
其中，所述第一边界和所述第二边界相对设置，所述第三边界和所述第四边界相对设置。The first boundary and the second boundary are oppositely disposed, and the third boundary and the fourth boundary are oppositely disposed.
在本申请的阵列基板中，所述第一边界与所述第二边界为直线状，所述第三边界和所述第四边界为非直线状。In the array substrate of the present application, the first boundary and the second boundary are linear, and the third boundary and the fourth boundary are non-linear.
在本申请的阵列基板中，所述多晶硅层包括第一多晶硅区域和第二多晶硅区域，所述第一多晶硅区域位于所述遮光层的正上方；In the array substrate of the present application, the polysilicon layer includes a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
其中，所述第一多晶硅区域为直线型结构，所述第一多晶硅区域位于所述遮光层上的投影与所述遮光层的第一边界相平行。The first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer is parallel to a first boundary of the light shielding layer.
在本申请的阵列基板中，所述第一多晶硅区域包括与所述遮光层边界相对应的第一晶界，所述第一晶界位于所述遮光层上的投影与所述第三边界和第四边界相交。In the array substrate of the present application, the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer, a projection of the first grain boundary on the light shielding layer, and the third The boundary intersects the fourth boundary.
根据本申请的另一个方面，还提供给了一种显示面板，所述显示面板彩膜基板和阵列基板，所述阵列基板包括：According to another aspect of the present application, there is also provided a display panel, the display panel color film substrate and the array substrate, the array substrate comprising:
衬底基板；Substrate substrate;
设置在所述衬底基板表面的遮光层；a light shielding layer disposed on a surface of the base substrate;
设置在所述衬底基板和所述遮光层上方的缓冲层；a buffer layer disposed above the base substrate and the light shielding layer;
设置在所述缓冲层上的薄膜晶体管，所述薄膜晶体管包括多晶硅层；a thin film transistor disposed on the buffer layer, the thin film transistor including a polysilicon layer;
其中，所述多晶硅层由晶块组成，相邻的所述晶块之间存在凸起的晶界，所述晶界与所述多晶硅层的边界相垂直，所述晶界所在的直线与所述遮光层边界所在的直线为异面直线。Wherein the polysilicon layer is composed of ingots, and there are convex grain boundaries between the adjacent crystal blocks, the grain boundaries are perpendicular to the boundary of the polysilicon layer, and the straight line where the grain boundaries are located The straight line where the boundary of the shading layer is located is a straight line.
在本申请的显示面板中，所述薄膜晶体管为U型薄膜晶体管。In the display panel of the present application, the thin film transistor is a U-type thin film transistor.
在本申请的显示面板中，所述缓冲层各区域的厚度相同。In the display panel of the present application, the thickness of each region of the buffer layer is the same.
在本申请的显示面板中，所述遮光层的结构为长方体结构和棱台结构的其中一种。In the display panel of the present application, the structure of the light shielding layer is one of a rectangular parallelepiped structure and a prismatic structure.
在本申请的显示面板中，所述多晶硅层包括第一多晶硅区域和第二多晶硅区域，所述第一多晶硅区域位于所述遮光层的正上方；In the display panel of the present application, the polysilicon layer includes a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
其中，所述第一多晶硅区域为直线型结构，所述第一多晶硅区域位于所述遮光层上的投影与所述遮光层的边界相交且不垂直。The first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer intersects a boundary of the light shielding layer and is not perpendicular.
在本申请的显示面板中，所述第一多晶硅区域包括与所述遮光层边界相对应的第一晶界，所述第一晶界位于所述遮光层上的投影与所述遮光层的边界相交。In the display panel of the present application, the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer, and a projection of the first grain boundary on the light shielding layer and the light shielding layer The boundaries intersect.
在本申请的显示面板中，所述遮光层包括第一边界、第二边界、第三边界和第四边界；In the display panel of the present application, the light shielding layer includes a first boundary, a second boundary, a third boundary, and a fourth boundary;
其中，所述第一边界和所述第二边界相对设置，所述第三边界和所述第四边界相对设置。The first boundary and the second boundary are oppositely disposed, and the third boundary and the fourth boundary are oppositely disposed.
在本申请的显示面板中，所述第一边界与所述第二边界为直线状，所述第三边界和所述第四边界为非直线状。In the display panel of the present application, the first boundary and the second boundary are linear, and the third boundary and the fourth boundary are non-linear.
在本申请的显示面板中，所述多晶硅层包括第一多晶硅区域和第二多晶硅区域，所述第一多晶硅区域位于所述遮光层的正上方；In the display panel of the present application, the polysilicon layer includes a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
其中，所述第一多晶硅区域为直线型结构，所述第一多晶硅区域位于所述遮光层上的投影与所述遮光层的第一边界相平行。The first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer is parallel to a first boundary of the light shielding layer.
在本申请的显示面板中，所述第一多晶硅区域包括与所述遮光层边界相对应的第一晶界，所述第一晶界位于所述遮光层上的投影与所述第三边界和第四边界相交。In the display panel of the present application, the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer, and a projection of the first grain boundary on the light shielding layer and the third The boundary intersects the fourth boundary.
有益效果Beneficial effect
有益效果：本申请通过在多晶硅层跨过遮光层时，设置所述多晶硅层的晶界与所述遮光层边界异面，能够避免晶块之间出现较大沟道导致薄膜晶体管器件电阻过大的问题，从而提高了阵列基板中薄膜晶体管的导电性能。[Advantageous Effects] The present application can prevent the boundary between the grain boundary of the polysilicon layer and the boundary of the light shielding layer when the polysilicon layer crosses the light shielding layer, thereby avoiding a large channel between the crystal blocks and causing excessive resistance of the thin film transistor device. The problem is thus improved the conductivity of the thin film transistor in the array substrate.
附图说明DRAWINGS
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments or the technical solutions in the prior art, the drawings to be used in the embodiments or the prior art description will be briefly described below. Obviously, the drawings in the following description are merely inventions. For some embodiments, other drawings may be obtained from those of ordinary skill in the art without departing from the drawings.
图1为现有阵列基板的结构示意图；1 is a schematic structural view of a conventional array substrate;
图2为图1中阵列基板1-1截面的剖面结构图；2 is a cross-sectional structural view showing a cross section of the array substrate 1-1 of FIG. 1;
图3为本申请第一实施例中阵列基板的结构示意图；3 is a schematic structural view of an array substrate in a first embodiment of the present application;
图4为本申请第一实施例中2-2截面的剖面图；Figure 4 is a cross-sectional view taken along line 2-2 of the first embodiment of the present application;
图5为本申请第二实施例中遮光层的结构示意图；5 is a schematic structural view of a light shielding layer in a second embodiment of the present application;
图6为本申请第三实施例中阵列基板的俯视图。Figure 6 is a plan view of an array substrate in a third embodiment of the present application.
本申请的实施方式Embodiment of the present application
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。The following description of the various embodiments is provided to illustrate the specific embodiments of the invention. Directional terms mentioned in this application, such as [upper], [lower], [previous], [post], [left], [right], [inside], [outside], [side], etc., are only references Attach the direction of the drawing. Therefore, the directional terminology used is for the purpose of illustration and understanding, and is not intended to be limiting. In the figures, structurally similar elements are denoted by the same reference numerals.
下面结合附图和具体实施例对本申请做进一步的说明：The present application is further described below in conjunction with the accompanying drawings and specific embodiments:
请参阅图3，图3为本申请第一实施例中阵列基板的结构示意图。Please refer to FIG. 3. FIG. 3 is a schematic structural diagram of an array substrate according to a first embodiment of the present application.
请参阅图4，图4为本申请第一实施例中2-2截面的剖面图。Please refer to FIG. 4. FIG. 4 is a cross-sectional view taken along line 2-2 of the first embodiment of the present application.
本申请提供了一种阵列基板2，包括：The application provides an array substrate 2, comprising:
衬底基板21；Substrate substrate 21;
设置在所述衬底基板21表面的遮光层22；a light shielding layer 22 disposed on a surface of the base substrate 21;
设置在所述衬底基板21和所述遮光层22上方的缓冲层23；a buffer layer 23 disposed above the base substrate 21 and the light shielding layer 22;
设置在所述缓冲层23上的薄膜晶体管，所述薄膜晶体管包括多晶硅层24；a thin film transistor disposed on the buffer layer 23, the thin film transistor comprising a polysilicon layer 24;
其中，所述多晶硅层24由晶块241组成，相邻的所述晶块241之间存在凸起的晶界242，所述晶界242与所述多晶硅层24的边界相垂直，所述晶界242所在的直线与所述遮光层22边界所在的直线为异面直线。Wherein, the polysilicon layer 24 is composed of ingots 241, and there are convex grain boundaries 242 between the adjacent crystal blocks 241, and the grain boundaries 242 are perpendicular to the boundary of the polysilicon layer 24, the crystal The straight line where the boundary of the boundary 242 and the boundary of the light shielding layer 22 are different from each other.
在一种实施例中，当多晶硅层24包括平面部分和爬坡部分。在多晶硅层24的平面部分中，所述晶块241之间紧紧贴合，使得所述多晶硅层24没有沟道，此时所述多晶硅层24的阻值较小；在多晶硅层的爬坡部分中，所述多晶硅层24在遮光层22上方的晶界242处出现沟道，使得该区域多晶硅的异常增大。本申请通过设置所述晶界242所在的直线与所述遮光层22边界所在的直线为异面直线，能够避免所述晶界242处沟道过大进而使得多晶硅层的电阻增大。In one embodiment, the polysilicon layer 24 includes a planar portion and a hill climbing portion. In the planar portion of the polysilicon layer 24, the ingots 241 are closely adhered to each other such that the polysilicon layer 24 has no channel, and the polysilicon layer 24 has a small resistance; the polysilicon layer is climbed. In the portion, the polysilicon layer 24 appears at the grain boundary 242 above the light shielding layer 22, causing an abnormal increase in polysilicon in the region. In the present application, by setting a straight line where the boundary between the grain boundary 242 and the light shielding layer 22 is a different line straight line, it is possible to prevent the channel at the grain boundary 242 from being excessively large and the resistance of the polysilicon layer to increase.
在一种实施例中，所述薄膜晶体管2为U型薄膜晶体管。In one embodiment, the thin film transistor 2 is a U-type thin film transistor.
在一种实施例中，所述缓冲层上各区域的厚度相同。In one embodiment, the regions on the buffer layer have the same thickness.
在上述实施例中，本申请通过改变所述多晶硅层24跨过遮光层22时与所述遮光层22边界的角度进而达到所述晶界242所在的直线与所述遮光层22边界所在的直线为异面直线这一目的；另一方面，也可以设置避免水平的晶界242与所述遮光层22的边界非平行设置以避免晶界处处沟道过大。In the above embodiment, the present application determines the line between the line where the grain boundary 242 is located and the boundary of the light shielding layer 22 by changing the angle of the boundary between the polysilicon layer 24 and the light shielding layer 22 when the polysilicon layer 24 is crossed. For the purpose of the out-of-plane line; on the other hand, it is also possible to prevent the horizontal grain boundary 242 from being non-parallel to the boundary of the light-shielding layer 22 to avoid the channel being excessively large at the grain boundary.
在一种实施例中，所述遮光层22的结构为长方体结构和棱台结构的其中一种，不需进行特殊的限定，即能达到减小多晶硅层24电阻的作用。In one embodiment, the structure of the light shielding layer 22 is one of a rectangular parallelepiped structure and a prismatic structure, and the effect of reducing the resistance of the polysilicon layer 24 can be achieved without special limitation.
在一种实施例中，所述多晶硅层24包括第一多晶硅区域和第二多晶硅区域，所述第一多晶硅区域位于所述遮光层的正上方；In one embodiment, the polysilicon layer 24 includes a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
其中，所述第一多晶硅区域为直线型结构，所述第一多晶硅区域位于所述遮光层22上的投影与所述遮光层22的边界相交且不垂直。The first polysilicon region is a linear structure, and the projection of the first polysilicon region on the light shielding layer 22 intersects with the boundary of the light shielding layer 22 and is not perpendicular.
这里的投影指的是，在所述多晶硅层24的正上方进行平行光的竖直照射，所述多晶硅层24在所述遮光层22所在平面上形成的图形即为所述多晶硅层22在所述遮光层22上的投影。The projection here refers to vertical illumination of parallel light directly above the polysilicon layer 24, and the pattern formed on the plane of the light shielding layer 22 is the polysilicon layer 22 The projection on the light shielding layer 22.
在一种实施例中，所述第一多晶硅区域包括与所述遮光层22边界相对应的第一晶界，所述第一晶界位于所述遮光层22上的投影与所述遮光层22的边界相交。In one embodiment, the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer 22, a projection of the first grain boundary on the light shielding layer 22 and the light shielding The boundaries of layer 22 intersect.
请参阅图5，图5为本申请第二实施例中遮光层的结构示意图。Please refer to FIG. 5. FIG. 5 is a schematic structural diagram of a light shielding layer according to a second embodiment of the present application.
请参阅图6，图6为本申请第三实施例中阵列基板的俯视图。在本申请的第二实施例和第三实施例中，本申请通过保持多晶硅层34结构不变，改变所述遮光性的形状来实现所述晶界342所在的直线与所述遮光层32边界所在的直线为异面直线这一目的。Please refer to FIG. 6. FIG. 6 is a top view of the array substrate in the third embodiment of the present application. In the second embodiment and the third embodiment of the present application, the present application realizes the boundary between the straight line where the grain boundary 342 is located and the light shielding layer 32 by changing the structure of the polysilicon layer 34 and changing the shape of the light shielding property. The line in which it is located is the purpose of a different line.
在一种实施例中，所述遮光层22包括第一边界、第二边界、第三边界和第四边界；In an embodiment, the light shielding layer 22 includes a first boundary, a second boundary, a third boundary, and a fourth boundary;
其中，所述第一边界和所述第二边界相对设置，所述第三边界和所述第四边界相对设置。The first boundary and the second boundary are oppositely disposed, and the third boundary and the fourth boundary are oppositely disposed.
在一种实施例中，所述第一边界与所述第二边界为直线状，所述第三边界和所述第四边界为非直线状。In one embodiment, the first boundary and the second boundary are linear, and the third boundary and the fourth boundary are non-linear.
在一种实施例中，所述多晶硅层24包括第一多晶硅区域和第二多晶硅区域，所述第一多晶硅区域位于所述遮光层22的正上方；In one embodiment, the polysilicon layer 24 includes a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer 22;
其中，所述第一多晶硅区域为直线型结构，所述第一多晶硅区域位于所述遮光层22上的投影与所述遮光层22的第一边界相平行。The first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer 22 is parallel to a first boundary of the light shielding layer 22 .
在一种实施例中，所述第一多晶硅区域包括与所述遮光层22边界相对应的第一晶界，所述第一晶界位于所述遮光层22上的投影与所述第三边界和第四边界相交。In one embodiment, the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer 22, and a projection of the first grain boundary on the light shielding layer 22 and the first The three boundaries intersect with the fourth boundary.
在本申请中，第一实施例、第二实施例和第三实施例均是为了实现所述晶界242所在的直线与所述遮光层22边界所在的直线为异面直线这一目的；区别在于，第一实施例是进行的是通过多晶硅层24结构的改变来实现，而第二实施例则是通过遮光层22结构的改变来实现。In the present application, the first embodiment, the second embodiment, and the third embodiment are both for the purpose of realizing that the straight line where the boundary between the grain boundary 242 and the light shielding layer 22 is a straight line; It is to be noted that the first embodiment is carried out by a change in the structure of the polysilicon layer 24, and the second embodiment is realized by a change in the structure of the light shielding layer 22.
有益效果：本申请通过在多晶硅层跨过遮光层时，设置所述多晶硅层的晶界与所述遮光层边界异面，能够避免晶块之间出现较大沟道导致薄膜晶体管器件电阻过大的问题，从而提高了阵列基板中薄膜晶体管的导电性能。[Advantageous Effects] The present application can prevent the boundary between the grain boundary of the polysilicon layer and the boundary of the light shielding layer when the polysilicon layer crosses the light shielding layer, thereby avoiding a large channel between the crystal blocks and causing excessive resistance of the thin film transistor device. The problem is thus improved the conductivity of the thin film transistor in the array substrate.
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。In the above, although the present application has been disclosed in the above preferred embodiments, the preferred embodiments are not intended to limit the application, and those skilled in the art can make various modifications without departing from the spirit and scope of the application. The invention is modified and retouched, and the scope of protection of the present application is determined by the scope defined by the claims.

Claims (20)

  1. 一种阵列基板，其包括：An array substrate comprising:
    衬底基板；Substrate substrate;
    设置在所述衬底基板表面的遮光层；a light shielding layer disposed on a surface of the base substrate;
    设置在所述衬底基板和所述遮光层上方的缓冲层；a buffer layer disposed above the base substrate and the light shielding layer;
    设置在所述缓冲层上的薄膜晶体管，所述薄膜晶体管包括多晶硅层；a thin film transistor disposed on the buffer layer, the thin film transistor including a polysilicon layer;
    其中，所述多晶硅层由晶块组成，相邻的所述晶块之间存在凸起的晶界，所述晶界与所述多晶硅层的边界相垂直，所述晶界所在的直线与所述遮光层边界所在的直线为异面直线。Wherein the polysilicon layer is composed of ingots, and there are convex grain boundaries between the adjacent crystal blocks, the grain boundaries are perpendicular to the boundary of the polysilicon layer, and the straight line where the grain boundaries are located The straight line where the boundary of the shading layer is located is a straight line.
  2. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管为U型薄膜晶体管。The array substrate according to claim 1, wherein the thin film transistor is a U-type thin film transistor.
  3. 根据权利要求1所述的阵列基板，其中，所述缓冲层各区域的厚度相同。The array substrate according to claim 1, wherein each of the buffer layers has the same thickness.
  4. 根据权利要求1所述的阵列基板，其中，所述遮光层的结构为长方体结构和棱台结构的其中一种。The array substrate according to claim 1, wherein the light shielding layer has a structure of one of a rectangular parallelepiped structure and a prismatic structure.
  5. 根据权利要求4所述的阵列基板，其中，所述多晶硅层包括第一多晶硅区域和第二多晶硅区域，所述第一多晶硅区域位于所述遮光层的正上方；The array substrate according to claim 4, wherein the polysilicon layer comprises a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
    其中，所述第一多晶硅区域为直线型结构，所述第一多晶硅区域位于所述遮光层上的投影与所述遮光层的边界相交且不垂直。The first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer intersects a boundary of the light shielding layer and is not perpendicular.
  6. 根据权利要求5所述的阵列基板，其中，所述第一多晶硅区域包括与所述遮光层边界相对应的第一晶界，所述第一晶界位于所述遮光层上的投影与所述遮光层的边界相交。The array substrate according to claim 5, wherein the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer, and a projection of the first grain boundary on the light shielding layer The boundaries of the light shielding layer intersect.
  7. 根据权利要求1所述的阵列基板，其中，所述遮光层包括第一边界、第二边界、第三边界和第四边界；The array substrate according to claim 1, wherein the light shielding layer comprises a first boundary, a second boundary, a third boundary, and a fourth boundary;
    其中，所述第一边界和所述第二边界相对设置，所述第三边界和所述第四边界相对设置。The first boundary and the second boundary are oppositely disposed, and the third boundary and the fourth boundary are oppositely disposed.
  8. 根据权利要求7所述的阵列基板，其中，所述第一边界与所述第二边界为直线状，所述第三边界和所述第四边界为非直线状。The array substrate according to claim 7, wherein the first boundary and the second boundary are linear, and the third boundary and the fourth boundary are non-linear.
  9. 根据权利要求8所述的阵列基板，其中，所述多晶硅层包括第一多晶硅区域和第二多晶硅区域，所述第一多晶硅区域位于所述遮光层的正上方；The array substrate according to claim 8, wherein the polysilicon layer comprises a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
    其中，所述第一多晶硅区域为直线型结构，所述第一多晶硅区域位于所述遮光层上的投影与所述遮光层的第一边界相平行。The first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer is parallel to a first boundary of the light shielding layer.
  10. 根据权利要求9所述的阵列基板，其中，所述第一多晶硅区域包括与所述遮光层边界相对应的第一晶界，所述第一晶界位于所述遮光层上的投影与所述第三边界和第四边界相交。The array substrate according to claim 9, wherein the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer, and a projection of the first grain boundary on the light shielding layer The third boundary and the fourth boundary intersect.
  11. 一种显示面板，其包括彩膜基板和阵列基板，所述阵列基板包括：A display panel includes a color filter substrate and an array substrate, the array substrate comprising:
    衬底基板；Substrate substrate;
    设置在所述衬底基板表面的遮光层；a light shielding layer disposed on a surface of the base substrate;
    设置在所述衬底基板和所述遮光层上方的缓冲层；a buffer layer disposed above the base substrate and the light shielding layer;
    设置在所述缓冲层上的薄膜晶体管，所述薄膜晶体管包括多晶硅层；a thin film transistor disposed on the buffer layer, the thin film transistor including a polysilicon layer;
    其中，所述多晶硅层由晶块组成，相邻的所述晶块之间存在凸起的晶界，所述晶界与所述多晶硅层的边界相垂直，所述晶界所在的直线与所述遮光层边界所在的直线为异面直线。Wherein the polysilicon layer is composed of ingots, and there are convex grain boundaries between the adjacent crystal blocks, the grain boundaries are perpendicular to the boundary of the polysilicon layer, and the straight line where the grain boundaries are located The straight line where the boundary of the shading layer is located is a straight line.
  12. 根据权利要求11所述的显示面板，其中，所述薄膜晶体管为U型薄膜晶体管。The display panel according to claim 11, wherein the thin film transistor is a U-type thin film transistor.
  13. 根据权利要求11所述的显示面板，其中，所述缓冲层各区域的厚度相同。The display panel according to claim 11, wherein each of the buffer layers has the same thickness.
  14. 根据权利要求11所述的显示面板，其中，所述遮光层的结构为长方体结构和棱台结构的其中一种。The display panel according to claim 11, wherein the structure of the light shielding layer is one of a rectangular parallelepiped structure and a prismatic structure.
  15. 根据权利要求14所述的显示面板，其中，所述多晶硅层包括第一多晶硅区域和第二多晶硅区域，所述第一多晶硅区域位于所述遮光层的正上方；The display panel according to claim 14, wherein the polysilicon layer comprises a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
    其中，所述第一多晶硅区域为直线型结构，所述第一多晶硅区域位于所述遮光层上的投影与所述遮光层的边界相交且不垂直。The first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer intersects a boundary of the light shielding layer and is not perpendicular.
  16. 根据权利要求15所述的显示面板，其中，所述第一多晶硅区域包括与所述遮光层边界相对应的第一晶界，所述第一晶界位于所述遮光层上的投影与所述遮光层的边界相交。The display panel according to claim 15, wherein the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer, and a projection of the first grain boundary on the light shielding layer The boundaries of the light shielding layer intersect.
  17. 根据权利要求11所述的显示面板，其中，所述遮光层包括第一边界、第二边界、第三边界和第四边界；The display panel according to claim 11, wherein the light shielding layer includes a first boundary, a second boundary, a third boundary, and a fourth boundary;
    其中，所述第一边界和所述第二边界相对设置，所述第三边界和所述第四边界相对设置。The first boundary and the second boundary are oppositely disposed, and the third boundary and the fourth boundary are oppositely disposed.
  18. 根据权利要求17所述的显示面板，其中，所述第一边界与所述第二边界为直线状，所述第三边界和所述第四边界为非直线状。The display panel according to claim 17, wherein the first boundary and the second boundary are linear, and the third boundary and the fourth boundary are non-linear.
  19. 根据权利要求18所述的显示面板，其中，所述多晶硅层包括第一多晶硅区域和第二多晶硅区域，所述第一多晶硅区域位于所述遮光层的正上方；The display panel according to claim 18, wherein the polysilicon layer comprises a first polysilicon region and a second polysilicon region, the first polysilicon region being located directly above the light shielding layer;
    其中，所述第一多晶硅区域为直线型结构，所述第一多晶硅区域位于所述遮光层上的投影与所述遮光层的第一边界相平行。The first polysilicon region is a linear structure, and a projection of the first polysilicon region on the light shielding layer is parallel to a first boundary of the light shielding layer.
  20. 根据权利要求19所述的显示面板，其中，所述第一多晶硅区域包括与所述遮光层边界相对应的第一晶界，所述第一晶界位于所述遮光层上的投影与所述第三边界和第四边界相交。The display panel according to claim 19, wherein the first polysilicon region includes a first grain boundary corresponding to a boundary of the light shielding layer, and a projection of the first grain boundary on the light shielding layer The third boundary and the fourth boundary intersect.
PCT/CN2018/123706 2017-12-28 2018-12-26 Array substrate and display panel WO2019129019A1 (en)

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