WO2019128809A1 - Procédé et dispositif de traitement d'informations - Google Patents

Procédé et dispositif de traitement d'informations Download PDF

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Publication number
WO2019128809A1
WO2019128809A1 PCT/CN2018/122127 CN2018122127W WO2019128809A1 WO 2019128809 A1 WO2019128809 A1 WO 2019128809A1 CN 2018122127 W CN2018122127 W CN 2018122127W WO 2019128809 A1 WO2019128809 A1 WO 2019128809A1
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correction value
spreading factor
information
factor
check matrix
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PCT/CN2018/122127
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English (en)
Chinese (zh)
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张朝龙
王坚
乔云飞
张公正
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华为技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes

Definitions

  • the present application relates to the field of information processing, and in particular, to a method and apparatus for processing information.
  • Low density parity check is a class of linear block codes with sparse check matrices proposed by Dr. Robert G. Gallage in 1963. Because LDPC codes not only have good performance close to the Shannon limit, but also have the advantages of low decoding complexity and flexible structure, they have been widely used in many fields in recent years.
  • the quasi-cyclic low-density parity check (QC-LDPC) is an LDPC code with a quasi-cyclic structure, which is a subclass of the LDPC code, because of its simple description, easy construction, and saving. The advantages of storage space have become a research hotspot in the field of channel coding in recent years.
  • the construction process of the QC-LDPC code is the construction process of the parity check matrix of the QC-LDPC code.
  • the check matrix of QC-LDPC is obtained by extending the base matrix by a spreading factor on the basis of a base matrix.
  • many existing methods for constructing the QC-LDPC check matrix inevitably have error leveling.
  • the error leveling layer is a key factor that causes the decoding performance to be low in the actual application process of QC-LDPC.
  • the present application provides a method and apparatus for processing information, and the QC-LDPC constructed by the method helps to reduce the error leveling layer occurring in the decoding process, thereby improving the decoding performance.
  • the present application provides a method for processing information, the method comprising: determining a first spreading factor and a correction value of a first spreading factor; determining a check matrix according to the first spreading factor and the modified value; using a school
  • the proof matrix encodes a sequence of information of length K, which is a positive integer.
  • the method for processing information in the embodiment of the present application may correct the spreading factor corresponding to the length K of the information sequence in which the error leveling occurs when determining the spreading factor Z of the QC-LDPC check matrix, so as to skip the error level.
  • the position of the layer can thus improve the decoding performance of the QC-LDPC.
  • the correction value of the first spreading factor is related to the length K of the information sequence.
  • the length K of the information sequence and the correction value of the first spreading factor satisfy at least one of the following table:
  • the length K of the information sequence and the correction value of the first spreading factor satisfy at least one of the following tables:
  • determining the correction value of the first spreading factor comprises determining a correction value of the first spreading factor based on the length K of the information sequence and the code rate R. That is to say, the correction value of the first spreading factor can be related to the length K of the information sequence and the code rate R. A more refined correction can be achieved by determining the correction value of the first spreading factor in combination with K and the code rate R as compared to determining the correction value of the first spreading factor based only on the length K of the information sequence.
  • the length K of the information sequence, the correction value of the first spreading factor, and the code rate R satisfy at least one of the following tables:
  • the information sequence K, the correction value of the first spreading factor, and the code rate R satisfy at least one of the following tables:
  • the value range (0, 1) of the code rate R can be divided into six sections.
  • the correction value of the first spreading factor can be determined from the above table regardless of the actual code rate. In this way, according to the interval in which the actually used code rate falls, the first spreading factor is corrected by using the correction value corresponding to the interval, so that the finer correction of the spreading factor of the check matrix can be realized, and the decoding of the LDPC is further improved. performance.
  • the present application provides an apparatus for processing information having the functionality to implement the method of any of the above-described first aspects and any one of the possible implementations of the first aspect.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more units corresponding to the functions described above.
  • the apparatus includes a processing unit, the processing unit is configured to: determine a correction factor of the first spreading factor and the first spreading factor; determine a check matrix according to the first spreading factor and the corrected value of the first spreading factor; use a check matrix pair A sequence of information of length K is encoded, and K is a positive integer.
  • the apparatus may further include a receiving unit, configured to receive the information sequence of length K to be encoded.
  • the apparatus for processing information in the second aspect may be a terminal or a base station.
  • the QC-LDPC constructed by the apparatus for processing information provided by the embodiment of the present application helps to reduce the error leveling layer occurring in the decoding process, thereby improving the decoding performance.
  • the present application provides a computer readable storage medium having stored therein computer instructions that, when executed on a computer, cause the computer to perform any of the first aspect or the first aspect described above The method in the implementation.
  • the present application provides a chip (or a chip system) including a memory and a processor for storing a computer program, the processor for calling and running the computer program from the memory, so that the communication with the chip is installed
  • a chip or a chip system
  • the apparatus performs the method of the first aspect above and any one of its possible implementations.
  • the application provides a computer program product, comprising: computer program code, when the computer program code is run on a computer, causing the computer to perform the first aspect and any one possible implementation thereof The method in .
  • the present application provides a method for processing information, the method comprising: determining a first spreading factor and a correction value of a first spreading factor; determining a check matrix according to a first spreading factor and a modified value of the first spreading factor
  • the decoding sequence is used to decode the decoded sequence.
  • the process of determining the check matrix by the decoding end is the same as that of the transmitting end. Therefore, the relationship between the correction value of the first spreading factor and the length K of the information sequence described in any one of the possible implementation manners of the first aspect, or the correction value of the first spreading factor, the length K of the information sequence, and The relationship satisfied between the code rates R is also applicable in the method of processing information of the sixth aspect. For the sake of brevity, it will not be repeated here.
  • the QC-LDPC constructed by the method for processing information provided by the present application helps to reduce the error leveling layer occurring in the decoding process, thereby improving the decoding performance.
  • the present application provides an apparatus for processing information, the apparatus having the function of implementing the method in any of the above-described sixth aspects and any one of the possible implementations of the sixth aspect.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more units corresponding to the functions described above.
  • the apparatus includes a processing unit, the processing unit is configured to: determine a correction value of the first spreading factor and the first spreading factor; determine a check matrix according to the first spreading factor and the corrected value of the first spreading factor; The decoding sequence is decoded.
  • the apparatus for processing information in the seventh aspect may be a terminal or a base station.
  • the present application provides a computer readable storage medium having stored therein computer instructions that, when executed on a computer, cause the computer to perform any of the foregoing sixth or sixth aspects The method in the implementation.
  • the present application provides a chip (or a chip system) including a memory and a processor for storing a computer program, the processor for calling and running the computer program from the memory such that communication of the chip is installed
  • a chip or a chip system
  • the processor for calling and running the computer program from the memory such that communication of the chip is installed
  • the apparatus performs the method of the sixth aspect described above and any one of its possible implementations.
  • the application provides a computer program product, comprising: computer program code, when the computer program code is run on a computer, causing the computer to perform the sixth aspect and any possible implementation thereof The method in .
  • the method for processing information in the embodiment of the present application corrects the expansion factor (ie, the first spreading factor) of the check matrix, so that the check matrix used for encoding skips the position of the error leveling layer, thereby Improve decoding performance.
  • the expansion factor ie, the first spreading factor
  • FIG. 1 is a wireless communication system 100 suitable for use in an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a check matrix for constructing an LDPC based on a matrix.
  • FIG. 4 is a schematic flowchart of a method 200 of encoding according to an embodiment of the present application.
  • Figure 5 is a schematic diagram of BLER derived from the BG2 matrix and LOMS algorithm in NR.
  • 6 to 11 are examples of determining whether or not there is an error leveling layer based on a performance curve.
  • FIG. 12 is a schematic block diagram of an apparatus 600 for processing information according to an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of an apparatus 700 for processing information according to an embodiment of the present application.
  • FIG. 14 is a schematic block diagram of an apparatus 800 for processing information according to an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of an apparatus 900 for processing information according to an embodiment of the present application.
  • FIG. 1 is a wireless communication system 100 suitable for use in an embodiment of the present application.
  • the wireless communication system can include at least one network device 101 in communication with one or more terminal devices (e.g., terminal device 102 and terminal device 103 shown in FIG. 1).
  • the network device may be a base station, or may be a device integrated with the base station controller, or may be another device having similar communication functions.
  • the terminal is a device having a communication function, and may include a handheld device having a wireless communication function, an in-vehicle device, a wearable device, a computing device, or other processing device connected to the wireless modem.
  • the terminals can be deployed on land, including indoors or outdoors, handheld or on-board; they can also be deployed on the water (such as ships, etc.); they can also be deployed in the air (such as airplanes, balloons, satellites, etc.).
  • the terminal may be a mobile phone, a tablet, a computer with wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, industrial control (industrial) Wireless terminal in control), wireless terminal in self driving, wireless terminal in remote medical, wireless terminal in smart grid, wireless in transport safety A terminal, a wireless terminal in a smart city, a wireless terminal in a smart home, and the like.
  • Terminals can be called different names in different networks, such as: user equipment, mobile stations, subscriber units, stations, cellular phones, personal digital assistants, wireless modems, wireless communication devices, handheld devices, laptops, cordless phones, Wireless local loop station, etc.
  • the present application is simply referred to as a terminal.
  • a base station which may also be called a base station device, is a device deployed in a radio access network to provide wireless communication functions.
  • the name of a base station may be different in different wireless access systems.
  • a base station is called a Node B
  • a base station in an LTE network is called a base station.
  • a base station in an LTE network is called a base station.
  • a base station in an LTE network is called a base station.
  • a base station in a new radio (NR) network is called a transmission reception point (TRP) or a generation node B (gNB).
  • TRP transmission reception point
  • gNB generation node B
  • other base stations may be used in other networks where multiple technologies are converged, or in other various evolved networks. The invention is not limited to this.
  • the wireless communication system mentioned in the embodiments of the present application includes, but is not limited to, a narrow band-Internet of things (NB-IoT), a global system for mobile communications (GSM), and an enhanced data rate.
  • GSM evolution EDGE
  • WCDMA wideband code division multiple access
  • CDMA2000 code division multiple access
  • TD-SCDMA time division synchronization code
  • LTE long term evolution
  • 5G mobile communication systems namely enhanced mobile broadband (eMBB) ), ultra reliable low latency communication (URLLC) and enhanced mass machine type communication (eMTC) or new communication systems that will emerge in the future.
  • eMBB enhanced mobile broadband
  • URLLC ultra reliable low latency communication
  • eMTC enhanced mass machine type communication
  • the network device in FIG. 1 communicates with the terminal device using wireless technology.
  • the network device sends a signal, it is the encoding end.
  • the network device receives the signal, it is the decoding end.
  • the terminal device is also the same.
  • the terminal device sends a signal, it is the encoding end.
  • the terminal device receives the signal, it is the decoding end.
  • the encoding end is the information and/or data transmitting end
  • the decoding end is the receiving end of the information and/or data.
  • Low density parity check is a kind of linear block code with sparse check matrix, which means that the check matrix of LDPC code has far more zero elements than non-zero elements, and non-zero elements. The distribution is irregular.
  • a linear block code whose code length is equal to N and whose length of the information sequence is equal to K can be uniquely determined by its check matrix.
  • LDPC codes not only have good performance close to the Shannon limit, but also have low decoding complexity and flexible structure. They are hotspots in the field of channel coding in recent years, and have been widely used in deep space communication, optical fiber communication, satellite digital video and audio broadcasting. And other fields.
  • a quasi-cyclic low density parity check is a subclass of LDPC.
  • the parity check matrix of the QC-LDPC is obtained by expanding a base matrix.
  • the base matrix is denoted as H b
  • the parity check matrix is denoted as H.
  • the position of the non-zero element in the base matrix for example, the row and column where the non-zero element is located, can be described by a base graph (BG).
  • the size of the base matrix H b is m b ⁇ n b
  • the size of the check matrix H is (m b ⁇ Z) ⁇ (n b ⁇ Z), where Z is called the spreading factor of the check matrix.
  • each element of the check matrix H Is a zero matrix or cyclic shift matrix, wherein the cyclic shift matrix is obtained by cyclically shifting the a ij bit of the unit matrix I of the Z ⁇ Z size. Therefore, a ij is also referred to as the shift factor of the cyclic shift matrix, and in some examples, a ij can also be expressed as P i,j .
  • the range of a ij is -1 ⁇ a ij ⁇ Z.
  • each information bit position after expansion is used to place information bits. If K is not divisible by k b , resulting in Z ⁇ k b >K, there will be (Z ⁇ k b -K) redundant information bit positions in the parity check matrix H of the extended LDPC, which may be referred to as padding bits.
  • FIG. 2 is a schematic diagram of a check matrix for constructing an LDPC based on a matrix.
  • A represents the number of bits shifted and I is the identity matrix.
  • a linear block code having a code length of N and a number of information bits K can be defined by a generator matrix G K ⁇ N .
  • the information sequence S L ⁇ K to be encoded is mapped to the code words by the generator matrix G K ⁇ N .
  • the linear block code can also be equivalently described by a check matrix H (NK) ⁇ K.
  • the determined expansion factor Z must satisfy the expression (2), and the value of Z must fall into Table 1.
  • the index corresponding to the value of Z (corresponding to the value of set indexi LS in Table 1) is determined.
  • the index corresponding to 72 is 5.
  • an index corresponding to the value of Z is obtained.
  • the extension factor Z is determined, and the corresponding value of the set index i LS is obtained.
  • a check matrix is determined based on the value.
  • Table 2 is an example of a check matrix. The check matrix can be determined by querying Table 2 below.
  • the first column and the second column are respectively a row index and a column index of a non-zero element, which can be used as information of the base map, and are represented here as H BG .
  • each non-zero element has a corresponding value V i,j .
  • the shift factor P i,j mod(V i,j ,Z) is correspondingly shifted.
  • each non-zero element may be replaced by a Z ⁇ Z-sized cyclic shift matrix to obtain a check matrix, where each cyclic shift matrix is a non-zero of the unit matrix I according to the position.
  • the shift factor of the element is obtained by cyclic shifting.
  • the LDPC compared with the polarization code (ie, Polar code), the LDPC exhibits a relatively significant error leveling layer when the BLER is less than 10 -4 .
  • N is the length after encoding.
  • FIG. 3 is a graph of BLER obtained by iterating 20 times according to the BG2 matrix and (layered offset min-sum, LOMS) decoding algorithm.
  • the BG2 matrix is the matrix HBG defined in Table 2 above.
  • the LOMS decoding algorithm is one of the decoding algorithms of the LDPC.
  • the common LDPC decoding algorithms are evolved based on a message passing algorithm, which is also called a belief propagation algorithm.
  • the LOMS decoding algorithm is a variant of the message passing algorithm, which is characterized by iterative calculation between the check node and the bit node (also called a variable node). Details regarding the LOMS algorithm and the check nodes and bit nodes can be referred to the prior art and will not be described in detail herein.
  • the decoding performance curve is usually divided into two regions: a low/medium signal to noise ratio region and a high signal to noise ratio region.
  • the decisive factor causing the error is that the signal-to-noise ratio is too low. Due to insufficient signal strength, a large number of erroneous bits occur and the bit error rate is high.
  • the high signal-to-noise ratio region the signal strength is already large enough, and decoding failures are still mainly caused by trap sets.
  • the concept of trap sets can be referred to the prior art and will not be described in detail herein.
  • the error leveling layer refers to a sudden decrease in the error performance curve from the low/medium channel to the high signal to noise ratio region.
  • bit error rate is required to be extremely low, such as data storage and optical communication systems, requiring bit error rates below 10 -12 to 10 -15 . Therefore, how to reduce the error leveling of LDPC codes is one of the key issues in practical applications of LDPC.
  • the present application proposes a method of information processing.
  • the LDPC constructed by this method helps to reduce the error leveling layer occurring in the decoding process, so as to improve the decoding performance of the LDPC.
  • FIG. 4 is a schematic flowchart of a method 200 for processing information according to an embodiment of the present application.
  • Method 200 can be performed by a sender of information and/or data.
  • the sender of information and/or data can also be considered as the encoding end.
  • it is executed by the terminal device 102 in the uplink transmission scenario shown in FIG. 1.
  • it can be performed by the network device 101 in the downlink transmission scenario shown in FIG.
  • the first spreading factor here refers to the spreading factor of the check matrix of the LDPC, that is, the spreading factor Z described above.
  • whether the modification of the first spreading factor needs to be performed may be determined according to the length K of the information sequence.
  • the expansion factor before the correction is referred to as a first expansion factor
  • the expansion factor after correction is referred to as a second expansion factor.
  • the length K of the information sequence has an error leveling layer on some values, and the expansion factor corresponding to the length K of these information sequences can be corrected.
  • a comparison of these slopes is compared to a predetermined decision threshold to determine if there is an error leveling.
  • the change in these slopes is compared to a predetermined decision threshold. If the change in slope is greater than or equal to the predetermined decision threshold, then an error leveling is considered. If the change in slope is less than the preset decision threshold, then there is no error leveling.
  • the decision threshold is an integer greater than 1, for example, 1.1, 1.2, 1.3, 1.4, 1.5, and the like. Among them, the decision threshold is set according to the strictness of the judgment. If the decision to level the error is relatively strict, the decision threshold can be set higher. If the decision to level the error is relatively loose, the decision threshold can be set lower.
  • whether the length K of the information sequence has an error leveling layer is for a certain BLER. In other words, it is judged whether or not the length K of the information sequence has an error leveling layer, that is, whether or not the length K of the information sequence has an error leveling layer at a certain BLER.
  • K [40,48,56 64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,224,240,256,272,288,304,320,336,352,368,384,400, 424, 448,472, 688, 520, 544, 568, 592, 624, 688, 688, 720, 752, 784, 824, 864, 944, 1000, 1048, 1080, 1144, 1176, 1208, 1240, 1272 , 1304, 1336, 1368, 1432, 1496, 1560, 1624, 1688, 1752, 1816, 1880, 1944, 2040, 2104, 2168, 2232, 2296, 2424, 2488, 2552, 2616, 2680, 2744, 2808, 2872 , 2992, 3120, 3256, 3384, 3512, 3640, 3768,
  • 0 in the table indicates that there is no error leveling layer
  • 1 in the table indicates that there is an error leveling layer
  • Fig. 6 is an example of determining whether or not there is an error leveling layer based on a performance curve.
  • SNR signal-to-noise ratio
  • the spike in Figure 5 means that an error leveling has occurred.
  • the fitting can be performed at a performance curve corresponding to each code rate. The raw data is then compared to the fitted data for comparison. If the difference exceeds the preset decision threshold, then an error leveling is considered.
  • the length K of the sequence of information in Figures 6-11 includes check bits.
  • the parity bit is 24 bits.
  • the decision threshold is related to the degree of rigor of the decision leveling layer. Therefore, whether the length K of the information sequence has an error leveling layer at a certain BLER is related to the size of the set decision threshold value.
  • the present application does not limit the method of determining which level of error is to be used. In other words, any method of determining the error leveling layer can be used, and in the case where there is an error leveling layer, the expansion factor of the check matrix can be corrected using the method of the present application to minimize the error level. Floor.
  • the transmitting end may determine the first spreading factor by the process of determining the spreading factor of the check matrix in the NR described above. That is, the first spreading factor is determined based on the length K of the information sequence.
  • the correction value of the first spreading factor may be related to the length of the information sequence. Alternatively, it may be related to the length K of the information sequence and the code rate R. In a possible implementation manner, the correction value of the first expansion factor may be determined by looking up a table.
  • At least one of the following Table 7 may be satisfied between the correction value of K and the first spreading factor.
  • Length of information sequence K Correction value of the first expansion factor 96 1 152 1 176 1 272 2 304 2 368 2 400 3
  • At least one of the following Table 8 may be satisfied between the correction value of K and the first spreading factor.
  • Tables 7 and 8 are mainly corrected for the length K of the information sequence. Further, in order to achieve finer adjustment, the first spreading factor may be corrected in conjunction with the code rate R with reference to Tables 7 and 8, instead of only correcting for the K pair.
  • the value of the code rate R is 0 ⁇ R ⁇ 1, and therefore, the interval (0, 1) of the six code rates shown in Table 9 can be divided into six intervals, each of which corresponds to one correction value.
  • the first spreading factor is corrected by using the correction value corresponding to the interval. See Table 10.
  • the first expansion factor is corrected by using the correction value of the first expansion factor to obtain the modified expansion factor.
  • the first spreading factor can be added to the corrected value to obtain a modified spreading factor.
  • it may be another correction method.
  • the check matrix is determined using the second spreading factor.
  • the process of determining the check matrix according to the second spreading factor is the same as the process of the step (3) in the flow of determining the check matrix by the lookup table 2 according to the spreading factor Z in the NR described above. In order to avoid redundancy, it will not be described in detail here.
  • the value of the second spreading factor may be directly subjected to a residual operation to determine the check matrix.
  • Step 240 can be seen in the prior art and will not be described in detail herein.
  • the transmitting end may send the encoded codeword to the receiving end.
  • the receiving end receives the sequence to be decoded, and determines the check matrix H in the same manner as the transmitting end. Finally, the receiving end decodes the sequence to be decoded using the check matrix to obtain a decoded sequence.
  • the position of the erroneous leveling layer is skipped, thereby improving the decoding performance.
  • skipping the position with the wrong leveling layer only increases the number of puncturing bits in the check matrix without any other influence, so there is no other performance loss. .
  • FIG. 12 is a schematic block diagram of an apparatus 600 for processing information according to an embodiment of the present application.
  • the device 600 mainly includes a processing unit 610 and a transmitting unit 620.
  • the processing unit 610 is configured to:
  • the information sequence of length K is encoded using a check matrix, and K is a positive integer.
  • the sending unit 620 is configured to send the encoded codeword.
  • processing unit 610 when used for encoding, it may also be referred to as a coding unit.
  • the apparatus 600 when part or all of the functions of the apparatus 600 are implemented by hardware, the apparatus 600 includes: an input interface circuit for acquiring a sequence of information; and logic circuitry for determining the first spreading factor and the first extension The correction value of the factor, the check matrix is determined according to the first spreading factor and the correction value, and the information sequence of length K is encoded according to the check matrix, K is a positive integer; and the output interface circuit is configured to output the encoded codeword.
  • the device 600 when the above functions of the device 600 are all implemented by hardware, the device 600 includes: a memory for storing a program; a processor for executing the program stored by the memory when the program is executed Apparatus 600 may implement the method of processing information as described in any of the possible designs above.
  • device 600 can be a chip or an integrated circuit.
  • device 600 when some or all of the above functions of device 600 are implemented by software, device 600 includes a processor and a memory.
  • the processor implements the above described functions of device 800 by reading stored software code in memory.
  • the above described memory and memory may be physically separate units, or the memory may be integrated with the processor.
  • FIG. 13 is a schematic structural diagram of an apparatus 700 for processing information according to an embodiment of the present application.
  • device 700 includes one or more processors 701, one or more memories 702.
  • device 700 may also include one or more transceivers 703.
  • the processor 701 is configured to control the transceiver 703 to send and receive signals
  • the memory 702 is used to store a computer program
  • the processor 701 is configured to call and run the computer program from the memory 702, so that the device 700 performs the corresponding process of processing information of the embodiment of the present application. And / or operation. I will not repeat them here.
  • processing unit 610 can be implemented by processor 701
  • transmitting unit 620 can be implemented by transceiver 703, and the like.
  • the present application provides a computer readable storage medium having stored therein computer instructions that, when executed on a computer, cause the computer to perform processing information as described in any one of the embodiments herein method.
  • the present application also provides a computer program product comprising computer program code for causing a computer to perform a method of processing information as described in any one of the embodiments of the present application when the computer program code is run on a computer.
  • the present application also provides a chip (or a chip system) including a memory and a processor for storing a computer program, the processor for calling and running the computer program from the memory, such that the communication device on which the chip is mounted executes the program A method of processing information of an embodiment is applied.
  • the communication device described herein may be the transmitting end or the encoding end of the information.
  • the terminal device in uplink transmission, is equipped with the chip to encode the information sequence, such as the terminal device 102 shown in FIG.
  • the network device 101 At the time of downlink transmission, the network device 101 is equipped with the chip to encode the information sequence.
  • FIG. 14 is a schematic block diagram of an apparatus 800 for processing information according to an embodiment of the present application.
  • the device 800 mainly includes a receiving unit 810 and a processing unit 820.
  • the receiving unit 810 is configured to receive a sequence to be decoded.
  • the processing unit 820 is configured to determine a correction value of the first spreading factor and the first spreading factor; determine a check matrix according to the first spreading factor and the modified value of the first spreading factor; and decode the sequence to be decoded using the check matrix.
  • processing unit 820 when used for decoding, it may also be referred to as a decoding unit (or a decoding unit).
  • the device 800 referred to herein may be the receiving end or the decoding end of the information.
  • the device 800 when uplinking, the device 800 may be the network device 101, and decode the received information (or the sequence to be decoded) from the terminal device 102.
  • the device 800 In the downlink transmission, the device 800 may be the terminal device 103, which decodes the received information from the network device 101.
  • device 800 when some or all of the described functions of device 800 are implemented in hardware, device 800 may be a logic circuit, an integrated circuit, or the like.
  • the apparatus 800 includes: an input interface circuit, configured to acquire a sequence to be decoded; a logic circuit, configured to determine a first spreading factor and a correction value of the first spreading factor, and determine a check matrix according to the first spreading factor and the modified value, And decoding the sequence to be decoded according to the check matrix; and outputting an interface circuit for outputting the decoded sequence.
  • the device 800 when the above-described functions of the device 800 are all implemented by hardware, the device 800 includes: a memory for storing a program; a processor for executing the program stored by the memory when the program is executed Apparatus 800 can implement a process for decoding a sequence to be decoded.
  • device 800 can be a chip or an integrated circuit.
  • device 800 when some or all of the above described functions of device 800 are implemented in software, device 800 includes a processor and a memory.
  • the processor implements the above described functions of device 800 by reading stored software code in memory.
  • the memory can be integrated in the processor or external to the processor.
  • FIG. 15 is a schematic structural diagram of an apparatus 900 for processing information according to an embodiment of the present application.
  • device 900 includes one or more processors 901, one or more memories 902.
  • device 900 may also include one or more transceivers 903.
  • the processor 901 is configured to control the transceiver 903 to send and receive signals
  • the memory 902 is used to store a computer program
  • the processor 901 is configured to call and run the computer program from the memory 902, such that the device 900 performs a corresponding process of decoding the sequence to be coded. And / or operation. I will not repeat them here.
  • receiving unit 810 can be implemented by transceiver 903
  • processing unit 820 can be implemented by processor 901, and the like.
  • the present application provides a computer readable storage medium having stored therein computer instructions for causing a computer to perform decoding of a sequence to be decoded in an embodiment of the present application when the computer instruction is run on a computer Corresponding processes and/or operations.
  • the present application also provides a computer program product, comprising: computer program code, when the computer program code is run on a computer, causing the computer to perform a corresponding process of decoding the sequence to be decoded in the embodiment of the present application and/or Or operation.
  • the present application also provides a chip (or a chip system) including a memory and a processor for storing a computer program, the processor for calling and running the computer program from the memory, such that the communication device on which the chip is mounted executes the program
  • a chip or a chip system
  • the processor for calling and running the computer program from the memory, such that the communication device on which the chip is mounted executes the program
  • the communication device described herein may be the receiving end or the decoding end of the information.
  • the network device 101 is installed with the chip.
  • the terminal device 103 is mounted with the chip.
  • the processor may be a central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more programs for controlling the program of the present application. Execution of integrated circuits, etc.
  • the processor can include a digital signal processor device, a microprocessor device, an analog to digital converter, a digital to analog converter, and the like.
  • the processor can distribute the control and signal processing functions of the mobile device among the devices according to their respective functions.
  • the processor can include functionality to operate one or more software programs, which can be stored in memory.
  • the functions of the processor may be implemented by hardware or by software executing corresponding software.
  • the hardware or software includes one or more units corresponding to the functions described above.
  • the memory can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of information and instructions that can be stored. Dynamic storage device. It can also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, and a disc storage (including a compact disc, a laser disc, a compact disc, a digital versatile disc, a Blu-ray disc, etc.), a disk storage medium or other magnetic storage device, or any other device that can be used to carry or store desired program code in the form of an instruction or data structure and accessible by a computer. Medium, but not limited to this.
  • EEPROM electrically erasable programmable read-only memory
  • CD-ROM compact disc read-only memory
  • disc storage including a compact disc, a laser disc, a compact disc, a digital versatile disc, a Blu-ray disc, etc.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present application which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

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  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

La présente invention concerne un procédé de traitement d'informations, et un QC-LDPC construit par le procédé qui aide à réduire une couche d'erreur qui se produit pendant un décodage et à améliorer encore la performance de décodage. Le procédé consiste à : déterminer un premier facteur d'extension et une valeur de correction du premier facteur d'extension ; déterminer une matrice de contrôle conformément au premier facteur d'extension et à la valeur de correction du premier facteur d'extension ; et coder une séquence d'informations de longueur K à l'aide de la matrice de contrôle.
PCT/CN2018/122127 2017-12-29 2018-12-19 Procédé et dispositif de traitement d'informations WO2019128809A1 (fr)

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