WO2019127416A1 - 连通域检测方法、电路、设备、计算机可读存储介质 - Google Patents

连通域检测方法、电路、设备、计算机可读存储介质 Download PDF

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WO2019127416A1
WO2019127416A1 PCT/CN2017/119971 CN2017119971W WO2019127416A1 WO 2019127416 A1 WO2019127416 A1 WO 2019127416A1 CN 2017119971 W CN2017119971 W CN 2017119971W WO 2019127416 A1 WO2019127416 A1 WO 2019127416A1
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image data
block
type
pixel
data block
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PCT/CN2017/119971
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English (en)
French (fr)
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高明明
李涛
杨康
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深圳市大疆创新科技有限公司
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Priority to PCT/CN2017/119971 priority Critical patent/WO2019127416A1/zh
Priority to CN201780022802.4A priority patent/CN109074654A/zh
Publication of WO2019127416A1 publication Critical patent/WO2019127416A1/zh
Priority to US16/912,008 priority patent/US20200327638A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/20—Analysis of motion
    • G06T7/223—Analysis of motion using block-matching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/10—Segmentation; Edge detection
    • G06T7/11—Region-based segmentation
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/10—Segmentation; Edge detection
    • G06T7/187—Segmentation; Edge detection involving region growing; involving region merging; involving connected component labelling
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    • G06V10/457—Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersections; Connectivity analysis, e.g. of connected components by analysing connectivity, e.g. edge linking, connected component analysis or slices
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    • G06T2207/20—Special algorithmic details
    • G06T2207/20021—Dividing image into blocks, subimages or windows

Definitions

  • the present invention relates to the field of image processing technologies, and in particular, to a connected domain detection method, circuit, device, and computer readable storage medium.
  • Computer vision is a simulation of biological vision using a computer and a camera device. By processing the acquired image to obtain three-dimensional information of the corresponding scene, it is a data on how to use the camera device and the computer to acquire the image of the object.
  • the technology of information is currently widely used.
  • Connected domain detection is a typical application of computer vision. For example, in the processing of depth maps such as BM (Block Matching) and SGBM (Semi-Global Block Matching), communication is performed. Domain detection.
  • BM Block Matching
  • SGBM Semi-Global Block Matching
  • the present invention provides a connected domain detection method, circuit, device, and computer readable storage medium.
  • a first aspect of the present invention provides a connectivity domain detection method, where the method includes:
  • Reading an image data block from a first type of address block of an external storage medium wherein the raw image data is divided into a plurality of image data blocks, and for each image data block, partial line data of the original image data is included, and Each row of data includes partial column data of the original image data;
  • the first type of address block is an arbitrary address block of the external storage medium
  • the second type of address block is any address block of the internal storage medium.
  • a detection circuit configured to:
  • Reading an image data block from a first type of address block of an external storage medium wherein the raw image data is divided into a plurality of image data blocks, and for each image data block, partial line data of the original image data is included, and Each row of data includes partial column data of the original image data;
  • the first type of address block is an arbitrary address block of the external storage medium
  • the second type of address block is any address block of the internal storage medium.
  • a third aspect of the present invention provides a connected domain detecting device, where the connected domain detecting device includes:
  • a memory for storing program code, a detecting circuit for calling the program code, and implementing the connected domain detecting method when the program code is executed.
  • a computer readable storage medium on which a plurality of computer instructions are stored, and when the computer instructions are executed, the connected domain detection method is implemented.
  • the storage resources of the on-chip cache are limited, data is not frequently read from the DDR, the number of data readings is reduced, a large amount of DDR bandwidth is saved, and connectivity performance of the connected domain is improved.
  • the storage resources of the occupied on-chip cache can also be reduced.
  • 1A-1D are schematic diagrams of application scenarios of connected domain detection
  • FIG. 2 is a schematic diagram of an embodiment of a connected domain detection method
  • FIG. 3 is a schematic diagram of another embodiment of a connected domain detection method
  • FIG. 4 is a block diagram of one embodiment of a connected domain detection device.
  • first, second, third, etc. may be used to describe various information in the present invention, such information should not be limited to these terms. These terms are used to distinguish the same type of information from each other.
  • first information may also be referred to as the second information without departing from the scope of the invention.
  • second information may also be referred to as the first information.
  • word “if” may be interpreted as "at time”, or "when", or "in response to determination.”
  • a connected domain detection method for performing connected domain detection on an image. See FIG. 1A, which is an example of an image.
  • this image is referred to as original image data, and original image data. It can be either collected or generated, and there is no limit to this.
  • each square represents a pixel, such as pixel 11, pixel 12, pixel 13, etc.
  • the value of each pixel may include, but is not limited to, pixel value, gray value, RGB (Red Green Blue, red green blue) value, disparity value, etc., there is no limit to this, this value is related to the original image data.
  • RGB Red Green Blue, red green blue
  • disparity value etc.
  • the original image data includes 16 rows of pixels and 12 columns of pixels.
  • the number of rows of original image data is much larger than 16 rows, for example, the number of rows of original image data is 800 rows, and the original image.
  • the number of columns of data is much larger than 12 columns, such as the number of columns of the original image data is 1200 columns.
  • 16 rows of pixels and 12 columns of pixels are taken as an example for description.
  • a gray pixel dot area (such as a pixel 11 , a pixel 12 , a pixel 22 , etc . ) is a connected domain.
  • the following operations may be performed: At pixel A, it is determined whether there are pixel points that meet the requirements in the adjacent pixel points (upper, lower, left, and right) of the pixel point A.
  • the pixel that meets the requirements refers to the effective pixel point (in this paper, all pixels are assumed to be effective pixels, in actual applications, there may be invalid pixels), and the gray value between the gray value and the gray value of the pixel A The difference is less than the threshold (can be configured empirically).
  • the pixel point 11 is selected, and the adjacent pixel point is the pixel point 12 and the pixel point 21, and after judging (such as determination of effective pixel point, determination of threshold value, etc.), the pixel point 12 is a pixel point that meets the requirement, and the pixel point 21 is not A pixel that meets the requirements. Therefore, the pixel point 12 is continuously selected, and the adjacent pixel points are the pixel point 11, the pixel point 13, and the pixel point 22. The pixel point 11 has been judged, and no judgment is made at this time. After the judgment, the pixel point 13 is not a pixel that meets the requirements. Point, pixel 22 is a pixel that meets the requirements.
  • the pixel point 22 is continuously selected, and the adjacent pixel points are the pixel point 12, the pixel point 21, the pixel point 23, and the pixel point 32.
  • the pixel point 12 has been judged, and no judgment is made at this time. After the judgment, the pixel point 21 is not
  • the pixel points that meet the requirements, pixel 23 and pixel 32 are all pixels that meet the requirements.
  • the pixel point 23 and the pixel point 32 are continuously selected, and so on, all the pixel points of the gray pixel dot area are the desired pixel points. Further, the area of the gray pixel area can be calculated. If the area of the area is smaller than the threshold, the gray pixel area is not connected. If the area is larger than the threshold, the gray pixel area is considered to be the connected domain.
  • the original image data can be stored in a DDR (Double Data Rate, Double Rate Synchronous Dynamic Random Access Memory).
  • DDR Double Data Rate, Double Rate Synchronous Dynamic Random Access Memory
  • the original image data can also be stored in other storage media, and no limitation is imposed on the original image.
  • Data storage to DDR is an example.
  • the original image data is stored to the DDR
  • the original image data is stored in rows, for example, the gradation value of the pixel point 11 - the pixel point 1c is sequentially stored, and after the gradation value of the pixel point 1c, the pixel point 21 is sequentially stored.
  • the gradation value of the pixel point 2c after the gradation value of the pixel point 2c, sequentially stores the gradation value of the pixel point 31 - the pixel point 3c, and so on, and finally stores the gradation value of the pixel point gc.
  • the data in the DDR (such as the gray value of each pixel in the original image data) can be read into the on-chip buffer, and the connected domain detection is performed by using the on-chip buffered data.
  • the connected domain detection is implemented by a CPU (Central Processing Unit)
  • the CPU reads the data in the DDR to the on-chip cache of the CPU, and uses the on-chip buffered data for the connected domain detection;
  • the detection circuit reads the data in the DDR to the on-chip buffer of the detection circuit, and uses the on-chip buffered data for the connected domain detection.
  • the traditional connected domain detection mode needs to occupy a large amount of storage resources on the on-chip cache.
  • the traditional connected domain detection mode and processing capability are limited by various factors, which in turn leads to the detection of connected domains.
  • the application scenario of the mode is limited.
  • the on-chip cached storage resource can only store the gray value of 12 pixels. Therefore, when the CPU or the detection circuit reads the data for the first time, it is the gray value of the pixel point 11-pixel point 1c in the DDR. Read out and store the gray value of pixel 11-pixel 1c to its own on-chip buffer.
  • the pixel 12 and the pixel 21 are adjacent pixels. Since the on-chip buffer has the gray value of the pixel 12, determining the pixel 12 by using the gray value of the pixel 12 is satisfactory. pixel. Since there is no gray value of the pixel 21 in the on-chip buffer, the data buffered on the chip can be deleted, and the gray value of the pixel 21-pixel 2c in the DDR is read out, and the pixel 21-pixel 2c is read. The gray value is stored in its own on-chip cache. Thus, since the on-chip buffer has the gradation value of the pixel point 21, the gradation value of the pixel point 21 is used to determine that the pixel point 21 is not a desired pixel point. By analogy, the above operation is performed for each pixel selected.
  • the CPU or the detection circuit needs to frequently read data from the DDR, occupying a large amount of DDR bandwidth, and the connectivity domain detection performance is low.
  • the storage resources of the on-chip cache may be increased. For example, in order to detect the connected domain of the gray pixel dot area, the gray value of all the pixel points may be read from the DDR, so that the storage resource needs to be stored. * Gray value of 12 pixels, which occupies a large amount of storage resources. Obviously, when the original image data has more rows and more columns, more storage resources are needed.
  • the pixel point 13 in order to detect the connected domain of the gray pixel dot area, after the pixel point 12 is selected, the pixel point 13 needs to be judged. Since the pixel point 13 is not a required pixel point, the pixel point 14- The gray value of the pixel 1c has no value, that is, it is not necessary to use the gray value of the pixel 14-pixel 1c. Similarly, it is not necessary to use the gray value of the pixel 29-pixel 2c, the gray value of the pixel 34-pixel 3c, the gray value of the pixel 44-pixel 4c, and so on. No longer. Obviously, there are a large number of pixel points in the original image data that do not need to be judged.
  • the original image data when the original image data is stored to the DDR, the original image data is not stored in a row, but is stored in the image data block.
  • the original image data can be divided into 18 image data blocks, and as shown in FIG. 1C, the original image data is divided into image data blocks 1 - image data blocks 18 .
  • the image data block 1 - image data block 18 can be sequentially stored to the DDR. For example, when the image data block 1 is stored, the gradation value of the pixel point 11 - the pixel point 14 is sequentially stored.
  • the gradation value of the pixel point 14 After the gradation value of the pixel point 14, the gradation value of the pixel point 15 is not stored, but the pixel point is sequentially stored.
  • the image data block 2 is stored, that is, after the gradation value of the pixel point 34, the gradation value of the pixel point 15-pixel point 18 is sequentially stored, and so on, and finally the image data block 1 - the storage of the image data block 18 is completed. Finally, the image data block 18 is stored.
  • the data in the DDR when the data in the DDR is read into the on-chip buffer, the data of the image data block of the DDR (ie, the gray value of each pixel point) can be read, and the read The data is stored to the on-chip cache.
  • the data of the image data block 1 in order to detect the connected domain of the gray pixel dot area, it is only necessary to read the data of the image data block 1, the data of the image data block 2, the data of the image data block 4, and the data of the image data block 7.
  • the data of the image data block 10, the data of the image data block 13, and the data of the image data block 16 are not used to read the data of all the image data blocks.
  • the on-chip cache has limited storage resources, data is not frequently read from the DDR, the number of data reads is reduced, a large amount of DDR bandwidth is saved, and the connectivity performance of the connected domain is improved.
  • the storage resources of the occupied on-chip cache can also be reduced.
  • the on-chip cached storage resource only needs to store the gray value of 4*3*6+4 pixels, which can significantly reduce the occupied storage resources.
  • the CPU or the detection circuit can read more row data and column data in one reading process. Reduce the number of accesses to the DDR by row, such as reading 3 rows * 4 columns of data at a time.
  • the number of rows and columns of the image data block are other values, such as 8 rows * 16 columns, 8 rows * 16 columns of data can be read at a time, that is, a row of DDR access can read 8 rows and 16 columns. The data.
  • the connectivity domain detection method proposed by the present invention is described below.
  • the connectivity domain detection method can be applied to a CPU (implemented by a software method) or to a detection circuit (implemented by a hardware method), which is not limited thereto.
  • a CPU implemented by a software method
  • a detection circuit implemented by a hardware method
  • the following is applied to the detection circuit as an example for description.
  • the detection circuit may include, but is not limited to, an FPGA (Field Programmable Gate Array) chip or an ASIC (Application Specific Integrated Circuit) chip. Of course, other types of chips can also be used, and no limitation is imposed on this.
  • FPGA Field Programmable Gate Array
  • ASIC Application Specific Integrated Circuit
  • the storage medium of the detection circuit may be referred to as an internal storage medium, and the storage medium storing the original image data is referred to as an external storage medium, and the external storage medium is not The storage medium of the detection circuit.
  • the internal storage medium may include, but is not limited to, an on-chip buffer of the detection circuit
  • the external storage medium may include, but is not limited to, a dynamic random access memory, such as the DDR described above, which may also be referred to as an off-chip DDR of the detection circuit.
  • the connected domain detection method in the embodiment of the present invention may include the following steps:
  • step 201 the original image data is divided into a plurality of image data blocks.
  • the dividing the original image data into a plurality of image data blocks comprises: dividing the original image data into a plurality of image data blocks according to a division strategy of M*N (ie, M rows*N columns). Wherein, for each image data block, at most M rows of data of the original image data may be included, and at most N columns of data of the original image data may be included. Further, M is an integer value greater than or equal to 1, N is an integer value greater than or equal to 1, M is smaller than the total number of lines of the original image data, and N is smaller than the total number of columns of the original image data.
  • both M and N can be configured according to experience. There is no limitation on this. As long as M is greater than or equal to 1, it is smaller than the total number of rows of the original image data, and N is greater than or equal to 1, which is smaller than the total number of columns of the original image data. For example, when M is 3 and N is 4, each image data block includes at most 3 lines of data of the original image data, and at most 4 columns of data of the original image data. As shown in FIG. 1C, M is 3. An example of an image data block with N being 4. For another example, when M is 8, and N is 6, each image data block includes at most 8 lines of data of the original image data, and at most 6 columns of data of the original image data.
  • Step 202 The storage space of the external storage medium is divided into a plurality of first type address blocks corresponding to the plurality of image data blocks (for convenience of distinction, each address block in the external storage medium may be referred to as a first type of address block. ), that is, each image data block corresponds to a first type of address block of the external storage medium.
  • the storage space of the external storage medium can be divided into 18 first-class address blocks.
  • the first type of address block 1 is used to store the data of the image data block 1, that is, the first type of address block 1 sequentially stores the gray value of the pixel point 11 - the pixel point 14, and the gray level of the pixel point 21 - the pixel point 24 Value, pixel point 31 - the gray value of pixel point 34.
  • the first type of address block 2 is used to store the data of the image data block 2
  • the first type of address block 3 is used to store the data of the image data block 3, and so on, and will not be described again for other first type of address blocks.
  • the size of each first type of address block is M*N, that is, the gray value of M*N pixels can be stored.
  • the first type of address block 1 - the first type of address block 18 may be 3 * 4.
  • the first type of address block 16 - the first type of address block 18, its size is also 3 * 4, although these first type of address blocks only store 1 * 4 gray values.
  • Step 203 Store each image data block into a first type of address block corresponding to the image data block.
  • the data of the image data block 1 can be stored to the first type of address block 1
  • the data of the image data block 2 can be stored to the first type of address block 2, and so on.
  • the specific storage method refer to the above steps.
  • the detecting circuit adopts an image data block manner, data is read from the first type of address block of the external storage medium, and the data is stored in the internal storage medium, so that the storage space of the internal storage medium can be divided.
  • the second type of address block (for the convenience of distinction, each address block in the internal storage medium can be referred to as a second type of address block), since the image data block is at most M*N, each of the second type of address blocks
  • the size is M*N, that is, the gray value of M*N pixels can be stored.
  • the number of the second type of address blocks is at least one, and is related to the storage resources of the internal storage medium (such as an on-chip cache). Because the storage resources of the internal storage medium are limited, the number of the second type of address blocks in the internal storage medium is Usually smaller than the number of first type of address blocks in the external storage medium.
  • each second type of address block can be 3*4
  • each second type of address block is used to store 12
  • the gray value of the pixel based on which, the storage space of the internal storage medium can be divided into four second type address blocks, and the four second type address blocks can be the second type address block 1 - the second type address respectively.
  • each of the first type of address blocks may be mapped to a second type of address block, ie, each A type of address block has a corresponding second type of address block so that data of the first type of address block can be stored to the second type of address block.
  • the first type of address block 1 can be mapped to the second type of address block 1, so that the data of the first type of address block 1 can be stored to the second type of address block 1.
  • each second type of address block may correspond to one or more The first type of address block, and each of the first type of address blocks may correspond to only one second type of address block.
  • mapping relationship After mapping the first type of address block to the second type of address block, the mapping relationship between the first type of address block and the second type of address block may be obtained, and the first type of address block and the second type of address block are recorded in the mapping table. Mapping relationship.
  • the mapping relationship between the first type of address block and the second type of address block can be configured according to experience. This is not limited.
  • the mapping relationship After the mapping relationship is obtained, the mapping relationship can be recorded in the mapping table, as shown in Table 1. , is an example of a mapping table, and the content of this mapping table is not limited.
  • First class address block Second type of address block 1, 5, 9, 13, 17 1 2, 6, 10, 14, 18 2 3, 7, 11, 15 3 4, 8, 12, 16 4
  • FIG. 3 it is a flowchart of a connected domain detection method, including:
  • Step 301 Read an image data block from a first type of address block of an external storage medium.
  • the original image data is divided into a plurality of image data blocks, and for each image data block, partial line data of the original image data is included, and each line of data includes partial column data of the original image data.
  • the first type of address block is an arbitrary address block of an external storage medium (such as DDR).
  • reading the image data block from the first type of address block of the external storage medium includes: sequentially reading M*N pixels from the start address of the first type of address block of the external storage medium
  • the data and the read data make up the image data block.
  • the M and the N are integer values greater than or equal to 1, and the M is the number of rows of the image data block, and the N is the number of columns of the image data block.
  • the M is smaller than the total number of lines of the original image data, which is smaller than the total number of columns of the original image data.
  • Step 302 Store the read image data block into a second type of address block of the internal storage medium.
  • the second type of address block is an arbitrary address block of an internal storage medium (such as an on-chip cache).
  • the storing the read image data block into the second type of address block of the internal storage medium includes: determining, according to the mapping table, the first type of address block (ie, the first type of address block where the image data block is located) a second type of address block; storing the read image data block to a second type of address block corresponding to the first type of address block; the mapping table is configured to record a mapping relationship between the first type of address block and the second type of address block .
  • storing the read image data block to the second type of address block corresponding to the first type of address block may include: if the second type of address block corresponding to the first type of address block has stored the image data block And deleting the image data block stored in the second type of address block, and storing the read image data block to the second type of address block. If the second type of address block corresponding to the first type of address block does not store an image data block, the read image data block may be directly stored in the second type of address block.
  • Step 303 Perform connectivity domain detection by using image data blocks stored in the second type of address block.
  • the connected domain detection is performed by using the image data block stored in the second type of address block
  • the pixel when the connected domain is detected for the pixel in the image data block stored in the second type of address block, the pixel may be determined.
  • determining the image data block associated with the pixel may include, but is not limited to, the following method: if the last column of data of the current image data block is detected, the image of the next column of the last column of data may be A data block, determined as an image data block associated with the pixel. And/or, if the last row of data of the current image data block is detected, the image data block in which the next row of data of the last row of data is located may be determined as an image data block associated with the pixel.
  • reading the image data block from the first type of address block for storing the image data block may include, but is not limited to, the following method: in the current image data block for performing connected domain detection on the pixel After the detection of the image is completed, the image data block is read from the first type of address block for storing the image data block. Alternatively, after the image data block associated with the pixel is determined, the image data block can be directly read from the first type of address block for storing the image data block.
  • the original image data is divided into a plurality of image data blocks according to a division strategy of M*N (ie, M rows * N columns), if the lowermost image data block and/or the rightmost image data block
  • the boundary is exceeded (that is, the boundary of the original image data), that is, there may be some invalid data.
  • this part of the invalid data is judged according to the size of the image, and does not participate in the connected domain detection.
  • the current comparison position is recorded, and when the position is compared with the size of the image, the boundary of the image cannot be exceeded.
  • the original image data includes 16 rows of pixels and 12 columns of pixels, and the original image data can be divided into 18 image data blocks as shown in FIG. 1C. Since each image data block is 3 rows * 4 columns, in fact, the image data block 16 - the image data block 18 has two rows of data, as shown in FIG. 1D, both rows of data are represented by w, that is, all w is invalid data, and these invalid data can be identified by using the size of the original image data.
  • a gray pixel dot area (such as a pixel 11 , a pixel 12 , a pixel 22 , etc . ) is a connected domain.
  • a gray pixel dot area such as a pixel 11 , a pixel 12 , a pixel 22 , etc .
  • the following operations can be performed:
  • the image data block 1 is read from the first type address block 1 of the external storage medium, the image data block 1 includes 3 lines of data of the original image data, and each line of data includes 4 columns of data of the original image data. Specifically, data of 3*4 pixel points can be sequentially read from the start address of the first type address block 1, and the data is composed into the image data block 1.
  • the first type of address block 1 sequentially stores the gray value of the pixel point 11 - the pixel point 14, the gray value of the pixel point 21 - the pixel point 24, the gray value of the pixel point 31 - the pixel point 34, therefore, from the first
  • the start address of the class address block 1 starts reading data of 3*4 pixels
  • the gradation values of the above-mentioned pixel points can be read, and these gradation values are combined into the image data block 1.
  • the image data block 1 can be stored in the second type of address block 1. Since the second type of address block 1 does not currently store image data blocks, the image data block 1 can be directly stored in the second type of address block 1.
  • the second type address block 1 can store the image data block 1 .
  • the connected domain detection is performed using the image data block 1 stored in the second type address block 1. Specifically, the pixel 11 is selected, and the adjacent pixel is the pixel 12 and the pixel 21. Since the image data block 1 has the pixel 12 and the pixel 21, the new image data block is no longer read from the external storage medium.
  • pixel 12 is a pixel that meets the requirements, and pixel 21 is not a pixel that meets the requirements.
  • the pixel point 12 is selected, and the adjacent pixel points are the pixel point 11, the pixel point 13, and the pixel point 22.
  • the pixel point 11 has been judged, no longer judged, and after the judgment, the pixel point 13 is not a pixel point that meets the requirement, and the pixel point 22 Is the pixel that meets the requirements.
  • the pixel point 22 is selected, and the adjacent pixel points are the pixel point 12, the pixel point 21, the pixel point 23, and the pixel point 32. Since the pixel point 12 and the pixel point 21 have been judged, the pixel is no longer judged, and after the judgment, the pixel is judged. Both point 23 and pixel 32 are pixel points that meet the requirements. Then, the pixel 23 and the pixel 32 can be selected to select the pixel 23 first, and then the pixel 32 is taken as an example for description.
  • the pixel point 23 is selected, and the adjacent pixel points are the pixel point 13, the pixel point 22, the pixel point 24, and the pixel point 33. Since the pixel point 13 and the pixel point 22 have been judged, it is no longer judged, and after judging, the pixel point 24 is judged. It is a pixel that meets the requirements, and pixel 33 is not a pixel that meets the requirements.
  • the pixel 24 is selected, and the adjacent pixel is the pixel 14, the pixel 23, the pixel 25, and the pixel 34. Since the pixel 24 is the last column of data of the current image data block 1, the image data block 2 in which the next column of data of the last column of data is located is determined as the image data block associated with the pixel 11.
  • the image data block 2 can be read directly from the first type of address block 2 of the external storage medium.
  • the image data block 2 can be read from the first type of address block 2 of the external storage medium after the detection of the current image data block 1 is completed.
  • the process is not limited. The following is an example of reading the image data block 2 directly from the first type of address block 2, and then determining the second type of address block 2 corresponding to the first type of address block 2 by querying the table 1.
  • the image data block 2 is stored in the second type of address block 2.
  • the pixel point 25 is a pixel point that meets the requirements, and the pixel point 14 and the pixel point 34 are not the required pixel points.
  • the pixel point 26 is determined to be a pixel point that meets the requirement.
  • the pixel point 27 is determined to be a pixel point that meets the requirement.
  • the pixel 32 is selected. Since the pixel 32 is the last row of data of the current image data block 1, the image data block 4 in which the next row of data is located is determined as the image data block associated with the pixel 11. Then, the image data block 4 is read from the first type of address block 4, and the second type of address block 4 corresponding to the first type of address block 4 is determined by querying the table 1, and the image data block 4 is stored to the second type of address block. 4 in.
  • the pixel point 42 is a pixel point that meets the requirements. Then, after the pixel 42 is selected, it is determined that the pixel 52 is a pixel that meets the requirement. After the pixel 52 is selected, the pixel 62 is determined to be a pixel that meets the requirement.
  • the associated image data block 7 is determined, and the image data block 7 is read from the first type of address block 7, and the second type of address block corresponding to the first type of address block 7 is determined by querying the table 1. 3.
  • the image data block 7 is stored in the second type of address block 3.
  • For pixel 62 it is determined that pixel point 72 is a desired pixel point.
  • the pixel point 82 is a pixel point that meets the requirement.
  • the pixel point 92 is determined to be a pixel point that meets the requirement.
  • the associated image data block 10 is determined, and the image data block 10 is read from the first type of address block 10, and the second type of address block 2 corresponding to the first type of address block 10 is determined by querying the table 1.
  • the image data block 2 stored in the second type address block 2 is deleted, and the image data block 10 is stored in the second type address block 2.
  • pixel 92 it is determined that pixel a2 is a pixel that meets the requirements.
  • the pixel point b2, the pixel point c2, the pixel point d2, the pixel point e2, the pixel point f2, the pixel point g2, and the pixel point g3 are also the required pixel points, and the determination process will not be described again.
  • all the pixels in the gray pixel area are the required pixel points, and then, based on the area of the gray pixel area, it is determined that the gray pixel area is the connected domain.
  • the detecting of the connected domain by using the image data block stored in the second type of address block includes: when performing the connected domain detection on the first pixel in the image data block stored in the second type of address block, The second pixel point associated with the first pixel point may be selected from the image data block; if the state information of the second pixel point exists, the connected domain detection may be performed according to the state information of the second pixel point.
  • the status information may be used to indicate whether the second pixel is detected by the connected domain, and the status information may include that the connected domain is not detected; or the connected domain is detected, and the detection result is disconnected; or has been performed. Connected domain detection, and the test result is connected.
  • performing connectivity domain detection according to the state information of the second pixel includes: if the state information is that connectivity domain detection is not performed, detecting whether the second pixel and the first pixel belong to the same connected domain, and Updating the state information of the second pixel according to the detection result. If the status information is connected domain detection, and the detection result is disconnected, it may be determined that the second pixel point and the first pixel point do not belong to the same connected domain. If the status information is connected domain detection, and the detection result is connected, it may be determined that the second pixel point and the first pixel point belong to the same connected domain, that is, the second pixel point has been detected by the connected domain. It is no longer necessary to repeat the connected domain detection.
  • the state information of the second pixel point may be detected. It belongs to the same connected domain, and updates the state information of the second pixel according to the detection result.
  • status information corresponding to each pixel in the image data block may also be read from an external storage medium, and The read status information is stored in a register of the internal storage medium. Based on this, the detection circuit can acquire the state information of the second pixel from the register of the internal storage medium.
  • the state information corresponding to the pixel point may also be determined, and is in the register.
  • the status information corresponding to the pixel is updated; then, all status information in the register can be updated to an external storage medium, such as a register of an external storage medium.
  • status information can be recorded for each pixel, such as using 2 bits to represent status information of the pixel points. For example, 00 indicates that the state information of the pixel is not connected domain detection, 01 indicates that the state information of the pixel is the connected domain detection, and the detection result is disconnected, and 10 indicates that the state information of the pixel is the connected domain detection. And the test result is connected.
  • the external storage medium may include a register for recording status information of all the pixels.
  • the register includes 16*12*2 bits, which sequentially record the state information of each pixel in each image data block.
  • the first and second bits are used to record the state information of the pixel point 11
  • the third and fourth bits are used to record the state information of the pixel point 12
  • the fifth and sixth bits are used to record the state information of the pixel point 13
  • the seventh and eighth bits are used to record the state information of the pixel point 14
  • the ninth and tenth bits are used to record the state information of the pixel point 21 (instead of recording the state information of the pixel point 15), and so on.
  • the internal storage medium may also include a register for recording state information of all the pixels, and may also record state information of the partial pixels.
  • the register is used to record state information of a part of the pixel.
  • the internal storage medium includes four second type address blocks, and each of the second type of address blocks has a size of 3*.
  • the register includes 3*4*4*2 bits, which sequentially record the state information of each pixel in the image data block of each second type of address block.
  • the first and second bits are used to record the state information of the first pixel of the second type of address block 1
  • the third and fourth bits are used to record the state of the second pixel of the second type of address block 1.
  • Information, and so on, the 25th and 26th bits are used to record the state information of the first pixel of the second type of address block 2, and so on, and will not be described again.
  • all bits of the register of the external storage medium are 0, indicating that the state information of all the pixels is not connected domain detection.
  • All bits of the register of the internal storage medium are 0, indicating that the state information of all the pixels stored in the second type of address block 1-4 is not connected domain detection.
  • a gray pixel dot area (such as a pixel 11 , a pixel 12 , a pixel 22 , etc . ) is a connected domain.
  • a gray pixel dot area such as a pixel 11 , a pixel 12 , a pixel 22 , etc .
  • the following operations can be performed:
  • the image data block 1 is read from the first type of address block 1, and the state information corresponding to the image data block 1 is read from the register of the external storage medium, for example, the 1st to 24th bits of the register of the external storage medium. Then, the image data block 1 is stored in the second type address block 1, and the read state information is stored to the 1st to 24th bits of the register of the internal storage medium, that is, the 1st to 24th bits are all 0.
  • the 1st to 24th bits are state information of an image data block in the second type of address block 1
  • the 25th to 48th bits of the register are the second type of address block.
  • the state information of the image data block in 2 are the state information of the image data block in the second type address block 3
  • the 73-96 bits of the register are the image data in the second type address block 4.
  • the pixel point 12 is a pixel point that meets the requirement, and the pixel point 21 is not a pixel point that meets the requirement. Therefore, the state information of the pixel point 11 and the pixel point 12 is modified to have been connected to the connected domain, and the detection is performed.
  • the result is connectivity, and the state information of the pixel 21 is modified to have been connected to the connected domain, and the detection result is disconnected, that is, the first and second bits corresponding to the pixel 11 are modified to 10, and the pixel is
  • the third and fourth bits corresponding to 12 are modified to 10, and the ninth and tenth bits corresponding to the pixel 21 are modified to be 01, as shown in Table 3, which is an example of the modified state information.
  • the pixel (adjacent pixel) associated with the pixel 12 is the pixel 11, the pixel 13, and the pixel 22.
  • the state information corresponding to the pixel point 11 is 10 (that is, the connected domain detection has been performed, and the detection result is connected), and the pixel point 11 is no longer judged, and it is determined that the pixel point 12 and the pixel point 11 belong to the same Connected domain (only preliminary determination, ultimately need to determine whether it is really connected domain according to the area and other factors).
  • the state information corresponding to the pixel point 13 is 00 (ie, the connected domain detection is not performed), and it is detected whether the pixel point 13 and the pixel point 11 belong to the same connected domain, and since the pixel point 13 is not a required pixel point, Therefore, the state information of the pixel 13 is that the connected domain detection has been performed, and the detection result is not connected, and the fifth and sixth bits corresponding to the pixel point 13 are modified to 01.
  • the pixel point 22 is a pixel point that meets the requirement, that is, the state information of the pixel point 22 is connected domain detection, and the detection result is connected, the 11th and 12th bits corresponding to the pixel point 22 are modified to 10, see Table 4 shows an example of the modified status information.
  • the pixel point associated with the pixel point 22 is the pixel point 12, the pixel point 21, the pixel point 23, and the pixel point 32.
  • the state information corresponding to the pixel point 12 is 10, that is, The connected domain detection is performed, and the detection result is connected, and the state information corresponding to the pixel 21 is determined to be 01, that is, the connected domain detection has been performed, and the detection result is disconnected.
  • the state information corresponding to the pixel point 23 is 00, the connected field detection can be performed on the pixel point 23, and the pixel point 23 is determined to be a pixel point that meets the requirement.
  • the state information corresponding to the pixel point 32 is 00
  • Connected domain detection is performed on pixel 32 to determine that pixel 32 is a desired pixel.
  • the 13th and 14th bits corresponding to the pixel point 23 can be modified to 10
  • the 19th and 20th bits corresponding to the pixel point 32 can be modified to 10, as shown in Table 5, which is an example of the modified state information.
  • the status information of the pixel can be queried every time the connected domain detection is performed. If the status information is 01 or 10, the connected domain detection is no longer performed on the pixel. If the status information is 00, then Connected domain detection is performed on the pixel. After performing the connected domain detection on the pixel, the status information of the pixel may also be updated according to the detection result, such as updating 00 to 01 or 10.
  • the obtained state information is shown in Table 6. Further, after the image data block 2 is read from the first type of address block 2, the 24 bits corresponding to the image data block 2 can also be read from the register of the external storage medium, and the 24 bits corresponding to the image data block 2 can be read. Registers recorded to the internal storage medium, as shown in Table 7, the 25th to 48th bits are 0.
  • the obtained state information can be seen in Table 8.
  • the 24 bits corresponding to the image data block 4 are read from the register of the external storage medium, and the 24 bits corresponding to the image data block 4 are recorded to the internal storage.
  • the 73-96 bits are 0.
  • the obtained state information is shown in Table 10.
  • the 24 bits corresponding to the image data block 7 are read from the register of the external storage medium, and the 24 bits corresponding to the image data block 7 are recorded to the internal storage.
  • the 49th to 72th bits are 0.
  • the obtained state information is shown in Table 12.
  • the 24 bits corresponding to the image data block 10 are read from the registers of the external storage medium, and the 24 bits corresponding to the image data block 10 are recorded to the internal storage. In the register of the medium.
  • the status information "010101001010100101010100" of the 25th to 48th bits is updated to The register of the external storage medium updates the 25th to 48th bits of the register of the external storage medium (the status information corresponding to the image data block 2) to "0101010010101001010100". Then, the 25-48th bit of the register of the internal storage medium is updated to 24 zeros corresponding to the image data block 10, as shown in Table 13.
  • the register of the internal storage medium After the connected domain detection is completed, the register of the internal storage medium has stored the state information of the last 4 image data blocks, and then the state information of other image data blocks can be read from the register of the external storage medium, and all state information is analyzed. Out of the connected domain. For example, if the image data block 1, the image data block 2, the image data block 4, the image data block 7, the image data block 10, the image data block 13, and the image data block 16 are sequentially detected in the connected domain, after the connected domain detection is completed, The register of the internal storage medium can store the state information of the image data block 7, the image data block 10, the image data block 13, and the image data block 16, and therefore, the image data block 1 and the image data can be read from the register of the external storage medium.
  • the state information of the block 2 and the image data block 4 can be based on the image data block 1, the image data block 2, the image data block 4, the image data block 7, the image data block 10, the image data block 13, and the image data block 16.
  • the state information of the connected domain is analyzed, and the process will not be described again.
  • the embodiment of the present invention further provides a detecting circuit for: reading an image data block from a first type of address block of an external storage medium; wherein the original image data is divided into multiple Image data blocks, including partial line data of the original image data for each image data block, and each line of data including partial column data of the original image data; storing the read image data block to an internal storage medium In the second type of address block; performing connected domain detection by using the image data block stored in the second type of address block; the first type of address block is an arbitrary address block of the external storage medium;
  • the address block is any address block of the internal storage medium.
  • the detecting circuit is further configured to perform a connected domain on the pixel points in the image data block stored in the second type of address block after performing the connected domain detection by using the image data block stored in the second type of address block At the time of detection, determining an image data block associated with the pixel point;
  • the image data block is read from a first type of address block for storing the image data block, and the read image data block is stored in a second type of address block of the internal storage medium.
  • the detecting circuit is configured to: when detecting the image data block associated with the pixel point, if the last column of data of the current image data block is detected, determine the image data block where the next column of data of the last column of data is located The image data block associated with the pixel point;
  • the image data block in which the next row of data of the last row of data is located is determined as the image data block associated with the pixel.
  • the detecting circuit is configured to: when the image data block is read from a first type of address block for storing the image data block, in a current image data block for performing connected domain detection on the pixel After the detection of the image is completed, the image data block is read from a first type of address block for storing the image data block.
  • the detecting circuit When the detecting circuit reads the image data block from the first type of address block of the external storage medium, the detecting circuit is specifically configured to: sequentially read M*N pixels from the starting address of the first type of address block of the external storage medium. Point data, and the read data is composed into the image data block; wherein, M and N are integer values greater than or equal to 1, M is the number of rows of the image data block, and N is a column of the image data block number.
  • the detecting circuit is further configured to: divide the original image data into a plurality of image data blocks, and divide a storage space of the external storage medium into a plurality of first class addresses corresponding to the plurality of image data blocks Block; storing each image data block to a first type of address block corresponding to the image data block.
  • the detecting circuit is configured to: when the stored image data block is stored in the second type of address block of the internal storage medium, determine, by using a mapping table, a second type of address block corresponding to the first type of address block; The read image data block is stored in a second type of address block corresponding to the first type of address block; wherein the mapping table is used to record a mapping relationship between the first type of address block and the second type of address block.
  • the detecting circuit When the detecting circuit performs the connected domain detection by using the image data block stored in the second type of address block, the detecting circuit is specifically configured to: perform, on the first pixel in the image data block stored in the second type of address block When the connected domain is detected, the second pixel associated with the first pixel is selected from the image data block; if the state information of the second pixel is present, the state information of the second pixel is used according to the state information of the second pixel Connected domain detection; wherein the state information is used to indicate whether the second pixel point is subjected to connected domain detection.
  • the detecting circuit is configured to: when the connectivity information is detected according to the state information of the second pixel, if the state information is that the connected domain detection is not performed, detecting the second pixel and the first pixel Whether the point belongs to the same connected domain, and the state information of the second pixel is updated according to the detection result; if the state information is connected domain detection, and the detection result is disconnected, determining the second pixel and the The first pixel does not belong to the same connected domain; if the state information is connected domain detection, and the detection result is connected, it is determined that the second pixel and the first pixel belong to the same connected domain.
  • the detecting circuit is further configured to: if the state information of the second pixel point does not exist, detect the second pixel point and the first Whether the pixel points belong to the same connected domain, and the state information of the second pixel point is updated according to the detection result.
  • the detecting circuit is further configured to: when reading an image data block from a first type of address block of an external storage medium, read a state corresponding to each pixel point in the image data block from the external storage medium Information; storing the read status information into a register of the internal storage medium;
  • the detecting circuit is further configured to: after the read state information is stored in the register of the internal storage medium, determine the state corresponding to the pixel point after performing the connected domain detection using the pixel point in the image data block Information, and updating status information corresponding to the pixel in the register; updating all status information in the register to the external storage medium.
  • the detection circuit includes: an FPGA chip or an ASIC chip.
  • the embodiment of the present invention further provides a connected domain detecting device.
  • the connected domain detecting device includes a memory and a detecting circuit (such as an FPGA chip or an ASIC chip): a memory.
  • a detecting circuit for calling the program code, when the program code is executed, implementing the connected domain detecting method.
  • the embodiment of the present invention further provides a computer readable storage medium, where the computer readable storage medium stores a plurality of computer instructions, and when the computer instructions are executed, the connected domain is implemented. Detection method.
  • the system, apparatus, module or unit set forth in the above embodiments may be implemented by a computer chip or an entity, or by a product having a certain function.
  • a typical implementation device is a computer, and the specific form of the computer may be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email transceiver, and a game control.
  • embodiments of the invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, embodiments of the invention may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • these computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the instruction means implements the functions specified in one or more blocks of the flowchart or in a flow or block diagram of the flowchart.

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Abstract

一种连通域检测方法、电路、设备、计算机可读存储介质，所述方法包括：从外部存储介质的第一类地址块中读取图像数据块；其中，原始图像数据被划分为多个图像数据块，针对每个图像数据块，包括所述原始图像数据的部分行数据，且每行数据包括所述原始图像数据的部分列数据；将读取的图像数据块存储到内部存储介质的第二类地址块中；利用所述第二类地址块中存储的图像数据块进行连通域检测。应用本发明实施例，减少数据读取次数，节约大量DDR带宽，提高连通域检测性能。

Description

连通域检测方法、电路、设备、计算机可读存储介质 技术领域
本发明涉及图像处理技术领域，尤其是涉及连通域检测方法、电路、设备、计算机可读存储介质。
背景技术
计算机视觉是使用计算机和摄像设备对生物视觉的一种模拟，通过对采集的图像进行处理，以获得相应场景的三维信息，是一门关于如何运用摄像设备和计算机来获取被拍摄对象的数据与信息的技术，目前被广泛应用。
连通域检测是计算机视觉的一种典型应用，例如，在BM(Block Matching，块匹配)、SGBM(Semi-Global Block Matching，半全局块匹配)等针对深度图的处理过程中，均会进行连通域检测。但是，传统的连通域检测算法，处理能力受到多方面因素的限制，继而导致连通域检测算法的应用场景受限。
发明内容
本发明提供连通域检测方法、电路、设备、计算机可读存储介质。
本发明第一方面，提供一种连通域检测方法，所述方法包括：
从外部存储介质的第一类地址块中读取图像数据块；其中，原始图像数据被划分为多个图像数据块，针对每个图像数据块，包括所述原始图像数据的部分行数据，且每行数据包括所述原始图像数据的部分列数据；
将读取的图像数据块存储到内部存储介质的第二类地址块中；
利用所述第二类地址块中存储的图像数据块进行连通域检测；
其中，所述第一类地址块是所述外部存储介质的任意地址块；
所述第二类地址块是所述内部存储介质的任意地址块。
本发明第二方面，提供一种检测电路，所述检测电路用于：
从外部存储介质的第一类地址块中读取图像数据块；其中，原始图像数据被划分为多个图像数据块，针对每个图像数据块，包括所述原始图像数据的部分行数据，且每行数据包括所述原始图像数据的部分列数据；
将读取的图像数据块存储到内部存储介质的第二类地址块中；
利用所述第二类地址块中存储的图像数据块进行连通域检测；
其中，所述第一类地址块是所述外部存储介质的任意地址块；
所述第二类地址块是所述内部存储介质的任意地址块。
本发明第三方面，提供一种连通域检测设备，所述连通域检测设备包括：
存储器，用于存储程序代码；检测电路，用于调用所述程序代码，当所述程序代码被执行时，实现上述连通域检测方法。
本发明第四方面，提供一种计算机可读存储介质，所述计算机可读存储介质上存储有若干计算机指令，所述计算机指令被执行时，实现上述连通域检测方法。
基于上述技术方案，本发明实施例中，若片上缓存的存储资源有限，不会频繁从DDR读取数据，减少数据读取次数，节约大量DDR带宽，提高连通域检测性能。为了减少读取次数，也可以减少占用的片上缓存的存储资源。
附图说明
为了更加清楚地说明本发明实施例或者现有技术中的技术方案，下面将对本发明实施例或者现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明中记载的一些实施例，对于本领域普通技术人员来讲，还可以根据本发明实施例的这些附图获得其它的附图。
图1A-图1D是连通域检测的应用场景示意图；
图2是一个连通域检测方法的实施例示意图；
图3是另一个连通域检测方法的实施例示意图；
图4是连通域检测设备的一个实施例框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。另外，在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。
本发明使用的术语仅仅是出于描述特定实施例的目的，而非限制本发明。本发明和权利要求书所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其它含义。应当理解，本文中使用的术语“和/或”是指包含一个或者多个相关联的列出项目的任何或所有可能组合。
尽管在本发明可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语用来将同一类型的信息彼此区分开。例如，在不脱离本发明范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，此外，所使用的词语“如果”可以被解释成为“在……时”，或者，“当……时”，或者，“响应于确定”。
本发明实施例中提出一种连通域检测方法，用于对图像进行连通域检测，参见图1A所示，为图像的一个示例，为了方便描述，将这个图像称为原始图像数据，原始图像数据可以是采集的，也可以是生成的，对此不做限制。
在原始图像数据中，每个方格代表一个像素点，如像素点11、像素点12、像素点13等，每个像素点的取值可以包括但不限于：像素值、灰度值、RGB(Red Green Blue，红绿蓝)值、disparity(差距)值等，对此不做限制，这个取值与原始图像数据有关。为了方便描述，后续以灰度值为例进行说明。
参见图1A所示，原始图像数据包括16行像素点，12列像素点，在实际应用中，原始图像数据的行数远远大于16行，如原始图像数据的行数为800行，原始图像数据的列数远远大于12列，如原始图像数据的列数为1200列。 为了方便描述，本应用场景下，以16行像素点，12列像素点为例进行说明。
参见图1B所示，假设灰色像素点区域(如像素点11、像素点12、像素点22等组成的区域)是一个连通域，为了检测到该连通域，则可以进行如下操作：选取某个像素点A，判断像素点A的相邻像素点(如上、下、左、右)中是否存在符合要求的像素点。符合要求的像素点是指有效像素点(本文中，假设所有像素点都是有效像素点，实际应用中，可能存在无效像素点)，且其灰度值与像素点A的灰度值之间的差值小于阈值(可以根据经验进行配置)。若存在符合要求的像素点，则继续判断该像素点的相邻像素点中是否存在符合要求的像素点，以此类推，直到无法查询到符合要求的像素点。这样，就可以找到灰色像素点区域的所有像素点，而这些像素点就组成一个连通域。
例如，选取像素点11，相邻像素点为像素点12、像素点21，经过判断(如有效像素点的判断、阈值的判断等)，像素点12是符合要求的像素点，像素点21不是符合要求的像素点。因此，继续选取像素点12，相邻像素点为像素点11、像素点13、像素点22，像素点11已进行过判断，此时不再判断，经过判断，像素点13不是符合要求的像素点，像素点22是符合要求的像素点。
因此，继续选取像素点22，相邻像素点为像素点12、像素点21、像素点23、像素点32，像素点12已进行过判断，此时不再判断，经过判断，像素点21不是符合要求的像素点，像素点23和像素点32均是符合要求的像素点。
因此，继续选取像素点23和像素点32，以此类推，灰色像素点区域的所有像素点均是符合要求的像素点。进一步的，还可以计算灰色像素点区域的区域面积，若这个区域面积小于阈值，就认为这个灰色像素点区域不是连通域，若这个区域面积大于阈值，就认为这个灰色像素点区域是连通域。
在一个例子中，原始图像数据可以存储到DDR(Double Data Rate，双倍速率同步动态随机存储器)，当然，也可以将原始图像数据存储到其它存储介质，对此不做限制，后续以原始图像数据存储到DDR为例进行说明。
在将原始图像数据存储到DDR时，原始图像数据是按行存储的，例如，依次存储像素点11-像素点1c的灰度值，在像素点1c的灰度值之后，依次存储像素点21-像素点2c的灰度值，在像素点2c的灰度值之后，依次存储像素点31-像素点3c的灰度值，以此类推，最后存储的是像素点gc的灰度值。
为了实现连通域检测，则可以将DDR中的数据(如原始图像数据中每个像素点的灰度值)读取到片上缓存，并利用片上缓存的数据进行连通域检测。例如，若由CPU(Central Processing Unit，中央处理器)实现连通域检测，则由CPU将DDR中的数据读取到CPU的片上缓存，并利用片上缓存的数据进行连通域检测；若由检测电路实现连通域检测，则由检测电路将DDR中的数据读取到检测电路的片上缓存，并利用片上缓存的数据进行连通域检测。
但是，传统的连通域检测方式，需要占用片上缓存的大量存储资源，而由于片上缓存的存储资源有限，因此，传统的连通域检测方式，处理能力受到多方面因素的限制，继而导致连通域检测方式的应用场景受到限制。
例如，片上缓存的存储资源，只能存储12个像素点的灰度值，因此，CPU或者检测电路第一次读取数据时，是将DDR中的像素点11-像素点1c的灰度值读取出来，并将像素点11-像素点1c的灰度值存储到自身的片上缓存。
在选取像素点11后，像素点12和像素点21是相邻像素点，由于片上缓存具有像素点12的灰度值，因此，利用像素点12的灰度值确定像素点12是符合要求的像素点。由于片上缓存没有像素点21的灰度值，因此可以将片上缓存的数据删除，并将DDR中的像素点21-像素点2c的灰度值读取出来，并将像素点21-像素点2c的灰度值存储到自身的片上缓存。这样，由于片上缓存具有像素点21的灰度值，因此，利用像素点21的灰度值确定像素点21不是符合要求的像素点。以此类推，针对选取的每个像素点执行上述操作。
综上可以看出，由于片上缓存的存储资源有限，导致CPU或者检测电路需要频繁从DDR中读取数据，占用大量DDR带宽，连通域检测性能很低。
为了减少读取次数，则可以增加片上缓存的存储资源，例如，为了检测出灰色像素点区域这个连通域，则可以从DDR中读取所有像素点的灰度值，这样，存储资源需要存储16*12个像素点的灰度值，即占用大量存储资源。显然，当原始图像数据的行数更多，列数更多时，则需要的存储资源更多。
参见图1B所示，为了检测出灰色像素点区域这个连通域，在选取像素点12后，需要对像素点13进行判断，由于该像素点13不是符合要求的像素点，因此，像素点14-像素点1c的灰度值已经没有价值，即不需要使用像素点14-像素点1c的灰度值。同理，也不需要使用像素点29-像素点2c的灰度值、像素点34-像素点3c的灰度值、使用像素点44-像素点4c的灰度值，以此类推，对此不再赘述。显然，原始图像数据中存在大量不需要判断的像素点。
针对上述发现，本发明实施例中，在将原始图像数据存储到DDR时，原始图像数据不是按行存储的，而是按图像数据块存储的。例如，假设图像数据块的大小为3行*4列，则可以将原始图像数据划分成18个图像数据块，参见图1C所示，将原始图像数据划分成图像数据块1-图像数据块18。基于此，可以依次将图像数据块1-图像数据块18存储到DDR。例如，在存储图像数据块1时，依次存储像素点11-像素点14的灰度值，在像素点14的灰度值之后，不是存储像素点15的灰度值，而是依次存储像素点21-像素点24的灰度值，在像素点24的灰度值之后，依次存储像素点31-像素点34的灰度值。这样，可以完成图像数据块1的存储。然后，存储图像数据块2，即在像素点34的灰度值之后，依次存储像素点15-像素点18的灰度值，以此类推，最终完成图像数据块1-图像数据块18的存储，最后存储的是图像数据块18。
基于上述存储方式，本发明实施例中，在将DDR中的数据读取到片上缓存时，可以读取DDR的图像数据块的数据(即各像素点的灰度值)，并将读取的数据存储到片上缓存。例如，参见图1C所示，为了检测出灰色像素点区域这个连通域，只需要读取图像数据块1的数据、图像数据块2的数据、图像数据块4的数据、图像数据块7的数据、图像数据块10的数据、图像数据 块13的数据、图像数据块16的数据，而不用读取所有图像数据块的数据。
这样，若片上缓存的存储资源有限，不会频繁从DDR中读取数据，减少数据读取次数，节约大量DDR带宽，提高连通域检测性能。而且，为了减少读取次数，也可以减少占用的片上缓存的存储资源。例如，片上缓存的存储资源只需要存储4*3*6+4个像素点的灰度值，可以显著减少占用的存储资源。
综上所述，本发明实施例中，在DDR采用图像数据块(即block)的方式存储数据后，使得CPU或者检测电路的一次读取过程，可以读取更多的行数据、列数据，降低按行读取对DDR的访问次数，如一次读取3行*4列的数据。当然，当图像数据块的行数和列数为其它值时，如8行*16列，一次也可以读取8行*16列的数据，也就是一次DDR访问就可以读出8行16列的数据。
以下对本发明提出的连通域检测方法进行说明，该连通域检测方法可以应用于CPU(采用软件方式实现)，也可以应用于检测电路(采用硬件方式实现)，对此不做限制。为了方便描述，后续以应用于检测电路为例进行说明。
其中，所述检测电路可以包括但不限于：FPGA(Field Programmable Gate Array，现场可编程门阵列)芯片或者ASIC(Application Specific Integrated Circuit，专用集成电路)芯片。当然，还可以为其它类型芯片，对此不做限制。
在一个例子中，由于在检测电路实现连通域检测方法，因此，可以将检测电路的存储介质称为内部存储介质，并将存储原始图像数据的存储介质称为外部存储介质，这个外部存储介质不是检测电路的存储介质。其中，内部存储介质可以包括但不限于检测电路的片上缓存，而外部存储介质可以包括但不限于动态随机存储器，如上述DDR，其也可以称为检测电路的片外DDR。
为了在外部存储介质(如DDR)存储原始图像数据的图像数据块，参见图2所示，本发明实施例中提出的连通域检测方法，可以包括以下步骤：
步骤201，将原始图像数据划分成多个图像数据块。
其中，将原始图像数据划分成多个图像数据块，包括：按照M*N(即M 行*N列)的划分策略，将原始图像数据划分成多个图像数据块。其中，对于每个图像数据块，最多可以包括原始图像数据的M行数据，最多可以包括原始图像数据的N列数据。而且，M为大于等于1的整数值，N为大于等于1的整数值，M小于原始图像数据的总行数，N小于原始图像数据的总列数。
例如，M和N均可以根据经验配置，对此不做限制，只要M大于等于1，小于原始图像数据的总行数，N大于等于1，小于原始图像数据的总列数即可。例如，当M为3，N为4时，则每个图像数据块，最多包括原始图像数据的3行数据，最多包括原始图像数据的4列数据，参见图1C所示，为M为3，N为4的图像数据块示例。又例如，当M为8，N为6时，则每个图像数据块，最多包括原始图像数据的8行数据，最多包括原始图像数据的6列数据。
步骤202，将外部存储介质的存储空间划分成与多个图像数据块对应的多个第一类地址块(为了区分方便，可以将外部存储介质中的每个地址块称为第一类地址块)，即每个图像数据块对应外部存储介质的一个第一类地址块。
参见图1C所示，在将原始图像数据划分成18个图像数据块后，可以将外部存储介质的存储空间划分成18个第一类地址块。其中，第一类地址块1用于存储图像数据块1的数据，即该第一类地址块1依次存储像素点11-像素点14的灰度值，像素点21-像素点24的灰度值，像素点31-像素点34的灰度值。此外，第一类地址块2用于存储图像数据块2的数据，第一类地址块3用于存储图像数据块3的数据，以此类推，对于其它第一类地址块不再赘述。
其中，由于图像数据块最大可以为M*N，因此，每个第一类地址块的大小为M*N，即可以存储M*N个像素点的灰度值。参见图1C所示，第一类地址块1-第一类地址块18可以为3*4。对于第一类地址块16-第一类地址块18来说，其大小也为3*4，虽然这些第一类地址块只存储1*4个灰度值。
步骤203，将每个图像数据块存储到该图像数据块对应的第一类地址块。
例如，可以将图像数据块1的数据存储到第一类地址块1，将图像数据块2的数据存储到第一类地址块2，以此类推，具体存储方式参见上述步骤。
在一个例子中，由于检测电路采用图像数据块的方式，从外部存储介质的第一类地址块中读取数据，并将数据存储到内部存储介质，因此，可以将内部存储介质的存储空间划分成第二类地址块(为了区分方便，可以将内部存储介质中的每个地址块称为第二类地址块)，由于图像数据块最大为M*N，因此每个第二类地址块的大小为M*N，即可以存储M*N个像素点的灰度值。
其中，第二类地址块的数量为至少一个，与内部存储介质(如片上缓存)的存储资源有关，由于内部存储介质的存储资源有限，因此，内部存储介质中的第二类地址块的数量，通常小于外部存储介质中的第一类地址块的数量。
例如，假设内部存储介质的存储资源只能存储48个像素点的灰度值，而每个第二类地址块的大小可以为3*4，即每个第二类地址块用于存储12个像素点的灰度值，基于此，可以将内部存储介质的存储空间划分成4个第二类地址块，这4个第二类地址块可以分别为第二类地址块1-第二类地址块4。
为了将外部存储介质的第一类地址块中的数据，存储到内部存储介质的第二类地址块，则可以将每个第一类地址块映射到一个第二类地址块，即每个第一类地址块具有一个对应的第二类地址块，这样，可以将该第一类地址块的数据存储到该第二类地址块。例如，可以将第一类地址块1映射到第二类地址块1，这样，可以将第一类地址块1的数据存储到第二类地址块1。
其中，在将第一类地址块映射到第二类地址块时，由于第二类地址块的数量小于第一类地址块的数量，因此，每个第二类地址块可以对应一个或者多个第一类地址块，而每个第一类地址块可以只对应一个第二类地址块。
在将第一类地址块映射到第二类地址块之后，可以获取第一类地址块和第二类地址块的映射关系，并在映射表中记录第一类地址块和第二类地址块的映射关系。其中，第一类地址块和第二类地址块的映射关系可以根据经验配置，对此不做限制，在得到该映射关系后，就可以在映射表中记录该映射关系，如表1所示，为映射表的一个示例，对此映射表的内容不做限制。
表1
第一类地址块 第二类地址块
1、5、9、13、17 1
2、6、10、14、18 2
3、7、11、15 3
4、8、12、16 4
在上述应用场景下，参见图3所示，为连通域检测方法的流程图，包括：
步骤301，从外部存储介质的第一类地址块中读取图像数据块。其中，原始图像数据被划分为多个图像数据块，针对每个图像数据块，包括该原始图像数据的部分行数据，且每行数据包括原始图像数据的部分列数据。
其中，该第一类地址块是外部存储介质(如DDR)的任意地址块。
在一个例子中，从外部存储介质的第一类地址块中读取图像数据块，包括：可以从外部存储介质的第一类地址块的起始地址开始，依次读取M*N个像素点的数据，并将读取的数据组成图像数据块。其中，该M和该N均为大于等于1的整数值，该M为图像数据块的行数，该N为图像数据块的列数。而且，该M小于原始图像数据的总行数，该N小于原始图像数据的总列数。
步骤302，将读取的图像数据块存储到内部存储介质的第二类地址块中。
其中，该第二类地址块是内部存储介质(如片上缓存)的任意地址块。
其中，将读取的图像数据块存储到内部存储介质的第二类地址块中，包括：从映射表中确定该第一类地址块(即图像数据块所在的第一类地址块)对应的第二类地址块；将读取的该图像数据块存储到该第一类地址块对应的第二类地址块；该映射表用于记录第一类地址块和第二类地址块的映射关系。
在一个例子中，将读取的图像数据块存储到该第一类地址块对应的第二类地址块，可以包括：若该第一类地址块对应的第二类地址块已经存储图像数据块，则删除该第二类地址块中存储的图像数据块，并将读取的图像数据块存储到该第二类地址块。若该第一类地址块对应的第二类地址块没有存储图像数据块，则可以直接将读取的图像数据块存储到该第二类地址块。
步骤303，利用第二类地址块中存储的图像数据块进行连通域检测。
其中，在利用第二类地址块中存储的图像数据块进行连通域检测之后，在对第二类地址块中存储的图像数据块中的像素点进行连通域检测时，可以确定与该像素点关联的图像数据块，并从用于存储该图像数据块的第一类地址块中读取该图像数据块，并将读取的图像数据块存储到内部存储介质的第二类地址块中，继续利用第二类地址块中存储的图像数据块进行连通域检测。
在一个例子中，确定与该像素点关联的图像数据块，可以包括但不限于如下方式：若检测到当前图像数据块的最后一列数据，则可以将该最后一列数据的下一列数据所在的图像数据块，确定为与该像素点关联的图像数据块。和/或，若检测到当前图像数据块的最后一行数据，则可以将该最后一行数据的下一行数据所在的图像数据块，确定为与该像素点关联的图像数据块。
在一个例子中，从用于存储该图像数据块的第一类地址块中读取该图像数据块，可以包括但不限于如下方式：在用于对像素点进行连通域检测的当前图像数据块的检测完成之后，从用于存储该图像数据块的第一类地址块中读取该图像数据块。或者，在确定出与该像素点关联的图像数据块之后，可以直接从用于存储该图像数据块的第一类地址块中读取该图像数据块。
在一个例子中，按照M*N(即M行*N列)的划分策略，将原始图像数据划分成多个图像数据块后，如果最下边的图像数据块和/或最右边的图像数据块超出边界(即原始图像数据的边界)，也就是说，可能会存在一部分无效数据。基于此，在连通域检测的过程中，这部分无效数据会根据图像的尺寸进行判断，不参与连通域检测。具体的，在比较过程中，会记录当前的比较位置，并当该位置与图像的尺寸进行比较，从而不能超出图像的边界。
例如，参见图1A和图1B所示，原始图像数据包括16行像素点，12列像素点，可以将原始图像数据划分成图1C所示的18个图像数据块。由于每个图像数据块为3行*4列，因此，实际上，图像数据块16-图像数据块18还有两行数据，参见图1D所示，这两行数据均用w表示，即所有w均为无效数据，通过使用原始图像数据的尺寸(size)，就可以识别出这些无效数据。
以下结合图1C所示的应用场景，对上述步骤301-步骤303进行说明。
参见图1C所示，假设灰色像素点区域(如像素点11、像素点12、像素点22等组成的区域)是一个连通域，为了检测到连通域，可以进行如下操作：
从外部存储介质的第一类地址块1中读取图像数据块1，图像数据块1包括原始图像数据的3行数据，且每行数据包括原始图像数据的4列数据。具体的，可以从第一类地址块1的起始地址开始，依次读取3*4个像素点的数据，并将这些数据组成图像数据块1。由于第一类地址块1依次存储像素点11-像素点14的灰度值，像素点21-像素点24的灰度值，像素点31-像素点34的灰度值，因此，从第一类地址块1的起始地址开始读取3*4个像素点的数据时，可以读取到上述像素点的灰度值，并将这些灰度值组成图像数据块1。
通过查询表1，确定第一类地址块1对应第二类地址块1，因此，可以将图像数据块1存储到第二类地址块1中。由于第二类地址块1当前没有存储图像数据块，因此，可以直接将图像数据块1存储到第二类地址块1中。
进一步的，由于图像数据块1的大小为3行*4列，而第二类地址块1的大小也为3行*4列，因此，该第二类地址块1能够存储该图像数据块1。
然后，利用第二类地址块1中存储的图像数据块1进行连通域检测。具体的，选取像素点11，相邻像素点为像素点12、像素点21，由于图像数据块1存在像素点12、像素点21，因此不再从外部存储介质读取新的图像数据块。
经过判断(如有效像素点的判断、阈值判断等)，像素点12是符合要求的像素点，像素点21不是符合要求的像素点。选取像素点12，相邻像素点为像素点11、像素点13、像素点22，像素点11已进行过判断，不再判断，经过判断，像素点13不是符合要求的像素点，像素点22是符合要求的像素点。
然后，选取像素点22，相邻像素点为像素点12、像素点21、像素点23、像素点32，由于像素点12和像素点21已进行过判断，因此不再判断，经过判断，像素点23和像素点32均是符合要求的像素点。然后，可以选取像素点23和像素点32，以先选取像素点23，后选取像素点32为例进行说明。
选取像素点23，相邻像素点为像素点13、像素点22、像素点24、像素 点33，由于像素点13和像素点22已进行过判断，因此不再判断，经过判断，像素点24是符合要求的像素点，而像素点33不是符合要求的像素点。选取像素点24，相邻像素点为像素点14、像素点23、像素点25、像素点34。由于像素点24是当前图像数据块1的最后一列数据，因此，将最后一列数据的下一列数据所在的图像数据块2，确定为与像素点11关联的图像数据块。
在一个例子中，在确定出与像素点11关联的图像数据块2后，可以直接从外部存储介质的第一类地址块2中读取图像数据块2。或者，在另一个例子中，在当前的图像数据块1的检测完成后，才可以从外部存储介质的第一类地址块2中读取图像数据块2。对此过程不做限制，后续以直接从第一类地址块2中读取图像数据块2为例，然后通过查询表1，确定该第一类地址块2对应的第二类地址块2，并将该图像数据块2存储到该第二类地址块2中。
针对像素点24，由于相邻像素点(像素点14、像素点23、像素点25、像素点34)已经存储在内部存储介质的第二类地址块1和第二类地址块2中，因此对像素点24的相邻像素点进行判断。由于像素点23已进行过判断，因此不再判断，经过判断，像素点25是符合要求的像素点，像素点14、像素点34不是符合要求的像素点。进一步，选取像素点25后，确定像素点26是符合要求的像素点，选取像素点26后，确定像素点27是符合要求的像素点。
选取像素点32，由于像素点32是当前图像数据块1的最后一行数据，因此，将下一行数据所在的图像数据块4，确定为与像素点11关联的图像数据块。然后，从第一类地址块4中读取图像数据块4，通过查询表1，确定第一类地址块4对应的第二类地址块4，将图像数据块4存储到第二类地址块4中。
针对像素点32，由于像素点22已进行过判断，因此不再判断，经过判断，像素点42是符合要求的像素点。然后，选取像素点42后，确定像素点52是符合要求的像素点，选取像素点52后，确定像素点62是符合要求的像素点。
选取像素点62后，确定关联的图像数据块7，并从第一类地址块7中读取图像数据块7，通过查询表1，确定该第一类地址块7对应的第二类地址块3，并将图像数据块7存储到第二类地址块3中。针对像素点62，经过判断， 像素点72是符合要求的像素点。然后，选取像素点72后，确定像素点82是符合要求的像素点，选取像素点82后，确定像素点92是符合要求的像素点。
选取像素点92后，确定关联的图像数据块10，并从第一类地址块10中读取图像数据块10，通过查询表1，确定第一类地址块10对应的第二类地址块2，删除第二类地址块2中存储的图像数据块2，并将图像数据块10存储到第二类地址块2中。针对像素点92，经过判断，像素点a2是符合要求的像素点。以此类推，像素点b2、像素点c2、像素点d2、像素点e2、像素点f2、像素点g2、像素点g3也是符合要求的像素点，对此判断过程不再赘述。
综上所述，灰色像素点区域的所有像素点均是符合要求的像素点，然后，基于灰色像素点区域的区域面积，确定这个灰色像素点区域是连通域。
在上述实施例中，利用第二类地址块中存储的图像数据块进行连通域检测，包括：在对第二类地址块中存储的图像数据块中的第一像素点进行连通域检测时，可以从该图像数据块中选取该第一像素点关联的第二像素点；若存在该第二像素点的状态信息，则可以根据该第二像素点的状态信息进行连通域检测。其中，该状态信息可以用于指示第二像素点是否进行过连通域检测，而且，该状态信息可以包括未进行连通域检测；或已进行连通域检测，且检测结果为不连通；或已进行连通域检测，且检测结果为连通。
进一步的，根据该第二像素点的状态信息进行连通域检测，包括：若该状态信息为未进行连通域检测，则可以检测第二像素点与第一像素点是否属于同一个连通域，并根据检测结果更新该第二像素点的状态信息。若该状态信息为已进行连通域检测，且检测结果为不连通，则可以确定第二像素点和第一像素点不属于同一个连通域。若该状态信息为已进行连通域检测，且检测结果为连通，则可以确定第二像素点和第一像素点属于同一个连通域，也就是说，第二像素点已进行了连通域检测，不必再重复进行连通域检测。
在一个例子中，从该图像数据块中选取该第一像素点关联的第二像素点之后，若不存在该第二像素点的状态信息，则可以检测第二像素点与第一像素点是否属于同一个连通域，并根据检测结果更新第二像素点的状态信息。
在一个例子中，在从外部存储介质的第一类地址块中读取图像数据块时，还可以从外部存储介质中读取该图像数据块中的每个像素点对应的状态信息，并将读取的状态信息存储到内部存储介质的寄存器中。基于此，则检测电路可以从内部存储介质的寄存器中，获取到第二像素点的状态信息。
进一步的，在将读取的状态信息存储到内部存储介质的寄存器中后，在使用图像数据块中的像素点进行连通域检测后，还可以确定该像素点对应的状态信息，并在寄存器中更新该像素点对应的状态信息；然后，可以将寄存器中的所有状态信息更新到外部存储介质，如外部存储介质的寄存器中。
以下结合图1C所示的应用场景，对上述状态信息的相关过程进行说明。
为了降低重复计算次数，可以为每个像素点记录状态信息，如使用2个比特表示像素点的状态信息。例如，00表示像素点的状态信息是未进行连通域检测，01表示像素点的状态信息是已进行连通域检测，且检测结果为不连通，10表示像素点的状态信息是已进行连通域检测，且检测结果为连通。
为了记录像素点的状态信息，外部存储介质可以包括寄存器，这个寄存器用于记录所有像素点的状态信息。例如，当像素点数量为16*12时，寄存器包括16*12*2个比特，这些比特依次记录了每个图像数据块中各像素点的状态信息。例如，第1、2个比特用于记录像素点11的状态信息，第3、4个比特用于记录像素点12的状态信息，第5、6个比特用于记录像素点13的状态信息，第7、8个比特用于记录像素点14的状态信息，第9、10个比特用于记录像素点21的状态信息(而不是记录像素点15的状态信息)，以此类推。
为了记录像素点的状态信息，内部存储介质也可以包括寄存器，该寄存器用于记录所有像素点的状态信息，也可以记录部分像素点的状态信息。考虑到内部存储介质的存储资源有限，因此，该寄存器用于记录部分像素点的状态信息，例如，内部存储介质包括4个第二类地址块，每个第二类地址块的大小为3*4时，则寄存器包括3*4*4*2个比特，这些比特依次记录了每个第二类地址块的图像数据块中各像素点的状态信息。例如，第1、2个比特用于记录第二类地址块1的第一个像素点的状态信息，第3、4个比特用于记录 第二类地址块1的第二个像素点的状态信息，以此类推，第25、26个比特用于记录第二类地址块2的第一个像素点的状态信息，以此类推，不再赘述。
在初始状态下，外部存储介质的寄存器的所有比特为0，表示所有像素点的状态信息是未进行连通域检测。内部存储介质的寄存器的所有比特为0，表示第二类地址块1-4中存储的所有像素点的状态信息是未进行连通域检测。
参见图1C所示，假设灰色像素点区域(如像素点11、像素点12、像素点22等组成的区域)是一个连通域，为了检测到连通域，可以进行如下操作：
从第一类地址块1中读取图像数据块1，并从外部存储介质的寄存器中读取图像数据块1对应的状态信息，例如，外部存储介质的寄存器的第1-24个比特。然后，将图像数据块1存储到第二类地址块1中，并将读取的状态信息存储到内部存储介质的寄存器的第1-24个比特，即第1-24个比特均为0。
参见表2所示，为内部存储介质的寄存器的示例，第1-24个比特为第二类地址块1中图像数据块的状态信息，寄存器的第25-48个比特为第二类地址块2中图像数据块的状态信息，寄存器的第49-72个比特为第二类地址块3中图像数据块的状态信息，寄存器的第73-96个比特为第二类地址块4中图像数据块的状态信息。初始状态下，这96个比特均为空(没有值)，在将图像数据块1对应的24个比特记录到寄存器后，如表2所示，第1-24个比特为0。
表2
000000000000000000000000
在选取像素点11时，像素点12是符合要求的像素点，像素点21不是符合要求的像素点，因此，将像素点11、像素点12的状态信息修改为已进行连通域检测，且检测结果为连通，并将像素点21的状态信息修改为已进行连通域检测，且检测结果为不连通，也就是说，将像素点11对应的第1、2个比特修改为10，将像素点12对应的第3、4个比特修改为10，将像素点21对应的第9、10个比特修改为01，参见表3所示，为修改后的状态信息示例。
表3
101000000100000000000000
在选取像素点12时，像素点12关联的像素点(相邻像素点)为像素点11、像素点13、像素点22。通过查询表3，确定像素点11对应的状态信息为10(即已进行连通域检测，且检测结果为连通)，不再对像素点11进行判断，确定像素点12与像素点11属于同一个连通域(只是初步确定，最终还需要根据面积等因素，确定是否真的是连通域)。通过查询表3，确定像素点13对应的状态信息为00(即未进行连通域检测)，检测像素点13与像素点11是否属于同一个连通域，由于像素点13不是符合要求的像素点，因此，像素点13的状态信息是已进行连通域检测，且检测结果为不连通，将像素点13对应的第5、6个比特修改为01。此外，由于像素点22是符合要求的像素点，即像素点22的状态信息是已进行连通域检测，且检测结果为连通，将像素点22对应的第11、12个比特修改为10，参见表4所示，为修改后的状态信息示例。
表4
101001000110000000000000
在选取像素点22时，与像素点22关联的像素点为像素点12、像素点21、像素点23、像素点32，通过查询表4，确定像素点12对应的状态信息为10，即已进行连通域检测，且检测结果为连通，并确定像素点21对应的状态信息为01，即已进行连通域检测，且检测结果为不连通。此外，由于像素点23对应的状态信息为00，因此，可以对像素点23进行连通域检测，确定像素点23是符合要求的像素点，由于像素点32对应的状态信息为00，因此，可以对像素点32进行连通域检测，确定像素点32是符合要求的像素点。然后，可以将像素点23对应的第13、14个比特修改为10，将像素点32对应的第19、20个比特修改为10，参见表5所示，为修改后的状态信息示例。
表5
101001000110100000100000
以此类推，在每次进行连通域检测时，可以查询像素点的状态信息，若该状态信息是01或者10，则不再对该像素点进行连通域检测，若该状态信息 是00，则对该像素点进行连通域检测。在对该像素点进行连通域检测后，还可以根据检测结果更新该像素点的状态信息，如将00更新为01或者10。
在对图像数据块1中各像素点进行检测后，得到的状态信息参见表6所示。此外，在从第一类地址块2中读取图像数据块2后，还可以从外部存储介质的寄存器中读取图像数据块2对应的24个比特，将图像数据块2对应的24个比特记录到内部存储介质的寄存器，如表7所示，第25-48个比特为0。
表6
101001010110101001100101
表7
101001010110101001100101000000000000000000000000
在对图像数据块2中各像素点进行检测后，得到的状态信息可以参见表8所示。在从第一类地址块4中读取图像数据块4后，从外部存储介质的寄存器中读取图像数据块4对应的24个比特，将图像数据块4对应的24个比特记录到内部存储介质的寄存器中，如表9所示，即第73-96个比特为0。
表8
101001010110101001100101010101001010100101010100
表9
Figure PCTCN2017119971-appb-000001
在对图像数据块4中各像素点进行检测后，得到的状态信息参见表10所示。在从第一类地址块7中读取图像数据块7后，从外部存储介质的寄存器中读取图像数据块7对应的24个比特，将图像数据块7对应的24个比特记录到内部存储介质的寄存器中，如表11所示，即第49-72个比特为0。
表10
Figure PCTCN2017119971-appb-000002
表11
Figure PCTCN2017119971-appb-000003
在对图像数据块7中各像素点进行检测后，得到的状态信息参见表12所示。在从第一类地址块10中读取图像数据块10后，从外部存储介质的寄存器中读取图像数据块10对应的24个比特，将图像数据块10对应的24个比特记录到内部存储介质的寄存器中。由于这24个比特记录到寄存器的第25-48个比特，而第25-48个比特已经有图像数据块2的状态信息，因此，将第25-48个比特的状态信息“010101001010100101010100”更新到外部存储介质的寄存器，即将外部存储介质的寄存器的第25-48个比特(是图像数据块2对应的状态信息)更新为“010101001010100101010100”。然后，将内部存储介质的寄存器的第25-48个比特更新为图像数据块10对应的24个0，如表13所示。
表12
Figure PCTCN2017119971-appb-000004
表13
Figure PCTCN2017119971-appb-000005
以此类推，对于之后的状态信息更新过程不再赘述。从上述实施例中可以看出，内部存储介质的寄存器中只存储最后4个图像数据块对应的状态信息，对于这4个图像数据块的连通域检测，可以基于状态信息(如00、01、10等)分析连通域检测结果，从而可以避免多次重复计算，减少计算次数。
在连通域检测完成后，内部存储介质的寄存器已经存储最后4个图像数据块的状态信息，然后，可以从外部存储介质的寄存器中读取其它图像数据块的状态信息，并利用所有状态信息分析出连通域。例如，若依次对图像数据块1、图像数据块2、图像数据块4、图像数据块7、图像数据块10、图像数据块13、图像数据块16进行连通域检测，在连通域检测完成后，内部存储介质的寄存器可以存储图像数据块7、图像数据块10、图像数据块13、图像 数据块16的状态信息，因此，可以从外部存储介质的寄存器中读取图像数据块1、图像数据块2、图像数据块4的状态信息，这样，就可以基于图像数据块1、图像数据块2、图像数据块4、图像数据块7、图像数据块10、图像数据块13、图像数据块16的状态信息，分析出连通域，对此过程不再赘述。
在连通域检测完成后，还可以将内部存储介质的寄存器中存储的所有状态信息，更新到外部存储介质的寄存器中，对此更新过程不再赘述。
基于与上述方法同样的发明构思，本发明实施例中还提供一种检测电路，用于：从外部存储介质的第一类地址块中读取图像数据块；其中，原始图像数据被划分为多个图像数据块，针对每个图像数据块，包括所述原始图像数据的部分行数据，且每行数据包括所述原始图像数据的部分列数据；将读取的图像数据块存储到内部存储介质的第二类地址块中；利用所述第二类地址块中存储的图像数据块进行连通域检测；所述第一类地址块是所述外部存储介质的任意地址块；所述第二类地址块是所述内部存储介质的任意地址块。
所述检测电路在利用所述第二类地址块中存储的图像数据块进行连通域检测之后还用于：在对所述第二类地址块中存储的图像数据块中的像素点进行连通域检测时，确定与所述像素点关联的图像数据块；
从用于存储所述图像数据块的第一类地址块中读取所述图像数据块，并将读取的图像数据块存储到内部存储介质的第二类地址块中。
所述检测电路在确定与所述像素点关联的图像数据块时具体用于：若检测到当前图像数据块的最后一列数据，将最后一列数据的下一列数据所在的图像数据块，确定为与所述像素点关联的图像数据块；
和/或，若检测到当前图像数据块的最后一行数据，将最后一行数据的下一行数据所在的图像数据块，确定为与所述像素点关联的图像数据块。
所述检测电路在从用于存储所述图像数据块的第一类地址块中读取所述图像数据块时具体用于：在用于对所述像素点进行连通域检测的当前图像数据块的检测完成之后，从用于存储所述图像数据块的第一类地址块中读取所述图像数据块。
所述检测电路在从外部存储介质的第一类地址块中读取图像数据块时具体用于：从外部存储介质的第一类地址块的起始地址开始，依次读取M*N个像素点的数据，并将读取的数据组成所述图像数据块；其中，M和N为大于等于1的整数值，M为所述图像数据块的行数，N为所述图像数据块的列数。
所述检测电路还用于：将所述原始图像数据划分成多个图像数据块，并将所述外部存储介质的存储空间划分成与所述多个图像数据块对应的多个第一类地址块；将每个图像数据块存储到该图像数据块对应的第一类地址块。
所述检测电路在将读取的图像数据块存储到内部存储介质的第二类地址块中时具体用于：从映射表中确定所述第一类地址块对应的第二类地址块；将读取的图像数据块存储到所述第一类地址块对应的第二类地址块；其中，所述映射表用于记录第一类地址块和第二类地址块的映射关系。
所述检测电路在利用所述第二类地址块中存储的图像数据块进行连通域检测时具体用于：在对所述第二类地址块中存储的图像数据块中的第一像素点进行连通域检测时，从所述图像数据块中选取所述第一像素点关联的第二像素点；若存在所述第二像素点的状态信息，则根据所述第二像素点的状态信息进行连通域检测；其中，所述状态信息用于指示所述第二像素点是否进行过连通域检测。
所述检测电路在根据所述第二像素点的状态信息进行连通域检测时具体用于：若所述状态信息为未进行连通域检测，则检测所述第二像素点与所述第一像素点是否属于同一个连通域，根据检测结果更新第二像素点的状态信息；若所述状态信息为已进行连通域检测，且检测结果为不连通，则确定所述第二像素点和所述第一像素点不属于同一个连通域；若所述状态信息为已进行连通域检测，且检测结果为连通，则确定所述第二像素点和所述第一像素点属于同一个连通域。
所述检测电路在选取与所述第一像素点关联的第二像素点之后还用于：若不存在所述第二像素点的状态信息，则检测所述第二像素点与所述第一像素点是否属于同一个连通域，根据检测结果更新第二像素点的状态信息。
所述检测电路还用于：在从外部存储介质的第一类地址块中读取图像数据块时，从所述外部存储介质中读取所述图像数据块中的每个像素点对应的状态信息；将读取的状态信息存储到所述内部存储介质的寄存器中；
所述检测电路在将读取的状态信息存储到所述内部存储介质的寄存器中之后还用于，在使用所述图像数据块中的像素点进行连通域检测后，确定该像素点对应的状态信息，并在所述寄存器中更新该像素点对应的状态信息；将所述寄存器中的所有状态信息更新到所述外部存储介质。
所述检测电路包括：FPGA芯片或者ASIC芯片。
基于与上述方法同样的发明构思，本发明实施例中还提供一种连通域检测设备，如图4所示，所述连通域检测设备包括存储器和检测电路(如FPGA芯片或者ASIC芯片)：存储器，用于存储程序代码；检测电路，用于调用所述程序代码，当所述程序代码被执行时，实现上述连通域检测方法。
基于与上述方法同样的发明构思，本发明实施例中还提供一种计算机可读存储介质，所述计算机可读存储介质上存储有若干计算机指令，所述计算机指令被执行时，实现上述连通域检测方法。
上述实施例阐明的系统、装置、模块或单元，可以由计算机芯片或实体实现，或者由具有某种功能的产品来实现。一种典型的实现设备为计算机，计算机的具体形式可以是个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件收发设备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任意几种设备的组合。
为了描述的方便，描述以上装置时以功能分为各种单元分别描述。当然，在实施本发明时可以把各单元的功能在同一个或多个软件和/或硬件中实现。
本领域内的技术人员应明白，本发明实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明实施例可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于 磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可以由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其它可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其它可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
而且，这些计算机程序指令也可以存储在能引导计算机或其它可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或者多个流程和/或方框图一个方框或者多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其它可编程数据处理设备，使得在计算机或者其它可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其它可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述仅为本发明实施例而已，并不用于限制本发明。对于本领域技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原理之内所作的任何修改、等同替换、改进，均应包含在本发明的权利要求范围之内。

Claims (37)

  1. 一种连通域检测方法，其特征在于，所述方法包括：
    从外部存储介质的第一类地址块中读取图像数据块；其中，原始图像数据被划分为多个图像数据块，针对每个图像数据块，包括所述原始图像数据的部分行数据，且每行数据包括所述原始图像数据的部分列数据；
    将读取的图像数据块存储到内部存储介质的第二类地址块中；
    利用所述第二类地址块中存储的图像数据块进行连通域检测；
    其中，所述第一类地址块是所述外部存储介质的任意地址块；
    所述第二类地址块是所述内部存储介质的任意地址块。
  2. 根据权利要求1所述的方法，其特征在于，所述利用所述第二类地址块中存储的图像数据块进行连通域检测之后，所述方法还包括：
    在对所述第二类地址块中存储的图像数据块中的像素点进行连通域检测时，确定与所述像素点关联的图像数据块；
    从用于存储所述图像数据块的第一类地址块中读取所述图像数据块，并将读取的图像数据块存储到内部存储介质的第二类地址块中。
  3. 根据权利要求2所述的方法，其特征在于，
    所述确定与所述像素点关联的图像数据块，包括：
    若检测到当前图像数据块的最后一列数据，将最后一列数据的下一列数据所在的图像数据块，确定为与所述像素点关联的图像数据块；
    和/或，
    若检测到当前图像数据块的最后一行数据，将最后一行数据的下一行数据所在的图像数据块，确定为与所述像素点关联的图像数据块。
  4. 根据权利要求2所述的方法，其特征在于，所述从用于存储所述图像数据块的第一类地址块中读取所述图像数据块，包括：
    在用于对所述像素点进行连通域检测的当前图像数据块的检测完成之后，从用于存储所述图像数据块的第一类地址块中读取所述图像数据块。
  5. 根据权利要求1所述的方法，其特征在于，
    所述从外部存储介质的第一类地址块中读取图像数据块，包括：
    从外部存储介质的第一类地址块的起始地址开始，依次读取M*N个像素点的数据，并将读取的数据组成所述图像数据块；其中，M和N为大于等于1的整数值，M为所述图像数据块的行数，N为所述图像数据块的列数。
  6. 根据权利要求5所述的方法，其特征在于，所述M小于所述原始图像数据的总行数，所述N小于所述原始图像数据的总列数。
  7. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    将所述原始图像数据划分成多个图像数据块，并将所述外部存储介质的存储空间划分成与所述多个图像数据块对应的多个第一类地址块；
    将每个图像数据块存储到该图像数据块对应的第一类地址块。
  8. 根据权利要求7所述的方法，其特征在于，
    所述将所述原始图像数据划分成多个图像数据块，包括：
    按照M*N的划分策略，将所述原始图像数据划分成多个图像数据块；其中，对于每个图像数据块，最多包括所述原始图像数据的M行数据，最多包括所述原始图像数据的N列数据；M和N为大于等于1的整数值。
  9. 根据权利要求1所述的方法，其特征在于，
    所述将读取的图像数据块存储到内部存储介质的第二类地址块中，包括：
    从映射表中确定所述第一类地址块对应的第二类地址块；
    将读取的图像数据块存储到所述第一类地址块对应的第二类地址块；
    其中，所述映射表用于记录第一类地址块和第二类地址块的映射关系。
  10. 根据权利要求9所述的方法，其特征在于，所述方法还包括：
    获取第一类地址块和第二类地址块的映射关系；
    在映射表中记录所述第一类地址块和第二类地址块的映射关系。
  11. 根据权利要求9或10所述的方法，其特征在于，外部存储介质中的第一类地址块的数量，大于内部存储介质中的第二类地址块的数量。
  12. 根据权利要求9或10所述的方法，其特征在于，每个第二类地址块对应一个或者多个第一类地址块，每个第一类地址块对应一个第二类地址块。
  13. 根据权利要求9所述的方法，其特征在于，所述将读取的图像数据块存储到所述第一类地址块对应的第二类地址块，包括：
    若所述第一类地址块对应的第二类地址块已经存储图像数据块，则删除该第二类地址块中存储的图像数据块，将读取的图像数据块存储到该第二类地址块。
  14. 根据权利要求1所述的方法，其特征在于，
    利用所述第二类地址块中存储的图像数据块进行连通域检测，包括：
    在对所述第二类地址块中存储的图像数据块中的第一像素点进行连通域检测时，从所述图像数据块中选取所述第一像素点关联的第二像素点；
    若存在所述第二像素点的状态信息，则根据所述第二像素点的状态信息进行连通域检测；其中，所述状态信息用于指示所述第二像素点是否进行过连通域检测。
  15. 根据权利要求14所述的方法，其特征在于，
    所述根据所述第二像素点的状态信息进行连通域检测，包括：
    若所述状态信息为未进行连通域检测，则检测所述第二像素点与所述第一像素点是否属于同一个连通域，根据检测结果更新第二像素点的状态信息。
  16. 根据权利要求14所述的方法，其特征在于，
    所述根据所述第二像素点的状态信息进行连通域检测，包括：
    若所述状态信息为已进行连通域检测，且检测结果为不连通，则确定所述第二像素点和所述第一像素点不属于同一个连通域。
  17. 根据权利要求14所述的方法，其特征在于，
    所述根据所述第二像素点的状态信息进行连通域检测，包括：
    若所述状态信息为已进行连通域检测，且检测结果为连通，则确定所述第二像素点和所述第一像素点属于同一个连通域。
  18. 根据权利要求14所述的方法，其特征在于，
    所述选取与所述第一像素点关联的第二像素点之后，所述方法还包括：
    若不存在所述第二像素点的状态信息，则检测所述第二像素点与所述第 一像素点是否属于同一个连通域，根据检测结果更新第二像素点的状态信息。
  19. 根据权利要求14-18任一所述的方法，其特征在于，所述方法还包括：
    在从外部存储介质的第一类地址块中读取图像数据块时，从所述外部存储介质中读取所述图像数据块中的每个像素点对应的状态信息；
    将读取的状态信息存储到所述内部存储介质的寄存器中。
  20. 根据权利要求19所述的方法，其特征在于，所述将读取的状态信息存储到所述内部存储介质的寄存器中之后，所述方法还包括：
    在使用所述图像数据块中的像素点进行连通域检测后，确定该像素点对应的状态信息，并在所述寄存器中更新该像素点对应的状态信息；
    将所述寄存器中的所有状态信息更新到所述外部存储介质。
  21. 根据权利要求1所述的方法，其特征在于，该方法应用于检测电路。
  22. 根据权利要求21所述的方法，其特征在于，所述检测电路包括：
    现场可编程门阵列FPGA芯片或者专用集成电路ASIC芯片。
  23. 根据权利要求21所述的方法，其特征在于，所述内部存储介质包括所述检测电路的片上缓存；所述外部存储介质包括动态随机存储器。
  24. 一种检测电路，其特征在于，所述检测电路用于：
    从外部存储介质的第一类地址块中读取图像数据块；其中，原始图像数据被划分为多个图像数据块，针对每个图像数据块，包括所述原始图像数据的部分行数据，且每行数据包括所述原始图像数据的部分列数据；
    将读取的图像数据块存储到内部存储介质的第二类地址块中；
    利用所述第二类地址块中存储的图像数据块进行连通域检测；
    其中，所述第一类地址块是所述外部存储介质的任意地址块；
    所述第二类地址块是所述内部存储介质的任意地址块。
  25. 根据权利要求24所述的检测电路，其特征在于，
    所述检测电路在利用所述第二类地址块中存储的图像数据块进行连通域检测之后还用于：在对所述第二类地址块中存储的图像数据块中的像素点进行连通域检测时，确定与所述像素点关联的图像数据块；
    从用于存储所述图像数据块的第一类地址块中读取所述图像数据块，并将读取的图像数据块存储到内部存储介质的第二类地址块中。
  26. 根据权利要求25所述的检测电路，其特征在于，
    所述检测电路在确定与所述像素点关联的图像数据块时具体用于：若检测到当前图像数据块的最后一列数据，将最后一列数据的下一列数据所在的图像数据块，确定为与所述像素点关联的图像数据块；
    和/或，若检测到当前图像数据块的最后一行数据，将最后一行数据的下一行数据所在的图像数据块，确定为与所述像素点关联的图像数据块。
  27. 根据权利要求25所述的检测电路，其特征在于，所述检测电路在从用于存储所述图像数据块的第一类地址块中读取所述图像数据块时具体用于：在用于对所述像素点进行连通域检测的当前图像数据块的检测完成之后，从用于存储所述图像数据块的第一类地址块中读取所述图像数据块。
  28. 根据权利要求24所述的检测电路，其特征在于，
    所述检测电路在从外部存储介质的第一类地址块中读取图像数据块时具体用于：从外部存储介质的第一类地址块的起始地址开始，依次读取M*N个像素点的数据，并将读取的数据组成所述图像数据块；其中，M和N为大于等于1的整数值，M为所述图像数据块的行数，N为所述图像数据块的列数。
  29. 根据权利要求24所述的检测电路，其特征在于，
    所述检测电路还用于：将所述原始图像数据划分成多个图像数据块，并将所述外部存储介质的存储空间划分成与所述多个图像数据块对应的多个第一类地址块；将每个图像数据块存储到该图像数据块对应的第一类地址块。
  30. 根据权利要求24所述的检测电路，其特征在于，
    所述检测电路在将读取的图像数据块存储到内部存储介质的第二类地址块中时具体用于：从映射表中确定所述第一类地址块对应的第二类地址块；将读取的图像数据块存储到所述第一类地址块对应的第二类地址块；其中，所述映射表用于记录第一类地址块和第二类地址块的映射关系。
  31. 根据权利要求24所述的检测电路，其特征在于，所述检测电路在利 用所述第二类地址块中存储的图像数据块进行连通域检测时具体用于：在对所述第二类地址块中存储的图像数据块中的第一像素点进行连通域检测时，从所述图像数据块中选取所述第一像素点关联的第二像素点；若存在所述第二像素点的状态信息，则根据所述第二像素点的状态信息进行连通域检测；其中，所述状态信息用于指示所述第二像素点是否进行过连通域检测。
  32. 根据权利要求31所述的检测电路，其特征在于，所述检测电路在根据所述第二像素点的状态信息进行连通域检测时具体用于：若所述状态信息为未进行连通域检测，则检测所述第二像素点与所述第一像素点是否属于同一个连通域，根据检测结果更新第二像素点的状态信息；若所述状态信息为已进行连通域检测，且检测结果为不连通，则确定所述第二像素点和所述第一像素点不属于同一个连通域；若所述状态信息为已进行连通域检测，且检测结果为连通，则确定所述第二像素点和所述第一像素点属于同一个连通域。
  33. 根据权利要求31所述的检测电路，其特征在于，
    所述检测电路在选取与所述第一像素点关联的第二像素点之后还用于：若不存在所述第二像素点的状态信息，则检测所述第二像素点与所述第一像素点是否属于同一个连通域，根据检测结果更新第二像素点的状态信息。
  34. 根据权利要求31-33任一项所述的检测电路，其特征在于，
    所述检测电路还用于：在从外部存储介质的第一类地址块中读取图像数据块时，从所述外部存储介质中读取所述图像数据块中的每个像素点对应的状态信息；将读取的状态信息存储到所述内部存储介质的寄存器中；
    所述检测电路在将读取的状态信息存储到所述内部存储介质的寄存器中之后还用于，在使用所述图像数据块中的像素点进行连通域检测后，确定该像素点对应的状态信息，并在所述寄存器中更新该像素点对应的状态信息；将所述寄存器中的所有状态信息更新到所述外部存储介质。
  35. 根据权利要求24所述的检测电路，其特征在于，所述检测电路包括：
    现场可编程门阵列FPGA芯片或者专用集成电路ASIC芯片。
  36. 一种连通域检测设备，其特征在于，所述连通域检测设备包括：
    存储器，用于存储程序代码；
    检测电路，用于调用所述程序代码，当所述程序代码被执行时，实现权利要求1-23任一项所述的连通域检测方法。
  37. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有若干计算机指令，所述计算机指令被执行时，实现权利要求1-23任一项所述的连通域检测方法。
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