WO2019127054A1

WO2019127054A1 - Frequency generating apparatus and frequency generating method

Info

Publication number: WO2019127054A1
Application number: PCT/CN2017/118763
Authority: WO
Inventors: 杨光; 李志成
Original assignee: 海能达通信股份有限公司
Priority date: 2017-12-26
Filing date: 2017-12-26
Publication date: 2019-07-04

Abstract

Disclosed in the present invention is a frequency generating apparatus, comprising: a reference frequency generating circuit used for producing a reference frequency; a frequency synthesising circuit connected to the reference frequency generating circuit and used for producing a corresponding synthesised frequency on the basis of the reference frequency and the configuration parameters of the frequency synthesising circuit; a frequency extraction circuit connected to the frequency synthesising circuit and used for extracting a high order mirror image frequency from the synthesised frequency; and a phase-locked loop circuit connected to the frequency extraction circuit and used for outputting a corresponding output frequency on the basis of the high order mirror image frequency and the configuration parameters of the phase-locked loop circuit. Also disclosed in the present invention is a frequency generating method. By means of the present method, the present invention can reduce phase noise and spurs whilst implementing rapid frequency hopping and high frequency resolution.

Description

Frequency generating device and frequency generating method

[Technical Field]

The present invention relates to the field of electronic circuit technology, and in particular, to a frequency generating device and a frequency generating method.

【Background technique】

The development of frequency hopping communication technology is very rapid, with anti-interception and anti-interference characteristics. The frequency hopping frequency source is the core of the frequency hopping technology, and its advantages and disadvantages will directly affect the performance of the entire system. The faster the lock time, the higher the frequency jump rate, and the better the anti-interception and anti-interference performance. Phase noise and spurs are also extremely important for improving adjacent channel immunity and blocking. Therefore, designing a fast frequency hopping frequency source with low spurious, low phase noise and high frequency resolution is especially important for frequency hopping technology.

At present, for the FM frequency source, the frequency hopping frequency is generated in the following ways: the first is to use the fractional frequency division double phase-locked loop to achieve fast frequency hopping, high frequency resolution; the second is to use DDS (Direct Digital Synthesizer, direct digital frequency synthesizer) output the fundamental frequency f ₀ as the reference frequency of the PLL (Phase Locked Loop); the third is to take the fundamental frequency f _{0 of the} DDS output, and then the clock frequency f _clk Mixing, after raising the frequency to f _clk +f ₀ , as the reference frequency of the PLL. In the first scheme, the VCO (Voltage-Controlled Oscillator) of the fractional-frequency dual-PLL leaks and interferes with each other, and the loop bandwidth is too narrow, the anti-vibration capability is weak, and the frequency drifts with the vibration; In the two schemes, the fundamental frequency f _{0 of the} DDS output is used as the reference frequency of the PLL, and the reference frequency is not higher than f _clk /2, which leads to an increase in the octave number of the PLL, which in turn leads to a higher output spur of the PLL. In the third scheme, the fundamental frequency of the DDS output is taken, and then mixed with the clock to increase the frequency to f _clk +f ₀ . As the reference frequency of the PLL, the circuit structure of the scheme is complicated, and high-order is easy to be generated after mixing. Stray.

[Summary of the Invention]

The technical problem to be solved by the present invention is to provide a frequency generating device and a frequency generating method capable of reducing phase noise and spurs in the case of realizing fast frequency hopping and high frequency resolution.

In order to solve the above technical problem, a technical solution adopted by the present invention is to provide a frequency generating device, the frequency generating device comprising: a base frequency generating circuit for generating a reference frequency; and a frequency synthesizing circuit connected to the base frequency generating circuit, The utility model is configured to generate a corresponding synthesis frequency according to a configuration parameter of the reference frequency and the frequency synthesis circuit; a frequency extraction circuit connected to the frequency synthesis circuit for extracting a high-order image frequency from the synthesized frequency; and a phase-locked loop circuit connected to the frequency extraction circuit For outputting the corresponding output frequency according to the high-order image frequency and the configuration parameters of the phase-locked loop circuit.

The frequency extraction circuit is a band pass filter.

Among them, the frequency synthesis circuit is a direct digital frequency synthesizer.

The phase-locked loop circuit is an integer frequency division phase-locked loop.

The frequency generating device further includes an amplifying circuit, and the phase locked loop circuit is connected to the frequency extracting circuit through the amplifying circuit, and the amplifying circuit is configured to amplify the high order image frequency and output the signal to the phase locked loop circuit.

The phase-locked loop circuit comprises: a phase detector, connected to the frequency extraction circuit; a loop filter circuit connected to the phase detector; and a voltage controlled oscillator connected to the loop filter circuit and the phase detector.

The loop filter circuit includes a wide loop filter, a narrow loop filter, a first selection circuit, and a second selection circuit. The first end of the wide loop filter is connected to the phase detector through the first selection circuit, and is wide. The second end of the loop filter is connected to the voltage controlled oscillator through a second selection circuit, and the first end of the narrow loop filter is connected to the phase detector through the first selection circuit, and the second end of the narrow loop filter is passed The second selection circuit is coupled to the voltage controlled oscillator.

Among them, the wide loop filter and the narrow loop filter are low pass filters.

The frequency generating device further includes an output end filter circuit, and the output end filter circuit is connected to the phase locked loop circuit and configured to filter the output frequency and output the same.

The output filter circuit is a high-pass filter.

The fundamental frequency generating circuit is a crystal oscillator.

In order to solve the above technical problem, another technical solution adopted by the present invention is to provide a frequency generating method, which comprises: generating a reference frequency by using a base frequency generating circuit; and synthesizing a circuit according to a reference frequency and a frequency using a frequency synthesizing circuit The parameter generates a corresponding synthesis frequency; the frequency extraction circuit is used to extract a high-order image frequency from the synthesized frequency; and the phase-locked loop circuit is used to output a corresponding output frequency according to the high-order image frequency and the configuration parameter of the phase-locked loop circuit.

The invention has the beneficial effects that: in contrast to the prior art, the present invention generates a reference frequency by setting a fundamental frequency generating circuit; the frequency synthesizing circuit is connected with the fundamental frequency generating circuit to generate a corresponding synthesis according to the configuration parameters of the reference frequency and the frequency synthesizing circuit. Frequency; the frequency extraction circuit and the frequency synthesis circuit are connected to extract a high-order image frequency from the synthesized frequency; the phase-locked loop circuit is connected with the frequency extraction circuit for outputting a corresponding output frequency according to the high-order image frequency and the configuration parameter of the phase-locked loop circuit, By extracting the high-order image frequency of the synthesized frequency of the frequency synthesis circuit as the reference frequency of the phase-locked loop circuit, the reference frequency of the phase-locked loop circuit can be improved, the spur and phase noise of the output frequency of the phase-locked loop circuit can be reduced, and The frequency synthesizing circuit improves the frequency resolution and avoids the use of the fractional-frequency phase-locked loop, thereby avoiding the defects of high spurious amplitude, many spurious points, high-end phase noise elevation and leakage of the double-loop phase-locked loop voltage-controlled oscillator. To achieve low spur, low phase noise, fast frequency hopping frequency source, can achieve fast frequency hopping and Reduce the phase noise and spurious frequency resolution of the case.

[Description of the Drawings]

1 is a schematic diagram showing the circuit structure of a frequency generating device of the present invention;

2 is a schematic flow chart of a frequency generating method of the present invention;

3 is a schematic diagram of phase noise of a low noise reference source _fr1 ;

4 is a schematic diagram of phase noise of a high noise reference source _fr2 ;

5 is a schematic diagram of phase noise of a phase-locked loop circuit when the reference source of the phase-locked loop circuit is f _r1 and the loop bandwidth of the phase-locked loop circuit is a narrow loop bandwidth;

6 is a schematic diagram of phase noise of a phase-locked loop circuit when the reference source of the phase-locked loop circuit is f _r2 and the loop bandwidth of the phase-locked loop circuit is a narrow loop bandwidth;

7 is a schematic diagram of phase noise of a phase-locked loop circuit when the reference source of the phase-locked loop circuit is f _r1 and the loop bandwidth of the phase-locked loop circuit is a wide loop bandwidth;

8 is a schematic diagram of phase noise of a phase-locked loop circuit when the reference source of the phase-locked loop circuit is f _r2 and the loop bandwidth of the phase-locked loop circuit is a wide loop bandwidth;

9 is a schematic diagram of a lock time of a phase-locked loop circuit when the reference source of the phase-locked loop circuit is f _r1 and the loop bandwidth of the phase-locked loop circuit is a wide loop bandwidth;

10 is a schematic diagram of a lock time of a phase-locked loop circuit when the reference source of the phase-locked loop circuit is f _r2 and the loop bandwidth of the phase-locked loop circuit is a wide loop bandwidth;

11 is a schematic diagram showing phase noise of a phase-locked loop circuit in which the phase-locked loop circuit reference source is f _r1 , the phase-locked loop circuit has a narrow loop bandwidth, and the phase-locked loop circuit uses a fractional-frequency loop;

12 is a schematic diagram of phase noise of a phase-locked loop circuit when the reference phase of the phase-locked loop circuit is f _r2 , the loop bandwidth of the phase locked loop circuit is a narrow loop bandwidth, and the phase locked loop circuit adopts a fractional frequency division;

13 is a schematic diagram showing phase noise of a phase-locked loop circuit when the reference phase of the phase-locked loop circuit is f _r1 , the loop bandwidth of the phase-locked loop circuit is a wide loop bandwidth, and the phase-locked loop circuit uses fractional frequency division;

14 is a schematic diagram of phase noise of a phase-locked loop circuit in which the phase-locked loop circuit reference source is f _r2 , the phase-locked loop circuit has a wide loop bandwidth, and the phase-locked loop circuit uses a fractional-frequency loop.

【Detailed ways】

The invention will now be described in detail in conjunction with the drawings and embodiments.

Please refer to FIG. 1. FIG. 1 is a schematic diagram showing the circuit structure of a frequency generating apparatus according to the present invention. In the present embodiment, the frequency generating means includes a fundamental frequency generating circuit 11, a frequency synthesizing circuit 12, a frequency extracting circuit 13, an amplifying circuit 14, a phase locked loop circuit 15, and an output side filter circuit 16.

The fundamental frequency generating circuit 11 is for generating a reference frequency. The fundamental frequency generating circuit 11 can be a crystal oscillator. The reference frequency can be the clock frequency f _clk .

The crystal oscillator may be a TCXO (Temperature Compensate X'tal Oscillator). The crystal oscillator can also be a non-temperature compensated crystal oscillator, a voltage controlled crystal oscillator, a thermostatically controlled crystal oscillator, or a digital / μp compensated crystal oscillator.

The frequency synthesizing circuit 12 is connected to the fundamental frequency generating circuit 11 for generating a corresponding synthesizing frequency based on the reference frequency and the configuration parameters of the frequency synthesizing circuit.

The frequency synthesizing circuit 12 may be a DDS (Direct Digital Synthesizer).

In particular, in one embodiment, frequency synthesis circuit 12 may include a frequency control register, a high speed phase accumulator, a sinusoidal calculator, and a digital to analog converter. The frequency control register can load and register the frequency control code input by the user (ie, the configuration parameters of the frequency synthesizing circuit described above) in a serial or parallel manner. The phase accumulator performs phase accumulation in each clock cycle (determined by the clock frequency f _clk received from the fundamental frequency generating circuit) according to the frequency control code to obtain a phase value; the sine calculator calculates the digital sine wave amplitude for the phase value. A digital sine wave is obtained (by looking up the table); the digital-to-analog converter converts the digitized sine wave into an analog frequency signal, which is the above-mentioned synthesized frequency. It can be seen from the Nyquist criterion that the clock frequency must be at least twice the synthesized frequency output by the frequency synthesizing circuit 12, and the synthesized frequency of the actual highest output is limited to about 1/3 of the clock frequency f _clk .

The frequency extraction circuit 13 is connected to a frequency synthesis circuit 12 for extracting a high-order image frequency from the synthesized frequency.

The frequency extraction circuit 13 can be a band pass filter. The bandpass filter is set to allow only high-order image frequencies to pass, while filtering the frequency components of other bands. The synthesized frequencies including the fundamental frequency f ₀ (main signal), the fundamental frequency harmonic component m f _₀ f ₀ of the fundamental frequency f ₀ of the image frequency _{_{n * f clk ± f 0 (}} n is a positive integer) and a harmonic component m f The image frequency of ₀ is n*f _clk ±m f ₀ . Image frequency can be higher order frequency _{_{n * f clk ± f 0 (}} n is a positive integer) frequency f ₀ of the mirror group.

In this embodiment, the method of extracting the high-order image frequency of the synthesized frequency by using the band pass filter is simple, and the circuit structure is simplified, and no additional spurs are generated.

The phase locked loop circuit (PLL) 15 can be connected to the frequency extracting circuit 13 through the amplifying circuit 14. The amplifying circuit 14 is used for amplifying the high-order image frequency and outputting it to the phase-locked loop circuit 15, which may be a high-order The power of the image frequency is amplified and output to the phase locked loop circuit 15. The phase locked loop circuit can be an integer frequency division phase locked loop.

The amplifier circuit 14 may be an LNA (Low Noise Amplifier).

The phase locked loop circuit 15 is configured to output a corresponding output frequency according to the high order image frequency and the configuration parameters of the phase locked loop circuit.

The phase locked loop circuit 15 includes a phase detector (PD) 151, a loop filter circuit 152, and a voltage controlled oscillator (VCO) 153. The reference source connection terminal a of the phase detector 151 is connected to the frequency extraction circuit 13 through the amplification circuit 14 so that the high-order image frequency is used as a reference source of the phase-locked loop circuit; the loop filter circuit 152 and the output terminal c of the phase detector 151 The voltage controlled oscillator 153 is connected to the loop filter circuit 152 and the phase detector 151. Specifically, the voltage controlled oscillator 153 is connected to the feedback terminal b of the phase detector 151.

The phase locked loop circuit 15 can also include a frequency division ratio register (not shown). The configuration parameter of the phase locked loop circuit 15 may be a configuration parameter of the frequency division ratio register of the phase locked loop circuit 15, by which the output frequency of the voltage controlled oscillator 153 can be controlled.

The loop filter circuit 152 includes a wide loop filter 21, a narrow loop filter 22, a first selection circuit 23, and a second selection circuit 24. The first end of the wide loop filter 21 is connected to the phase detector 151 via a first selection circuit 23, and the second end of the wide loop filter 21 is connected to the voltage controlled oscillator 153 via a second selection circuit 24, a narrow loop The first end of the filter 22 is connected to the phase detector 151 via a first selection circuit 23, and the second end of the narrow loop filter 22 is connected to the voltage controlled oscillator 153 via a second selection circuit 24. The wide loop filter 21 or the narrow loop filter 22 is connected between the phase detector 151 and the voltage controlled oscillator 153 by the control of the first selection circuit 23 and the second selection circuit 24.

In this embodiment, the wide-band and narrow-band loop low-pass filter is switched by using a switch, so that the frequency generating device can be used to generate both a frequency hopping frequency and a fixed frequency. The frequency hopping mode shortens the loop lock time with a larger loop bandwidth, and the fixed frequency mode reduces the near phase noise and the adjacent channel power ratio (ACPR, Adjacent Channel Power Ratio) with a smaller loop bandwidth.

The first selection circuit 23 can be a first single pole double throw switch 23 and the second selection circuit 24 can be a second single pole double throw switch 24. The fixed end of the first single-pole double-throw switch 23 is connected to the phase detector. The first moving end of the first single-pole double-throw switch 23 is connected to the wide loop filter, and the second moving end of the first single-pole double-throw switch 23 is connected to the narrow loop. filter. The fixed end of the second single pole double throw switch 24 is connected to the voltage controlled oscillator, the first moving end of the second single pole double throw switch 24 is connected to the wide loop filter, and the second moving end of the second single pole double throw switch 24 is connected to the narrow loop. Road filter.

Both the wide loop filter 21 and the narrow loop filter 22 are low pass filters.

The output filter circuit 16 is connected to the phase locked loop circuit 15 and is used for filtering the output frequency and outputting it.

The frequency generating device may further include a control circuit (not shown), the frequency control register of the frequency synthesizing circuit 12, the frequency dividing ratio register of the phase locked loop circuit 15, the phase detector 151, the first selecting circuit 23, and the The two selection circuits 24 are connected.

Next, the operation flow of the frequency generating apparatus of this embodiment will be described.

1. The control circuit reads the target frequency and the working mode.

2. The control circuit outputs a corresponding control signal to the first selection circuit 23 and the second selection circuit 24 according to the operation mode to select the wide loop filter 21 or the narrow loop filter 22 to be connected to the phase detector 151 and the voltage controlled oscillator. Between 153, when the wide loop filter 21 is connected between the phase detector 151 and the voltage controlled oscillator 153, the loop bandwidth of the phase locked loop circuit 15 is a wide loop bandwidth, for example, the loop bandwidth is 150 kHz, When the narrow loop filter 22 is connected between the phase detector 151 and the voltage controlled oscillator 153, the loop bandwidth of the phase locked loop circuit 15 is a wide loop bandwidth, for example, the loop bandwidth is 40 kHz.

3. The control circuit calculates the frequency control register of the frequency synthesizing circuit 12 and the configuration parameter of the frequency division ratio register of the phase locked loop circuit 15 according to the target frequency;

4. configuring the frequency control register of the frequency synthesis circuit 12 according to the configuration parameters;

5. Configure the division ratio register of the phase locked loop circuit 15 according to the configuration parameters.

6. Detect the locking condition of the phase locked loop circuit 15 and report the locking condition.

Please refer to FIG. 2. FIG. 2 is a schematic flow chart of the frequency generating method of the present invention. In this embodiment, the frequency generating method includes the following steps:

Step S11: generating a reference frequency by using a fundamental frequency generating circuit.

In step S11, for example, the reference frequency is generated by the fundamental frequency generating circuit 11. See the description above for details.

Step S12: The frequency synthesis circuit generates a corresponding synthesis frequency according to the reference frequency and the configuration parameters of the frequency synthesis circuit.

In step S12, the frequency synthesizing circuit 12 generates a corresponding synthesizing frequency based on the reference frequency and the configuration parameters of the frequency synthesizing circuit 12. See the description above for details.

Step S13: extracting a high-order image frequency from the synthesized frequency by using a frequency extraction circuit.

In step S13, for example, the high-order image frequency is extracted from the synthesized frequency by the frequency extracting circuit 13.

Step S14: The phase-locked loop circuit is used to output a corresponding output frequency according to the high-order image frequency and the configuration parameter of the phase-locked loop circuit.

In step S14, for example, the phase-locked loop circuit 15 outputs a corresponding output frequency based on the high-order image frequency and the configuration parameters of the phase-locked loop circuit 15.

It may also include prior to step S14 amplifying the higher order image frequency with the amplifying circuit 14.

It may also include, after step S14, filtering the output frequency of the phase locked loop circuit 15 using the output filter circuit 16.

The synthesis frequency will be described below by taking the frequency synthesizing circuit 12 as an example of the DDS.

The phase noise of the output frequency of the phase-locked loop circuit is degraded by 20logN. To reduce the amount of deterioration, only the frequency division ratio can be reduced. To reduce the frequency division ratio, the combined frequency of the DDS output must be increased. After the clock frequency f _clk of the DDS is determined, the DDS is determined. The synthesized output of the highest output is not higher than f _clk /2 (the actual output is lower, not higher than f _clk /3). However, the band-pass filter (i.e., the frequency extraction circuit 13) extracts the high-order image frequency n*f _clk ±f ₀ of the synthesized frequency of the DDS output to obtain a higher output frequency.

The following describes the effect of the high-order image frequency as the reference source of the phase-locked loop circuit on the phase noise of the phase-locked loop circuit.

The amplitude of the high-order image frequency is small, and the noise of the bottom is deteriorated after being amplified by the amplifying circuit. However, the phase noise in the loop bandwidth of the phase-locked loop circuit is determined by the near-phase phase noise phase noise of the reference source, and the phase noise outside the loop bandwidth of the phase-locked loop circuit is determined by the phase noise of the far-end phase noise of the voltage controlled oscillator. . Therefore, the noise floor degradation of the reference source has no significant effect on the phase noise of the phase-locked loop circuit and can be ignored.

The following describes the influence of the noise floor of the reference source of the phase-locked loop circuit on the phase noise and lock-up time of the phase-locked loop circuit.

Please refer to FIG. 3-8. FIG. 3 is a schematic diagram of the phase noise of the low noise reference source f _r1 ; FIG. 4 is a schematic diagram of the phase noise of the high noise reference source f _r2 ; FIG. 5 is a reference source of the phase locked loop circuit as f _r1 and phase locked The phase noise diagram of the phase-locked loop circuit when the loop bandwidth of the loop circuit is a narrow loop bandwidth; FIG. 6 is the phase-locked loop circuit reference source is f _r2 and the loop bandwidth of the phase-locked loop circuit is phase-locked when the loop bandwidth is narrow The phase noise diagram of the loop circuit; FIG. 7 is a schematic diagram of the phase noise of the phase-locked loop circuit when the reference source of the phase-locked loop circuit is f _r1 and the loop bandwidth of the phase-locked loop circuit is a wide loop bandwidth; FIG. 8 is a phase-locked loop The phase noise diagram of the phase-locked loop circuit when the circuit reference source is f _r2 and the loop bandwidth of the phase-locked loop circuit is a wide loop bandwidth. In Figure 3-4, the abscissa is the offset frequency (Offset Frqunency) in Hertz (Hz); the ordinate represents the SSB Phase Noise in dBc/Hz. In Figure 5-8, the abscissa is the frequency (Frqunency), the unit is Hertz (Hz); the ordinate is phase noise (Phase Noise), the unit is dBc/Hz.

The phase noise of the phase-locked loop circuit is simulated by using two reference sources respectively. Except for the reference source noise, the other parameters are set the same, and the loop bandwidth of the phase-locked loop circuit is set to 40KHz. Specifically, two 104MHz reference sources f _r1 and f _r2 with different bottom noises are selected, and the reference noise of the reference source f _r1 is lower than f _r2 . Approximate equivalent to f _r1 is the output of the crystal oscillator and f _r2 is the extracted high-order image frequency. The simulation results are shown in Figures 5 and 6. Analysis of Figures 3-6 shows that the phase noise outside the loop bandwidth is essentially unaffected by the reference source noise; the effect within the loop bandwidth is also very small.

The phase noise of the phase-locked loop circuit is simulated by using two reference sources respectively. Except for the reference source noise, the other parameters are set the same, and the loop bandwidth of the phase-locked loop circuit is set to 150KHz. Specifically, two 104MHz reference sources f _r1 and f _r2 with different bottom noises are selected, and the reference noise of the reference source f _r1 is lower than f _r2 . Approximate equivalent to f _r1 is the output of the crystal oscillator and f _r2 is the extracted high-order image frequency. The simulation results are shown in Figures 7 and 8. Analysis of Figure 3, Figure 4, Figure 7, and Figure 8 shows that the phase noise outside the loop bandwidth is basically unaffected by the reference source noise; the effect within the loop bandwidth is also very small.

Please refer to FIG. 9 and FIG. 10. FIG. 9 is a schematic diagram of the lock time of the phase-locked loop circuit when the reference source of the phase-locked loop circuit is f _r1 and the loop bandwidth of the phase-locked loop circuit is a wide loop bandwidth; FIG. 10 is a phase-locked loop. The lock time of the phase-locked loop circuit when the circuit reference source is f _r2 and the loop bandwidth of the phase-locked loop circuit is a wide loop bandwidth. In Figure 9-10, the abscissa represents time (Time) in microseconds (μs); the ordinate represents abs frequency error in Hertz (Hz).

The lock time is simulated using the reference sources f _r1 and f _r2 respectively, and the other parameters are set the same except for the reference source noise. The loop bandwidth is set to 150KHz. If the lock request: frequency deviation Δf ≤ 10Hz. The simulation results are shown in Figures 9 and 10. Analysis of Figure 3, Figure 4, Figure 9, and Figure 10 shows that the lock time is not affected by the noise floor of the reference source, and the lock time is about 40 microseconds.

It is worth noting that in the above simulation examples, the division ratio of the division ratio register of the phase-locked loop circuit is configured as an integer division ratio. The following describes the division ratio of the phase-locked loop circuit using the fractional reference frequency source. The effect of noise on the phase noise of the phase-locked loop circuit.

Please refer to FIG. 11-14. FIG. 11 is the phase noise of the phase-locked loop circuit reference source is f _r1 , the loop bandwidth of the phase locked loop circuit is a narrow loop bandwidth, and the phase locked loop circuit adopts fractional frequency division. Schematic diagram; FIG. 12 is a schematic diagram of the phase noise of the phase-locked loop circuit when the reference source of the phase-locked loop circuit is f _r2 , the loop bandwidth of the phase-locked loop circuit is a narrow loop bandwidth, and the phase-locked loop circuit adopts fractional frequency division; The phase-locked loop circuit reference source is f _r1 , the phase-locked loop circuit has a wide loop bandwidth and the phase-locked loop circuit uses a fractional-frequency loop phase-locked loop circuit phase noise diagram; FIG. 14 is a phase-locked loop circuit The reference source is f _r2 , the loop bandwidth of the phase locked loop circuit is a wide loop bandwidth, and the phase noise of the phase locked loop circuit is adopted when the phase locked loop circuit adopts fractional frequency division. In Figure 11-14, the abscissa is the frequency (Frqunency), the unit is Hertz (Hz); the ordinate is phase noise (Phase Noise), the unit is dBc/Hz.

Analysis of Figure 11 - Figure 14 shows that when the division ratio of the phase-locked loop circuit is configured as a fractional number, the influence of the noise floor of the reference source on the phase noise in the loop bandwidth is very small. This is related to the division ratio of the phase-locked loop circuit. The conclusions configured as integers are consistent. However, when fractional division is used, the phase noise outside the loop bandwidth is obviously not as good as the integer division, which is prone to spurs, and the wider the loop bandwidth, the more obvious the out-of-band phase noise deterioration. That is to say, when the loop bandwidth of the phase-locked loop circuit is wide, the far-end phase noise using the integer frequency division fractional frequency division is better, and there is no fractional spur and phase noise of Δ-∑ modulation, and the loop bandwidth is higher. The wider the gap is.

Different from the prior art, the embodiment of the present invention generates a reference frequency by setting a base frequency generating circuit; the frequency synthesizing circuit is connected with the base frequency generating circuit to generate a corresponding synthesized frequency according to a configuration parameter of the reference frequency and the frequency synthesizing circuit; the frequency extracting circuit The high-order image frequency is extracted from the synthesized frequency by connecting with the frequency synthesizing circuit; the phase-locked loop circuit is connected with the frequency extracting circuit for outputting the corresponding output frequency according to the high-order image frequency and the configuration parameter of the phase-locked loop circuit, and extracting the frequency synthesizing circuit The high-order image frequency of the synthesized frequency is used as the reference frequency of the phase-locked loop circuit, which can improve the reference frequency of the phase-locked loop circuit, reduce the spur and phase noise of the output frequency of the phase-locked loop circuit, and improve the frequency synthesis circuit by using Frequency resolution, avoiding the use of fractional phase-locked loops, thus avoiding the drawbacks of high spurious amplitude, high spurious points, high-end phase noise elevation and leakage of double-loop phase-locked loop voltage-controlled oscillator, achieving low spurs , low phase noise, fast frequency hopping frequency source, can achieve fast frequency hopping and high frequency resolution Reduce phase noise and spurs in the case.

The above is only the embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent structure or equivalent process transformations made by the description of the invention and the drawings are directly or indirectly applied to other related technologies. The fields are all included in the scope of patent protection of the present invention.

Claims

A frequency generating device, wherein the frequency generating device comprises:

a base frequency generating circuit for generating a reference frequency;

a frequency synthesizing circuit, coupled to the baseband generating circuit, configured to generate a corresponding synthesized frequency according to the reference frequency and a configuration parameter of the frequency synthesizing circuit;

a frequency extraction circuit coupled to the frequency synthesis circuit for extracting a high-order image frequency from the synthesized frequency;

The phase-locked loop circuit is connected to the frequency extraction circuit for outputting a corresponding output frequency according to the high-order image frequency and the configuration parameter of the phase-locked loop circuit.
The frequency generating device according to claim 1, wherein said frequency extracting circuit is a band pass filter.
The frequency generating device according to claim 1, wherein said frequency synthesizing circuit is a direct digital frequency synthesizer.
The frequency generating apparatus according to claim 1, wherein said phase locked loop circuit is an integer frequency division phase locked loop.
The frequency generating device according to claim 1, wherein said frequency generating means further comprises an amplifying circuit, said phase locked loop circuit being connected to said frequency extracting circuit through said amplifying circuit, said amplifying circuit being used for The high-order image frequency is amplified and output to the phase-locked loop circuit.
The frequency generating device of claim 1 wherein said phase locked loop circuit comprises:

a phase detector connected to the frequency extraction circuit;

a loop filter circuit connected to the phase detector;

A voltage controlled oscillator is coupled to the loop filter circuit and the phase detector.
The frequency generating apparatus according to claim 6, wherein said loop filter circuit comprises a wide loop filter, a narrow loop filter, a first selection circuit, and a second selection circuit, said wide loop filter a first end is coupled to the phase detector by the first selection circuit, and a second end of the wide loop filter is coupled to the voltage controlled oscillator by the second selection circuit, the narrow loop A first end of the filter is coupled to the phase detector by the first selection circuit, and a second end of the narrow loop filter is coupled to the voltage controlled oscillator by the second selection circuit.
The frequency generating apparatus according to claim 7, wherein said wide loop filter and said narrow loop filter are both low pass filters.
The frequency generating device according to claim 1, wherein said frequency generating means further comprises an output filter circuit, said output filter circuit being coupled to said phase locked loop circuit and for filtering said output frequency Output.
The frequency generating device according to claim 8, wherein said output filter circuit is a high pass filter.
The frequency generating device according to claim 1, wherein said fundamental frequency generating circuit is a crystal oscillator.
A frequency generating method, wherein the frequency generating method comprises:

Generating a reference frequency using a baseband generating circuit;

Generating, by the frequency synthesizing circuit, a corresponding synthesized frequency according to the reference frequency and a configuration parameter of the frequency synthesizing circuit;

Extracting a high-order image frequency from the synthesized frequency by using a frequency extraction circuit;

And outputting a corresponding output frequency according to the high-order image frequency and the configuration parameter of the phase-locked loop circuit by using a phase-locked loop circuit.