WO2019120309A1

WO2019120309A1 - Wafer-level chip scale package (csp) structure and preparation method therefor

Info

Publication number: WO2019120309A1
Application number: PCT/CN2018/123064
Authority: WO
Inventors: 王书昶; 范艾杰; 孙智江
Original assignee: 海迪科（南通）光电科技有限公司
Priority date: 2017-12-22
Filing date: 2018-12-24
Publication date: 2019-06-27

Abstract

The present invention relates to a wafer-level chip scale package (CSP) structure and a preparation method therefor. The wafer-level CSP structure comprises a chip. A light-exiting surface of the chip is provided with a first-concentration fluorescent layer to form a package A, and less than 10% of the area of the light-exiting surface of the chip is covered by the first-concentration fluorescent layer. The top surface and side surfaces of the package A are further provided with a translucent or transparent second-concentration fluorescent layer to form a package B. The concentration of fluorescent powder in the first-concentration fluorescent layer is recorded as w1, the concentration of fluorescent powder in the second-concentration fluorescent layer is recorded as w2, and w1>w2. The first-concentration fluorescent layer and the second-concentration fluorescent layer are formed by spraying fluorescent powder twice successively, thereby facilitating achieving a target value in process production, reducing the process difficulty, and improving the yield of devices. The wafer-level CSP structure of the present invention can improve the heat dissipation performance of light emitting chips, reduce the preparation costs of devices, and improve the reliability and uniformity of the devices.

Description

Wafer level chip level CSP package structure and preparation method thereof

Technical field

The invention belongs to the technical field of semiconductor packaging, and in particular relates to a wafer level chip level CSP package structure and a preparation method thereof.

Background technique

Light-emitting diodes (LEDs) have the advantages of small size, long service life, energy saving, fast response, and durability. They are widely used in automotive and indoor lighting, traffic lights, screen displays and LCD backlights. They are ideal for replacing traditional light sources. light source. The package structure of the light emitting diode usually wraps the phosphor. The phosphor is typically mixed in an encapsulant to change the color of the light emitted by the LED. LEDs from the package form sooner or later, can be roughly divided into: the earliest in-line package (LAMP), commonly seen in some low-end lighting display devices; surface mount package (SMD, Surface Mount Device), this package The method generally started in China around 2008; COB (Chip On Board), this packaging method was first promoted by Toshiba, and popular in China after 2010; Chip Scale Package (CSP), This type of packaging has emerged in recent years based on the development of flip chip technology, and commercial mass production has occurred after 2015. The development of packaging technology can refer to the literature: Wang Jietian, the current status and development of LED packaging technology [J]. Technology Innovation and Application, 2017(12):42.

The COB package is a solder and phosphor colloidal package in which the LED chip is directly fixed on the PCB with a conductive adhesive or an insulating paste, and then the LED chip is turned on. The main process flow of COB packaging technology is shown in Figure 8.

In recent years, with the continuous advancement of LED in device materials, chip technology, packaging technology, etc., especially the gradual maturity of flip-chip and the diversification of phosphor coating technology, a new chip-scale package CSP technology It came into being. The so-called CSP light source refers to a type of LED device, the core of which is that the CSP light source uses a phosphor or a fluorescent colloid film to wrap the flip chip structure. Therefore, most of the packaging steps and structures of the conventional LED light source are eliminated, so that the package size is greatly reduced, which is 1/5 to 1/10 of the original. However, the current CSP light source packaging technology is often after the wafer is diced and split, after sorting and rearranging the light-emitting chip, followed by phosphor or fluorescent colloid lamination, spraying and other subsequent processes, and often forming a single layer of opaque phosphor colloid The layer is thicker. Such a process is still cumbersome and the process cost is high; and because the phosphor or the fluorescent colloid layer is thick, the heat dissipation of the light-emitting chip is poor; the distance of the light-emitting chip after the split is small, which is to cut and separate the phosphor or fluorescent. The colloidal light-emitting chip has greater precision requirements. Moreover, it is often difficult to achieve the amount of powder sprayed or the accuracy of the amount of powder sprayed. These problems will increase the cost of the device, and the reliability and uniformity of the device will be greatly reduced.

The four major challenges faced by conventional CSP light source technology are:

(1) CSP is not easy to mount, and it is difficult to weld on the upper plate. Since the positive and negative electrode spacing of the chip is only 90-200 micrometers, the precision of the SMT patch is high, which is easy to cause the CSP to rotate or tilt. Therefore, the chip and the solder paste need to be precisely aligned, otherwise the risk of leakage and open circuit reliability is easy. . In addition, the traditional CSP phosphor is opaque, whether the chip is neatly arranged in the package, and whether the offset is unknown, which will increase the difficulty of mounting, and the chip and the pad cannot be accurately positioned, as shown in FIG. 9 and FIG. 10 ( Inside the red box is the chip core).

(2) The width of the side of the CSP is generally uneven, resulting in uneven color of light, and some products may even produce yellow edges, as shown in Figure 11; chip placement, cutting error brings inconsistent CSP side thickness, resulting in side Light uniformity is affected, as shown in Figure 12. At the same time, high-precision placement and cutting equipment are expensive and have low production capacity.

(3) Since the uniformity, width, and side luminescence of the phosphor are difficult to control, the Bin rate after one application is low, as shown in FIG.

(4) The phosphor layer is thicker, resulting in poor heat dissipation. Generally, at high optical density, in addition to the LED chip itself, the phosphor generates a large amount of heat while emitting yellow-green light in the down-conversion, so it is necessary to perform good heat dissipation. When the phosphor colloid is thick, heat dissipation will occur. Blocked. The results show that when the surface temperature of the CSP chip reaches 150 degrees or more, the light efficiency of the light source is significantly reduced, and the phosphor colloid is cracked. At the same time, too thick a phosphor layer can cause yellowing problems; of course, the thickness of the phosphor layer is too thin, which also causes mounting and cutting problems. Due to the limitation of equipment accuracy, the error range of mounting and cutting is about 30 micrometers. If the phosphor layer is too thin, it will inevitably lead to unevenness of the sidewall phosphor layer, which will also cause unevenness of light color and blue light. The problem of leaking. The thickness of the phosphor layer selected by the invention can effectively avoid the above-mentioned problems of cutting and mounting due to the thick phosphor layer. A schematic diagram of the structure of the conventional CSP technique and the technique of the present invention is shown in FIGS. 14 and 15.

At present, the four technical problems of conventional CSP light source make CSP application face two limitations: First, small-size chip CSP placement is difficult, current CSP application is mainly limited to 1W or more applications; second, the cost is high, leading to its main The use of high-intensity, high-brightness, high-directivity light sources, including headlights, flashlights, backlights, and high-end color-adjustable lighting applications, is difficult to extend to other areas. See the table below for a comparison of several common LED chip package technologies.

Comparison of several common LED chip packaging technologies

In view of the conventional CSP technical problem, the CSP structure of the present invention further extends the packaging process and the chip process to the upstream chip process, and encapsulates on the wafer scale to form an opaque core, and an outer peripheral semi-transparent phosphor, which effectively solves The above-mentioned problems faced by conventional CSPs can greatly improve the CSP technology.

First, the translucent layer package facilitates placement. The solid crystal machine mainly has two main parts, a PC Contronl (control) system, and a PRS (image recognition processing system), which are separately controlled by two hosts. For the CSP chip, only the chip core is accurately identified. In order to accurately mount. The second layer of the semi-transparent phosphor layer coated in the structure of the invention can greatly facilitate the solid crystal machine to accurately and accurately identify the position of the packaged chip core, and can more accurately control the position between the light source and the substrate; For the conventional CSP with an opaque phosphor layer, the solid crystal machine will not be able to accurately identify the chip core when it is solid crystal, which will easily lead to a greatly reduced chip placement yield, which will cause leakage and the like, greatly reducing the light source. Reliability. At the same time, with regard to the wafer level chip-level CSP technology of the present invention, in the application of the color temperatureable filament lamp, even two different CSP light sources can be mounted in a range of one millimeter; for accurate placement, this is One of the advantages of the present invention, as shown in FIG. 16, is that after the chip core is accurately discriminated, efficient placement can be achieved.

Second, the phosphor layer is thickened and thinned, and the heat dissipation performance is greatly improved. Generally, at high optical density, the heat source of the light source, in addition to the LED chip that is traditionally concerned, the phosphor will generate a large amount of heat while down-converting to emit yellow-green light, so it is necessary to perform good heat dissipation when the phosphor colloid is thick. The heat will be blocked. For general products, when the power reaches 4W or more, the surface temperature will reach 150 degrees or more, and the light effect will be easily reduced, and the colloid will be cracked. The wafer level chip scale CSP package structure of the present invention is the first phosphor spray on the wafer level scale, so the phosphor can be easily precipitated downward, and the precipitation only requires two-dimensional uniformity and longitudinal uniformity. No requirements. After the phosphor is precipitated, the denseness is strong, which can be closely arranged from the SEM photographs of Figs. 17 and 18. Therefore, when the phosphor absorbs about 70% of the blue light, the light is quickly conducted downward by the phosphor. In the conventional CSP technology, after the phosphor absorbs heat, in the silica gel with a thermal conductivity of only 0.2-0.7, the phosphor will continue to be heated by the excitation of the blue light, and this heat is difficult to conduct. In the same case, the surface temperature of the package structure of the present invention is only 110 to 120 degrees, thereby improving high reliability; facilitating heat dissipation, which is the second advantage of the present invention.

Third, the light color is more uniform. In the case of conventional CSP, the front side of the chip is 70% light and the side is 30% light. That is, when a certain concentration of phosphor on the front side of the chip and 70% of blue light form a positive white color, the light of the same concentration of phosphor and 30% of the blue side of the chip will be yellowish, and yellow edges appear on the edges, as shown in FIG. . In the invention, a wafer level chip-scale CSP package structure is a high concentration phosphor in the middle, and a low concentration phosphor on the side, so that 30% of the blue light on the side and 20% to 30% of the intermediate high concentration phosphor A combination of low-concentration second-layer phosphors on the left and right sides, the color of light thus obtained is uniform and uniform, as shown in FIG. The invention can effectively prevent side leakage blue light and yellow edge phenomenon caused by uneven distribution of phosphors; the light angle can be adjusted arbitrarily, and is adapted to different application requirements. The light color is more uniform, which is the third advantage of the present invention.

Therefore, the wafer level chip-scale CSP package structure capable of improving the heat dissipation performance of the light-emitting chip, reducing the device fabrication cost, and improving the reliability and uniformity of the device is very promising.

Summary of the invention

The technical problem to be solved by the present invention is to provide a wafer level chip scale CSP package structure and a preparation method thereof capable of improving heat dissipation performance of a light emitting chip, reducing device fabrication cost, and improving device reliability and uniformity.

In order to solve the above technical problem, the technical solution of the present invention is: a wafer level chip-scale CSP package structure, which is innovative in that it comprises a rectangular chip, and a first concentration phosphor layer is disposed on the light emitting surface of the chip to form Package A, and the side of the light-emitting surface of the chip is <10% area covered by the first concentration fluorescent layer; and the top surface and the side surface of the package A are further provided with a second concentration of fluorescent layer which is translucent or transparent Forming a package B; a phosphor concentration in the first concentration phosphor layer is denoted as w ₁ , a phosphor concentration in the second concentration phosphor layer is denoted as w ₂ , and w ₁ >w ₂ ; the first concentration The phosphor layers are uniform in thickness on the top surface of the chip, the second concentration phosphor layer is uniform in thickness on the top surface of the chip, and the package body B has a rectangular structure.

Further, the fluorescent layers of the first concentration fluorescent layer and the second concentration fluorescent layer are formed of any one of a phosphor or a fluorescent colloid.

Further, the phosphor concentration in the first concentration fluorescent layer is 50-90%, and the phosphor content in the second concentration fluorescent layer is 0-40%.

A method for fabricating a wafer level chip-scale CSP package structure described above is innovative: the preparation method includes the following steps:

(1) The wafer is subjected to sampling;

(2) Perform step 2.1 or step 2.2 on the qualified wafer in step (1).

The step 2.1 is specifically for filming the qualified wafers in the step (1), and cutting and dicing the wafer after the filming, and forming a first fluorescent layer directly on the entire wafer after the dicing;

The step 2.2 is specifically to form a first fluorescent layer directly on the qualified wafer on the step (1), and then to perform filming, and to cut and split the wafer after the filming;

(3) expanding the film covered with the first fluorescent layer to form a first concentration fluorescent layer, thereby forming a package A, and the orthographic projection of the top surface of the package A and the orthographic projection of the light emitting surface of the chip The error between the sides of the contour is less than 30 microns;

(4) baking and curing the expanded wafer;

(5) After baking and curing, the chip in the wafer is tested and sorted and rearranged;

(6) forming a second concentration phosphor layer that is translucent or transparent on the sorted rearranged chip, and baking and curing the chip covered with the second concentration phosphor layer;

(7) before the step (6) or after the step (6), the chip is again divided to form a wafer level chip scale package structure;

(8) For the wafer level chip scale package structure formed in the step (7), the concentration difference between the first and second concentration phosphor layers is utilized, so that the first concentration of the fluorescent layer can be observed from the outside of the package structure, and the first concentration of the fluorescent layer is passed. The position is subjected to a solid crystal test on the chip, and the qualified product package after the sorting is tested and put into storage.

Further, the first phosphor layer is in a non-cured state before the wafer is expanded in step (3).

Further, the thickness of the first concentration fluorescent layer is ≤150 μm, the thickness of the top layer of the second concentration fluorescent layer is 10 to 1000 μm, and the thickness of the sidewall is 10 to 2000 μm.

Further, after the second concentration of the phosphor layer is formed, the adjacent chip pitch is greater than 1 time of the chip size.

Further, in the step (7), before the second concentration of the fluorescent layer is formed, the sorted rearranged chip is placed on the screen type jig to evenly divide the chip.

Further, in the step (7), after the baking is cured, the chip is again divided.

Further, the second concentration of the fluorescent layer in the step (7) is formed by coating, laminating or molding.

The advantages of the invention are:

(1) The wafer level chip-scale CSP package structure of the present invention has a higher concentration of phosphors used in the first concentration phosphor layer, and the formed phosphor layer has a single side, a thin thickness, a high density, and a similar size of the light-emitting chip, which is advantageous. The light-emitting chip dissipates heat, reduces the occurrence of colloid cracking, and improves the light efficiency of the LED chip; the second concentration of the fluorescent layer uses a lower concentration of the phosphor, and the second concentration of the fluorescent layer formed is translucent or transparent, which is beneficial to the other hand. In the later process, a larger pitch of adjacent light-emitting chips is obtained, and the precision requirement of cutting and separating the light-emitting chip covering the phosphor or the fluorescent colloid is reduced, thereby improving the reliability and uniformity of the device; on the other hand, the first concentration of the phosphor layer is non- Transparent and contour is basically the same as the chip, and the second concentration layer is translucent or transparent. The double-layer WLCSP package thus produced needs to accurately and precisely align the positive and negative electrodes on the back surface to the corresponding positive and negative electrodes on the substrate. When the transparent layer is transparent or translucent, the first fluorescent layer with opaque but contour and chip equivalent can be used for accurate crystal bonding and electrode pairing. And other subsequent processes, to reduce the difficulty of the process, thereby reducing production cost devices;

(2) The method for preparing a wafer level chip-scale CSP package structure of the present invention, wherein the packaging technology adopts a phosphor layer formed twice at a wafer level and a chip level, respectively, and the surface of the phosphor layer is dense; wherein, the first formation is After the fluorescent layer, the process of expanding, baking, and rearranging the light-emitting chip, the second process of cutting and splitting the fluorescent colloid layer after spraying the phosphor on the light-emitting chip, the process flow is simple and stable, and the device is simple and stable. The yield is greatly improved;

(3) The method for preparing a wafer level chip-level CSP package structure according to the present invention, wherein the phosphor layer formed before the film expansion is in a non-hardened state, which is more advantageous for chip separation, and facilitates subsequent chip test rearrangement and the like.

DRAWINGS

The present invention will be further described in detail below in conjunction with the drawings and specific embodiments.

1 is a schematic diagram of a wafer level chip scale CSP package structure of the present invention.

2 is a cross-sectional view showing a wafer level chip-scale CSP package structure of the present invention after forming a first concentration phosphor layer.

3 is a bottom view of the wafer level chip scale CSP package structure of the present invention after forming a first concentration phosphor layer.

4 is a cross-sectional view showing the wafer level chip-scale CSP package structure of the present invention after forming a second concentration phosphor layer.

FIG. 5 is a schematic top view showing the use of a screen-like jig to assist in forming a second concentration of phosphor layer.

Fig. 6 is a schematic cross-sectional view showing the completion of the second concentration of the phosphor layer by a lamination method.

Figure 7 is a schematic cross-sectional view showing the formation of a second concentration of phosphor layer by means of a die top.

Figure 8 is a main process flow diagram of the COB packaging technology.

Figure 9 and Figure 10 show the effect of the CSP chip being inaccurately aligned and the placement failure.

Fig. 11 is a diagram showing the effect of unevenness in light color of the CSP chip and yellowing phenomenon.

Fig. 12 is a view showing an effect of inconsistency in the thickness of the CSP side due to the cutting error.

Figure 13 is a graph showing the data of the Bin rate test.

14 is a schematic structural view of a conventional CSP technology.

Figure 15 is a schematic structural view of a CSP technology of the present invention.

Figure 16 is a photo of a chip mount microscope.

Figure 17 is a schematic view of a conventional CSP structure and a cross-sectional SEM image.

Figure 18 is a schematic view of a CSP structure and a cross-sectional SEM image of the present invention.

Fig. 19 is a view showing the conventional CSP light-emitting effect.

Fig. 20 is a view showing the effect of the CSP light emission of the present invention.

Detailed ways

The following examples are intended to provide a fuller understanding of the invention, and are not intended to limit the invention.

Example 1

The wafer level chip-level CSP package structure of the present embodiment, as shown in FIG. 1 , includes a chip 1 and a chip electrode 4 disposed on the chip 1 , and a first concentration phosphor layer is disposed on a top surface of the light emitting surface of the chip 1 . 2, forming a package A; a second concentration of the phosphor layer 3 in a semi-transparent or transparent shape on the top surface and the side surface of the package A to form a package B; the phosphor in the first concentration phosphor layer 2 The concentration is denoted as w ₁ , the phosphor concentration in the second concentration fluorescent layer 3 is denoted as w ₂ , and w ₁ >w ₂ ; the first concentration of the fluorescent layer 2 is located on the top surface of the chip 1 having the same thickness, and the second concentration of the fluorescent layer 3 The thickness of the top surface of the chip 1 is uniform, and the package body B has a rectangular structure.

In this embodiment, regarding the translucent or transparent second concentration fluorescent layer 3, the second concentration fluorescent layer (ie, the skirt) and the inner chip (ie, the inner core) are imaged by the image recognition technology under the LED mounting device. The gray scale contrast is used to identify and distinguish the two. Image recognition technology is a well-known technology, and its working principle will not be described again here.

When the skirt gray value - the kernel gray value | ≥ 30, the LED mounting device can smoothly recognize the boundary between the core and the skirt, that is, the second concentration fluorescent layer 3 is considered to be transparent or translucent;

When the skirt gray value - the kernel gray value | < 30, the LED mounting device cannot smoothly distinguish the boundary between the core and the skirt, that is, the second concentration fluorescent layer 3 is considered to be opaque;

Of course, the benchmark for the above-mentioned placement equipment to be successfully identified is that in the batch industrial production, the recognition accuracy of the equipment is usually 99.5% or even higher.

For example, under the LED placement equipment, the image recognition technology is used for transparency recognition. When the concentration ratio is phosphor: silica gel: solvent=0.35:1:0.5, the machine recognition threshold is obtained by calculating the binary value of the gray value. The kernel gray value is 255. When the skirt gray value is 200, the machine kernel recognition success rate is greater than 99.95%. When the kernel gray value is 255 and the skirt gray value is 225, the machine kernel recognition success rate is 99.5%. The second concentration fluorescent layer 3 is a translucent layer; when the concentration ratio is phosphor: silica gel: solvent = 0.6:1:0.5, the machine recognizes the threshold, and the kernel gray value is 255 by calculating the gray value binary number thereof. When the skirt gray value is 240, the machine core recognition success rate is only 15%, and the second concentration phosphor layer 3 is an opaque layer.

In this embodiment, the fluorescent layers of the first concentration fluorescent layer 2 and the second concentration fluorescent layer 3 are formed by a fluorescent colloid, and the phosphor concentration in the first concentration fluorescent layer 2 is 50-90%, and the second concentration is fluorescent. The phosphor powder in layer 3 has a mass ratio of 0 to 40%; the thickness of the first concentration phosphor layer 2 is ≤150 μm, the thickness of the top layer of the second concentration phosphor layer 3 is 10 to 1000 μm, and the thickness of the sidewall is 10 to 2000 μm. In this embodiment, the side surface of the light-emitting surface of the chip may be covered by a small amount of the first concentration fluorescent layer near the top surface, and the side surface of the light-emitting surface of the chip is covered by the first concentration fluorescent layer.

The wafer level chip scale CSP package structure of this embodiment is prepared by the following steps:

(1) The wafer is subjected to sampling;

(2) Perform step 2.1 or step 2.2 on the qualified wafer in step (1).

Step 2.1 is specifically as shown in FIG. 2, the film of the qualified wafer is sampled in step (1), and the wafer is cut and lobed after the film is affixed, and the mass of the phosphor powder is sprayed on the entire wafer after the cleavage. a 50 to 90% fluorescent glue, directly forming a first sprayed fluorescent layer 5 on the chip in the wafer;

Step 2.2 is specifically as shown in FIG. 2, in the step (1), the qualified wafer is sprayed with a fluorescent glue having a phosphor mass ratio of 50-90%, and the first sprayed fluorescent layer is directly formed on the chip in the wafer. 5, and then film, and the wafer after the film is cut and split;

(3) Spreading the wafer covered with the first sprayed fluorescent layer 5, before the film is expanded, the first sprayed fluorescent layer 5 is in a non-cured state, and after the film is expanded, as shown in FIG. 3, a thickness of ≤150 μm is formed. The first concentration of the fluorescent layer 2, and further the package A, and the error between the orthographic projection of the top surface of the package A and the side of each side of the orthographic projection of the light exit surface of the chip 1 is less than 30 micrometers;

(4) baking and solidifying the wafer after the film expansion, the baking curing temperature is 30 ° C ~ 200 ° C, baking curing time is 3 ~ 12h;

(5) After baking and curing, the chip in the wafer is tested for brightness, index and color temperature photoelectric parameters, and sorted according to the test result;

(6) As shown in FIG. 4, a fluorescent paste having a phosphor mass ratio of 0 to 40% is sprayed on the sorting and rearranging chip to form a top layer having a thickness of 10 to 1000 μm and a sidewall thickness of 10 to 2000 μm. a semi-transparent or transparent second concentration phosphor layer 3, after forming the second concentration phosphor layer 3, the adjacent chip pitch is greater than 1 times the chip size, and the chip covered with the second concentration phosphor layer 3 is baked and cured, and baked. Baking curing temperature is 30 ° C ~ 200 ° C, baking curing time is 3 ~ 12h;

(7) After the baking is cured, the chip is again cut and split to form a wafer level chip scale package structure;

Example 2

Compared with the first embodiment, the wafer level chip-level CSP package structure is unchanged, and only the steps (6) and (7) in the preparation step of the wafer level chip-level CSP package structure are changed, step (6) Specifically, as shown in FIG. 5, before the second concentration of the fluorescent layer 3 is applied, the sorting and rearranging chip 1 is placed on the screen-like jig 6 to evenly divide the chip 1, and then on the chip 1 which is again divided. Spraying phosphor powder with a mass ratio of 0-40%, forming a second concentration of phosphor layer 3 having a thickness of 10 to 1000 μm, a sidewall thickness of 10 to 2000 μm, and being translucent or transparent to form a second concentration After the phosphor layer 3, the distance between adjacent chips is greater than 1 times of the chip size, and the chip covered with the second concentration phosphor layer 3 is baked and cured, the baking curing temperature is 30 ° C ~ 200 ° C, and the baking curing time is 3 ~ 12h; Step (7) is specifically: after baking and curing, forming a wafer level chip scale package structure.

For the formation of the second concentration fluorescent layer 3 in Embodiment 1 and Embodiment 2, a lamination or a mold top may be used. The lamination process is as shown in FIG. 6, and the silica gel and the phosphor are mixed in proportion to form a film. Phosphors with a phosphor content of 0-40%, then pour the fluorescent glue into the mold, bake and solidify to obtain a fluorescent film, and then adhere the fluorescent film to the surface of the sorted rearranged chip 1 and solidify again to form The second concentration of the fluorescent layer 3; using the lamination process, the second concentration of the fluorescent layer 3 is controllable in shape, uniform in thickness, and high in stability.

The mold top process is as shown in Fig. 7. First, the mold 7 is nested on the sorting and rearranging chip 1, and then the phosphor is mixed in proportion to the silica gel to form a fluorescent glue having a phosphor powder content of 0-40%. It is injected into the mold 7, and is subjected to red baking curing. After curing, the mold 7 is removed to form a solid and stable second concentration fluorescent layer 3, and then cutting is performed to obtain a single packaged chip.

The wafer level chip-scale CSP package structure prepared by the first embodiment and the second embodiment has a higher concentration of the phosphor used in the first concentration of the fluorescent layer 2, and the phosphor mass ratio is generally 50 to 90%. The single-sided, thin thickness and high density of the fluorescent layer are similar to the size of the light-emitting chip, which is beneficial to the heat dissipation of the light-emitting chip, and reduces the occurrence of colloid cracking and improves the light-effect of the LED chip; the phosphor concentration of the second-concentration fluorescent layer 3 is low. The phosphor powder proportion is generally 0-40%, and the formed second concentration fluorescent layer 3 is semi-transparent or even transparent. On the one hand, it is advantageous to obtain a larger spacing of adjacent light-emitting chips in the later process flow, and reduce the separation and separation of the fluorescent light. The accuracy of the light-emitting chip of the powder or fluorescent colloid, thereby improving the reliability and uniformity of the device; on the other hand, the semi-transparent or transparent second-concentration fluorescent layer is advantageous for accurate solid-crystal bonding through the first formed fluorescent layer. Subsequent processes such as electrode alignment reduce process difficulty and thus reduce device fabrication costs.

The basic principles and main features of the invention and the advantages of the invention have been shown and described above. It should be understood by those skilled in the art that the present invention is not limited by the foregoing embodiments, and that the present invention is only described in the foregoing description and the description of the present invention, without departing from the spirit and scope of the invention. Various changes and modifications are intended to be included within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and their equivalents.

Claims

A wafer-level chip-scale CSP package structure, comprising: a rectangular chip, a first concentration of phosphor layer disposed on the light-emitting surface of the chip, forming a package A, and a side of the light-emitting surface of the chip <10 The % area is covered by the first concentration of the fluorescent layer; the second concentration of the fluorescent layer is translucent or transparent on the top surface and the side surface of the package A to form the package B; the first concentration of the fluorescent layer The phosphor concentration is denoted as w 1 , the phosphor concentration in the second concentration phosphor layer is denoted as w 2 , and w 1 >w 2 ; the first concentration phosphor layer is located at the same thickness on the top surface of the chip, the second The concentration phosphor layer is uniform in thickness on the top surface of the chip, and the package body B has a rectangular structure.
The wafer level chip scale CSP package structure according to claim 1, wherein the phosphor layers of the first concentration phosphor layer and the second concentration phosphor layer are formed by any one of a phosphor or a fluorescent colloid. .
The wafer level chip scale CSP package structure according to claim 1 or 2, wherein the phosphor concentration in the first concentration phosphor layer is 50-90%, and the fluorescence in the second concentration phosphor layer is The powder mass ratio is 0-40%.
A method of fabricating a wafer level chip scale CSP package structure according to claim 1, wherein the preparation method comprises the following steps:

(1) The wafer is subjected to sampling;

(2) Perform step 2.1 or step 2.2 on the qualified wafer in step (1).

The step 2.1 is specifically for filming the qualified wafers in the step (1), and cutting and dicing the wafer after the filming, and forming a first fluorescent layer directly on the entire wafer after the dicing;

The step 2.2 is specifically to form a first fluorescent layer directly on the qualified wafer on the step (1), and then to perform filming, and to cut and split the wafer after the filming;

(3) expanding the film covered with the first fluorescent layer to form a first concentration fluorescent layer, thereby forming a package A, and the orthographic projection of the top surface of the package A and the orthographic projection of the light emitting surface of the chip The error between the sides of the contour is less than 30 microns;

(4) baking and curing the expanded wafer;

(5) After baking and curing, the chip in the wafer is tested and sorted and rearranged;

(6) forming a second concentration phosphor layer that is translucent or transparent on the sorted rearranged chip, and baking and curing the chip covered with the second concentration phosphor layer;

(7) before the step (6) or after the step (6), the chip is again divided to form a wafer level chip scale package structure;

(8) For the wafer level chip scale package structure formed in the step (7), the concentration difference between the first and second concentration phosphor layers is utilized, so that the first concentration of the fluorescent layer can be observed from the outside of the package structure, and the first concentration of the fluorescent layer is passed. The position is subjected to a solid crystal test on the chip, and the qualified product package after the sorting is tested and put into storage.
The method of fabricating a wafer level chip scale CSP package structure according to claim 4, wherein the first phosphor layer is in a non-hardened state before the wafer is expanded in the step (3).
The method of fabricating a wafer level chip-scale CSP package structure according to claim 4, wherein the first concentration of the phosphor layer has a thickness of ≤150 μm, and the second concentration of the phosphor layer has a top layer thickness of 10 to 1000 μm. The thickness of the side wall is 10 to 2000 μm.
The method for fabricating a wafer level chip scale CSP package structure according to claim 4, wherein after the second concentration of the phosphor layer is formed, the distance between adjacent chips is greater than 1 time of the chip size.
The method for fabricating a wafer level chip scale CSP package structure according to claim 4, wherein the step (7) places the sorted rearranged chip on the screen before forming the second concentration phosphor layer. With the chip evenly divided.
The method of fabricating a wafer level chip-scale CSP package structure according to claim 4, wherein the step (7) divides the chip again after baking and curing.
The method for fabricating a wafer level chip scale CSP package structure according to claim 4, wherein the second concentration phosphor layer in the step (7) is formed by coating, laminating or molding.