WO2019116737A1

WO2019116737A1 - Switch device

Info

Publication number: WO2019116737A1
Application number: PCT/JP2018/039494
Authority: WO
Inventors: 佑輔中小原; 裕太大河内; 健中原
Original assignee: ローム株式会社
Priority date: 2017-12-11
Filing date: 2018-10-24
Publication date: 2019-06-20

Abstract

This switch device 1 has: transistors N1 and N2 which are connected in parallel to each other and controlled to be turned on/off in response to a common gate signal SG; and inductors L1 and L2 which are respectively connected to source sides (or emitter sides) of the transistors N1 and N2. The inductor L1 and the inductor L2 are coupled to each other to have reverse polarities. Furthermore, parasitic inductors of source wires can be used as the inductors L1 and L2, respectively. For example, it is preferable that at least some sections of the source wires of the respective transistors N1 and N2 overlap each other in a plan view, and are disposed on different wire layers in a sectional view such that currents flowing through the respective sections flow in directions opposite to each other.

Description

Switch device

The invention disclosed herein relates to a switch device.

Conventionally, in a high-power switch device (for example, a switching output stage of a bidirectional power supply circuit), a large current capacity as a whole is obtained by synchronously driving a plurality of parallel-connected transistors.

In addition, patent document 1 and patent document 2 can be mentioned as an example of the prior art relevant to the above.

JP-A-9-172359 (for example, FIG. 4) Patent No. 3421544 (for example, FIG. 1)

However, when the on threshold value or the source inductance value of each of the plurality of transistors varies, the rising timing or the falling timing of the current flowing in each of the transistors deviates, which causes a problem in that each switching loss varies.

In Patent Document 1, the variation in current flowing in each of the plurality of transistors is suppressed by adjusting the gate resistance value of each of the plurality of transistors. However, such a method is not necessarily practical because fine adjustment of the gate resistance value is required. In addition, when the gate resistance value of the transistor is increased in order to suppress the variation of the current, the switching speed is decreased, which causes a problem that the switching loss is increased.

Further, in Patent Document 2, an inductor is connected to each of the plurality of transistors to suppress variations in current flowing therethrough. However, in such a method, the rise of the current is delayed to increase the switching loss, and there is room for further improvement in the current balance accuracy.

In view of the above problems found by the inventors of the present invention, the invention disclosed in the present specification causes a decrease in switching speed when synchronously driving a plurality of transistors connected in parallel. It is another object of the present invention to provide a switch device capable of suppressing variation in switching loss in each transistor.

The switch devices disclosed in the present specification are a first transistor and a second transistor connected in parallel with each other and controlled to be turned on / off according to a common gate signal, and the first transistor and the second transistor. Configuration having a first inductor and a second inductor connected to respective source side or emitter side, wherein the first inductor and the second inductor are coupled in reverse polarity to each other (first configuration) It is assumed.

In the switch device having the first configuration, the first inductor is a parasitic inductance of a first wiring connected to the source or the emitter of the first transistor, and the second inductor is the second transistor. It is preferable that the parasitic inductance of the second wiring connected to the source or the emitter of the above (second configuration).

In the switch device having the second configuration, at least a part of the sections of the first wiring and the second wiring overlap each other in a plan view, and currents flowing in the sections are opposite to each other. In order to achieve this, it is preferable to have a configuration (third configuration) laid in different wiring layers in a cross sectional view.

In the switch device having the third configuration, the first wiring is laid on a first main surface of a substrate, and the second wiring is disposed on a second main surface facing the first main surface. It is good to set it as the structure (4th structure) currently installed.

Further, in the switch device having the fourth configuration, the first transistor and the second transistor may be modularized with the substrate (fifth configuration).

Further, in the switch device having any one of the first to fifth configurations, the first transistor and the second transistor may be configured as a field effect transistor (sixth configuration).

In the switch device having any one of the first to fifth configurations, the first transistor and the second transistor may be configured as an insulated gate bipolar transistor (seventh configuration).

Further, the switch devices disclosed in the present specification include first to nth transistors (where n ≧ 2) connected in parallel with each other and turned on / off according to a common gate signal; And the (k = 1, 2,..., N−1) transformers are connected to the source side or the emitter side of the k th transistor and the (k + 1) transistor, respectively. The first inductor and the second inductor may be configured to be coupled in opposite polarities to each other (eighth configuration).

In addition, the power supply circuit disclosed in the present specification includes a switch device having any one of the first to eighth configurations as a component of a switching output stage that generates an output voltage from an input voltage Configuration of 9).

Also, the substrate disclosed in the present specification includes a first gate connection terminal for connecting the gate of the first transistor, a second gate connection terminal for connecting the gate of the second transistor, and the first gate connection terminal. A first drain connection terminal for connecting the drain of one transistor, a second drain connection terminal for connecting the drain of the second transistor, and a first source connection terminal for connecting the source of the first transistor A second source connection terminal for connecting the source of the second transistor, a common gate connection terminal for connection to the first gate connection terminal and the second gate connection terminal, and the first source connection terminal And a common source connection terminal for connection to the second source connection terminal, the first gate connection terminal, and the second gate connection terminal. A gate line for conducting the gate connection terminal, a drain line for conducting the first drain connection terminal and the second drain connection terminal, and a first source line for conducting the first source connection terminal and the common source connection terminal And a second source wiring for electrically connecting the second source connection terminal and the common source connection terminal, wherein the first source wiring and the second source wiring have at least a partial section in a plan view. A configuration (10th configuration) is laid in different wiring layers in a cross-sectional view so that the currents flowing in the sections overlap with each other in opposite directions.

According to the switch device disclosed in the present specification, it is possible to suppress variation in switching loss in each transistor when synchronously driving a plurality of parallel connected transistors without causing a decrease in switching speed. Can.

The figure which shows 1st Embodiment of a switch apparatus Diagram showing drain current and loss when on (Vth variation / without transformer) Diagram showing off drain current and loss (Vth variation / without transformer) Diagram showing drain current and loss when on (Ls variation / no transformer) Diagram showing drain current and loss when off (Ls variation / no transformer) Diagram for explaining the operating principle of the transformer at the on time Diagram showing gate-source voltage and drain current when on Diagram for explaining the operating principle of the transformer at off time Diagram showing drain current and loss when on (Vth variation / with transformer) Diagram showing off drain current and loss (Vth variation / with transformer) Diagram showing drain current and loss when on (Ls variation / with transformer) Diagram showing drain current and loss at off (with Ls variation / with transformer) Diagram showing drain current when on (coupling between inductors / without coupling) Diagram showing simulated model of source wiring A diagram showing one configuration example of a printed wiring board The figure which shows 2nd Embodiment of a switch apparatus The figure which shows 3rd Embodiment of a switch apparatus The figure which shows 4th Embodiment of a switch apparatus A diagram showing an example of configuration of a bidirectional power supply circuit

<Switch Device (First Embodiment)>
FIG. 1 is a view showing a first embodiment of the switch device. As shown in the drawing, the switch device 1 of the present embodiment includes N-channel type MOS [metal oxide semiconductor] field effect transistors N1 and N2 (for example, SiC semiconductor) and inductors L1 and L2.

The gates of the transistors N1 and N2 are both connected to the connection terminal T1 (= input terminal of the gate signal SG). The drains of the transistors N1 and N2 are both connected to the connection terminal T2. The source and back gate of the transistor N1 are connected to the connection terminal T3 via the inductor L1. The source and back gate of the transistor N2 are connected to the connection terminal T3 via the inductor L2.

Thus, the transistors N1 and N2 are connected in parallel between the connection terminal T2 and the connection terminal T3 and turned on / off according to the common gate signal SG. More specifically, the transistors N1 and N2 turn on when the gate signal SG is at high level, and turn off when the gate signal SG is at low level. The gate signal SG is supplied from a gate driver (not shown) for driving the gates of the transistors N1 and N2.

The inductors L1 and L2 are coupled in reverse polarity to each other to form a transformer TR1. In the present specification, the term "transformer" does not necessarily refer to only an electronic component in which a coil is wound around a core, and as described later, parasitic inductances associated with the source wiring of each of the transistors N1 and N2. Are to be interpreted in a broad sense so as to include an air core inductance pair, which is coupled to each other, as a kind of transformer.

In the following, in order to clarify the introduction significance of the above-mentioned transformer TR1, first, the behavior in the case where the transformer TR1 is not introduced will be briefly described.

When there is variation in on threshold Vth1 and Vth2 or source inductance values Ls1 and Ls2 of transistors N1 and N2, respectively, if transformer TR1 is not introduced, rising timings of drain currents Id1 and Id2 respectively flowing in transistors N1 and N2 Since the falling timings are shifted, the switching losses Ploss1 and Ploss2 become uneven.

FIGS. 2A and 2B are diagrams showing drain currents Id1 and Id2 (solid line and broken line in upper row) and switching losses Ploss1 and Ploss2 (solid line and broken line in lower row) when transistor N1 and N2 are on and off, respectively. . Note that, as a premise of this figure, Vth1 <Vth2 and Ls1 = Ls2, and the transformer TR1 is not introduced.

As shown in FIG. 2A, when the transistors N1 and N2 are on, the rising timing of the drain current Id1 is earlier than the rising timing of the drain current Id2. Therefore, the switching loss Ploss1 of the transistor N1 is larger than the switching loss Ploss2 of the transistor N2.

On the other hand, as shown in FIG. 2B, when the transistors N1 and N2 are off, the falling timing of the drain current Id1 is later than the falling timing of the drain current Id2. Therefore, the switching loss Ploss1 of the transistor N1 becomes larger than the switching loss Ploss2 of the transistor N2 as in the case of turning on the transistors N1 and N2.

FIGS. 3A and 3B also show drain currents Id1 and Id2 (solid line and broken line in the upper row) and switching losses Ploss1 and Ploss2 (lower row) in the on and off states of the transistors N1 and N2, respectively, as in FIGS. 2A and 2B. (Solid line and broken line) of FIG. However, the premise of this figure is different from the above, and it is assumed that Vth1 = Vth2 and Ls1> Ls2. The point that the transformer TR1 has not been introduced is the same as above.

As shown in FIG. 3A, when the transistors N1 and N2 are on, the rise timing of the drain current Id2 is earlier than the rise timing of the drain current Id1. Therefore, the switching loss Ploss2 of the transistor N2 is larger than the switching loss Ploss1 of the transistor N1.

On the other hand, as shown in FIG. 3B, when the transistors N1 and N2 are off, the falling timing of the drain current Id1 is later than the falling timing of the drain current Id2. Therefore, the switching loss Ploss1 of the transistor N1 is larger than the switching loss Ploss2 of the transistor N2, contrary to the turning on of the transistors N1 and N2.

As described above, when the transformer TR1 is not introduced, the switching losses Ploss1 and Ploss2 when the transistors N1 and N2 are on and off vary (bias). As a result, since the heat generation of each of the transistors N1 and N2 is also biased, the safety of the switch device 1 may be impaired. In particular, the higher the switching frequency of the transistors N1 and N2 is, the more the above problem becomes apparent.

Therefore, in the switch device 1 of the present embodiment, the rising timings of the drain currents Id1 and Id2 and the respective rising timings of the drain currents Id1 and Id2 are introduced by introducing the transformer TR1 of coupling coefficient K (for example, K ≧ 0.9) on the source side of each of the transistors N1 and N2. Fall timing is aligned. Hereinafter, the operation principle of the transformer TR1 will be described in detail with reference to the drawings.

FIG. 4 is a diagram for explaining the operation principle of the transformer TR1 when the transistors N1 and N2 are on (= FIG. 1 added to FIG. 1). In this figure, it is assumed that Vth1 <Vth2 and Ls1 = Ls2 as a premise.

When the gate signal SG rises from the low level to the high level, the gate-source voltages Vgs1 and Vgs2 of the transistors N1 and N2 rise, and the drain current Id1 of the transistor N1 having a lower on threshold starts to increase earlier .

At this time, the inductor L1 acts to lower the gate-source voltage Vgs1 of the transistor N1 to suppress the increase of the drain current Id1. Further, at the same time, the inductor L2 coupled in reverse polarity to the inductor L1 acts to raise the gate-source voltage Vgs2 of the transistor N2 and promote the increase of the drain current Id2. As a result, rising timings of the drain currents Id1 and Id2 are aligned and balanced with each other.

FIG. 5 is a diagram showing gate-source voltages Vgs1 and Vgs2 (solid line and dashed line in upper stage) and drain currents Id1 and Id2 (solid line and dashed line in lower stage) when the transistors N1 and N2 are on. As shown in the figure, the transformer TR1 acts to pull down one of the gate-source voltages Vgs1 and Vgs2 when the other is pulled up. As a result, it can be seen that the drain currents Id1 and Id2 increase in a balanced state without large variations.

FIG. 6 is a diagram for explaining the operation principle of the transformer TR1 when the transistors N1 and N2 are off (= what has been added to FIG. 1 above). Also in this figure, as in the case of FIG. 4 described above, it is assumed that Vth1 <Vth2 and Ls1 = Ls2 as a premise.

When the gate signal SG rises from the high level to the low level, the gate-source voltages Vgs1 and Vgs2 of the transistors N1 and N2 respectively decrease, and the drain current Id2 of the transistor N2 having a higher on threshold starts to decrease earlier. .

At this time, the inductor L2 acts to raise the gate-source voltage Vgs2 of the transistor N2 to suppress a decrease in the drain current Id2 (= promote an increase). Further, at the same time, the inductor L1 coupled in reverse polarity to the inductor L2 acts to lower the gate-source voltage Vgs1 of the transistor N1 to promote reduction (= suppress increase) of the drain current Id1. As a result, the falling timings of the drain currents Id1 and Id2 are aligned and balanced with each other.

FIGS. 7A and 7B are diagrams showing drain currents Id1 and Id2 (solid line and dashed line in the upper stage) and switching losses Ploss1 and Ploss2 (solid line and dashed line in the lower stage) when the transistors N1 and N2 are on and off, respectively. . As a premise of this figure, it is assumed that Vth1 <Vth2 and Ls1 = Ls2, and the transformer TR1 has been introduced.

As shown in both figures, even if the on threshold values Vth1 and Vth2 of the transistors N1 and N2 vary, the drain current Id1 and drain current Id1 both when the transistors N1 and N2 are on and off can be obtained by introducing the transformer TR1. The rising timing and the falling timing of each Id 2 can be aligned. Therefore, it is possible to effectively suppress the variation of the switching losses Ploss1 and Ploss2.

In FIGS. 4 to 6, and FIGS. 7A and 7B, the operation principle and the effect of the transformer TR1 are described taking as an example the case where the on threshold values Vth1 and Vth2 of the transistors N1 and N2 vary. However, even when the source inductances Ls1 and Ls2 vary, it is possible to receive the same function and effect as described above.

FIGS. 8A and 8B respectively show drain currents Id1 and Id2 (solid line and broken line in the upper row) and switching losses Ploss1 and Ploss2 (lower row) in the on and off states of the transistors N1 and N2, respectively, as in FIGS. 7A and 7B. (Solid line and broken line) of FIG. However, the premise of this figure is different from the above, and it is assumed that Vth1 = Vth2 and Ls1> Ls2. The point where the transformer TR1 has been introduced is the same as above.

As shown in both figures, even if the source inductances Ls1 and Ls2 of the transistors N1 and N2 vary, the drain current Id1 and drain current Id1 both when the transistors N1 and N2 are on and off can be obtained by introducing the transformer TR1. The rising timing and the falling timing of each Id 2 can be aligned. Therefore, it is possible to effectively suppress the variation of the switching losses Ploss1 and Ploss2.

In particular, when the source inductances Ls1 and Ls2 vary, the variation in switching loss when the transistors N1 and N2 are on and the variation in switching loss when the transistors N1 and N2 are off offset each other (FIG. 3A). And compare FIG. 3B). Therefore, for example, when soft switching control of the transistors N1 and N2 is carried out, the introduction of the transformer TR1 can be said to be more effective if only one of the switching losses is to be taken care of. For example, in a circuit in which the switching loss at the on time can be made almost zero by soft switching control, the variation of the loss at the off time becomes the variation of the total switching loss of each transistor. In addition, there is a risk that the safety of the switch device 1 may be impaired. In such a circuit, it is possible to effectively suppress the variation in loss.

<Coupling between inductors>
Next, when inductors L1 and L2 are coupled in reverse polarity with each other (= when transformer TR1 is formed) and when inductors L1 and L2 are not coupled at all (= transformer TR1 is not formed) If), compare and consider with reference to the drawings.

FIG. 9 is a diagram showing drain currents Id1 and Id2 when the transistors N1 and N2 are on. Note that thick solid lines and broken lines respectively indicate drain currents Id1 and Id2 when the inductors L1 and L2 are coupled in reverse polarity to each other. On the other hand, thin solid lines and broken lines respectively indicate drain currents Id1 and Id2 when the inductors L1 and L2 are not coupled at all.

As apparent from comparison between the thick line and the thin line in this figure, when the inductors L1 and L2 are not coupled in reverse polarity with each other, the rising speed (= the rising slope) of the drain currents Id1 and Id2 is delayed. It can be seen that the switching loss increases and the two are not well balanced. From this, it is not sufficient to simply connect the inductors L1 and L2 to the source side of each of the transistors N1 and N2, and it is extremely important to couple the two in reverse polarity.

<Diversion of parasitic inductance>
Next, the mounting method of the inductors L1 and L2 will be examined. The inductors L1 and L2 exhibit the above-described effects even if their inductance values are minute values (about 10 nH). Therefore, when the inductors L1 and L2 are mounted, it is possible to divert parasitic inductances associated with the source wirings of the transistors N1 and N2.

FIG. 10 is a diagram showing a model simulating source interconnections SL1 and SL2 of transistors N1 and N2, respectively. For example, as a result of performing simulation using a model (thickness 0.072 mm, width 2 mm, length 10 mm) simulating the source lines SL1 and SL2 of a two-layer substrate, parasitic inductance Lp1 accompanying each of the source lines SL1 and SL2 And Lp2 were both confirmed to have an inductance value of 7 nH.

Further, source wirings SL1 and SL2 overlap each other at a distance of 0.2 mm in a plan view, and by laying drain currents Id1 and Id2 respectively flowing in opposite directions, coupling coefficient K It was confirmed that it works as a transformer TR1 (= air core inductance pair) of 0.92.

From these findings, it is possible to divert the parasitic inductance Lp1 accompanying the source wiring SL1 of the transistor N1 as the inductor L1, and divert the parasitic inductance Lp2 accompanying the source wiring SL2 of the transistor N2 as the inductor L2. It can be said that it is possible.

FIG. 11 is a diagram showing a configuration example of a printed wiring board PCB (= a two-layer board having wiring layers on the front and back sides) on which the transistors N1 and N2 are mounted. In the upper, middle and lower portions of the drawing, plan views of the printed wiring board PCB as viewed from the front side are depicted.

In particular, in the upper part of the drawing, the surface wiring layers (gate wiring GL2, drain wiring DL2, source wiring SL2) of the printed wiring board PCB are shown by solid lines, and the extracted ones are also shown in the middle part of the drawing. It is depicted. Further, in the upper part of the figure, the back surface wiring layer (gate wire GL1, drain wire DL1, source wire SL1) of the printed wiring board PCB is shown transparently by a broken line. It is also described in the lower part.

In the upper part of the figure, the transistors N1 and N2 mounted on the surface of the printed wiring board PCB are shown transparently by alternate long and short dash lines. Furthermore, gate connection terminals G1 and G2, drain connection terminals D1 and D2, source connection terminals S1 and S2, driver output connection terminal DO, and driver reference connection terminals in the upper, middle and lower portions of the figure, respectively. DR is depicted. These connection terminals can be understood as through vias which electrically conduct between the front surface and the back surface of the printed wiring board PCB.

Next, components of the printed wiring board PCB will be described. The gate connection terminal G1 is a terminal for connecting the gate of the transistor N1. The gate connection terminal G2 is a terminal for connecting the gate of the transistor N2. The drain connection terminal D1 is a terminal for connecting the drain of the transistor N1. The drain connection terminal D2 is a terminal for connecting the drain of the transistor N2. The source connection terminal S1 is a terminal for connecting the source of the transistor N1. The source connection terminal S2 is a terminal for connecting the source of the transistor N2.

The driver output connection terminal DO is a terminal for connecting the signal output terminal of the gate driver (= output terminal of the gate signal SG), and corresponds to the connection terminal T1 in FIG. The driver output connection terminal DO may be understood as a common gate connection terminal for connection to the gate connection terminals G1 and G2. The driver reference connection terminal DR is a terminal for connecting the reference potential end of the gate driver, and corresponds to the connection terminal T3 in FIG. The driver reference connection terminal DR may be understood as a common source connection terminal for connection to the source connection terminals S1 and S2.

The gate wirings GL1 and GL2 are respectively laid on the back surface wiring layer and the surface wiring layer of the printed wiring board PCB so as to electrically connect the gate connection terminals G1 and G2 and the driver output connection terminal GO.

The drain wires DL1 and DL2 are respectively laid on the back surface wiring layer and the surface wiring layer of the printed wiring board PCB so as to electrically connect the drain connection terminals D1 and D2.

The source wiring SL1 is laid on the back surface wiring layer (corresponding to the first main surface) of the printed wiring board PCB so as to electrically connect the source connection terminal S1 and the driver reference connection terminal DR. The source wiring SL2 is laid on the surface wiring layer (corresponding to the second main surface) of the printed wiring board PCB so as to electrically connect the source connection terminal S2 and the driver reference connection terminal DR.

In particular, the source wiring SL1 and the source wiring SL2 have different wiring layers so that at least a part of the sections overlap each other in plan view, and the drain currents Id1 and Id2 flowing in the sections are opposite to each other ( Here, it is laid in the front wiring layer and the back wiring layer).

By adopting such a wiring layout, a part of source interconnections SL1 and SL2 can be coupled as shown in FIG. 10, so that parasitic inductances Lp1 and Lp2 accompanying them can be diverted as inductors L1 and L2 respectively. Is possible.

Although the example of the discrete configuration is described in this drawing, the transistors N1 and N2 may be disposed on the printed wiring board PCB and sealed together with the printed wiring board PCB to be modularized. Even in the case of performing such modularization, it is possible to adopt the same wiring layout as described above.

Further, in the drawing, the printed wiring board PCB having a two-layer structure is described as an example, but the number of layers is not limited to this, and a multilayer structure of three or more layers may be adopted. Further, in the case of using the printed wiring board PCB having a multilayer structure, the wiring layers on which the source wirings SL1 and SL2 are respectively laid are not necessarily limited to the front surface wiring layer and the back surface wiring layer, for example, among the source wirings SL1 and SL2. Alternatively, at least one of them may be laid in the middle wiring layer.

<Switch Device (Second Embodiment)>
FIG. 12 is a view showing a second embodiment of the switch device 1. The switch device 1 of this embodiment is based on the first embodiment (FIG. 1) described above, and the number of parallel transistors is expanded from “2” to “n” (where n ≧ 2). More specifically, the switch device 1 of this embodiment includes n transistors N1 to Nn and (n-1) transformers TR1 to TR (n-1), which is smaller by one than this. Have.

The transistors N1 to Nn are connected in parallel between the connection terminal T2 and the connection terminal T3, and are turned on / off according to the common gate signal SG. There is no difference in this point from the first embodiment described above.

The transformer TRk (where k = 1, 2,..., N−1) includes an inductor L1 connected to the source of the transistor Nk and an inductor L2 connected to the source of the transistor N (k + 1). The inductors L1 and L2 are coupled in opposite polarities to each other. As described above, the configuration of each of the transformers TRk is the same as that of the first embodiment described above. The same applies to the point that the parasitic inductance of the source wiring can be used as the inductors L1 and L2.

Thus, when the number of paralleled transistors is expanded to "n", the same operation and effect as the first embodiment can be obtained by preparing (n-1) transformers smaller by one than this. It is possible to enjoy

<Switch Device (Third Embodiment)>
FIG. 13 is a view showing a third embodiment of the switch device 1. The switch device 1 of this embodiment is based on the first embodiment (FIG. 1), but uses P-channel MOS field effect transistors P1 and P2 instead of the N-channel MOS field effect transistors N1 and N2. It is done. Even in such a case, the inductors L1 and L2 are connected to the sources of the transistors P1 and P2, respectively, and by combining them in reverse polarity, it is possible to receive the same effects as those of the first embodiment described above. It becomes.

<Switch Device (Fourth Embodiment)>
FIG. 14 is a view showing a fourth embodiment of the switch device 1. The switch device 1 of the present embodiment is based on the first embodiment (FIG. 1) and uses npn insulated gate bipolar transistors Q1 and Q2 instead of the N channel MOS field effect transistors N1 and N2. ing. Even in such a case, inductors L1 and L2 are connected to the emitters of transistors Q1 and Q2, respectively, and by combining them in reverse polarity, it is possible to achieve the same function and effect as the first embodiment described above. It becomes.

<Bidirectional power supply circuit>
FIG. 15 is a diagram showing a configuration example of a bidirectional power supply circuit to which the switch device 1 described above can be applied. The bidirectional power supply circuit 10 of this configuration example includes the

switches

11 and 12, the

capacitors

13 and 14, the inductor 15, and the controller 16, and the DC voltage V1 and the DC voltage V2 (where V1> V2). And a bi-directional DC / DC converter that performs bi-directional voltage conversion.

The first end of each of the switch 11 and the capacitor 13 is connected to the application end of the DC voltage V1. The second end of the switch 11 and the first end of the switch 12 are both connected to the first end of the inductor 15. The second end of the inductor 15 and the first end of the capacitor 14 are both connected to the application end of the DC voltage V2. The second end of the switch 12 and the second ends of the

capacitors

13 and 14 are all connected to the ground end. The

switches

11 and 12 thus connected, the

capacitors

13 and 14, and the inductor 15 generate a DC voltage V1 from the DC voltage V2 or a step-down switching output stage that generates the DC voltage V2 from the DC voltage V1. It functions as a step-up switching output stage. Further, the controller 16 detects both of the DC voltages V1 and V2 to control the

switches

11 and 12.

The switch device 1 described above can be applied as the

switches

11 and 12. For example, when applying the switch device 1 as the switch 11, the connection terminal T1 described above is connected to the controller 16, the connection terminal T2 is connected to the application end of the DC voltage V1, and the connection terminal T3 is connected to the third terminal of the inductor 15. It may be connected to one end. When the switch device 1 is applied as the switch 12, the connection terminal T1 described above is connected to the controller 16, the connection terminal T2 is connected to the first end of the inductor 15, and the connection terminal T3 is connected to the ground end. do it. Thus, the switch device 1 can be used as an upper switch or can be used as a lower switch.

Of course, the application of the switch device 1 is not limited to the switching output stage of the bidirectional power supply circuit 10, and is applied to various applications such as an upper switch alone, a lower switch alone, a synchronous rectification circuit, and a level shift circuit. It is possible.

<Other Modifications>
In addition to the embodiments described above, various technical features disclosed in the present specification can be modified in various ways without departing from the scope of the technical creation. That is, the above embodiment should be considered as illustrative in all points and not restrictive, and the technical scope of the present invention is not limited to the above embodiment, and claims It is to be understood that the scope and equivalent meaning and all modifications that fall within the scope are included.

The switch device disclosed herein can be used, for example, as a switching output stage of a bidirectional power supply circuit.

1 Switch Device 10 Bidirectional

Power Supply Circuit

11, 12

Switch

13, 14 Capacitor 15 Inductor 16 Controller N1, N2, N3 to Nn N channel type MOS field effect transistor P1, P2 P channel type MOS field effect transistor Q1, Q2 npn type insulation Gate Bipolar Transistor L1, L2 Inductor Lp1, Lp2 Parasitic Inductance TR1 to Tr (n-1) Transformer T1 to T3 Connection Terminal PCB Printed Wiring Board G1, G2 Gate Connection Terminal D1, D2 Drain Connection Terminal S1, S2 Source Connection Terminal DO Driver Output connection terminal (common gate connection terminal)
DR driver reference connection terminal (common source connection terminal)
GL1, GL2 gate wiring DL1, DL2 drain wiring SL1, SL2 source wiring SG gate signal

Claims

A first transistor and a second transistor which are connected in parallel and which are on / off controlled according to a common gate signal;
A first inductor and a second inductor connected to the source side or the emitter side of the first transistor and the second transistor, respectively;
Have
The switch device, wherein the first inductor and the second inductor are coupled in reverse polarity to each other.
The first inductor is a parasitic inductance of a first wire connected to the source or emitter of the first transistor, and the second inductor is a parasitic wire of a second wire connected to the source or emitter of the second transistor The switch device according to claim 1, which is an inductance.
The first wiring and the second wiring are laid in different wiring layers in a cross-sectional view so that at least a part of the sections overlap each other in plan view and the currents respectively flowing in the sections are opposite to each other The switch device according to claim 2, characterized in that:
The first wiring is laid on a first main surface of a substrate, and the second wiring is laid on a second main surface facing the first main surface. The switch device described.
The switch device according to claim 4, wherein the first transistor and the second transistor are modularized with the substrate.
The switch device according to any one of claims 1 to 5, wherein the first transistor and the second transistor are field effect transistors.
The switch device according to any one of claims 1 to 5, wherein the first transistor and the second transistor are insulated gate bipolar transistors.
First to nth transistors (where n ≧ 2) connected in parallel and turned on / off in response to a common gate signal,
First to (n-1) transformers,
Have
The k th transformer (where k = 1, 2,..., N−1) is
A first inductor and a second inductor connected to the source side or the emitter side of the kth transistor and the (k + 1) th transistor,
The switch device, wherein the first inductor and the second inductor are coupled in reverse polarity to each other.
A power supply circuit comprising the switch device according to any one of claims 1 to 8 as a component of a switching output stage for generating an output voltage from an input voltage.
A first gate connection terminal for connecting the gate of the first transistor;
A second gate connection terminal for connecting the gate of the second transistor;
A first drain connection terminal for connecting a drain of the first transistor;
A second drain connection terminal for connecting the drain of the second transistor;
A first source connection terminal for connecting a source of the first transistor;
A second source connection terminal for connecting the source of the second transistor;
A common gate connection terminal for connection to the first gate connection terminal and the second gate connection terminal;
A common source connection terminal for connection to the first source connection terminal and the second source connection terminal;
A gate wiring which electrically connects the first gate connection terminal, the second gate connection terminal, and the common gate connection terminal;
A drain wire for electrically connecting the first drain connection terminal and the second drain connection terminal;
A first source wire electrically connecting the first source connection terminal and the common source connection terminal;
A second source wire electrically connecting the second source connection terminal and the common source connection terminal;
Have
The first source wiring and the second source wiring are different from each other in a sectional view so that at least a part of the sections overlap each other in a plan view and currents flowing in the sections are opposite to each other. A substrate characterized in that it is laid in layers.