WO2019114140A1 - Procédé d'affichage global et circuit d'attaque - Google Patents

Procédé d'affichage global et circuit d'attaque Download PDF

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Publication number
WO2019114140A1
WO2019114140A1 PCT/CN2018/079547 CN2018079547W WO2019114140A1 WO 2019114140 A1 WO2019114140 A1 WO 2019114140A1 CN 2018079547 W CN2018079547 W CN 2018079547W WO 2019114140 A1 WO2019114140 A1 WO 2019114140A1
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WIPO (PCT)
Prior art keywords
capacitor
switch
sub
voltage
pixel
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Application number
PCT/CN2018/079547
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English (en)
Chinese (zh)
Inventor
吴素华
黎守新
余有勇
Original Assignee
成都晶砂科技有限公司
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Publication date
Priority claimed from CN201711305274.1A external-priority patent/CN107845361B/zh
Priority claimed from CN201711305355.1A external-priority patent/CN107845362A/zh
Application filed by 成都晶砂科技有限公司 filed Critical 成都晶砂科技有限公司
Publication of WO2019114140A1 publication Critical patent/WO2019114140A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present invention relates to a display method and a driving circuit, and more particularly to a global display method suitable for display screen display and a global display driving circuit for driving display of specific sub-pixels in a pixel unit of a display screen.
  • Active display devices such as OLEDs, LEDs, QLEDs, Micro-OLEDs/LEDs are composed of pixel arrays, each of which contains several sub-pixels, and RGB systems and RGBW systems are common.
  • each pixel includes one red sub-pixel, one green sub-pixel, and one blue sub-pixel; in the RGBW system, each pixel includes one red sub-pixel, one green sub-pixel, one blue sub-pixel, and one white. Subpixel. Effectively controlling the brightness of each sub-pixel of the pixel unit to achieve the desired color to be displayed.
  • a typical display control method performs image display by scanning one line and lighting one line.
  • the brightness of the sub-pixel is linear with the magnitude of the current applied across it, and the display of different brightness is achieved by controlling the magnitude of the current flowing through the sub-pixel.
  • the gate drive control module selects a certain row of the pixel array, passes the video data through the DAC module to obtain an analog voltage Vdata, loads it into the first storage capacitor C1 of the sub-pixel unit drive circuit of FIG. 2, and illuminates the row. After all the lines have been scanned, a complete image is displayed.
  • the display control method of progressive scanning or interlaced scanning and lighting ensures that the lighting time of each pixel is one frame time, but when scanning to a certain line of the current frame, the unloaded data in the current frame corresponds to
  • the pixel array still maintains the data of the previous frame, and the whole image appears as a data image of the current frame and a part of the data image of the previous frame. This phenomenon is particularly noticeable when displaying a highly dynamic image at a low frame rate, such as a moving image of a car or train moving at a high speed, which is not the image that is expected to be seen.
  • the first object of the present invention is to provide a global display method capable of displaying a complete image at an effective one frame or approximately one frame time. Avoid the phenomenon that part of the whole image appears as the data image of the current frame, and part of it is the data image of the previous frame.
  • the method is applicable to self-luminous display devices and devices such as OLED/LED, QLED, Micro-OLED/LED.
  • a global display method in which a sub-pixel display is realized by using a linear relationship between an analog voltage stored in a sub-pixel driving circuit and a gray scale value corresponding to the sub-pixel.
  • the first capacitor and the second capacitor are respectively used for scanning voltage and driving display to realize global display.
  • Step 1 scanning the voltage, the control unit performs the progressive or interlaced scanning of the image or video to be obtained, and obtains the gray value of each sub-pixel in the image to be displayed; converts the acquired gray value into a corresponding analog voltage, in one frame.
  • Valid data to temporarily close the first switch, storing the scanned analog voltage in the first capacitor;
  • Step 2 Release the excess power. After the first capacitor is charged, the first switch is turned off. The third switch is controlled by the Clr signal to discharge the excess power on the second capacitor to ensure the accuracy of the voltage applied to the driving circuits of each sub-pixel unit. ;
  • Step 3 Drive the display, after releasing the second capacitor, close the second switch, charge the first capacitor to the second capacitor, and drive the drive tube to drive the sub-pixel display to display a complete and correct image. After the first capacitor is charged to the second capacitor, the second switch is turned off to prepare for the next frame display;
  • Step 4 Continue to cycle steps 1 to 3.
  • the shunt tube is disposed, and the current of the output end of the driving tube is shunted to ensure that the driving tube always operates in the saturation region, which is more advantageous for driving the sub-pixel display.
  • the time for charging the first capacitor in the step 3 to the second capacitor is determined by the charging characteristics of the two capacitors.
  • first capacitor and the second capacitor have the same charge and discharge characteristics, which not only ensures the correctness of the loading data, but also ensures sufficient charging and discharging time.
  • first, second, and third switches are all PMOS tubes, NMOS tubes, or transmission gates.
  • a second object of the present invention is to provide a sub-pixel driving circuit that implements the above global display method.
  • a first switch configured to introduce a frame of image valid data into the first capacitor for storage, temporarily closing the first switch with a frame of valid data; a first capacitor for storing valid data introduced by the first switch; and a second capacitor , for storing valid data stored by the first capacitor and driving the driving tube; a second switch for connecting the first capacitor and the second capacitor; a driving tube for driving the sub-pixel; and a third switch for releasing the second Excess data on the capacitor; the first, second, and third switches are all set to a PMOS tube, an NMOS tube, or a transmission gate.
  • connection relationship of the driving circuit is one end of the first switch as an input end of the analog voltage, and the other end is respectively connected to one end of the first capacitor and the second switch; the other end of the first capacitor is connected to the circuit reference voltage, and the second The other end of the switch is connected to one end of the second capacitor, the gate of the driving tube and one end of the third switch; the other end of the second capacitor and the other end of the third switch are respectively connected with the circuit reference voltage, and the power supply terminal of the driving tube is connected The operating voltage, the other end of the drive tube is connected to the active light-emitting device as the output of the entire drive circuit.
  • the sub-pixel driving circuit provided herein is an active driving, which includes:
  • a first switch configured to introduce an analog voltage corresponding to a gray value of the sub-pixel in the image to be displayed into the circuit
  • a first capacitor for storing an analog voltage introduced by the first switch and charging the second capacitor through the stored analog voltage; a second capacitor for storing an analog voltage on the first capacitor; and a third capacitor: a second switch for connecting and turning off the first capacitor and the second capacitor, and the first capacitor and the driving tube; and the analog voltage stored on the first capacitor is charged to the second capacitor via the second switch, a second capacitor driving the driving tube; a driving tube for driving the sub-pixel display; and a third switch for releasing the residual analog voltage on the second capacitor; the first switch, the second switch, and the third switch are both set to PMOS tube, NMOS tube or transmission gate.
  • the first capacitor and the second capacitor in the sub-pixel driving circuit are capable of storing (charging) the effective data of the image to be displayed (the video data of the image to be displayed acquired by the scanning surface, the gamma voltage formed by the gamma conversion), And it is possible to release (discharge) the effective data to drive the drive tube to start and drive the sub-pixel display connected thereto.
  • the image scanning circuit for scanning the gray value of each sub-pixel in the image to be displayed can realize the display of the image.
  • the second switch by designing the second switch, the excess data (voltage) of the second capacitor can be released (discharged), and the data of the previous sub-pixel is left on the second capacitor, so that the driving signal output by the driving circuit provided by the present invention is obtained. More accurate, it can completely solve the problems in the existing display.
  • the above circuit increases the third capacitance in series with the second capacitor to realize voltage division compensation.
  • a fourth switch configuration for cutting off and turning on the circuit power is further included.
  • a fifth switch configuration for releasing the residual voltage is provided, the fifth switch functioning to stabilize the voltage between the drive tube and the sub-pixel.
  • first capacitor and the second capacitor have the same charging characteristics. It not only ensures the correctness of the loaded data, but also ensures sufficient charging and discharging time.
  • a global display method for a compensation circuit uses a linear relationship between an analog voltage stored in a sub-pixel driving circuit and a gray scale value corresponding to the sub-pixel.
  • the sub-pixel corresponding to the image sub-pixel to be displayed is driven by the sub-pixel driving circuit to display a global display; wherein the sub-pixel driving circuit used is any sub-pixel provided by the present application.
  • Drive circuit the specific steps are as follows:
  • Step 1 scanning the voltage, the control unit performs the progressive or interlaced scanning of the image or video to be obtained, and obtains the gray value of each sub-pixel in the image to be displayed; converts the acquired gray value into a corresponding analog voltage, in one frame.
  • Valid data to temporarily close the first switch and store the scanned analog voltage in it;
  • Step 2 Release the excess power. After the first capacitor is charged, the first switch is turned off. The third switch is controlled by the Clr signal to discharge the excess power on the second capacitor to ensure the accuracy of the voltage applied to the driving circuits of each sub-pixel unit. ;
  • Step 4 driving the display, after releasing the second capacitor, closing the second switch, charging the second capacitor from the first capacitor, and driving the driving tube to drive the sub-pixel display to display a complete and correct image, waiting for After the first capacitor is charged to the second capacitor, the second switch is turned off to prepare for the next frame display;
  • Step 5 Continue to cycle steps 1 to 4.
  • the method sequentially stores the gray values of the sub-pixels in the display image, and waits for the gray voltage values of the sub-pixels in the display image to be in the analog voltage form, and then releases the analog voltage of the remaining previous sub-pixels in the sub-pixel driving circuit.
  • the corresponding sub-pixel display is driven again, and the circuit is compensated during the release of the voltage, which solves the problems in the conventional display method.
  • the global display method provided by the present invention has the beneficial effects of effectively solving the phenomenon that a part of the entire frame is a data image of the current frame and a part of the data image of the previous frame occurs in the existing display. To make the image display clearer.
  • the global display driving circuit provided by the invention has the beneficial effects of effectively solving the phenomenon that a part of the entire image appearing in the existing display is a data image of the current frame and a part of the data image of the previous frame. At the same time, it not only ensures the correctness of the loaded data, but also ensures sufficient charging and discharging time.
  • Figure 1 is a graph showing the relationship between analog voltage and gray scale
  • FIG. 2 is a schematic diagram of a common OLED/LED pixel unit driving circuit
  • FIG. 3 is a schematic diagram of an N-type driving circuit of a global display pixel unit of an OLED/LED according to the present invention
  • FIG. 4 is a schematic diagram of an N-type driving circuit of a global display pixel unit of a OLED/LED with a shunt function according to the present invention
  • FIG. 5 is a schematic diagram of a P-type driving circuit of a global display pixel unit of an OLED/LED according to the present invention.
  • FIG. 6 is a schematic diagram of a P-type driving circuit of a global display pixel unit of a OLED/LED with a shunt function according to the present invention
  • Figure 7 is a graph showing the charge and discharge characteristics of the capacitor according to the present invention.
  • FIG. 8 is a schematic diagram showing the global display of the OLED/LED according to the present invention.
  • FIG. 9 is a control signal diagram of a sub-pixel unit drive circuit according to the present invention.
  • FIG. 10 is a schematic diagram of a first sub-pixel driving circuit with compensation according to the present invention.
  • FIG. 11 is a timing diagram of a first seed pixel driving circuit
  • FIG. 13 is a schematic diagram of a second sub-pixel driving circuit with compensation according to the present invention.
  • FIG. 15 is a schematic diagram of a third sub-pixel driving circuit with compensation according to the present invention.
  • 16 is a timing chart of a third seed pixel driving circuit
  • FIG. 17 is a schematic diagram of a fourth sub-pixel driving circuit with compensation according to the present invention.
  • the technical solution claimed in the present application includes a global display method and a global display driving circuit.
  • the global display driving circuit includes but is not limited to the following structures:
  • the first structure the global display pixel unit N-type driving circuit of the OLED/LED, and its circuit schematic diagram is shown in FIG.
  • the structure includes a first switch S1, a first capacitor C1, a second switch S2, a second capacitor C2, a driving tube M1, and a third switch S3, wherein one end of the first switch S1 is used as an effective data analog voltage Vdata (gamma converted The analog voltage signal is input to the other end, and the other end is connected to one end of the first capacitor C1 and the second switch S2 respectively; the other end of the first capacitor C1 is connected to the circuit reference voltage Vref, and the other end of the second switch S2 is connected to the second capacitor at the same time.
  • One end of C2, the gate of the driving tube M1 and one end of the third switch S3, the other end of the second capacitor C2 and the other end of the third switch S3 are respectively connected to the circuit reference voltage Vref, and the power supply terminal of the driving tube M1 is connected to the operating voltage Vdd.
  • the other end of the driving tube M1 is connected to a specific sub-pixel (light emitting diode) as an output end of the entire driving circuit.
  • the working process of the circuit structure is: controlling the charging process of the first capacitor C1 and the second capacitor C2 through the first switch S1 and the second switch S2, and the voltage stored on the first capacitor C1 and the second capacitor C2 is to be displayed.
  • the gray value of the sub-pixel in the image is displayed.
  • Step 1 Scan the voltage and select two first storage capacitors C1 and C2 having the same charge and discharge characteristics.
  • the control unit performs gray-by-row or interlaced scanning on the image or video to be displayed to obtain the gray scale of each sub-pixel in the image to be displayed. a value; converting the acquired gray value into a corresponding analog voltage, temporarily closing the first switch S1 in one frame of valid data, and storing the scanned analog voltage in the first capacitor C1;
  • Step 2 Release the excess power, the first capacitor C1 is charged, the first switch S1 is turned off, and the third switch S3 is controlled by the Clr signal to discharge excess power on the second capacitor C2 to ensure loading to each sub-pixel unit driving circuit. Voltage accuracy;
  • Step 3 Driving the display, after releasing the second capacitor C2, closing the second switch S2, charging C1 to C2, and driving the driving tube M1 to drive the sub-pixel display, displaying a complete and correct image, waiting for C1 After charging C2, the second switch S2 is turned off to prepare for the next frame display;
  • Step 4 Continue to cycle steps 1 to 3.
  • Second seed pixel unit circuit structure global display pixel unit N-type driving circuit of OLED/LED with shunt function, the circuit schematic diagram is shown in FIG. 4 .
  • the structure includes a first switch S1, a first capacitor C1, a second switch S2, a second capacitor C2, a driving tube M1, a third switch S3, and a shunt tube M2, wherein one end of the first switch S1 serves as an effective data analog voltage Vdata
  • the input end of the (gamma converted analog voltage signal) is connected to one end of the first capacitor C1 and the second switch S2; the other end of the first capacitor C1 is connected to the circuit reference voltage Vref, and the other end of the second switch S2 is simultaneously
  • One end of the second capacitor C2, the gate of the driving tube M1 and one end of the third switch S3, the other end of the second capacitor C2 and the other end of the third switch S3 are respectively connected to the circuit reference voltage Vref, and the power terminal of the driving tube M1 Connected to the working voltage Vdd, the other end of the driving tube M1 is connected as a specific sub-pixel (light emitting diode) as the output end of the whole driving circuit; one end of the s
  • the circuit structure adds a shunt tube M2, which ensures that the driving tube M1 always operates in the saturation region when driving the sub-pixel display, so that the image display is more continuous and clear.
  • the working process of the circuit structure is the same as that of the first circuit structure, but the shunting function is realized by the shunt tube M2 during the driving sub-pixel display process, which ensures that the M1 always operates in the saturation region when driving the sub-pixel display.
  • the specific steps of the driving method for realizing the global display of the present invention are as follows:
  • Step 1 Scan the voltage and select two first storage capacitors C1 and C2 having the same charge and discharge characteristics.
  • the control unit performs gray-by-row or interlaced scanning on the image or video to be displayed to obtain the gray scale of each sub-pixel in the image to be displayed. a value; converting the acquired gray value into a corresponding analog voltage, temporarily closing the first switch S1 in one frame of valid data, and storing the scanned analog voltage in the first capacitor C1;
  • Step 2 Release the excess power, the first capacitor C1 is charged, the first switch S1 is turned off, and the third switch S3 is controlled by the Clr signal to discharge excess power on the second capacitor C2 to ensure loading to each sub-pixel unit driving circuit. Voltage accuracy;
  • Step 3 Drive the display, after releasing the C2 power, close the second switch S2, charge the first capacitor C1 to the second capacitor C2, and drive the driving tube M1 to drive the sub-pixel display to display a complete and correct image. After the first capacitor C1 is charged to the second capacitor C2, the second switch S2 is turned off to prepare for the next frame display;
  • Step 4 Continue to cycle steps 1 to 3.
  • the third structure the global display pixel unit P-type driving circuit of the OLED/LED, the schematic diagram of the circuit structure is shown in FIG. 5.
  • the structure includes a first switch S1, a first capacitor C1, a second switch S2, a second capacitor C2, a drive tube M1, and a third switch S3.
  • One end of the first switch S1 is used as an input end of the effective data analog voltage Vdata (analog voltage signal after gamma mode conversion), and the other end is respectively connected to one end of the first capacitor C1 and the second switch S2; the other end of the first capacitor C1 Connect the working voltage Vdd, the other end of the second switch S2 is one end of the second capacitor C2, the gate of the driving tube M1 and one end of the third switch S3, the other end of the second capacitor C2, the power end of the driving tube M1
  • the other end of the third switch S3 is connected to the working voltage Vdd, and the other end of the driving tube M1 is connected to a specific sub-pixel (light emitting diode) as an output end of the entire driving circuit.
  • the working process of the circuit structure is the same as the working process of the first circuit structure.
  • the two are only different circuit structures, and the working principle and process are the same.
  • the specific steps of the driving method for realizing the global display of the present invention are as follows:
  • Step 1 Scan the voltage and select two first storage capacitors C1 and C2 having the same charge and discharge characteristics.
  • the control unit performs gray-by-row or interlaced scanning on the image or video to be displayed to obtain the gray scale of each sub-pixel in the image to be displayed. a value; converting the acquired gray value into a corresponding analog voltage, temporarily closing the first switch S1 in one frame of valid data, and storing the scanned analog voltage in C1;
  • Step 2 Release excess power, C1 is charged, disconnect the first switch S1, and control the third switch S3 to discharge excess power on C2 through the Clr signal to ensure the accuracy of the voltage applied to the driving circuits of each sub-pixel unit;
  • Step 3 Drive the display, after releasing the C2 power, close the second switch S2, charge C1 to C2, and drive the drive tube M1 to drive the sub-pixel display to display a complete and correct image, and wait for C1 to charge C2. After completion, the second switch S2 is turned off to prepare for the next frame display;
  • Step 4 Continue to cycle steps 1 to 3.
  • the fourth structure a P-type driving circuit of a global display pixel unit of an OLED/LED with a shunt function, and its circuit schematic is shown in FIG. 6.
  • the structure includes a first switch S1, a first capacitor C1, a second switch S2, a second capacitor C2, a drive tube M1, a third switch S3, and a shunt tube M2.
  • One end of the first switch S1 is used as an input end of the effective data analog voltage Vdata (analog voltage signal after gamma conversion), and the other end is respectively connected to one end of the first capacitor C1 and the second switch S2; the other end of the first capacitor C1 is connected
  • the working voltage Vdd the other end of the second switch S2 is one end of the second capacitor C2, the gate of the driving tube M1 and one end of the third switch S3, the other end of the second capacitor C2, the power end of the driving tube M1, and
  • the other end of the third switch S3 is respectively connected to the working voltage Vdd, and the other end of the driving tube M1 is connected as a specific sub-pixel (light emitting diode) as an output end of the entire driving circuit; one end of the shunt tube M2 is connected to the
  • the working process of the circuit structure is: controlling the charging process of the first capacitor C1 and the second capacitor C2 through the first switch S1 and the second switch S2, and the voltage stored on the first capacitor C1 and the second capacitor C2 is to be displayed.
  • the gray value of the sub-pixel in the image is displayed.
  • Step 1 Scan the voltage and select two first storage capacitors C1 and C2 having the same charge and discharge characteristics.
  • the control unit performs gray-by-row or interlaced scanning on the image or video to be displayed to obtain the gray scale of each sub-pixel in the image to be displayed. a value; converting the acquired gray value into a corresponding analog voltage, temporarily closing the first switch S1 in one frame of valid data, and storing the scanned analog voltage in C1;
  • Step 2 Release excess power, C1 is charged, disconnect the first switch S1, and control the third switch S3 to discharge excess power on C2 through the Clr signal to ensure the accuracy of the voltage applied to the driving circuits of each sub-pixel unit;
  • Step 3 Drive the display, after releasing the C2 power, close the second switch S2, charge C1 to C2, and drive the drive tube M1 to drive the sub-pixel display to display a complete and correct image, and wait for C1 to charge C2. After completion, the second switch S2 is turned off to prepare for the next frame display;
  • Step 4 Continue to cycle steps 1 to 3.
  • step 3 in order to make the OLED/LED display drive tube M1 always work in the saturation region, the shunt tube M2 is added.
  • the shunt tube M2 operates under controlled conditions to achieve a shunt function.
  • the circuit structure divides the current on the output end of the driving tube M1 through the shunt tube M2 during the driving sub-pixel display process, thereby ensuring that the driving tube M1 always works in the saturation region during the whole driving process, so that the image display is more continuous and clear. .
  • the sub-pixel unit described in the embodiment of the present application is an OLED or LED-driven pixel unit as shown in the drawing.
  • the method is applicable to self-luminous display devices and devices such as OLED/LED, QLED, Micro-OLED/LED.
  • the first switch S1, the second switch S2, and the third switch S3 may adopt a PMOS tube, an NMOS tube, or a transmission gate.
  • the driving tube M1 and the shunt tube M2 may be a PMOS tube or an NMOS tube.
  • the gates of the first switch S1, the second switch S2, and the third switch S3 are respectively connected to the control signal N signal, the GS signal, and the Clr signal, and the control signals of the first switch S1, the second switch S2, and the third switch S3 are respectively N signal, GS signal, Clr signal.
  • the present invention employs two first capacitors C1 and a second capacitor C2 for scanning voltage and driving display, respectively.
  • the sub-pixel unit driving circuit provided by the present invention is only a better understanding of the method for realizing global display of the present invention, but is not limited to the specific driving circuit, and the application of the global display method of the present invention includes other sub- In the pixel unit driving circuit, the sub-pixel unit driving circuit of the present invention includes two energy storage first capacitors C1 and a second capacitor C2 at the same time as compared with the prior art sub-pixel unit driving circuit.
  • the time during which the first capacitor C1 charges the second capacitor C2 is determined by the charging characteristics of the two capacitors. Its charge and discharge characteristics are shown in Fig. 7.
  • the time ⁇ t at which the capacitor is charged from 0 to a certain voltage or discharged from a certain voltage to 0 is related to the capacitance value C of the capacitor and the resistance value R of the circuit.
  • the first capacitor C1 is a storage capacitor to the second capacitor C2.
  • the first capacitor C1 and the second capacitor C2 used in the embodiments of the present application have the same characteristics, and those skilled in the art should understand that the first capacitor C1
  • the second capacitor C2 can also be a storage capacitor having different charge and discharge characteristics.
  • the first capacitor C1 and the second capacitor C2 use the same characteristics to ensure data accuracy, and ensure sufficient charging and discharging time, and the analog voltage charged to the first capacitor C1 should be conventional.
  • the mode drive circuit (Fig. 2) is 2 times or slightly more than 2 times. In order to ensure that the voltage on the second capacitor C2 can be released cleanly, the interval between the Clr signals controlling the third switch S3 should be set sufficiently.
  • the global display principle of the global display driving circuit claimed in the present application is as shown in FIG. 8.
  • the specific process is as follows: the control unit scans the image or video data of the image to be displayed by progressive scan or interlaced scanning, converts it into an analog voltage through gamma, and loads it into the first capacitor C1 of the energy storage. After all the lines are scanned, the voltage of the third switch S3 is controlled by the clock signal (Clr signal) to release the voltage of the previous sub-pixel unit stored on the second capacitor C2, and then the first capacitor C1 is stored. The voltage is charged to the second capacitor C2, and the sub-pixel unit is driven for display.
  • the above driving circuit can realize the control of the sub-pixel display by combining the control unit, and the control signal outputted by the driving circuit is as shown in FIG. 9.
  • the working process of the circuit structure in the above embodiment will be described with reference to FIG. 9.
  • the N signal is switched from a low level to a high level to control the switch S1 to be turned on, and the GS signal is low to control the second switch S2.
  • the third switch S3 is turned off and the Clr signal is low, and the analog voltage Vdata is loaded on the first plate of the first capacitor C1 through the switch S1, and the data of one frame is all loaded on the first pole of the first capacitor C1.
  • the N signal jumps from the high level to the low level.
  • the GS signal continues to be low level, the Clr signal jumps from the low level to the high level, the switch S1 is turned off, and the N+1th frame data is prohibited. Input, the switch S2 is turned off, the switch S3 is turned on, the reference voltage Vref is loaded on the first plate of the second capacitor C2, and the data of the N-1th frame remaining on the first plate of the second capacitor C2 is cleared. , avoiding the phenomenon of the N-1th frame image during display; after the clearing, the N signal continues to be low level, the GS signal changes from low level to high level, and the Clr signal jumps to low level.
  • the switch S1 and the switch S3 are turned off, the switch S2 is turned on; the first capacitor C1 is turned on by the turned-on switch S2 A plate is connected to the first plate of the second capacitor C2, and the analog voltage Vdata on the first plate of the first capacitor C1 is written to the first plate of the second capacitor C2, and the voltage is applied to the driving tube M1.
  • the driving tube M1 is turned on, so that the driving tube M1 generates a driving current, and the light emitting device connected between the common ground Vss and the output end of the driving tube M1 is driven to emit light.
  • a sub-pixel driving circuit claimed in the present application includes:
  • the first switch S1 is configured to introduce an analog voltage corresponding to the gray value of the sub-pixel in the image to be displayed into the circuit;
  • the first capacitor C1 is configured to store the analog voltage introduced by the first switch S1, and charge and drive the driving capacitor M1 to the second capacitor C2 through the stored analog voltage; the second capacitor C2 is used to store the first capacitor C1. Analog voltage on;
  • the third capacitor C3 is used for voltage division; the second switch S2 is configured to connect the first capacitor C1 and the second capacitor C2, and the first capacitor C1 and the driving tube M1, and the analog voltage stored on the first capacitor C1 is passed through
  • the second switch S2 charges the second capacitor C2 and the second capacitor C2 drives the driving tube M1; the driving tube M1 is used to drive the sub-pixel display; and the third switch S3 is used to release the residual analog voltage on the second capacitor C2.
  • the first switch S1, the second switch S2, and the third switch S3 are each configured as a PMOS tube, an NMOS tube, or a transmission gate.
  • the circuit further includes a fourth switch S4 for turning off and turning on the circuit power, and/or a fifth switch S5 for stabilizing the voltage between the driving tube M1 and the sub-pixel, the fourth switch S4 And the fifth switch S5 is set as a PMOS tube, an NMOS tube or a transmission gate.
  • the present application provides specific structures of several driving circuits, as shown in FIG. 10, the circuit structure is as follows:
  • the first driving circuit includes a first switch S1, a second switch S2, a third switch S3, a first capacitor C1, a second capacitor C2, a driving tube M1, and a third capacitor C3.
  • the circuit schematic is shown in FIG.
  • One end of the first switch S1 is used as an input end of the effective data analog voltage Vdt (analog voltage signal after gamma conversion) for receiving the analog voltage corresponding to the gray value of the sub-pixel; the other end is connected with the one end and the second of the first capacitor C1
  • One end of the switch S2 is connected.
  • the other end of the first capacitor C1 is connected to the reference voltage Vref of the circuit, and the other end of the second switch S2 is connected to the reference voltage Vref through the third switch S3 and to the reference voltage Vref through the second capacitor C2 and the third capacitor C3, respectively.
  • the circuit structure is matched with a sub-pixel scanning circuit (for scanning gray values of each sub-pixel in an image to be displayed) and a digital-to-analog converter (for converting a sub-pixel gray value into an analog voltage for storing it in a sub-pixel)
  • a specific sub-pixel can be driven to display a gray value corresponding to the corresponding sub-pixel driving circuit to realize display.
  • the control timing of the first mode of operation is shown in Figure 11, and the control signal is shown in Figure 9.
  • the first switch S1 is closed, and an analog voltage linearly proportional to the gray value of the sub-pixel is stored in the first capacitor C1, and the sub-pixel driving circuit is received.
  • the first switch S1 is turned off; after the gradation values of the sub-pixels in the display image are stored in the driving circuit of each sub-pixel with the analog voltage, the third switch S3 is activated.
  • the second capacitor C2 releases the residual voltage, and pulls down the working voltage Vdd.
  • the Vdd voltage is applied to the intersection point O of the second capacitor C2 and the third capacitor C3, the whole process.
  • the operating voltage Vdd is restored to a high voltage, and the intersection of the first capacitor C1 and the second capacitor C2 is charged by Vdd for T2 time (the threshold voltage Vth of the driving tube is captured during charging); T3 time Segment, closing the second switch S2, the voltage stored in the first capacitor C1 is charged to the second capacitor C2 through the second switch S2 (ie, the effective gray value stored in the first capacitor C1 is transferred to the second capacitor C2 ) and drive all
  • the sub-pixel unit displays a complete and correct image.
  • the second switch S2 is turned off to prepare for the next frame display.
  • the driving tube M1 is activated to drive the sub-pixel (light-emitting device: LED or OLED) connected to the output end of the driving tube M1 to emit light.
  • the control timing of the second mode of operation is shown in Figure 12, and the control signal is shown in Figure 9.
  • This working mode is basically the same as the first working mode. The difference is that when the working voltage Vdd is low voltage during the T3 time period, the second switch S2 is closed, and the voltage stored in the first capacitor C1 is transferred to the first In the second capacitor C2, after the data transfer is completed, the operating voltage Vdd is restored to a high voltage during the T4 period, and the driving tube M1 drives the sub-pixel display.
  • the second driving circuit includes a first switch S1, a second switch S2, a third switch S3, a first capacitor C1, a second capacitor C2, a driving tube M1, a third capacitor C3, and a fourth switch S4.
  • the schematic diagram of the circuit is shown in Figure 13.
  • One end of the first switch S1 is used as an input end of the effective data analog voltage Vdt (analog voltage signal after gamma conversion) for receiving the analog voltage corresponding to the gray value of the sub-pixel; the other end is connected with the one end and the second of the first capacitor C1
  • One end of the switch S2 is connected.
  • the other end of the first capacitor C1 is connected to the reference voltage Vref of the circuit, and the other end of the second switch S2 is connected to the reference voltage Vref through the third switch S3, and is connected to the reference voltage Vref through the second capacitor C2 and the third capacitor C3 in sequence.
  • the working voltage Vdd or the common ground Vss one end of the second switch S2 is also connected to the gate of the driving tube M1; the power terminal of the driving tube M1 is connected to the working voltage Vdd through the fourth switch S4, and the other end is used as the output of the entire driving circuit End, used to connect sub-pixels (light-emitting devices: LED or OLED).
  • the control timing of this circuit is shown in Figure 14, and the control signal is shown in Figure 9.
  • the first switch S1 is closed, and an analog voltage linearly proportional to the gray value of the sub-pixel is stored in the first capacitor C1, and is received by each sub-pixel driving circuit.
  • the first switch S1 is turned off; after the gray values of the sub-pixels in the display image are stored in the driving circuit of each sub-pixel with an analog voltage, the third switch S3 is activated.
  • the residual voltage in the second capacitor C2 the second capacitor C2 releases the residual voltage, and pulls down the operating voltage Vdd.
  • the Vdd voltage is applied to the 0 point of the intersection of the second capacitor C2 and the third capacitor C3, the whole
  • the working voltage Vdd is restored to a high voltage, and after charging to 0 point through Vdd for T2 time (the valve voltage of the driving tube M1 is captured during charging); the Em signal is disconnected fourth during the T3 time period.
  • the switch S4 closes the second switch S2; the voltage stored in the first capacitor C1 is charged to the second capacitor C2 through the second switch S2 (ie, the effective gray value stored in the first capacitor C1 is transferred to the second capacitor C2) Medium) and drive all Pixel unit displays a complete and correct image.
  • the second switch S2 is turned off to prepare for the next frame display.
  • the Em signal control closes the fourth switch S4, and the voltage on the second capacitor C2 is input to the driving tube M1, and the driving tube M1 is activated to drive the sub-pixels connected to the output end of the driving tube M1 within T4 ( Light-emitting device: LED or OLED) light-emitting display.
  • the third driving circuit includes a first switch S1, a second switch S2, a third switch S3, a first capacitor C1, a second capacitor C2, a driving tube M1, a third capacitor C3, and a fourth switch S4.
  • the fifth switch S5 the circuit schematic diagram is shown in FIG.
  • One end of the first switch S1 is used as an input end of the effective data analog voltage Vdt (analog voltage signal after gamma conversion) for receiving the analog voltage corresponding to the gray value of the sub-pixel; the other end is connected with the one end and the second of the first capacitor C1
  • One end of the switch S2 is connected.
  • the other end of the first capacitor C1 is connected to the reference voltage Vref of the circuit, and the other end of the second switch S2 is connected to the reference voltage Vref through the third switch S3, and is sequentially connected to the reference voltage Vref through the second capacitor C2 and the third capacitor C3,
  • the working voltage Vdd or the common ground Vss, and the gate connected to the driving tube M1;
  • the power terminal of the driving tube M1 is connected to the working voltage Vdd through the fourth switch S4, and the other end serves as the output end of the entire driving circuit for connecting the sub-pixels (Light emitting device: LED or OLED),
  • the fifth switch S5 is connected between the output terminal of the driving tube M1 and the reference voltage Vref.
  • the control timing of this circuit is shown in Figure 16, and the control signal is shown in Figure 9.
  • the first switch S1 When there is an analog voltage input circuit converted by the digital-to-analog converter, the first switch S1 is closed, and an analog voltage linearly proportional to the gray value of the sub-pixel is stored in the first capacitor C1, and is received by each sub-pixel driving circuit.
  • the first switch S1 When the sub-pixel gray value to be displayed is completed, the first switch S1 is turned off; after the gray values of the sub-pixels in the display image are stored in the driving circuit of each sub-pixel with an analog voltage, the third switch S3 is activated.
  • the fourth switch S4 is closed, and the Vdd voltage is applied to the intersection A of the second capacitor C2, the third capacitor C3, and the fourth switch S4.
  • the fourth switch S4 is turned off, the fifth switch S5 is closed, and the reference voltage is discharged through the point A, and the threshold voltage Vth of the driving tube M1 is grasped for T2 time; in the T3 period, Em is disconnected from the fourth switch S4.
  • the fourth driving circuit includes a first switch S1, a second switch S2, a third switch S3, a first capacitor C1, a second capacitor C2, a driving tube M1, a third capacitor C3, and a fourth switch S4.
  • the circuit schematic is shown in Figure 17.
  • One end of the first switch S1 is used as an input end of the effective data analog voltage Vdt (analog voltage signal after gamma conversion) for receiving the analog voltage corresponding to the gray value of the sub-pixel; the other end is connected with the one end and the second of the first capacitor C1
  • One end of the switch S2 is connected.
  • the other end of the first capacitor C1 is connected to the reference voltage Vref of the circuit, and the other end of the second switch S2 is connected to the reference voltage Vref through the third switch S3, and is sequentially connected to the reference voltage Vref through the second capacitor C2 and the third capacitor C3,
  • the working voltage Vdd or the common ground Vss, and the gate connected to the driving tube M1; the power terminal of the driving tube M1 is connected to the working voltage Vdd through the fourth switch S4, and the other end serves as the output end of the entire driving circuit for connecting the sub-pixels (Light-emitting device: LED or OLED).
  • the control timing of this circuit is shown in Figure 18, and the control signal is shown in Figure 9.
  • the first switch S1 When there is an analog voltage input circuit converted by the digital-to-analog converter, the first switch S1 is closed, and an analog voltage linearly proportional to the gray value of the sub-pixel is stored in the first capacitor C1, and is received by each sub-pixel driving circuit.
  • the first switch S1 When the sub-pixel gray value to be displayed is completed, the first switch S1 is turned off; after the gray values of the sub-pixels in the display image are stored in the driving circuit of each sub-pixel with an analog voltage, the third switch S3 is activated.
  • the fourth switch S4 is closed, and the Vdd voltage is applied to the intersection A of the second capacitor C2, the third capacitor C3, and the fourth switch S4.
  • the fourth switch S4 is turned off, and is discharged to the power supply ground Vref through the point A, and the threshold voltage Vth of the drive tube M1 is grabbed for the T2 time.
  • the second switch S2 is closed, and the voltage stored in the first capacitor C1 is charged to the second capacitor C2 through the second switch S2 (ie, the effective gray value stored in the first capacitor C1 is transferred to the second capacitor) C2) and drive all sub-pixel units to display a complete and correct image.
  • the Em signal control closes the fourth switch S4, and the voltage on the second capacitor C2 is input to the driving tube M1, and the driving tube M1 is activated to be driven to be connected to the output end of the driving tube M1 in the T4 time.
  • Sub-pixels light-emitting devices: LED or OLED
  • the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, and the fifth switch S5 are all set as a PMOS tube, an NMOS tube or a transmission gate; the first switch S1 and the second switch The gates of the switch S2, the third switch S3, the fourth switch S4, and the fifth switch S5 are respectively connected to the control signal N signal, the GS signal, the ini signal, the Em signal, and the C signal, and the first switch S1 and the second switch S2 are respectively connected.
  • the control signals of the third switch S3, the fourth switch S4, and the fifth switch S5 are respectively an N signal, a GS signal, an ini signal, an Em signal, and a C signal, and the switching can be controlled to be turned on and off by the above signal, wherein
  • the voltages Vref, C signal, and ini signal are all generated by the DC portion of the outer IC, and the GS signal and the EM signal are generated by an external circuit, and the GS signal and the Em signal are the same signal or the pulse width of the GS signal is smaller than the pulse width of the Em signal.
  • the specific timing of several signals is shown in Figures 11, 12, 14, 14, and 18.
  • the driving tube M1 can be configured as a PMOS tube or an NMOS tube.
  • the first capacitor C1 and the second capacitor C2 described in the present invention may be capacitors having the same characteristics or capacitors having different characteristics.
  • the time during which the first capacitor C1 charges the second capacitor C2 is determined by the charging characteristics of the two capacitors. Its charge and discharge characteristics are shown in Fig. 7.
  • the time ⁇ t at which the capacitor is charged from 0 to a certain voltage or discharged from a certain voltage to 0 is related to the capacitance value C of the capacitor and the resistance value R of the circuit.
  • the first capacitor C1 and the second capacitor C2 used in the embodiments of the present application have the same characteristics.
  • the same characteristics are used to ensure the accuracy of the data, and sufficient charging and discharging time is ensured, and the analog voltage charged to the first capacitor C1 at this time should be twice or slightly more than twice the analog voltage of the conventional driving circuit (Fig. 2). .
  • the interval between the Clr signals controlling the third switch S3 should be set sufficiently.
  • the above driving circuit can realize the control of the sub-pixel display by combining the control unit, and the control signal outputted by the driving circuit is as shown in FIG. 9.
  • the global display principle of the global display driver circuit claimed in the present application is as shown in FIG.
  • the global display principle of the global display method claimed in the present application is as shown in FIG. 8.
  • the method realizes a single sub-pixel by using a linear relationship between the analog voltage stored in the sub-pixel driving circuit and the gray-scale value corresponding to the sub-pixel. Displaying, the sub-pixel corresponding to the image sub-pixel to be displayed is driven by the sub-pixel driving circuit to display a global display; wherein the sub-pixel driving circuit used is any one of the above four sub-pixel driving circuits; Proceed as follows:
  • Step 1 scanning the voltage, the control unit performs the progressive or interlaced scanning of the image or video to be obtained, and obtains the gray value of each sub-pixel in the image to be displayed; converts the acquired gray value into a corresponding analog voltage, in one frame.
  • the valid data temporarily closes the first switch S1, and stores the scanned analog voltage in C1;
  • Step 2 Release the excess power, the first capacitor C1 is charged, the first switch S1 is turned off, and the third switch S3 is controlled by the Clr signal to discharge excess power on the second capacitor C2 to ensure loading to each sub-pixel unit driving circuit. Voltage accuracy;
  • Step 4 driving the display, after releasing the second capacitor C2, the second switch S2 is closed, the first capacitor C1 is charged to the second capacitor C2, and the driving tube M1 is driven to drive the sub-pixel display to display a complete image.
  • the correct image after the first capacitor C1 is charged to the second capacitor C2, the second switch S2 is turned off to prepare for the next frame display;
  • Step 5 Continue to cycle steps 1 to 4.
  • step 3 the specific method of compensation in step 3 has the following two ways:
  • SA1 release voltage, when low voltage, release the voltage at the node where the second capacitor C2, the third capacitor C3 and the driving tube M1 intersect;
  • SA2 Voltage input, at a high voltage, a voltage is input to a node where the second capacitor C2, the third capacitor C3, and the driving tube M1 intersect, and the threshold voltage Vth of the driving tube M1 is grabbed.
  • SA1 voltage input, when the voltage is high, the voltage is input to the node where the second capacitor C2, the third capacitor C3 and the driving tube M1 intersect;
  • SA2 Release voltage, release the voltage at the node where the second capacitor C2, the third capacitor C3 and the driving tube M1 intersect, and grab the threshold voltage Vth of the driving tube M1.
  • the time during which the first capacitor C1 charges the second capacitor C2 in the above global display method is determined by the charging characteristics of the two capacitors.
  • the sub-pixel driving circuit and the global display method provided by the present application are applicable to self-luminous display devices and devices such as OLED/LED, QLED, Micro-OLED/LED.
  • the threshold voltage Vth of the driving tube M1 needs to be grabbed to eliminate the threshold voltage Vth in the saturation region, so that the image display is clearer.
  • Vref described in the embodiment of the present invention represents the reference voltage of the circuit;
  • Vbias represents the bias power control signal for controlling the conduction of the shunt tube M2;
  • the N signal the GS signal controls the opening and closing of the first switches S1 and S2.
  • Clr is a clock signal for controlling the conduction of the third switch S3;
  • Vsync is a field sync signal, and the above signals are all generated by an external circuit (such as an external DC) and then introduced into the circuit provided by the invention.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

L'invention concerne un procédé d'affichage global et un circuit d'attaque d'affichage global. Le circuit d'attaque comprend : un premier commutateur (S1) pour introduire des données valides d'une trame d'une image dans un premier condensateur (C1) en vue de leur stockage, et pour fermer le premier commutateur (S1) lorsque est atteint le niveau d'une trame de données valides; un premier condensateur (C1) pour stocker les données valides introduites par le premier commutateur (S1); un second condensateur (C2) pour stocker les données valides stockées par le premier condensateur (C2) et pour attaquer un tube d'attaque (M1); un deuxième commutateur (S2) pour connecter le premier condensateur (C1) et le second condensateur (C2); le tube d'attaque (M1) pour attaquer un sous-pixel (OLED); et un troisième commutateur (S3) pour libérer des données redondantes sur le second condensateur (C2). Les premier, deuxième et troisième commutateurs se présentent tous sous la forme d'un transistor PMOS, d'un transistor NMOS ou d'une porte de transmission. Le procédé d'affichage global et le circuit d'attaque d'affichage empêchent le phénomène dans lequel une partie d'une image complète appartient à une image de données d'une trame actuelle et une partie de ladite image complète appartient à une image de données d'une trame précédente.
PCT/CN2018/079547 2017-12-11 2018-03-20 Procédé d'affichage global et circuit d'attaque WO2019114140A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201711305274.1 2017-12-11
CN201711305274.1A CN107845361B (zh) 2017-12-11 2017-12-11 一种子像素驱动电路及全局显示方法
CN201711305355.1 2017-12-11
CN201711305355.1A CN107845362A (zh) 2017-12-11 2017-12-11 一种全局显示方法及驱动电路

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1932940A (zh) * 2005-09-16 2007-03-21 株式会社半导体能源研究所 显示器件及显示器件的驱动方法
CN101859535A (zh) * 2009-04-13 2010-10-13 精工爱普生株式会社 电光装置及其驱动方法以及电子设备
JP2015045830A (ja) * 2013-08-29 2015-03-12 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． 電気光学装置
CN106940982A (zh) * 2017-05-04 2017-07-11 成都晶砂科技有限公司 单晶硅cmos晶体管驱动显示的像素补偿电路
CN106940981A (zh) * 2017-05-04 2017-07-11 成都晶砂科技有限公司 单晶硅晶体管cmos驱动显示的像素补偿电路及显示设备
CN107086024A (zh) * 2017-05-04 2017-08-22 成都晶砂科技有限公司 单晶硅晶体管cmos驱动显示的像素补偿电路及显示设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1932940A (zh) * 2005-09-16 2007-03-21 株式会社半导体能源研究所 显示器件及显示器件的驱动方法
CN101859535A (zh) * 2009-04-13 2010-10-13 精工爱普生株式会社 电光装置及其驱动方法以及电子设备
JP2015045830A (ja) * 2013-08-29 2015-03-12 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． 電気光学装置
CN106940982A (zh) * 2017-05-04 2017-07-11 成都晶砂科技有限公司 单晶硅cmos晶体管驱动显示的像素补偿电路
CN106940981A (zh) * 2017-05-04 2017-07-11 成都晶砂科技有限公司 单晶硅晶体管cmos驱动显示的像素补偿电路及显示设备
CN107086024A (zh) * 2017-05-04 2017-08-22 成都晶砂科技有限公司 单晶硅晶体管cmos驱动显示的像素补偿电路及显示设备

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