WO2019111104A1 - Semiconductor device, memory device, and display device - Google Patents

Semiconductor device, memory device, and display device Download PDF

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Publication number
WO2019111104A1
WO2019111104A1 PCT/IB2018/059374 IB2018059374W WO2019111104A1 WO 2019111104 A1 WO2019111104 A1 WO 2019111104A1 IB 2018059374 W IB2018059374 W IB 2018059374W WO 2019111104 A1 WO2019111104 A1 WO 2019111104A1
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Prior art keywords
transistor
voltage
metal oxide
circuit
insulator
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PCT/IB2018/059374
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French (fr)
Japanese (ja)
Inventor
高橋圭
楠紘慈
渡邉一徳
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株式会社半導体エネルギー研究所
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Publication of WO2019111104A1 publication Critical patent/WO2019111104A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components

Definitions

  • One embodiment of the present invention relates to a semiconductor device, a memory device, and a display device.
  • one aspect of the present invention relates to a product, a method, or a manufacturing method.
  • one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • One aspect of the present invention relates to a driving method thereof or a manufacturing method thereof.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • the memory device, the display device, the electro-optical device, the power storage device, the semiconductor circuit, and the electronic device may include the semiconductor device.
  • oxide semiconductors have attracted attention as other materials.
  • oxide semiconductor not only oxides of single-component metals such as indium oxide and zinc oxide but also oxides of multi-component metals are known as an example.
  • oxides of multi-element metals in particular, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.
  • Non-Patent Documents 1 to 3 a c-axis aligned crystalline (CAAC) structure and an nc (nanocrystalline) structure which are neither single crystal nor amorphous were found in an oxide semiconductor (see Non-Patent Documents 1 to 3) .
  • Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Further, Non-Patent Documents 4 and 5 show that even oxide semiconductors with lower crystallinity than the CAAC structure and the nc structure have minute crystals.
  • Non-Patent Document 6 a transistor using IGZO as an active layer has an extremely low off current (see Non-Patent Document 6), and LSIs and displays utilizing the characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8) .
  • Patent Document 1 discloses a memory device having a configuration in which a transistor with extremely low off-state current is used for a memory cell.
  • One embodiment of the present invention is a semiconductor device including a band gap reference circuit, a voltage reference circuit, a voltage control oscillator, and a negative voltage generation circuit.
  • the voltage reference circuit comprises a first transistor having a metal oxide in the semiconductor layer.
  • the band gap reference circuit can output a first voltage and a first current. By supplying the first current to the first transistor, the threshold voltage of the first transistor can be output.
  • the voltage controlled oscillator may convert a voltage difference between the threshold voltage and the first voltage to a first frequency.
  • the negative voltage generation circuit may generate the first negative voltage according to the first frequency.
  • the back gate of the first transistor is a semiconductor device having a function of adjusting the threshold voltage of the first transistor to be the first voltage by receiving the first negative voltage.
  • the band gap reference circuit can further output the second voltage.
  • the voltage controlled oscillator can convert the potential difference between the threshold voltage and the second voltage into the second frequency.
  • the negative voltage generation circuit may generate the second negative voltage according to the second frequency. It is preferable that the back gate of the first transistor be a semiconductor device to which either a first negative voltage or a second negative voltage is applied.
  • the semiconductor device includes an operation mode control circuit. It is preferable that the back gate of the first transistor be a semiconductor device to which either the first negative voltage or the second negative voltage selected by the operation mode control circuit is applied.
  • the memory device includes a semiconductor device, and the memory device includes a plurality of memory cells.
  • Each memory cell includes a second transistor having a metal oxide in the semiconductor layer. It is preferable that a memory device in which either the first negative voltage or the second negative voltage is supplied to the back gate of the second transistor.
  • the display device includes a semiconductor device, and the display device includes a memory device and a display panel.
  • the display panel has a plurality of pixels.
  • Each pixel has a third transistor having a metal oxide in the semiconductor layer. It is preferable that the back gate of the third transistor be provided with either the first negative voltage or the second negative voltage.
  • the negative voltage generation circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitive element, a second capacitive element, a first input terminal, a second input terminal, It has an output terminal, a first wiring, and a second wiring.
  • the fourth to seventh transistors each include a metal oxide in the semiconductor layer.
  • the first input terminal is electrically connected to the gate of the fourth transistor, the gate of the fifth transistor, and the gate of the eighth transistor.
  • the second input terminal is electrically connected to the gate of the sixth transistor and the gate of the seventh transistor.
  • the first wiring is electrically connected to one of the source and the drain of the fourth transistor.
  • the second wiring is electrically connected to one of the source and the drain of the fifth transistor.
  • the other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the sixth transistor and one of the electrodes of the first capacitive element.
  • the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the seventh transistor and the other of the electrode of the first capacitive element.
  • the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the eighth transistor and one of the electrodes of the second capacitor.
  • the other of the source and the drain of the eighth transistor is electrically connected to the second wiring. It is preferable that the other of the source and the drain of the seventh transistor be a semiconductor device connected to the other of the electrodes of the second capacitor, the back gate of each of the fourth to eighth transistors, and the output terminal.
  • the third voltage is applied to the first wiring.
  • a fourth potential smaller than the third voltage is applied to the second wiring.
  • the first input terminal is supplied with a signal of the first frequency. It is preferable that the second input terminal be a semiconductor device which outputs a negative voltage to the back gate of each of the fourth to eighth transistors and the output terminal by receiving an inverted signal of the first frequency.
  • a novel semiconductor device can be provided. Further, according to one embodiment of the present invention, a semiconductor device in which data is held without being affected by a temperature change can be provided. According to one embodiment of the present invention, a semiconductor device in which an increase in power consumption is suppressed can be provided.
  • FIG. 2 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 2 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 2 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 2 is a block diagram showing an example of the configuration of a display device.
  • FIG. 2 is a circuit diagram showing a configuration example of a pixel.
  • FIG. 7 is a cross-sectional view showing a configuration example of a transistor.
  • FIG. 7 is a cross-sectional view showing a configuration example of a transistor.
  • FIG. 7 is a cross-sectional view showing a configuration example of a transistor.
  • FIG. 7 is a cross-sectional view showing a configuration example of a transistor.
  • FIG. 7 is a cross-sectional view showing a configuration example of a transistor.
  • FIG. 7 is a cross-sectional view showing a configuration example of a transistor.
  • FIG. 2 is a block diagram showing an example of the structure of a storage device.
  • FIG. 2 is a circuit diagram showing an example of the configuration of a memory cell.
  • 5 is a timing chart showing an operation example of a semiconductor device.
  • FIG. 2 is a block diagram showing an example of the structure of a memory cell array.
  • FIG. 2 is a circuit diagram showing an example of the structure of a memory cell.
  • FIG. 2 is a circuit diagram showing an example of the structure of a memory cell.
  • FIG. 2 is a circuit diagram showing an example of the structure of a memory cell.
  • FIG. 7 is a cross-sectional view showing a configuration example of a memory device.
  • FIG. 7 is a cross-sectional view showing a configuration example of a transistor.
  • FIG. 7 is a cross-sectional view showing a configuration example of a transistor.
  • FIG. 7 is a cross-sectional view showing a configuration example of a memory device.
  • FIG. 5 is a top view showing an example of the configuration of a resistance element.
  • FIG. 7 is a cross-sectional view showing a configuration example of a memory device having a resistance element. The figure explaining the range of the atomic ratio of a metal oxide.
  • 7A and 7B are a top view and a cross-sectional view illustrating a configuration example of a transistor.
  • 7A and 7B are a top view and a cross-sectional view illustrating a configuration example of a transistor.
  • 5A and 5B are a flowchart and a perspective view illustrating a manufacturing process of a semiconductor device.
  • FIG. 2 is a perspective view showing an example of an electronic device.
  • FIG. 2 is a perspective view showing an example of an electronic device.
  • a high power supply voltage may be referred to as an H level (or V DD ), and a low power supply voltage may be referred to as an L level (or GND).
  • the metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, and the like. For example, in the case where a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In the case of describing an OS transistor, the transistor can be put in another way as a transistor having a metal oxide or an oxide semiconductor. In the present specification and the like, metal oxides having nitrogen may also be generically referred to as metal oxides.
  • FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device which is an embodiment of the present invention.
  • the semiconductor device 10 can control a threshold voltage of a transistor included in the memory device, the display device, the electronic device, or the like by a feedback loop in accordance with a use environment of the memory device, the display device, the electronic device, or the like.
  • the semiconductor device 10 includes a band gap reference circuit 11, a voltage reference circuit 12, a selection circuit 13, a difference detection circuit 14, a voltage control oscillator 15, a negative voltage generation circuit 16, and an operation mode control circuit 17.
  • the band gap reference circuit 11 has an output terminal 11a, an output terminal 11b, and an output terminal 11c.
  • the first current is output to the output terminal 11a, the first potential is output to the output terminal 11b, and the second potential is output to the output terminal 11c.
  • the voltage reference circuit 12 has an input terminal 12a, an input terminal 12c, an input terminal 12d, and an output terminal 12b.
  • the voltage reference circuit 12 includes a first transistor having a metal oxide in the semiconductor layer. The first transistor will be described in detail with reference to FIG.
  • the first transistor has a back gate, and the back gate is electrically connected to the input terminal 12c.
  • the output terminal 12b outputs the threshold voltage of the first transistor.
  • the input terminal 12 d is electrically connected to the wiring RST.
  • the signal applied to the wiring RST can initialize the back gate potential of the first transistor.
  • the input terminal 12d may not necessarily be provided.
  • the selection circuit 13 has an input terminal 13a, an input terminal 13b, an input terminal 13d, and an output terminal 13c.
  • the input terminal 13a is electrically connected to the output terminal 11b, and the input terminal 13b is electrically connected to the output terminal 11c.
  • the operation mode control circuit 17 is electrically connected to the input terminal 13d. Therefore, according to the temperature detected by the operation mode control circuit 17, the selection circuit 13 outputs either the first potential applied to the input terminal 13a or the second potential applied to the input terminal 13b to the output terminal 13c.
  • the conditions for temperature selection may be managed more finely, and the selection circuit 13 may output different potentials according to the respective temperatures.
  • Operation mode control circuit 17 may have a configuration in which operation mode control circuit 17 for detecting temperature has a temperature sensor, or a configuration in which a temperature sensor is connected to operation mode control circuit 17 may be used, or The configuration may be such that temperature information is given from a CPU or the like.
  • the difference detection circuit 14 detects and outputs a difference between the threshold voltage of the first transistor and the output voltage of the selection circuit 13 as a difference voltage.
  • the difference detection circuit 14 can be easily detected by using an amplifier.
  • the difference detection circuit 14 may be configured by an analog-to-digital converter.
  • the voltage control oscillator 15 can convert the input differential voltage into a frequency.
  • the voltage controlled oscillator 15 preferably converts voltage to frequency using a VCO circuit (Voltage Controlled Oscillator) or the like.
  • the magnitude of the output frequency of the voltage control oscillator 15 is controlled in accordance with the magnitude of the input differential voltage.
  • the negative voltage generation circuit 16 has an input terminal 16a, an output terminal 16b, a level shifter circuit 16c, and a charge pump circuit 16d.
  • the output frequency is given as an input frequency to the level shifter circuit 16c via the input terminal 16a.
  • the level shifter circuit 16c can adjust the amplitude voltage of the input frequency applied to the charge pump circuit 16d. Also, the level shifter circuit 16c can generate a positive phase signal and an inverted signal to be supplied to the charge pump circuit 16d.
  • the charge pump circuit 16d can generate a negative voltage in accordance with the applied input frequency.
  • the negative voltage generated by the charge pump circuit 16 d can be applied to the input terminal 12 c of the voltage reference circuit 12. Therefore, the voltage applied to the back gate of the first transistor can be controlled such that the threshold voltage of the first transistor converges to the same voltage as the output voltage of the selection circuit 13.
  • a back gate of the transistor is controlled by a signal VBG output from the semiconductor device 10 by voltage. can do. Therefore, when the storage device or the display device is used in a large temperature change environment, signal VBG applied to the back gate of the transistor is set to the threshold voltage selected by operation mode control circuit 17. The threshold voltage is adjusted. Thus, the off-state current of the transistor is kept low. In addition, deterioration of data which occurs when the storage device is used in a high temperature environment or display defects of pixels which occur when the display device is used in a high temperature environment can be reduced. In addition, it is possible to suppress an increase in power consumption or standby power generated when the storage device or the display device is used in a high temperature environment.
  • FIG. 2A is a circuit diagram showing a configuration example of the band gap reference circuit 11.
  • the band gap reference circuit 11 includes a band gap reference circuit 11 d and a reference voltage / current generation circuit 11 e.
  • the band gap reference circuit 11d can output an arbitrary voltage to the output terminal.
  • the band gap reference circuit 11d may use a known circuit.
  • the arbitrary voltage is set to be, for example, the threshold voltage of the first transistor at normal temperature (25 ° C.).
  • the arbitrary voltage is not limited and is preferably set in accordance with the use environment of a storage device, a display device, an electronic device, or the like.
  • the reference voltage / current generation circuit 11e includes an amplifier 30, transistors 31a to 31d, and resistance elements 32a to 32c.
  • the transistors 31a to 31d are preferably p-type transistors.
  • the amplifier 30 preferably has a voltage follower connection.
  • the output terminal of the band gap reference circuit 11 d is electrically connected to the non-inverted input terminal of the amplifier 30.
  • the output terminal of the amplifier 30 is electrically connected to the inverting input terminal.
  • the output terminal of the amplifier 30 is electrically connected to the gate of each of the transistors 31a to 31d.
  • the sources of the transistors 31a to 31d are connected to the wiring VDD1 to form a current mirror circuit.
  • the drain of the transistor 31a is electrically connected to the resistance elements 32a to 32c connected in series.
  • the drain of the transistor 31b is electrically connected to the resistance elements 32b and 32c connected in series.
  • the drain of the transistor 31c is electrically connected to the resistance element 32c.
  • the current mirror circuit may be formed of an n-type transistor.
  • the resistive element which has the same code represents the resistive element of the same magnitude
  • the transistors 31a to 31d preferably have the same channel length.
  • the transistors 31a to 31c can have the same channel width to make the magnitudes of the currents flowing to the transistors 31a to 31c the same. Therefore, any voltage can be easily generated by changing the resistance value.
  • the reference voltage can be generated by causing the transistor 31a to flow a current to the resistance elements 32a to 32c connected in series.
  • the amplifier 30 functions as a voltage follower by applying the reference voltage to the inverting input terminal.
  • the first voltage can be generated by causing the transistor 31 b to flow a current through the resistance elements 32 b and 32 c connected in series. The first voltage is output to the output terminal 11b.
  • the transistor 31c can generate the second voltage by causing a current to flow through the resistor element 32c. The second voltage is output to the output terminal 11c.
  • the reference voltage / current generation circuit 11e further includes a transistor 31d that generates a first current.
  • the channel width of the transistor 31 d may be the same as or different from that of the transistors 31 a to 31 c.
  • the first current flowing to the transistor 31 d is output to the output terminal 11 a.
  • the threshold voltage of the first transistor may be more finely controlled by increasing the number of stages of the current mirror and finely setting the combination of the resistors.
  • FIG. 2B is a circuit diagram showing a configuration of voltage reference circuit 12.
  • the voltage reference circuit 12 includes a transistor 33, a resistive element 34, and a transistor 35.
  • the transistors 33 and 35 are transistors each including a metal oxide in a semiconductor layer.
  • the transistor 33 corresponds to a first transistor included in the voltage reference circuit 12.
  • the drain and gate of the transistor 33 are electrically connected to the input terminal 12a and the output terminal 12b.
  • the source of the transistor 33 is electrically connected to the wiring GND.
  • the back gate of the transistor 33 is electrically connected to one of the electrodes of the resistance element 34, one of the source or drain of the transistor 35, the back gate of the transistor 35, and the input terminal 12 c.
  • the other of the electrodes of the resistance element 34 is electrically connected to the wiring VDD1. Further, the other of the source and the drain of the transistor 35 is electrically connected to the wiring GND.
  • the drain and gate of the transistor 33 are supplied with the first current through the input terminal 12a.
  • the output terminal 12 b outputs the threshold voltage of the transistor 33.
  • the threshold voltage of the transistor 33 is shifted by the voltage applied to the back gate of the transistor 33. Therefore, the negative voltage generated by the negative voltage generation circuit 16 is given to the back gate of the transistor 33 through the input terminal 12c. That is, the voltage reference circuit 12, the selection circuit 13, the difference detection circuit 14, the voltage control oscillator 15, and the negative voltage generation circuit 16 can form a feedback loop centered on the transistor 33.
  • the selection circuit 13 can select the potential to be output to the output terminal 13c from either the first potential or the second potential according to the temperature detected by the operation mode control circuit 17. In the feedback loop, when the output voltage of the output terminal 12b of the voltage reference circuit 12 becomes equal to the potential output to the output terminal 13c, the feedback adjustment converges, and the adjustment ends.
  • the transistor 35 can initialize the back gate potential of the transistor 33.
  • the resistive element 34 can generate the back gate potential of the transistor 33 based on the voltage applied to the wiring VDD1. Instead of the resistive element 34, a capacitive element or a diode may be used. Since the negative voltage generation circuit 16 described later generates a negative voltage using the charge pump circuit 16 d, it is preferable that the negative voltage applied to the back gate of the transistor 33 can be finely adjusted. Therefore, by flowing a current through the resistor, the negative voltage applied to the back gate of the transistor 33 can be finely adjusted.
  • FIG. 3 is a circuit diagram showing a configuration of negative voltage generation circuit 16.
  • the negative voltage generation circuit 16 has an input terminal 16a, an output terminal 16b, a level shifter circuit 16c, and a charge pump circuit 16d.
  • the level shifter circuit 16 c includes a level shifter 36 a and a level shifter 36 b.
  • the level shifter circuit 16c can adjust the amplitude voltage of the signal supplied to the charge pump circuit 16d.
  • the level shifter 36a can expand the voltage to the positive voltage side.
  • the level shifter 36 b can extend the voltage to the negative voltage side.
  • the voltage applied to the wiring VDD1 is the maximum voltage on the positive voltage side.
  • the negative voltage generated by the charge pump circuit 16 d is the minimum voltage on the negative voltage side.
  • the level shifter 36a can generate a positive phase signal to be supplied to the charge pump circuit 16d, and the level shifter 36b can generate an inversion signal to be supplied to the charge pump circuit 16d.
  • the charge pump circuit 16d includes a transistor 37a, a transistor 37b, a capacitor 37c, a transistor 38a, a transistor 38b, a capacitor 38c, a transistor 39, an input terminal 16e, an input terminal 16f, an output terminal 16b, a wiring VDD2, and a wiring GND.
  • the transistors 37a, 37b, 38a, 38b, and 39 preferably each include a metal oxide in a semiconductor layer.
  • the input terminal 16 e is electrically connected to the gate of the transistor 37 a, the gate of the transistor 37 b, and the gate of the transistor 39.
  • the input terminal 16f is electrically connected to the gate of the transistor 38a and the gate of the transistor 38b.
  • the wiring VDD2 is electrically connected to one of the source and the drain of the transistor 37a.
  • the wiring GND is electrically connected to one of the source and the drain of the transistor 37b.
  • the other of the source and the drain of the transistor 37a is electrically connected to one of the source and the drain of the transistor 38a and one of the electrodes of the capacitor 37c.
  • the other of the source and the drain of the transistor 37b is electrically connected to one of the source and the drain of the transistor 38b and the other of the electrodes of the capacitor 37c.
  • the other of the source and the drain of the transistor 38a is electrically connected to one of the source and the drain of the transistor 39 and one of the electrodes of the capacitor 38c.
  • the other of the source and the drain of the transistor 39 is electrically connected to the wiring GND.
  • the other of the source or drain of the transistor 38b is the output terminal 16b, the level shifter 36a, the level shifter 36b, the other of the electrodes of the capacitor 38c, the transistor 37a, the transistor 37b, the transistor 38a, the transistor 38b, and the transistor 39 Connected.
  • a positive voltage is applied to the wiring VDD2.
  • a voltage smaller than the positive voltage applied to the wiring VDD2 is applied to the wiring GND.
  • the reference potential of the circuit is supplied to the wiring GND.
  • the wiring VDD2 is preferably a voltage lower than or equal to the voltage supplied to the wiring VDD1. More preferably, the wiring VDD2 is preferably a voltage smaller than the voltage applied to the wiring VDD1.
  • the output of the level shifter 36a turns on the transistor 37a, the transistor 37b, and the transistor 39.
  • the output of the level shifter 36b is the inverted state of the output of the level shifter 36a, and therefore the transistor 38a and the transistor 38b are turned off. Therefore, a positive voltage is applied to the one of the electrodes of the capacitive element 37c from the wiring VDD2, and 0 V is applied to the other of the electrodes of the capacitive element 37c as an example from the wiring GND. Accordingly, a voltage corresponding to a potential difference between the wiring VDD2 and 0 V is held in the capacitor 37c.
  • the output of the level shifter 36a is inverted, and the transistors 37a, 37b, and 39 are turned off.
  • the output of the level shifter 36b is the inverted state of the output of the level shifter 36a, and the transistor 38a and the transistor 38b are turned on.
  • the capacitive element 37c and the capacitive element 38c form a combined capacitance, and the voltage held by the capacitive element 37c becomes a smoothed potential.
  • the other of the electrodes of the capacitor 37c and the other of the electrodes of the capacitor 38c is formed through the transistor 38b becomes a floating node, the floating node becomes a reference potential of the smoothed potential. .
  • the output of the level shifter 36a turns on the transistor 37a, the transistor 37b, and the transistor 39.
  • the output of the level shifter 36b is the inverted state of the output of the level shifter 36a, and the transistor 38a and the transistor 38b are turned off.
  • the smoothed potential is held in the capacitive element 38c. Subsequently, when one of the electrodes of the capacitive element 38c changes to 0 V applied to the wiring GND, one of the electrodes of the capacitive element 38c becomes a reference potential, and the other of the electrodes of the capacitive element 38c is smoothed.
  • the potential is generated as a negative voltage.
  • the generated negative voltage is applied to the output terminal 16b, and is further applied to the back gates of the transistor 37a, the transistor 37b, the transistor 38a, the transistor 38b, and the transistor 39. Furthermore, the generated negative voltage is given as a negative power supply of the level shifter 36a and the level shifter 36b.
  • the threshold voltage of the transistor is controlled by the feedback loop in accordance with the use environment of the memory device, the display device, the electronic device, or the like, and the temperature change is not affected.
  • a semiconductor device in which data is held can be provided.
  • an increase in power consumption can be suppressed.
  • Second Embodiment ⁇ display device 20 >> In this embodiment, configuration examples of a display device which suppresses the influence of temperature change will be described with reference to FIGS. In the present embodiment, description of the operation and function of the semiconductor device 10 described in the first embodiment will be omitted.
  • FIG. 4A is a block diagram illustrating a configuration example of a display device.
  • the display device 20 includes a control unit 21 and a display panel 26.
  • the control unit 21 includes a semiconductor device 10, a display controller 22, a frame memory 23, a source driver 24, and a gate driver 25.
  • the frame memory 23 has a storage device 100.
  • the frame memory 23 includes, for example, a plurality of storage devices 100a and 100b, so that display data can be compared to distinguish still images from moving images, filtering to improve image quality, images and text information, etc. Can be used for image data combining processing for overlapping, and image data combining processing for overlapping different images.
  • the frame memory 23 is provided with image data from the CPU 27 or the like.
  • the CPU 27 can collect, from the temperature sensor 18 or the like, temperature information such as components such as a display device or a storage device, and an environmental temperature at which the display device is used, and give the semiconductor device 10.
  • the storage device 100 may use a storage circuit such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). Note that a still image or the like can be held for a long time by using a transistor with small off current in the memory circuit.
  • a memory device including a transistor with a small off current there is a DOSRAM (registered trademark) “Dynamic Oxide Semiconductor RAM”, a NOSRAM (registered trademark) “Nonvolatile Oxide Semiconductor RAM”, and the like.
  • a transistor with a small off current is described in detail in Embodiment 8.
  • a memory device 100 using a transistor with a small off current is described in detail in Embodiment 3.
  • the display panel 26 has a display area, and the display area has pixel groups arranged in an array, and each pixel has a transistor.
  • the pixel group arranged in an array will be described in other words as the pixel 26a.
  • the transistor included in the pixel 26 a can reduce off current by including a metal oxide in the semiconductor layer.
  • deterioration of display data can be suppressed and a display update interval can be lengthened.
  • a display period can be extended by suppressing an increase in off current from the transistors included in the frame memory 23 and the pixels 26a.
  • the off current of the transistor is further increased, so that the off current of the transistor included in the pixel 26 a is increased to deteriorate display data.
  • a change in threshold voltage of the transistor can be controlled. That is, even when used in a high temperature environment, the transistor included in the pixel 26a can suppress an increase in off current.
  • the transistor included in the storage device 100 can suppress an increase in off current.
  • FIG. 4B the display device 20 having a configuration different from that of FIG. 4A will be described.
  • the display device 20 shown in FIG. 4B is different in that the gate driver 25a is formed of a transistor having a metal oxide in a semiconductor layer.
  • the gate driver 25a and the pixel 26a are formed with the same transistor, the threshold voltage of the transistor can be controlled by the voltage applied to the back gate of the transistor. Therefore, since the gate driver 25a and the transistor used in the pixel 26a are the same, the timing of writing display data to the pixel 26a can be appropriately managed by the gate driver 25a.
  • an increase in power consumption of the display panel 26 can be suppressed.
  • FIG. 5 is a circuit diagram of a pixel circuit showing a configuration example of the pixel 26a of FIG. 4 (A). The description of the same contents in each configuration will be omitted.
  • FIG. 5A1 illustrates a pixel circuit in which a liquid crystal element is used as a display element.
  • the pixel circuit includes a transistor 41a, a capacitor 42a, a display element 43, a wiring GL1, a wiring SL1, a wiring COM, and a wiring BGL.
  • the gate of the transistor 41a is electrically connected to the wiring GL1.
  • One of the source and the drain of the transistor 41a is electrically connected to the wiring SL1.
  • the other of the source and the drain of the transistor 41 a is electrically connected to one of the electrodes of the capacitor 42 a and one of the display elements 43.
  • the wiring COM is electrically connected to the other of the electrodes of the capacitor 42 a and the other of the display element 43.
  • the back gate of the transistor 41a is electrically connected to the wiring BGL.
  • the wiring BGL is preferably connected in common to the pixels arranged in an array.
  • the display area may be divided into a plurality of display areas, and the divided display area wirings may be connected to different BGLs.
  • the output voltage of the semiconductor device 10 of the first embodiment is applied to the wiring BGL.
  • the pixel circuit illustrated in FIG. 5A2 further includes a transistor 41b, a capacitor 42b, a wiring GL2, and a wiring SL2.
  • the gate of the transistor 41 b is electrically connected to the wiring GL2.
  • One of the source and the drain of the transistor 41 b is electrically connected to the wiring SL2.
  • the other of the source and the drain of the transistor 41 b is electrically connected to one of the electrodes of the capacitor 42 b.
  • the other of the electrodes of the capacitor 42 b is electrically connected to the other of the source and the drain of the transistor 41 a, one of the electrodes of the capacitor 42 a, and one of the display elements 43.
  • the back gate of the transistor 41 b is electrically connected to the wiring BGL.
  • the output voltage of the semiconductor device 10 of the first embodiment is applied to the wiring BGL.
  • second display data can be added to the first display data supplied to the capacitor 42a through the capacitor 42b.
  • the first display data given to the display element 43 is given as a first data voltage
  • the second display data is given as a second data voltage. That is, since the display data can add the second data voltage to the first data voltage, the output voltage of the source driver can be reduced.
  • a plurality of display data can be added to the first display data.
  • the third display data can be added to the first display data by including the transistor 41c, the capacitor 42c, the wiring GL3, and the wiring SL3. Therefore, the number of display data to be added is not limited.
  • FIG. 5B1 illustrates a pixel circuit in which an EL (Electroluminescence) element is used as a display element.
  • the pixel circuit includes a transistor 44a, a transistor 45, a capacitor 46a, a display element 47, a wiring GL1, a wiring SL1, a wiring ANO, a wiring CATH, and a wiring BGL.
  • the gate of the transistor 44a is electrically connected to the wiring GL1.
  • One of the source and the drain of the transistor 44a is electrically connected to the wiring SL1.
  • the other of the source and the drain of the transistor 44a is electrically connected to one of the gate of the transistor 45, the back gate of the transistor 45, and the electrode of the capacitor 46a.
  • One of the source and the drain of the transistor 45 is electrically connected to the wiring ANO.
  • the other of the source and the drain of the transistor 45 is electrically connected to one of the electrodes of the display element 47 and the other of the electrodes of the capacitor 46a.
  • the other of the electrodes of the display element 47 is electrically connected to the wiring CATH.
  • the back gate of the transistor 44a is electrically connected to the wiring BGL.
  • the wiring BGL is preferably connected in common to the pixels arranged in an array. However, the display area may be divided into a plurality of display areas, and the divided display area wirings may be connected to different BGLs. Note that the back gate of the transistor 45 may be electrically connected to the other of the source and the drain of the transistor 45.
  • the output voltage of the semiconductor device 10 of the first embodiment is applied to the wiring BGL.
  • FIG. 5 (B2) a pixel circuit which is different from that in FIG. 5 (B1) is described.
  • the pixel circuit illustrated in FIG. 5B2 is further different in that the transistor 48 and the wiring GL2 are included.
  • the gate of the transistor 48 is electrically connected to the wiring GL2.
  • One of the source and the drain of the transistor 48 is electrically connected to the wiring MN.
  • the other of the source and the drain of the transistor 48 is electrically connected to the other of the source and the drain of the transistor 45, the other of the electrode of the capacitor 46a, and one of the electrodes of the display element 47.
  • the back gate of the transistor 48 is electrically connected to the wiring BGL.
  • the output voltage of the semiconductor device 10 of the first embodiment is applied to the wiring BGL.
  • writing of display data of the transistor 45 can be guaranteed by including the transistor 48.
  • the threshold voltage of the transistor 45 can be read out from the wiring MN through the transistor 48.
  • FIG. 5 (B3) a pixel circuit different from that in FIG. 5 (B2) is described.
  • the pixel circuit illustrated in FIG. 5B3 further includes a transistor 44b, a capacitor 46b, a wiring GL3, and a wiring SL2.
  • the gate of the transistor 44b is electrically connected to the wiring GL3.
  • One of the source and the drain of the transistor 44b is electrically connected to the wiring SL2.
  • the other of the source and the drain of the transistor 44b is electrically connected to one of the electrodes of the capacitor 46b.
  • the other of the electrodes of the capacitor 46b is electrically connected to the other of the source and the drain of the transistor 44a, the gate of the transistor 45, the back gate of the transistor 45, and one of the electrodes of the capacitor 46a.
  • the back gate of the transistor 44 b is electrically connected to the wiring BGL.
  • the wiring BGL is preferably connected in common to the pixels arranged in an array.
  • the output voltage of the semiconductor device 10 of the first embodiment is
  • the second display data can be added to the first display data given to the capacitor 46a via the capacitor 46b.
  • the first display data given to the display element 43 is given as a first data voltage
  • the second display data is given as a second data voltage. That is, since the display data can add the second data voltage to the first data voltage, the output voltage of the source driver can be reduced.
  • a plurality of display data can be added to the first display data.
  • the third display data can be added to the first display data by including the transistor 44c, the capacitor 46c, the wiring GL4, and the wiring SL3. Therefore, the number of display data to be added is not limited.
  • the display panel 26 can be manufactured using various types of transistors such as a bottom gate transistor and a top gate transistor. Therefore, according to the existing manufacturing line, the material of the semiconductor layer to be used and the transistor structure can be easily replaced.
  • FIG. 6A1 is a cross-sectional view in the channel length direction of a channel protective transistor 810 which is a kind of bottom gate transistor.
  • the transistor 810 is formed over a substrate 860.
  • the transistor 810 also includes an electrode 858 over the substrate 860 with the insulating layer 861 interposed therebetween.
  • the semiconductor layer 856 is provided over the electrode 858 with the insulating layer 852 interposed therebetween.
  • the electrode 858 can function as a gate electrode.
  • the insulating layer 852 can function as a gate insulating layer.
  • the insulating layer 855 is provided over the channel formation region of the semiconductor layer 856.
  • an electrode 857 a and an electrode 857 b are provided over the insulating layer 852 in contact with part of the semiconductor layer 856.
  • the electrode 857a can function as one of a source electrode and a drain electrode.
  • the electrode 857 b can function as the other of the source electrode and the drain electrode.
  • a portion of the electrode 857a and a portion of the electrode 857b are formed over the insulating layer 855.
  • the insulating layer 855 can function as a channel protective layer. By providing the insulating layer 855 over the channel formation region, exposure of the semiconductor layer 856 which is generated at the time of formation of the electrodes 857a and 857b can be prevented. Thus, the channel formation region of the semiconductor layer 856 can be prevented from being etched when the electrode 857a and the electrode 857b are formed. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.
  • the transistor 810 includes the insulating layer 853 over the electrode 857a, the electrode 857b, and the insulating layer 855, and the insulating layer 854 over the insulating layer 853.
  • an oxide semiconductor is used for the semiconductor layer 856
  • a material capable of generating oxygen vacancies by removing oxygen from part of the semiconductor layer 856 is used in at least a portion of the electrode 857a and the electrode 857b in contact with the semiconductor layer 856.
  • the region of the semiconductor layer 856 in which oxygen vacancies occur has an increased carrier concentration, and the region becomes n-type to be an n-type region (n + layer). Thus, the region can function as a source region or a drain region.
  • tungsten, titanium, or the like can be given as an example of a material that can deprive the semiconductor layer 856 of oxygen and cause oxygen vacancies.
  • the contact resistance between the electrode 857a and the electrode 857b and the semiconductor layer 856 can be reduced. Accordingly, electric characteristics of the transistor such as field effect mobility and threshold voltage can be improved.
  • a layer functioning as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 856 and the electrode 857a and between the semiconductor layer 856 and the electrode 857b.
  • a layer functioning as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of a transistor.
  • the insulating layer 854 is preferably formed using a material having a function of preventing or reducing diffusion of impurities into the transistor from the outside. Note that the insulating layer 854 can be omitted as needed.
  • a transistor 811 illustrated in FIG. 6A2 is different from the transistor 810 in that an electrode 850 that can function as a back gate electrode is provided over the insulating layer 854.
  • the electrode 850 can be formed with the same material and method as the electrode 858.
  • the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode are disposed so as to sandwich the channel formation region of the semiconductor layer.
  • the back gate electrode can function similarly to the gate electrode.
  • the potential of the back gate electrode may be the same as that of the gate electrode, or may be the ground potential (GND potential) or any potential.
  • the threshold voltage of the transistor can be changed by independently changing the potential of the back gate electrode without interlocking with the gate electrode.
  • the back gate electrode be supplied with the output voltage of the semiconductor device 10 of FIG.
  • each of the insulating layer 852, the insulating layer 853, and the insulating layer 854 can function as a gate insulating layer.
  • the electrode 850 may be provided between the insulating layer 853 and the insulating layer 854.
  • the other is referred to as a “back gate electrode”.
  • the electrode 858 when the electrode 850 is referred to as a “gate electrode”, the electrode 858 is referred to as a “back gate electrode”.
  • the transistor 811 can be considered as a kind of top gate transistor.
  • one of the electrode 858 and the electrode 850 may be referred to as a “first gate electrode”, and the other may be referred to as a “second gate electrode”.
  • the region in which the carrier flows in the semiconductor layer 856 becomes larger in the film thickness direction.
  • the amount of carrier movement increases.
  • the on current of the transistor 811 is increased, and the field effect mobility is increased.
  • the transistor 811 is a transistor having a large on current with respect to the occupied area. That is, the area occupied by the transistor 811 can be reduced with respect to the on current required. According to one embodiment of the present invention, the area occupied by the transistor can be reduced. Thus, according to one embodiment of the present invention, a semiconductor device with a high degree of integration can be realized.
  • the gate electrode and the back gate electrode are formed of a conductive layer, they have a function to prevent an electric field generated outside the transistor from acting on the semiconductor layer in which a channel is formed (in particular, an electric field shielding function against static electricity). .
  • the electric field shielding function can be enhanced by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode.
  • the back gate electrode is formed using a light-shielding conductive film
  • light can be prevented from entering the semiconductor layer from the back gate electrode side. Accordingly, light deterioration of the semiconductor layer can be prevented, and deterioration of electrical characteristics such as a shift in threshold voltage of a transistor can be prevented.
  • a highly reliable transistor can be realized.
  • a highly reliable semiconductor device can be realized.
  • FIG. 6B1 is a cross-sectional view in the channel length direction of a channel protective transistor 820 having a different structure from that in FIG. 6A1.
  • the transistor 820 has substantially the same structure as the transistor 810, except that the insulating layer 855 covers an end portion of the semiconductor layer 856.
  • the semiconductor layer 856 and the electrode 857a are electrically connected to each other in an opening portion which is formed by selectively removing part of the insulating layer 855 overlapping with the semiconductor layer 856.
  • the semiconductor layer 856 and the electrode 857 b are electrically connected to each other in another opening which is formed by selectively removing part of the insulating layer 855 overlapping with the semiconductor layer 856.
  • the region of the insulating layer 855 overlapping with the channel formation region can function as a channel protective layer.
  • a transistor 821 illustrated in FIG. 6B2 is different from the transistor 820 in that an electrode 850 that can function as a back gate electrode is provided over the insulating layer 854.
  • the exposure of the semiconductor layer 856 which is generated at the time of formation of the electrodes 857a and 857b can be prevented.
  • thinning of the semiconductor layer 856 can be prevented at the time of formation of the electrodes 857a and 857b.
  • the distance between the electrode 857a and the electrode 858 and the distance between the electrode 857b and the electrode 858 are longer than those in the transistors 810 and 811.
  • parasitic capacitance generated between the electrode 857a and the electrode 858 can be reduced.
  • parasitic capacitance generated between the electrode 857 b and the electrode 858 can be reduced.
  • a transistor with favorable electrical characteristics can be realized.
  • a transistor 825 illustrated in FIG. 6C1 is a cross-sectional view in the channel length direction of a channel-etched transistor 825 which is one of bottom-gate transistors.
  • the transistor 825 forms the electrode 857a and the electrode 857b without using the insulating layer 854. Therefore, part of the semiconductor layer 856 exposed when forming the electrode 857a and the electrode 857b may be etched. On the other hand, since the insulating layer 855 is not provided, productivity of the transistor can be increased.
  • a transistor 826 illustrated in FIG. 6C2 is different from the transistor 825 in that an electrode 850 that can function as a back gate electrode is provided over the insulating layer 854.
  • 7A1 to 7C2 are cross-sectional views in the channel width direction of the transistors 810, 811, 820, 821, 825, and 826, respectively.
  • the gate electrode and the back gate electrode are connected, and the potentials of the gate electrode and the back gate electrode are the same.
  • the semiconductor layer 856 is sandwiched between the gate electrode and the back gate electrode.
  • the length in the channel width direction of each of the gate electrode and the back gate electrode is longer than the length in the channel width direction of the semiconductor layer 856, and the entire channel width direction of the semiconductor layer 856 is the insulating layer 852, 855, 853, 854. It is the structure covered by the gate electrode or the back gate electrode on both sides.
  • the semiconductor layer 856 included in the transistor can be electrically surrounded by the electric field of the gate electrode and the back gate electrode.
  • a device structure of a transistor electrically surrounding a semiconductor layer 856 in which a channel formation region is formed by an electric field of a gate electrode and a back gate electrode, such as the transistor 821 or the transistor 826, is referred to as a surrounded channel (S-channel) structure.
  • S-channel surrounded channel
  • an electric field for inducing a channel can be effectively applied to the semiconductor layer 856 by one or both of the gate electrode and the back gate electrode, so that the current drive capability of the transistor is improved. It is possible to obtain high on-current characteristics. In addition, since the on current can be increased, the transistor can be miniaturized. In addition, with the S-channel structure, mechanical strength of the transistor can be increased.
  • the transistor 842 illustrated in FIG. 8A1 is one of top-gate transistors.
  • the transistor 842 is different from the transistor 810 and the transistor 820 in that the electrode 857 a and the electrode 857 b are formed after the insulating layer 854 is formed.
  • the electrode 857 a and the electrode 857 b are electrically connected to the semiconductor layer 856 in an opening formed in the insulating layer 853 and the insulating layer 854.
  • a portion of the insulating layer 852 which does not overlap with the electrode 858 is removed, and an impurity is introduced into the semiconductor layer 856 by using the electrode 858 and the remaining insulating layer 852 as a mask; Alignment) can form an impurity region.
  • the transistor 842 has a region where the insulating layer 852 extends beyond the end of the electrode 858.
  • the impurity concentration of the region into which the impurity is introduced through the insulating layer 852 of the semiconductor layer 856 is smaller than that of the region into which the impurity is introduced without the insulating layer 852.
  • a lightly doped drain (LDD) region is formed in a region which does not overlap with the electrode 858.
  • a transistor 843 illustrated in FIG. 8A2 is different from the transistor 842 in having an electrode 850.
  • the transistor 843 has an electrode 850 formed on a substrate 860.
  • the electrode 850 has a region overlapping with the semiconductor layer 856 through the insulating layer 861.
  • the electrode 850 can function as a back gate electrode.
  • the transistor 844 illustrated in FIG. 8B1 and the transistor 845 illustrated in FIG. 8B2 all the insulating layer 852 in a region which does not overlap with the electrode 858 may be removed.
  • the insulating layer 852 may be left.
  • the transistors 842 to 847 can also form impurity regions in the semiconductor layer 856 in a self-aligned manner by introducing an impurity into the semiconductor layer 856 using the electrode 858 as a mask after the electrodes 858 are formed. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. Further, according to one embodiment of the present invention, a semiconductor device with a high degree of integration can be realized.
  • 9A1 to 9C2 are cross-sectional views in the channel width direction of the transistors 842, 843, 844, 845, 846, and 847, respectively.
  • the transistor 843, the transistor 845, and the transistor 847 each have the S-channel structure described above. However, without limitation thereto, the transistor 843, the transistor 845, and the transistor 847 may not have an S-channel structure.
  • FIG. 10 is a block diagram showing a configuration example of a storage device.
  • a memory device 100 illustrated in FIG. 10 includes a memory cell array (Memory Cell Array) 110, a peripheral circuit 111, a control circuit (Control Circuit) 112, the semiconductor device 10, and power switches (PSW) 141 and 142.
  • each circuit, each signal, and each voltage can be appropriately discarded as needed.
  • other circuits or other signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1 and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • the signal CLK is a clock signal.
  • the signals CE, GW and the signal BW are control signals.
  • the signal CE is a chip enable signal
  • the signal GW is a global write enable signal
  • the signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • the signal WDA is write data
  • the signal RDA is read data.
  • Signals PON1 and PON2 are power gating control signals.
  • the signals PON1 and PON2 may be generated by the control circuit 112.
  • the control circuit 112 is a logic circuit having a function of controlling the overall operation of the storage device 100. For example, the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine an operation mode (for example, a write operation or a read operation) of the storage device 100. Alternatively, control circuit 112 generates a control signal of peripheral circuit 111 such that this operation mode is performed.
  • the memory cell array 110 includes a plurality of memory cells (MC) 130 and a plurality of wirings WL, NWL, BL, and BLB.
  • the plurality of memory cells 130 are arranged in a matrix.
  • the memory cells 130 in the same row are electrically connected to the wirings WL, NWL in the row.
  • the wirings WL and NWL are respectively word lines, and the wirings BL and BLB are a pair of bit lines for transmitting complementary data.
  • the wiring BLB is a bit line to which data obtained by inverting the logic of BL is input, and may be referred to as a complementary bit line or an inverted bit line.
  • the memory cell 130 has two types of memory SMC and memory NVM.
  • the SMC is a memory circuit capable of storing 1-bit complementary data.
  • the NVM is a memory circuit capable of storing complementary data of n bits (n is an integer larger than 1), and can hold data for a long time even in a power-off state.
  • the semiconductor device 10 has a function of generating a negative voltage (V BG ) and applying it to the memory cell array 110 through the wiring BGL.
  • V BG is applied to the back gate of the transistor used for NVM.
  • WAKE has a function of controlling the input of CLK to the semiconductor device 10. For example, when a signal at H level is supplied to WAKE, the signal CLK is input to the semiconductor device 10, and the semiconductor device 10 generates V BG .
  • the description of Embodiment 1 can be referred to for the details of the semiconductor device 10.
  • the SMC and NVM are electrically connected by a local bit line pair (wiring LBL, LBLB).
  • the wiring LBL is a local bit line for the wiring BL
  • the wiring LBLB is a local bit line for the wiring BLB.
  • the SMC and the NVM are electrically connected by the lines LBL and LBLB.
  • Memory cell 130 has a circuit LPC.
  • the LPC is a local precharge circuit for precharging the line LBL and the line LBLB.
  • the LPC control signal is generated by the peripheral circuit 111.
  • Peripheral circuit 111 is a circuit for writing data to and reading data from memory cell array 110.
  • the peripheral circuit 111 has a function of driving the wirings WL, NWL, BL, and BLB.
  • the peripheral circuit 111 includes a row decoder (Row Decorder) 121, a column decoder (Column Decorder) 122, a row driver (Row Driver) 123, a column driver (Column Driver) 124, an input circuit (Input Cir.) 125, and an output circuit Output Circuit 126.
  • the row decoder 121 and the column decoder 122 have a function of decoding the signal ADDR.
  • the row decoder 121 is a circuit for specifying a row to be accessed
  • the column decoder 122 is a circuit for specifying a column to be accessed.
  • the row driver 123 has a function of selecting the wirings WL and NWL of the row designated by the row decoder 121. Specifically, the row driver 123 has a function of generating a signal for selecting the wirings WL and NWL.
  • the column driver 124 has a function of writing data to the memory cell array 110, a function of reading data from the memory cell array 110, a function of holding the read data, a function of precharging the wiring BL and the wiring BLB, and the like.
  • the input circuit 125 has a function of holding the signal WDA.
  • the data held by the input circuit 125 is output to the column driver 124.
  • the output data of the input circuit 125 is data to be written to the memory cell array 110.
  • Data (Dout) read from the memory cell array 110 by the column driver 124 is output to the output circuit 126.
  • the output circuit 126 has a function of holding Dout.
  • the output circuit 126 outputs the held data to the outside of the storage device 100.
  • the data to be output is the signal RDA.
  • the PSW 141 has a function of controlling the supply of VDD to circuits (peripheral circuits 115) other than the memory cell array 110.
  • the PSW 142 has a function of controlling the supply of the VHM to the row driver 123.
  • the high power supply voltage of the storage device 100 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to make the wiring NWL high, and is higher than VDD.
  • the signal PON1 controls the on / off of the PSW 141
  • the signal PON2 controls the on / off of the PSW 142.
  • the number of power supply domains to which VDD is supplied is one, but it may be plural. In this case, a power switch may be provided for each power supply domain.
  • FIG. 11 shows a circuit configuration example of the memory cell 130.
  • the SMC is electrically connected to the wiring BL, the wiring BLB, the wiring LBL, the wiring LBLB, the wiring VHH, and the wiring VLL.
  • SMC has a circuit configuration similar to that of a CMOS type (6-transistor type) SRAM cell, and has transistors Tld1, Tld2, Tdr1, Tdr2, Tac1, Tac2.
  • the transistors Tld1 and Tld2 are load transistors (pull-up transistors), the transistors Tdr1 and Tdr2 are drive transistors (pull-down transistors), and the transistors Tac1 and Tac2 are access transistors (transfer transistors).
  • the conduction state between the wiring BL and the wiring LBL is controlled by the transistor Tac1.
  • the conduction state between the wiring BLB and the wiring LBLB is controlled by the transistor Tac2.
  • the on / off of the transistors Tac1 and Tac2 is controlled by the potential of the wiring WL.
  • the transistors Tld1 and Tdr1 constitute an inverter, and the transistors Tld2 and Tdr2 constitute an inverter.
  • the input terminals of these two inverters are respectively electrically connected to the other output terminal, and a latch circuit is configured. Power supply voltages are supplied to the two inverters by the wires VHH and VLL.
  • NVM NVM
  • the NVM shown in FIG. 11 has n (n is an even number of 2 or more) NMC.
  • the n NMCs are electrically connected to different interconnects NWL.
  • n NMCs are electrically connected to one wiring VCS.
  • codes such as [0] and [1] are used, and in order to distinguish n wires NWL, codes such as _0 and _1 are used.
  • the NMC is a memory circuit (also referred to as a memory cell) capable of holding 1-bit data.
  • the NMC has a circuit configuration similar to that of a dynamic random access memory (DRAM) memory cell having one transistor and one capacitive element.
  • the NMC has a transistor Tr1 and a capacitive element Cs.
  • the capacitive element Cs functions as a storage capacitor of the NMC.
  • the wiring VCS is a power supply line for the storage capacitance of the NMC, and GND is input here.
  • the gate (first gate) of the transistor Tr1 is electrically connected to the wiring NWL.
  • One of the source and the drain of the transistor Tr1 is electrically connected to the wiring LBL (or the wiring LBLB).
  • the first terminal of the capacitive element Cs is electrically connected to the other of the source and the drain of the transistor Tr1, and the second terminal of the capacitive element Cs is electrically connected to the VCS.
  • the transistor Tr1 has a second gate.
  • the second gate of the transistor Tr1 is electrically connected to the wiring BGL.
  • the wiring BGL is a signal line to which a signal for controlling the potential of the second gate of the transistor Tr1 is input, or a power supply line to which a constant potential is input.
  • the threshold voltage of the transistor Tr1 can be controlled by the potential of the wiring BGL. As a result, the transistor Tr1 can be prevented from being normally on.
  • NVM shown in FIG. 11 is a circuit diagram in the case where a folding type is applied as a layout method of memory cells. The folded memory cell will be described again with reference to FIG. 14 described later.
  • the retention time of the NMC can be extended.
  • the extremely low off-state current means, for example, that the off-state current per 1 ⁇ m of the channel width is 100 zA (zepto amps) or less.
  • the smaller the off-state current, the more preferable. Therefore, the standardized off-state current is preferably 10 zA / ⁇ m or less, or 1 zA / ⁇ m or less, and more preferably 10 yA (yoctamps) / ⁇ m or less.
  • 1zA is 1 ⁇ 10 ⁇ 21 A
  • 1yA is 1 ⁇ 10 ⁇ 24 A.
  • the retention time of the NMC can be extended, and the NMC can be used as a non-volatile memory circuit.
  • the number (n) of NMCs is preferably a multiple of eight. That is, the number of bits of data that can be held by NVM is preferably a multiple of eight.
  • the memory cell 130 can handle data in units of one byte (8 bits), one word (32 bits), half words (16 bits), and the like.
  • the LPC is electrically connected to the line PCL and the line VPC.
  • the line PCL is a signal line for supplying a signal for controlling the precharge operation of the lines LBL and LBLB.
  • the wiring VPC is a power supply line for supplying a precharge voltage.
  • the LPC includes transistors Teq1, Tpc1, and Tpc2. Gates of the transistors Teq1, Tpc1, and Tpc2 are electrically connected to the wiring PCL.
  • the transistor Teq1 controls conduction between the lines LBL and LBLB.
  • the transistor Tpc1 controls a conduction state between the wiring LBL and the wiring VPC.
  • the transistor Tpc2 controls conduction between the wiring LBLB and the wiring VPC.
  • the transistors Teq1, Tpc1, and Tpc2 are n-channel transistors, but they may be p-channel transistors. Alternatively, it is not necessary to provide Teq1 in the LPC. In this case, the transistors Tpc1 and Tpc2 may be either n-channel transistors or p-channel transistors. Alternatively, LPC can be configured with only the transistor Teq1. Also in this case, the transistor Teq1 may be an n-channel transistor or a p-channel transistor. The LPC including the transistor Teq1 performs precharging of the wiring LBL and the wiring LBLB by smoothing the potentials of the wiring LBL and the wiring LBLB.
  • Peripheral circuit 111 has a function of supplying a potential to various power supply lines (interconnects VHH, VLL, and VPC) provided in memory cell array 110. Therefore, when the PSW 141 is turned off and the supply of the VDD to the peripheral circuit 111 is stopped, the supply of the potential to the power supply lines is also stopped.
  • various power supply lines interconnects VHH, VLL, and VPC
  • FIG. 12 shows an operation example in which the data writing method is the write-through method.
  • the data read operation a method is selected in which one NMC in NVM is selected, data of the selected NMC is amplified by SMC, and the data is written in BL and BLB.
  • VDDM is a power supply line provided in the storage device 100 for VDD supply.
  • the PSW 141 controls the supply of VDD to VDDM.
  • the waveforms represented by dotted lines indicate that the potential is indeterminate.
  • the low level (L level) of the wiring such as VDDM is GND.
  • the high level (H level) of PCL and WL is VDD
  • the high level of NWL_0-NWL_ [n-1] is VHM.
  • the high level of NWL_0-NWL_ [n-1] is VHM because it is assumed that the threshold voltage of the transistor Tr1 is higher than that of the other transistors such as the transistor Tac1.
  • VDD the high level of NWL_0-NWL_ [n-1] can be VDD, as long as writing and reading of NVM data are possible.
  • the storage device 100 may not have the PSW 142 for VHM (see FIG. 10).
  • the power gating operation of the storage device 100 will be described.
  • the storage device 100 is in a power off period during which the supply of VDD is cut off.
  • the storage device 100 is a power on period during which VDD is supplied.
  • the PSW 141 When the PSW 141 is turned off at t0, the potential of the VDDM falls and eventually becomes GND. Since the supply of VDD to the peripheral circuit 111 is cut off, WL, NWL_0-NWL_ [n-1], PCL, and VPC also become GND. When PSW 141 is turned on at t1, VDDM is charged, and eventually its potential rises to VDD. t1-t2 is the time required for power supply recovery. Further, in conjunction with turning on and off the PSW 141, the PSW 142 may also be turned on and off.
  • an initialization operation for initializing the storage device 100 is performed. Specifically, VPC, VHH and VLL are set to VDD / 2.
  • the bit line pair (BL, BLB) and the local bit line pair (LBL, LBLB) are each precharged to VDD / 2.
  • Precharging of the bit line pair is performed by the column driver 124, and precharging of the local bit line pair is performed by the LPC.
  • PCL a high level (H level)
  • the transistors Teq1, Tpc1, and Tpc2 are turned on, and precharging of LBL and LBLB and smoothing of the potential are performed.
  • the column driver 124 brings the bit line pair into the floating state from the precharged state. Further, the local bit line pair is brought from the precharged state to the floating state by LPC. This is done by changing PCL from H level to L level.
  • data DA1 is written to the bit line pair by column driver 124.
  • BL is VDD
  • BLB is GND.
  • NWL_0 is set to H level to turn on the transistor Tr1 of NMC [1].
  • VHH is set to VDD and VLL is set to GND, so that SMC becomes active.
  • NWL_1 is selected, the WL of the write target row is set to the H level to turn on the transistors Tac1 and Tac2. Note that WL may be set to H level at the timing of setting NWL_1 to H level.
  • the data DA1 is written to the local bit line pair.
  • SMC since SMC is active, data DA1 is written to SMC.
  • the transistor Tr1 of the NMC [1] to be written in the NVM is on, the data DA1 is also written to the NMC [1].
  • L level is set. With WL at L level, the SMC and the bit line pair become nonconductive. When this state is reached, NWL_1 is set to L level, and NMC [1] is returned to the non-selected state.
  • Non-Access (NON-ACCESS) At t4-t5, the storage device 100 is in the non-access state where there is no access request from the host device.
  • PCL is at H level
  • WL and NWL_0-NWL_ [n-1] are at L level.
  • VPC, VHH and VLL are VDD / 2.
  • the bit line pair and the local bit line pair are precharged to VDD / 2.
  • SMC does not need to be operated, so by setting VHH and VLL to VDD / 2, the leakage current of SMC can be reduced.
  • the power consumption of the entire storage device 100 can be effectively reduced.
  • the storage device 100 performs an operation for the read access request of the host device.
  • data necessary for processing of the host device is stored in NMC [1] of NVM.
  • the column driver 124 brings the bit line pair to the floating state from the precharged state, and the LPC brings the local bit line pair to the floating state from the precharged state.
  • NWL_1 is set to H level to turn on the transistor Tr1 of NMC [1].
  • Data DA1 is written to the local bit line pair.
  • VHH is set to VDD and VLL is set to GND to activate SMC.
  • SMC functions as a differential amplifier circuit to amplify data DA1 of the local bit line pair.
  • WL is set to H level to write data DA1 of the local bit line pair to the bit line pair.
  • the data DA1 written to the bit line pair is read by the column driver 124.
  • the end operation of the read operation is the same as that of the write operation, and is an operation for setting the initialization operation and the non-access state.
  • PCL is transited to H level to start precharging of the local bit line pair, but this timing is not limited to the example of FIG. In a period from when NWL_1 goes to L level to when WL goes to H level, PCL may be raised to start precharging of the local bit line pair.
  • the local bit line pair is fixed at VDD / 2 by keeping the PCL at the H level in the non-access state, but the PCL is set to the L level to set the local bit line pair. It may be in a floating state. In this case, at the start of the write operation and the read operation, first, PCL may be changed from the L level to the H level to precharge the local bit line pair.
  • the NVM transistor Tr1 can be an OS transistor, and the other transistors can be, for example, a Si transistor or the like.
  • the memory cell array 110 can have a device structure in which a circuit including an OS transistor is stacked on a circuit including an Si transistor. An example of the device structure of the memory cell array 110 is schematically shown in FIG.
  • the memory cell array 110B is stacked on the memory cell array 110A.
  • the memory cell array 110A is provided with SMC and LPC in a matrix.
  • NVMs are provided in a matrix on the memory cell array 110B.
  • the memory cell array 110A constitutes a memory unit A having a high response speed
  • the memory cell array 110B constitutes a memory unit B for long-term storage of data.
  • the capacity and size of the memory cell array 110 can be increased.
  • the area per bit of the memory cell 130 can be further reduced as compared with the memory cell of the CMOS type SRAM.
  • the memory cell array 110B configured by NVM is highly compatible with CMOS circuits as compared to other nonvolatile memories such as flash memory, MRAM (magnetoresistive random access memory) and PRAM (phase change random access memory).
  • Flash memory requires a high voltage to drive. Since the MRAM and PRAM are current driven memories, elements and circuits for current driving are required.
  • the NVM operates by on / off control of the transistor Tr1. That is, NVM is a circuit composed of voltage-driven transistors in the same manner as a CMOS circuit, and can be driven at a low voltage. Therefore, it is easy to incorporate the processor and the storage device 100 into one chip. Also, the storage device 100 can reduce the area per bit without degrading the performance. In addition, the storage device 100 can reduce power consumption. Further, since the storage device 100 can store data even in the power-off state, power gating of the storage device 100 is possible.
  • SRAMs are used for standard processor on-chip cache memories.
  • SRAM has the disadvantages that it consumes power even during standby and that it is difficult to increase the capacity.
  • the standby power consumption of on-chip cache memory reaches 80% of the ratio of the average power consumption of the entire processor.
  • the storage device 100 is a RAM in which the disadvantages of the SRAM are eliminated while taking advantage of the advantage of the SRAM that reading and writing are fast. Therefore, applying the storage device 100 to the on-chip cache memory is useful for reducing the power consumption of the entire processor.
  • the storage device 100 is suitable for a cache memory or the like because the storage device 100 has a small area per bit and can easily be increased in capacity.
  • FIGS. 14 to 15 show an example in which NVM stores 8-bit data (NVM has NMC [0] to NMC [7]).
  • the circuit diagram shown in FIG. 14 is an example in which a folded type is applied as a layout method of the memory cell 130.
  • NMC [0] to NMC [7] are provided on the region where SMC and LPC are formed.
  • the NMC is classified into one connected to the wiring LBL and one connected to the wiring LBLB.
  • the memory cell 130 outputs data to the wiring LBL or the wiring LBLB in accordance with the change in the potential of the wiring NWL. For example, in the case where read data is output to the wiring LBL, the distance between the wiring LBL and the wiring LBL can be reduced, whereby the read data to be supplied to the wiring LBL can be reduced as noise to the wiring LBLB.
  • the circuit diagram shown in FIG. 15 is an example in which an open type is applied as a layout method of the memory cell 130.
  • the NMC is composed of one transistor and one capacitive element.
  • the NMC is classified into one connected to the wiring LBL and one connected to the wiring LBLB.
  • two NMCs appear to be connected to one interconnect NWL, but one of the two NMCs is connected to an adjacent memory cell 130.
  • the NMC can be highly integrated, and the capacity of data that can be stored in the storage device 100 can be increased compared to other layout methods.
  • the circuit diagram shown in FIG. 16 is an example in which a twin cell type is applied as a layout method of the memory cell 130.
  • NMC is composed of two transistors and two capacitive elements. That is, the NMC has two complementary memory cells.
  • the twin-cell memory cell 130 treats complementary data held in two memory cells as one bit.
  • the NMC can hold complementary data for a long time by providing a pair of memory cells. Since the NMC holds the complementary data, the SMC can function as a differential amplifier circuit when reading the complementary data held by the NMC. Therefore, the twin-cell type can perform highly reliable read operation even if the voltage difference between the voltage held by one of the pair of memory cells and the voltage held by the other of the pair of memory cells is small.
  • FIG. 17 illustrates an example of a cross-sectional view of the storage device 100.
  • the memory device 100 illustrated in FIG. 17 includes a layer L1, a layer L2, a layer L3, and a layer L4 stacked in order from the bottom.
  • the layer L1 includes the transistor M1, the substrate 300, the element isolation layer 301, the insulator 302, the plug 310, and the like.
  • the layer L2 includes an insulator 303, a wiring 320, an insulator 304, a plug 311, and the like.
  • the layer L3 includes an insulator 214, an insulator 216, a transistor Tr1, a plug 312, an insulator 282, a wiring 321, and the like.
  • the first gate of the transistor Tr1 has a function as a wiring NWL
  • the second gate of the transistor Tr1 has a function as a wiring BGL.
  • FIG. 22 shows an example in which an OS transistor is used as the transistor Tr1.
  • the layer L4 includes a capacitor Cs, a plug 313, a wiring LBL, and the like.
  • the capacitive element Cs includes the conductor 322, the conductor 323, and the insulator 305.
  • FIG. 18A is a cross-sectional view of the transistor M1 in the channel length direction
  • the right side of FIG. 18A is a cross-sectional view of the transistor M1 in the channel width direction.
  • the transistor M1 is provided over the substrate 300 and is separated from other adjacent transistors by the element separation layer 301.
  • the element isolation layer 301 silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like can be used.
  • oxynitride refers to a compound having a higher content of oxygen than nitrogen
  • nitrided oxide refers to a compound having a higher content of nitrogen than oxygen.
  • a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI (Silicon On Insulator) substrate, or the like can be used as the substrate 300.
  • a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a bonded film, a paper containing a fibrous material, a base film, or the like may be used as the substrate 300.
  • a semiconductor element may be formed using a certain substrate and then transferred to another substrate.
  • a flexible substrate may be used as the substrate 300.
  • a method for providing a transistor on a flexible substrate there is a method in which the transistor is peeled off after being manufactured on a non-flexible substrate and transposed to the substrate 300 which is a flexible substrate. In that case, a release layer may be provided between the non-flexible substrate and the transistor.
  • the substrate 300 a sheet, a film, a foil, or the like in which fibers are woven may be used.
  • the substrate 300 may have stretchability.
  • the substrate 300 may have a property of returning to the original shape when bending or pulling is stopped. Or you may have the property which does not return to an original shape.
  • the thickness of the substrate 300 is, for example, 5 ⁇ m to 700 ⁇ m, preferably 10 ⁇ m to 500 ⁇ m, further preferably 15 ⁇ m to 300 ⁇ m.
  • the substrate 300 is thinned, the weight of the semiconductor device can be reduced.
  • the substrate 300 is made thin, it may have elasticity even when glass or the like is used, or may return to its original shape when bending or pulling is stopped. Therefore, an impact or the like applied to the semiconductor device over the substrate 300 due to a drop or the like can be alleviated. That is, a robust semiconductor device can be provided.
  • the substrate 300 which is a flexible substrate, for example, a metal, an alloy, a resin or glass, or a fiber thereof can be used.
  • the substrate 300 which is a flexible substrate has a lower coefficient of linear expansion, deformation due to the environment is preferably suppressed.
  • a material having a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 / K or less, 5 ⁇ 10 ⁇ 5 / K or less, or 1 ⁇ 10 ⁇ 5 / K or less is used.
  • the resin include polyester resin, polyolefin resin, polyamide (nylon, aramid etc.) resin, polyimide resin, polycarbonate resin, acrylic resin, polytetrafluoroethylene (PTFE) resin and the like.
  • PTFE polytetrafluoroethylene
  • the transistor M1 includes a channel formation region 352, an impurity region 353 and an impurity region 354 provided in the well 351, a conductive region 355 and a conductive region 356 provided in contact with the impurity region, and the channel formation region 352.
  • a gate insulator 358 provided and a gate electrode 357 provided on the gate insulator 358 are provided. Note that for the conductive regions 355 and 356, metal silicide or the like may be used.
  • the channel formation region 352 has a convex shape, and the gate insulator 358 and the gate electrode 357 are provided along the side surface and the top surface.
  • a transistor having such a shape is called a FIN transistor.
  • a convex portion is formed by processing a part of a semiconductor substrate is described; however, a semiconductor layer having a convex shape may be formed by processing an SOI substrate.
  • the transistor M1 may be either an n-channel transistor or a p-channel transistor, and a suitable transistor may be used depending on the circuit.
  • FIG. 18B An example in that case is shown in FIG.
  • the left side of FIG. 18B is a cross-sectional view of the transistor M1 in the channel length direction, and the right side of FIG. 18B is a cross-sectional view of the transistor M1 in the channel width direction.
  • a transistor M1 illustrated in FIG. 18B includes a channel formation region 362, a low concentration impurity region 371, a low concentration impurity region 372, a high concentration impurity region 363, and a high concentration impurity region 364 provided in the well 361;
  • a conductive region 365 and a conductive region 366 provided in contact with the concentration impurity region, a gate insulator 368 provided on the channel formation region 362, a gate electrode 367 provided on the gate insulator 368, and a gate Side wall insulating layers 369 and 370 provided on the side walls of the electrode 367 are provided.
  • metal silicide or the like may be used for the conductive regions 365 and 366.
  • the insulator 302 has a function as an interlayer insulator.
  • the insulator 302 preferably contains hydrogen.
  • the insulator 302 containing hydrogen has an effect of terminating a dangling bond of silicon and improving the reliability of the transistor M1.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like is preferably used.
  • the insulator 303 it is preferable to use a barrier film to which hydrogen or an impurity is not diffused from the substrate 300, the transistor M1, or the like to the region where the transistor Tr1 is provided.
  • a barrier film to which hydrogen or an impurity is not diffused from the substrate 300, the transistor M1, or the like to the region where the transistor Tr1 is provided.
  • silicon nitride formed by a CVD method can be used.
  • the diffusion of hydrogen into the metal oxide of the transistor Tr1 may reduce the characteristics of the metal oxide. Therefore, it is preferable to use a film which suppresses the diffusion of hydrogen between the transistor M1 and the transistor Tr1.
  • the film that suppresses the diffusion of hydrogen refers to a film with a small amount of desorption of hydrogen.
  • the amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS) or the like.
  • TDS thermal desorption spectroscopy
  • the amount of desorption of hydrogen in the insulator 324 is equivalent to the amount of desorption of hydrogen atoms per area of the insulator 303 in the range of 50 ° C. to 500 ° C. of the film surface temperature. In this case, it is 10 ⁇ 10 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • insulators 304, 214, and 282 it is preferable to use an insulator that suppresses copper diffusion or has a barrier property to oxygen and hydrogen.
  • silicon nitride can be used as an example of a film which suppresses diffusion of copper.
  • a metal oxide such as aluminum oxide may be used.
  • a silicon oxide film, a silicon oxynitride film, or the like can be used, for example.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxide oxynitride, hafnium oxide oxynitride, hafnium oxide nitride, etc. are used for the insulator 305 Just do it.
  • the insulator 305 may have a stacked structure of the above insulators.
  • a stacked structure of a material having high dielectric breakdown resistance such as silicon oxynitride and a high dielectric constant (high-k) material such as aluminum oxide may be used.
  • high-k high dielectric constant
  • the transistor Tr1 may be formed on the capacitive element Cs.
  • a cross-sectional view in that case is shown in FIG. In the cross-sectional view shown in FIG. 19, the cross-sectional view in FIG. 17 is different between the layer L3 and the layer L4.
  • the layer L3 includes a wiring 341 and a capacitor Cs.
  • the layer L4 includes a plug 331, a plug 332, a plug 333, a plug 334, a wiring 342, a wiring 343, a wiring LBL, an insulator 214, an insulator 216, an insulator 280, an insulator 282, and a transistor Tr1.
  • the transistor Tr1 By providing the capacitive element Cs under the transistor Tr1, the transistor Tr1 can be prevented from the process damage or the influence of hydrogen which is generated when the capacitive element Cs is formed.
  • regions where reference numerals and hatching patterns are not given are made of an insulator.
  • an insulator aluminum oxide, aluminum nitride oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide
  • An insulator containing one or more materials selected from tantalum oxide and the like can be used.
  • an organic resin such as a polyimide resin, a polyamide resin, an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resin can also be used.
  • FIG. 20 is a schematic top view of the storage device 100. As shown in FIG. The storage device 100 has a plurality of sub arrays 150. Each subarray 150 includes a memory cell array 110, a row driver 123 and a column driver 124. Further, power supply lines 151 are arranged so as to surround the plurality of subarrays 150.
  • the semiconductor device 10 can be disposed outside the memory cell. For example, it can be disposed under the power supply line 151 of FIG. By doing so, the area overhead of the storage device 100 can be reduced.
  • Embodiment 4 In this embodiment, a resistive element that can be used for a temperature sensor that detects temperature information given to the operation mode control circuit 17 of FIG. 1 will be described.
  • FIG. 21 is a top view of the resistance element 400.
  • the resistive element 400 includes a metal oxide 401, a conductor 402, and a conductor 403.
  • the metal oxide 401 has a serpentine portion in the top view.
  • the metal oxide 401 has a property that the resistivity changes with temperature.
  • the resistance element 400 can detect a temperature by flowing a current between the conductor 402 and the conductor 403 and measuring the resistance value of the metal oxide 401.
  • FIG. 22 is a schematic cross-sectional view of the case where the resistance element 400 is incorporated in the cross-sectional view of the memory device 100 shown in FIG.
  • a resistive element 400 is provided in the same layer L3 as the transistor Tr1 which is an OS transistor.
  • the metal oxide 401 used for the resistance element 400 is made of the same metal oxide as the metal oxide 230b used for the transistor Tr1.
  • the metal oxide 401 has too high resistivity as it is and does not function sufficiently as a resistance element. Therefore, after the metal oxide 401 is etched into the shape shown in FIG. 21, it is preferable that a process for lowering the resistivity be performed.
  • Examples of the above-described treatment for reducing the resistivity include plasma treatment with a rare gas such as He, Ar, Kr, or Xe.
  • a rare gas such as He, Ar, Kr, or Xe.
  • nitrogen oxide, ammonia, nitrogen, or hydrogen may be introduced into the above-described rare gas, and plasma treatment may be performed as a mixed gas.
  • treatment for reducing the resistivity treatment in which a film containing a large amount of hydrogen such as silicon nitride is provided in contact with the metal oxide 401 can be given.
  • the resistivity of the metal oxide 401 can be reduced by the addition of hydrogen.
  • the metal oxide 401 can have a resistivity at room temperature of 1 ⁇ 10 ⁇ 3 ⁇ cm or more and 1 ⁇ 10 4 ⁇ cm or less.
  • the resistive element 400 can accurately detect the temperature of the transistor Tr1. Further, since the resistance element 400 and the transistor Tr1 can be formed in the same step, the steps can be shortened as compared to the case where they are formed in separate steps.
  • the resistance element 400 may be formed over the layer L4.
  • metal oxides used for the OS transistor will be described.
  • the metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium or tin is contained. In addition, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.
  • the metal oxide is an In-M-Zn oxide containing indium, an element M and zinc.
  • the element M is aluminum, gallium, yttrium, tin or the like.
  • Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like.
  • the element M a plurality of the aforementioned elements may be combined in some cases.
  • FIGS. 23A, 23B, and 23C a preferable range of the atomic ratio of indium, the element M, and zinc contained in the metal oxide according to the present invention will be described.
  • the atomic ratio of oxygen is not described in FIGS. 23 (A), 23 (B), and 23 (C).
  • the terms of the atomic ratio of indium to the element M to zinc contained in the metal oxide are denoted by [In], [M] and [Zn].
  • a line with ( ⁇ 1 ⁇ ⁇ ⁇ 1), a line with an atomic ratio of [In]: [M]: [Zn] (1 + ⁇ ) :( 1- ⁇ ): 2, [In]: [M]
  • a line having an atomic ratio of [Zn] (1 + ⁇ ) :( 1- ⁇ ): 3
  • a plurality of phases may coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.).
  • grain boundaries may be formed between different crystal structures.
  • a region A illustrated in FIG. 23A illustrates an example of a preferable range of the atomic ratio of indium to the element M to zinc contained in the metal oxide.
  • the metal oxide can increase the carrier mobility (electron mobility) of the metal oxide by increasing the indium content. Therefore, a metal oxide having a high indium content has higher carrier mobility than a metal oxide having a low indium content.
  • the metal oxide of one embodiment of the present invention preferably has an atomic ratio represented by a region A in FIG. 23A, which is likely to have a layered structure with high carrier mobility and few crystal grain boundaries. .
  • a c-axis aligned crystalline (CAAC) -OS is easily formed in the region A, and an excellent metal oxide with high carrier mobility can be obtained.
  • the CAAC-OS has a c-axis orientation, and has a strained crystal structure in which a plurality of nanocrystals are connected in the a-b plane direction.
  • distortion refers to a portion where the orientation of the lattice arrangement changes between the region in which the lattice arrangement is aligned and the region in which another lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.
  • the nanocrystals are based on hexagons, but may not be regular hexagons and may be non-hexagonal. Moreover, distortion may have a lattice arrangement such as pentagon and heptagon.
  • a clear crystal grain boundary also referred to as a grain boundary
  • the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, or that the bonding distance between atoms is changed due to metal element substitution. It is thought that it is for.
  • CAAC-OS is a highly crystalline metal oxide.
  • CAAC-OS can not confirm clear crystal grain boundaries, so that it can be said that the decrease in electron mobility due to crystal grain boundaries does not easily occur.
  • CAAC-OS can also be said to be a metal oxide with few impurities or defects (such as oxygen vacancies). Therefore, the metal oxide having a CAAC-OS has stable physical properties. Therefore, a metal oxide having a CAAC-OS is resistant to heat and has high reliability.
  • the properties of the metal oxide can not be uniquely determined by the atomic ratio. Even with the same atomic ratio, the properties of the metal oxide may differ depending on the forming conditions. For example, in the case of forming a metal oxide film by a sputtering apparatus, a film having an atomic ratio different from the atomic ratio of the target is formed. Further, depending on the substrate temperature at the time of film formation, the [Zn] of the film may be smaller than the [Zn] of the target. Therefore, the illustrated region is a region showing an atomic ratio in which the metal oxide tends to have specific characteristics, and the boundaries of the regions A to C are not strict.
  • FIG. 24A is a top view of a semiconductor device having a transistor Tr1 and a transistor Tr1.
  • FIG. 24B is a cross-sectional view of a portion indicated by an alternate long and short dash line A1-A2 in FIG. 24A, and also a cross-sectional view of the transistor Tr1 in the channel length direction.
  • FIG. 24C is a cross-sectional view of a portion indicated by an alternate long and short dash line A3-A4 in FIG. 24A, and also a cross-sectional view in the channel width direction of the transistor Tr1.
  • some elements are omitted for clarity of the drawing.
  • the semiconductor device of one embodiment of the present invention includes a substrate 213, an insulator 215 over the substrate 213, a transistor Tr1 over the insulator 215, an insulator 280 over the transistor Tr1, and an insulator 282 over the insulator 280.
  • the substrate 213 may be the insulator 214.
  • the transistor Tr1 includes the conductor 205 and the insulator 216 on the insulator 215, the insulator 220 on the conductor 205 and the insulator 216, the insulator 222 on the insulator 220, and the insulator on the insulator 222.
  • metal oxide 230a on the insulator 224 a metal oxide 230b on the metal oxide 230a, a conductor 240a1 and a conductor 240a2 having a region in contact with the top surface of the metal oxide 230b, and the conductor 240a1 Of the barrier film 240b1, the barrier film 240b2 on the conductor 240a2, the side surface of the conductor 240a1, the side surface of the conductor 240a2, the side surface of the barrier film 240b1, the side surface of the barrier film 240b2, and the region in contact with the top surface of the metal oxide 230b
  • Metal oxide 230c, an insulator 250 on the metal oxide 230c, and an upper surface of the metal oxide 230b It has a conductor 260 which has a region overlapping with each other through the metal oxide 230c and the insulator 250, the insulator 241 on the conductor 260.
  • the insulator 216 has an opening, and the conductor 205a and the conductor
  • the end of the insulator 241, the end of the insulator 250, and the end of the metal oxide 230c are flush with each other, and the barrier film 240b1 and the barrier in the channel length direction. It is disposed on the film 240 b 2 and on the insulator 224 in one of the channel width directions.
  • the conductor 260 has a function as a first gate electrode.
  • the conductor 260 can have a stacked structure of the conductor 260a and the conductor 260b. Furthermore, the conductor 260 can also have a stacked structure of three or more layers. For example, oxidation of the conductor 260b can be prevented by forming the conductor 260a having a function of suppressing permeation of oxygen under the conductor 260b.
  • the conductor 260 preferably includes a metal having oxidation resistance. Alternatively, for example, a metal oxide conductor or the like may be used. Alternatively, for example, a multilayer structure including a conductive metal oxide may be used.
  • the insulator 250 has a function as a first gate insulator.
  • the conductor 240a1 and the conductor 240a2 also function as a source electrode or a drain electrode.
  • the conductor 240a1 and the conductor 240a2 can have a stacked structure with a conductor having a function of suppressing permeation of oxygen.
  • oxidation of the conductor 240a1 and the conductor 240a2 can be prevented by forming a conductor with a function of suppressing permeation of oxygen over the upper layer.
  • the conductor 240a1 and the conductor 240a2 include a metal having oxidation resistance.
  • a metal oxide conductor or the like may be used.
  • the barrier film 240b1 and the barrier film 240b2 have a function of suppressing permeation of impurities such as hydrogen and water and oxygen.
  • the barrier film 240b1 is on the conductor 240a1, and prevents the diffusion of oxygen to the conductor 240a1.
  • the barrier film 240 b 2 is on the conductor 240 a 2 to prevent diffusion of oxygen to the conductor 240 a 2.
  • the metal oxide 230b and the metal oxide 230c have a channel formation region. That is, the transistor Tr1 can control the resistances of the metal oxide 230b and the metal oxide 230c by the potential applied to the conductor 260. That is, by the potential applied to the conductor 260, conduction / nonconduction between the conductor 240a1 and the conductor 240a2 can be controlled.
  • the conductor 260 having the function of the first gate electrode is the whole of the metal oxide 230b and the metal oxide through the insulator 250 having the function of the first gate insulator. It is arranged to cover a part of 230c. Therefore, the whole of the metal oxide 230 b and a part of the metal oxide 230 c can be electrically surrounded by the electric field of the conductor 260 having a function as the first gate electrode.
  • the structure of the transistor that electrically surrounds the channel formation region by the electric field of the first gate electrode is referred to as a surrounded channel (s-channel) structure.
  • the metal oxide 230b and the metal oxide 230c sandwich the conductor 240a1 and the conductor 240a2 each having a function as a source electrode or a drain electrode, thereby forming a source.
  • the area in contact with the electrode or drain electrode can be increased. Accordingly, the contact area between the metal oxide 230b and the metal oxide 230c, and the conductor 240a1 and the conductor 240a2 is increased, which is preferable because the contact resistance is lowered.
  • a metal oxide which functions as a metal oxide semiconductor (hereinafter, also referred to as a metal oxide semiconductor) is preferably used.
  • silicon including strained silicon
  • germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium indium, an organic semiconductor, or the like may be used instead of the metal oxide.
  • a transistor using a metal oxide semiconductor has extremely low leakage current in a non-conduction state; thus, a semiconductor device with low power consumption can be provided.
  • a metal oxide semiconductor can be formed by a sputtering method or the like, the metal oxide semiconductor can be used for a transistor included in a highly integrated semiconductor device.
  • a transistor using a metal oxide semiconductor the electrical characteristics thereof are likely to fluctuate due to impurities and oxygen vacancies in the metal oxide semiconductor, which may deteriorate reliability.
  • hydrogen contained in a metal oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • oxygen vacancies in the metal oxide semiconductor is likely to be normally on. Therefore, it is preferable that oxygen vacancies in the metal oxide semiconductor be reduced as much as possible.
  • the metal oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium or tin is contained. In addition, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.
  • the metal oxide semiconductor is an In-M-Zn metal oxide containing indium, an element M, and zinc.
  • the element M is aluminum, gallium, yttrium, tin or the like.
  • Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like.
  • the element M a plurality of the aforementioned elements may be combined in some cases.
  • metal oxides having nitrogen may also be collectively referred to as metal oxides.
  • a metal oxide having nitrogen may be referred to as metal oxynitride.
  • each of In preferably contains more atoms than the element M.
  • the mobility of the transistor Tr1 is increased, and the carrier density is also increased.
  • controllability of the channel formation region is preferably high.
  • the metal oxide 230b and the metal oxide 230c it is preferable to use a metal oxide semiconductor of the same composition or a metal oxide semiconductor of a nearby composition.
  • the metal oxide 230 b and the metal oxide 230 c are preferably deposited using the same sputtering target member.
  • the metal oxide 230 b and the metal oxide 230 c are preferably deposited using a sputtering target member having substantially the same composition.
  • the metal oxide 230 b and the metal oxide 230 c are preferably deposited under substantially the same process conditions (e.g., a deposition temperature, a ratio of oxygen gas, and the like).
  • the metal oxide 230 b and the metal oxide 230 c may be deposited using sputtering target members having different compositions.
  • the metal oxide 230b and the metal oxide 230c can be obtained by appropriately adjusting the process conditions (for example, the film formation temperature, the ratio of oxygen gas, and the like) between the metal oxide 230b and the metal oxide 230c. It may be possible to deposit a metal oxide semiconductor of the same composition or a metal oxide semiconductor of a nearby composition. It may be preferable to use a metal oxide semiconductor having a composition close to that of the metal oxide 230b and the metal oxide 230c, but since the required thickness and function are different, the optimum film formation conditions may also be different.
  • the metal oxide 230b and the metal oxide 230c can be made close to each other.
  • the electron affinity of the metal oxide 230b and the electron affinity of the metal oxide 230c are equal or the difference is small.
  • the electron affinity of the metal oxide 230b and the electron affinity of the metal oxide 230c are equal to or smaller than each other. Accordingly, the interface state density of the metal oxide 230 b and the metal oxide 230 c can be reduced. By reducing the interface state density, it is possible to prevent the decrease in the on current of the transistor Tr1.
  • the electron affinity can be rephrased as the energy value Ec at the lower end of the conduction band.
  • the difference between Ec of the metal oxide 230b and Ec of the metal oxide 230c is preferably small, and is 0 eV or more and 0.15 eV or less, more preferably 0 V or more and 0.07 eV.
  • the electron affinity or Ec can be obtained from the ionization potential Ip, which is the difference between the vacuum level and the energy Ev at the top of the valence band, and the energy gap Eg.
  • the ionization potential Ip can be measured, for example, using an ultraviolet photoelectron spectroscopy (UPS) device.
  • the energy gap Eg can be measured, for example, using a spectroscopic ellipsometer.
  • processing damage may occur when the source electrode or the drain electrode is formed on the upper surface and the side surface of the metal oxide 230b. That is, defects due to processing damage may occur in the vicinity of the interface between the metal oxide 230b and the metal oxide 230c.
  • the metal oxide 230b and the metal oxide 230c may be metal oxide semiconductors having the same composition or metal oxide semiconductors having a composition nearby, so that the Ec of the metal oxide 230b and the metal oxide 230c can be used. Since the Ec difference is the same or smaller, the region in which the channel is formed is not only in the vicinity of the interface between the metal oxide 230b and the metal oxide 230c, but also functions as the metal oxide 230c and the first gate insulator. It is also formed in the vicinity of the interface with the insulator 250.
  • the influence of the vicinity of the interface between the metal oxide 230b having processing damage and the metal oxide 230c can be reduced. Further, after a metal oxide to be the metal oxide 230c and an insulator to be the insulator 250 having a function as a first gate insulator are stacked and formed, a metal oxide to be the metal oxide 230c and If the insulator to be the insulator 250 is processed to form the metal oxide 230c and the insulator 250, the vicinity of the interface between the metal oxide 230c and the insulator 250 is affected by the damage caused by the processing. It becomes good without receiving.
  • the reliability of the transistor Tr1 can be improved. Further, since the whole of the metal oxide 230b and a part of the metal oxide 230c are surrounded by the electric field of the conductor 260, the current (off current) at the time of non-conduction can be reduced.
  • the transistor includes a region in which the conductor 260 having a function as a first gate electrode and the conductor 240a1 and the conductor 240a2 having a function as a source electrode or a drain electrode overlap with each other. And the conductor 240a1, and the parasitic capacitance formed by the conductor 260 and the conductor 240a2.
  • the transistor has a barrier film 240 b 1 in addition to the insulator 250 and the metal oxide 230 c between the conductor 260 and the conductor 240 a 1 to reduce the parasitic capacitance. Can.
  • the barrier film 240b2 is provided between the conductor 260 and the conductor 240a2, whereby the parasitic capacitance can be reduced. .
  • the transistor is a transistor with excellent frequency characteristics.
  • the transistor has the above-described structure, for example, when a potential difference occurs between the conductor 260 and the conductor 240a1 or 240a2 during operation of the transistor, the conductor 260 and the conductor 240a1 Alternatively, leakage current between the conductor 240a2 and the conductor 240a2 can be reduced or prevented.
  • the conductor 205 is provided in an opening formed in the insulator 216.
  • a conductor 205a is formed in contact with the inner wall of the opening of the insulator 216, and a conductor 205b is formed further inside.
  • the conductor 205 has a function as a second gate electrode.
  • the conductor 205 can also be a multilayer film including a conductor having a function of suppressing permeation of oxygen. For example, by using the conductor 205a as a conductor having a function of suppressing permeation of oxygen, a decrease in conductivity due to oxidation of the conductor 205b can be prevented.
  • the insulator 220, the insulator 222, and the insulator 224 function as a second gate insulating film.
  • the potential applied to the conductor 205 can control the threshold voltage of the transistor.
  • FIG. 25 is a top view of a semiconductor device having a transistor Tr1 having a configuration different from that of FIG.
  • the end of the conductor 260 is flush with the end of the insulator 250 and the end of the metal oxide 230c.
  • the insulator 241 is disposed so as to cover the top and side surfaces of the conductor 260, and is disposed in contact with the end of the insulator 250 and the end of the metal oxide 230c.
  • the insulator 241 is disposed on the barrier film 240b1 and the barrier film 240b2, and is in contact with the end of the barrier film 240b1, the end of the conductor 240a1, the end of the barrier film 240b2, and the end of the conductor 240a2. Will be placed. Furthermore, the insulator 241 is disposed on the insulator 224.
  • the insulator includes, for example, an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, and the like.
  • the electrical characteristics of the transistor can be stabilized by surrounding the transistor with an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen.
  • an insulator having a function of adsorbing an impurity such as hydrogen or suppressing permeation of oxygen may be used.
  • an insulator having a function of supplying oxygen may be used for the insulator 202, the insulator 215, the insulator 241, and the insulator 282, an insulator having a function of supplying oxygen may be used.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium
  • An insulator containing lanthanum, neodymium, hafnium or tantalum may be used in a single layer or a stack.
  • the insulator 202, the insulator 215, the insulator 241, and the insulator 282 aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like may be used.
  • the insulator 202, the insulator 215, the insulator 241, and the insulator 282 preferably include aluminum oxide.
  • oxygen can be added to the insulator to be the base layer of the insulator.
  • the insulator 216, the insulator 220, the insulator 224, and the insulator 250 for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,
  • An insulator containing lanthanum, neodymium, hafnium or tantalum may be used in a single layer or a stack.
  • silicon oxide, silicon oxynitride, or silicon nitride is preferably included.
  • the insulator 224 and the insulator 250 preferably include an insulator with a high dielectric constant.
  • the insulator 224 and the insulator 250 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, silicon and hafnium It is preferable to have oxynitride or nitride including silicon and hafnium.
  • the insulator 224 and the insulator 250 preferably have a stacked-layer structure of silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant.
  • Silicon oxide and silicon oxynitride are thermally stable, and thus, when combined with an insulator with a high dielectric constant, a stacked structure with a thermally stable high dielectric constant can be obtained.
  • silicon contained in silicon oxide or silicon oxynitride is mixed into the oxide 203 by providing aluminum oxide, gallium oxide, or hafnium oxide in contact with the oxide 203. Can be suppressed.
  • silicon oxide or silicon oxynitride is in contact with the oxide 203, whereby aluminum oxide, gallium oxide, or hafnium oxide, and silicon oxide or silicon oxynitride can be used.
  • Trap centers may be formed at the interface. The trap center may be able to shift the threshold voltage of the transistor in the positive direction by capturing electrons.
  • the insulator 280 preferably includes an insulator with a low relative dielectric constant.
  • the insulator 280 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having vacancies Alternatively, it is preferable to have a resin or the like.
  • the insulator 280 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with carbon and nitrogen, or silicon oxide with voids. It is preferable to have a laminated structure of and a resin.
  • Silicon oxide and silicon oxynitride are thermally stable, and thus, when combined with a resin, a stacked structure with a thermally stable and low dielectric constant can be obtained.
  • the resin include organic resins such as polyimide resin, polyamide (nylon, aramid etc.) resin, acrylic resin, siloxane resin, epoxy resin, phenol resin, polycarbonate resin, polyester resin, polyolefin resin and the like.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen can be used as the barrier film 240b1 and the barrier film 240b2.
  • the barrier film 240b1, the barrier film 240b2, the barrier film 240b1, and the barrier film 240b2 can prevent excess oxygen in the insulator 280 from diffusing into the conductor 240a1 and the conductor 240a2.
  • barrier film 240b1 and the barrier film 240b2 for example, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, metal oxide such as hafnium oxide or tantalum oxide, silicon nitride oxide Alternatively, silicon nitride or the like may be used.
  • Conductor 260a, the conductor 260b, the conductor 205a, the conductor 205b, the conductor 240a1, and the conductor 240a2 aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium,
  • a material containing one or more metal elements selected from vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium and the like can be used.
  • a semiconductor with high electrical conductivity typically a polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a conductive material containing a metal element contained in a metal oxide applicable to the oxide 203 and oxygen may be used.
  • a conductive material containing the above-described metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • a plurality of conductive layers formed of the above materials may be stacked.
  • a stacked structure in which a material containing a metal element described above and a conductive material containing oxygen are combined may be used.
  • a stacked structure in which the material containing the metal element described above and the conductive material containing nitrogen are combined may be used.
  • a stacked structure in which the above-described material containing a metal element, the conductive material containing oxygen, and the conductive material containing nitrogen are combined may be used.
  • a stacked structure in which a material containing a metal element described above as the gate electrode and a conductive material containing oxygen are preferably used.
  • a conductive material containing oxygen may be provided on the channel formation region side.
  • FIG. 26A shows a top view of the substrate 611 before the dicing process is performed.
  • a semiconductor substrate also referred to as a "semiconductor wafer”
  • a plurality of circuit regions 612 are provided on the substrate 611.
  • the circuit region 612 can be provided with the semiconductor device described in the above embodiment or the like.
  • a separation line also referred to as a “dicing line”
  • the chip 615 including the circuit region 612 can be cut from the substrate 611.
  • An enlarged view of the chip 615 is shown in FIG.
  • a conductive layer or a semiconductor layer may be provided in the separation region 613.
  • ESD that may occur in the dicing step can be alleviated and yield reduction in the dicing step can be prevented.
  • the dicing step is carried out while flowing pure water having a reduced specific resistance into the cutting portion for the purpose of cooling the substrate, removing shavings, preventing charging, etc.
  • the amount of pure water used can be reduced.
  • the productivity of the semiconductor device can be enhanced.
  • a material having a band gap of 2.5 eV or more and 4.2 eV or less, preferably 2.7 eV or more and 3.5 eV or less is preferably used.
  • the accumulated charge can be discharged slowly, so that rapid movement of the charge due to ESD can be suppressed and electrostatic breakdown can be made less likely to occur.
  • the electronic component is also referred to as a semiconductor package or a package for an IC.
  • the electronic component has a plurality of standards and names depending on the terminal extraction direction and the shape of the terminal.
  • the electronic component is completed by combining the semiconductor device described in the above embodiment and components other than the semiconductor device in an assembly process (post process).
  • a “back surface grinding step” is performed to grind the back surface (the surface on which the semiconductor device and the like are not formed) of the element substrate (step S1) ).
  • a “back surface grinding step” is performed to grind the back surface (the surface on which the semiconductor device and the like are not formed) of the element substrate (step S1) ).
  • a “dicing process” is performed to separate the element substrate into a plurality of chips (step S2).
  • a "die bonding step” is performed in which the separated chips are individually picked up and bonded onto the lead frame (step S3).
  • the bonding between the chip and the lead frame in the die bonding step is appropriately selected according to the product, such as bonding with a resin or bonding with a tape.
  • the chip may be bonded onto the interposer substrate instead of the lead frame.
  • a "wire bonding step” is performed to electrically connect the lead of the lead frame and the electrode on the chip with a metal thin wire (wire) (step S4).
  • a silver wire or a gold wire can be used for the thin metal wire.
  • wire bonding can use ball bonding or wedge bonding.
  • the wire-bonded chip is subjected to a “sealing process (molding process)” in which the chip is sealed with an epoxy resin or the like (step S5).
  • a sealing process molding process
  • the inside of the electronic component is filled with a resin, and the circuit portion incorporated in the chip and the wire connecting the chip and the lead can be protected from mechanical external force, and characteristics due to moisture and dust Degradation (reliability degradation) can be reduced.
  • a “lead plating process” is performed to plate the leads of the lead frame (step S6).
  • the plating process can prevent rusting of the leads, and can be more reliably soldered later when provided on a printed circuit board.
  • a "forming step” of cutting and forming the lead is performed (step S7).
  • a "marking process” is performed to print (mark) the surface of the package (step S8).
  • an electronic component is completed through an “inspection step” (step S9) for checking whether the appearance shape is good or bad, and the like.
  • FIG. 27B is a schematic perspective view of the completed electronic component.
  • FIG. 27B illustrates a schematic perspective view of a quad flat package (QFP) as an example of the electronic component.
  • An electronic component 650 illustrated in FIG. 27B illustrates a lead 655 and a semiconductor device 653.
  • the semiconductor device 653, the memory device or the semiconductor device described in the above embodiment can be used.
  • the electronic component 650 illustrated in FIG. 27B is provided, for example, on a printed substrate 652.
  • a plurality of such electronic components 650 are combined and electrically connected on the printed circuit board 652 to complete a substrate 654 provided with the electronic components.
  • the completed substrate 654 is used for an electronic device or the like.
  • the semiconductor device, the display device, and / or the memory device of one embodiment of the present invention can be mounted on various electronic devices.
  • the electronic devices include, for example, television devices, desktop or notebook personal computers, monitors for computers, etc., large-sized game machines such as digital signage (Digital Signage), pachinko machines, etc.
  • digital signage Digital Signage
  • pachinko machines large-sized game machines
  • electronic devices equipped with screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound reproduction devices, etc. may be mentioned.
  • the electronic device of one embodiment of the present invention may have an antenna. By receiving the signal with the antenna, display of images, information, and the like can be performed on the display portion.
  • the antenna may be used for contactless power transmission.
  • the electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow rate, humidity, inclination, vibration, smell or infrared light.
  • the electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function of displaying date or time, etc., a function of executing various software (programs), wireless communication A function, a function of reading a program or data recorded in a recording medium, or the like can be provided. 28 and 29 show an example of the electronic device.
  • the robot 2100 shown in FIG. 28A includes an arithmetic unit 2110, an illuminance sensor 2101, a microphone 2102, an upper camera 2103, a speaker 2104, a display 2105, a lower camera 2106, an obstacle sensor 2107, and a movement mechanism 2108.
  • a humanoid robot is shown as an example.
  • the semiconductor device and / or the storage device can be used for the arithmetic device 2110, the illuminance sensor 2101, the upper camera 2103, the lower camera 2106, the obstacle sensor 2107, and the like.
  • the microphone 2102 has a function of detecting the user's speech and environmental sounds.
  • the speaker 2104 has a function of emitting sound.
  • the robot 2100 can communicate with the user using the microphone 2102 and the speaker 2104.
  • the display 2105 has a function of displaying various information.
  • the robot 2100 can display information desired by the user on the display 2105.
  • the display device can be used for the display 2105.
  • the display 2105 may have a touch panel.
  • the upper camera 2103 and the lower camera 2106 have a function of imaging the periphery of the robot 2100.
  • the obstacle sensor 2107 can detect the presence or absence of an obstacle in the traveling direction when the robot 2100 moves forward with bipedal walking.
  • the robot 2100 can recognize the surrounding environment and move safely by using the upper camera 2103, the lower camera 2106 and the obstacle sensor 2107. In the case where the robot 2100 is used in a large temperature change environment, an increase in power consumption can be suppressed by using the semiconductor device, the memory device, the display device, and / or the electronic component. .
  • FIG. 28B is an external view showing an example of a car.
  • the automobile 2980 has a camera 2981 and the like.
  • the automobile 2980 includes various sensors such as an infrared radar, a millimeter wave radar, a laser radar, and the like.
  • the automobile 2980 can analyze an image captured by the camera 2981, determine a surrounding traffic condition such as the presence or absence of a pedestrian, and perform automatic driving.
  • an increase in power consumption can be suppressed by using the semiconductor device, the storage device, the display device, and / or the electronic component for the camera 2981.
  • FIG. 28C shows a state in which the portable electronic device 2130 is caused to perform simultaneous interpretation in communication between a plurality of people who speak different languages from each other.
  • the portable electronic device 2130 has a microphone, a speaker, and the like, and has a function of recognizing the user's speech and translating it into the language spoken by the other party.
  • the semiconductor device, the storage device, and / or the electronic component can be used for the arithmetic device of the portable electronic device 2130.
  • FIG. 29A is an external view showing an aircraft 2120.
  • the flying body 2120 includes an arithmetic unit 2121, a propeller 2123, and a camera 2122, and has a function of autonomously flying.
  • the semiconductor device, the storage device, and / or the electronic component can be used for the arithmetic device 2121 and the camera 2122.
  • the flying body 2120 is used in a large temperature change environment, an increase in power consumption can be suppressed by using the semiconductor device, the storage device, and / or the electronic component.
  • FIG. 29 (B-1) and 29 (B-2) show examples of usage of the flying object 2120.
  • FIG. 29 (B-1) the aircraft 2120 can be used to transport the cargo 2124.
  • FIG. 29 (B-2) a container 2125 in which a pesticide is sealed is mounted on a flying object 2120, and the flying object 2120 can be used for spraying a pesticide.
  • the CAC-OS is one configuration of a material in which, for example, an element constituting a metal oxide is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof.
  • an element constituting a metal oxide is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof.
  • an element constituting a metal oxide is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof.
  • an element constituting a metal oxide is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof.
  • the metal oxide preferably contains at least indium.
  • One or more selected from may be included.
  • CAC-OS in the In-Ga-Zn oxide is an indium oxide (hereinafter referred to as InO).
  • InO indium oxide
  • X1 X1 is a real number greater than 0
  • In X2 Zn Y2 O Z2 X2, Y2, and Z2 are real numbers greater than 0
  • GaO X3 X3 is a real number greater than 0
  • Ga X4 Zn Y4 O Z4 X4, Y4, and Z4 a real number greater than 0) to.
  • the material becomes mosaic by separate into, mosaic InO X1, or in X2 Zn Y2 O Z2 is configured uniformly distributed in the film (hereinafter, cloud Also referred to.) A.
  • CAC-OS is a composite metal oxide having a structure in which a region in which GaO X3 is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component are mixed.
  • the ratio of the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region, It is assumed that the concentration of In is higher than that in the region 2.
  • IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. Representative examples are represented by InGaO 3 (ZnO) m1 (m1 is a natural number), or In (1 + x0) Ga ( 1-x0) O 3 (ZnO) m0 (-1 ⁇ x0 ⁇ 1, m0 is an arbitrary number) Crystalline compounds are mentioned.
  • the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure.
  • the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane.
  • CAC-OS relates to the material composition of metal oxides.
  • the CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material configuration including In, Ga, Zn, and O, and nanoparticles composed mainly of In in some components.
  • region observed in shape says the structure currently disperse
  • CAC-OS does not include a stacked structure of two or more types of films different in composition. For example, a structure including two layers of a film containing In as a main component and a film containing Ga as a main component is not included.
  • the CAC-OS is partially observed in the form of nanoparticles having the metal element as a main component, and partially having In as a main component.
  • region observed in particle form says the structure currently each disperse
  • the CAC-OS can be formed, for example, by sputtering under the condition that the substrate is not heated.
  • one or more selected from an inert gas (typically, argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas.
  • the flow rate ratio of the oxygen gas to the total flow rate of the film forming gas at the time of film formation is preferably as low as possible.
  • the flow rate ratio of the oxygen gas is 0% to 30%, preferably 0% to 10%. .
  • CAC-OS has a feature that a clear peak is not observed when it is measured using a ⁇ / 2 ⁇ scan by the Out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods.
  • XRD X-ray diffraction
  • the CAC-OS has a ring-like high luminance region and a plurality of bright spots in the ring region. A point is observed. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and in the cross-sectional direction.
  • the CAC-OS has a structure different from the IGZO compound in which the metal element is uniformly distributed, and has different properties from the IGZO compound. That is, CAC-OS is phase-separated into a region in which GaO X3 or the like is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component, and a region in which each element is a main component Has a mosaic-like structure.
  • the region whose main component is In X2 Zn Y2 O Z2 or InO X1 is a region whose conductivity is higher than the region whose main component is GaO X3 or the like. That is, when carriers flow in a region mainly containing In X 2 Zn Y 2 O Z 2 or InO X 1 , conductivity as a metal oxide is exhibited. Therefore, high field-effect mobility ( ⁇ ) can be realized by distributing the region mainly containing In X 2 Zn Y 2 O Z 2 or InO X 1 in the form of a cloud in the metal oxide.
  • the region in which GaO X3 or the like is the main component is a region in which the insulating property is higher than the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component. That is, a region in which GaO X 3 or the like is a main component is distributed in the metal oxide, so that the leakage current can be suppressed and a good switching operation can be realized.
  • CAC-OS when CAC-OS is used for a semiconductor element, the insulating property caused by GaO X3 and the like and the conductivity caused by In X 2 Zn Y 2 O Z 2 or InO X 1 act complementarily to achieve high results.
  • the on current (I on ) and high field effect mobility ( ⁇ ) can be realized.
  • CAC-OS is most suitable for various semiconductor devices including displays.
  • the on current refers to the drain current when the transistor is in the on state.
  • the on state (sometimes abbreviated as on) is a state in which the voltage (V G ) between the gate and the source is equal to or higher than the threshold voltage (V th ) in the n-channel transistor unless otherwise noted.
  • V G is lower than or equal to V th .
  • the on current of an n-channel transistor refers to the drain current when V G is greater than or equal to V th .
  • the on current of the transistor may depend on the voltage (V D ) between the drain and the source.
  • the off current refers to the drain current when the transistor is in the off state.
  • the OFF state (sometimes referred to as OFF), unless otherwise specified, the n-channel type transistor, V G is lower than V th state, the p-channel type transistor, V G is higher than V th state
  • the off-state current of an n-channel transistor refers to the drain current when V G is lower than V th .
  • the off current of the transistor may depend on V G. Accordingly, the off current of the transistor is less than 10 -21 A, and may refer to the value of V G to off-current of the transistor is less than 10 -21 A are present.
  • the off-state current of the transistor may depend on V D.
  • the off-state current unless otherwise specified, has an absolute value of V D of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V. , 12 V, 16 V, or 20 V may represent an off current.
  • the off current in V D used in a semiconductor device or the like including the transistor may be expressed.
  • X and Y each denote an object (eg, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like).
  • an element for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, or the like
  • an element capable of electrically connecting X and Y
  • X and Y are connected without an element, a light emitting element, a load, etc.
  • an element for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, or the like
  • an element for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, or the like
  • the switch is turned on (on) or turned off (off) and has a function of controlling whether current flows or not.
  • the switch has a function of selecting and switching a path through which current flows.
  • X and Y are electrically connected, the case where X and Y are directly connected shall be included.

Abstract

The present invention provides a semiconductor device which maintains data without being influenced by a change in temperature. The present invention is provided with a band gap reference circuit, a voltage reference circuit, a voltage control oscillator, a negative voltage generating circuit, and an operation mode control circuit, and the voltage reference circuit has a first transistor which has a metal oxide in a semiconductor layer. The band gap reference circuit has a function of outputting a first voltage and a first current. The present invention has a function of outputting a threshold voltage of the first transistor by providing the first transistor with the first current . The voltage control oscillator has a function of switching a potential difference between the threshold voltage and the first voltage to a first frequency. The negative voltage generating circuit has a function of generating a first negative voltage according to the first frequency. The present invention has a function of stabilizing the threshold voltage by providing a back gate of the first transistor with the first negative voltage.

Description

半導体装置、記憶装置、及び表示装置Semiconductor device, storage device, and display device
　本発明の一形態は半導体装置、記憶装置、及び表示装置に関する。 One embodiment of the present invention relates to a semiconductor device, a memory device, and a display device.
　また、本発明に本発明の一形態は、物、方法、又は、製造方法に関する。又は、本発明の一態様は、プロセス、マシン、マニュファクチャ、又は、組成物（コンポジション・オブ・マター）に関する。本発明の一態様は、その駆動方法、又は、その作製方法に関する。 In addition, one aspect of the present invention relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). One aspect of the present invention relates to a driving method thereof or a manufacturing method thereof.
　なお、本明細書等において半導体装置とは、半導体特性を利用することで機能しうる装置全般を指す。記憶装置、表示装置、電気光学装置、蓄電装置、半導体回路及び電子機器は、半導体装置を有する場合がある。 Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. The memory device, the display device, the electro-optical device, the power storage device, the semiconductor circuit, and the electronic device may include the semiconductor device.
　トランジスタに適用可能な半導体薄膜としてシリコン系半導体材料が広く知られているが、その他の材料として酸化物半導体が注目されている。酸化物半導体としては、一例として、酸化インジウム、酸化亜鉛などの一元系金属の酸化物のみでなく、多元系金属の酸化物も知られている。多元系金属の酸化物の中でも、特にＩｎ−Ｇａ−Ｚｎ酸化物（以下、ＩＧＺＯとも呼ぶ）に関する研究が盛んに行われている。 Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have attracted attention as other materials. As an oxide semiconductor, not only oxides of single-component metals such as indium oxide and zinc oxide but also oxides of multi-component metals are known as an example. Among oxides of multi-element metals, in particular, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.
　ＩＧＺＯに関する研究により、酸化物半導体において、単結晶でも非晶質でもないＣＡＡＣ（ｃ−ａｘｉｓ　ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ）構造及びｎｃ（ｎａｎｏｃｒｙｓｔａｌｌｉｎｅ）構造が見出された（非特許文献１乃至非特許文献３参照）。非特許文献１及び非特許文献２では、ＣＡＡＣ構造を有する酸化物半導体を用いてトランジスタを作製する技術も開示されている。さらに、ＣＡＡＣ構造及びｎｃ構造よりも結晶性の低い酸化物半導体でさえも微小な結晶を有することが非特許文献４及び非特許文献５に示されている。 According to research on IGZO, a c-axis aligned crystalline (CAAC) structure and an nc (nanocrystalline) structure which are neither single crystal nor amorphous were found in an oxide semiconductor (see Non-Patent Documents 1 to 3) . Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Further, Non-Patent Documents 4 and 5 show that even oxide semiconductors with lower crystallinity than the CAAC structure and the nc structure have minute crystals.
　さらに、ＩＧＺＯを活性層として用いたトランジスタは極めて低いオフ電流を持ち（非特許文献６参照）、その特性を利用したＬＳＩ及びディスプレイが報告されている（非特許文献７及び非特許文献８参照）。 Furthermore, a transistor using IGZO as an active layer has an extremely low off current (see Non-Patent Document 6), and LSIs and displays utilizing the characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8) .
　また、オフ電流が極めて低いトランジスタをメモリセルに用いる構成の記憶装置が特許文献１に開示されている。 Further, Patent Document 1 discloses a memory device having a configuration in which a transistor with extremely low off-state current is used for a memory cell.
特開２０１１−１１９６７４号公報JP 2011-119674 A
　本発明の一形態は、新規な半導体装置を提供することを課題の一とする。また、本発明の一形態は、温度変化に影響されずにデータが保持される半導体装置を提供することを課題の一とする。また、本発明の一形態は、消費電力の増加が抑制された半導体装置を提供することを課題の一とする。 An object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device in which data is held without being affected by a temperature change. Another object of one embodiment of the present invention is to provide a semiconductor device in which an increase in power consumption is suppressed.
　なお、複数の課題の記載は、互いの課題の存在を妨げるものではない。なお、本発明の一態様は、これらの課題の全て解決する必要はない。また、列記した以外の課題が、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、これらの課題も、本発明の一形態の課題となり得る。 Note that the descriptions of a plurality of subjects do not disturb the existence of each other. Note that one embodiment of the present invention does not have to solve all of these problems. In addition, problems other than those listed are naturally apparent from the description in the specification, the drawings, the claims, and the like, and these problems may also be problems of one embodiment of the present invention.
　本発明の一形態は、バンドギャップリファレンス回路、電圧参照回路、電圧制御発振器、及び負電圧生成回路を有する半導体装置である。電圧参照回路は、半導体層に金属酸化物を有する第１トランジスタを有している。バンドギャップリファレンス回路は、第１電圧、及び第１電流を出力することができる。第１トランジスタに第１電流を与えることで、第１トランジスタの閾値電圧を出力することができる。電圧制御発振器は、閾値電圧と、第１電圧との電圧差を第１周波数に変換することができる。負電圧生成回路は、第１周波数によって第１負電圧を生成することができる。第１トランジスタのバックゲートは、第１負電圧が与えられることによって第１トランジスタの閾値電圧が第１電圧になるように調整する機能を有する半導体装置である。 One embodiment of the present invention is a semiconductor device including a band gap reference circuit, a voltage reference circuit, a voltage control oscillator, and a negative voltage generation circuit. The voltage reference circuit comprises a first transistor having a metal oxide in the semiconductor layer. The band gap reference circuit can output a first voltage and a first current. By supplying the first current to the first transistor, the threshold voltage of the first transistor can be output. The voltage controlled oscillator may convert a voltage difference between the threshold voltage and the first voltage to a first frequency. The negative voltage generation circuit may generate the first negative voltage according to the first frequency. The back gate of the first transistor is a semiconductor device having a function of adjusting the threshold voltage of the first transistor to be the first voltage by receiving the first negative voltage.
　上記形態において、バンドギャップリファレンス回路は、さらに第２電圧を出力することができる。電圧制御発振器は、閾値電圧と、第２電圧との電位差を第２周波数に変換することができる。負電圧生成回路は、第２周波数によって第２負電圧を生成することができる。第１トランジスタのバックゲートには、第１負電圧、又は第２負電圧のいずれかが与えられる半導体装置が好ましい。 In the above embodiment, the band gap reference circuit can further output the second voltage. The voltage controlled oscillator can convert the potential difference between the threshold voltage and the second voltage into the second frequency. The negative voltage generation circuit may generate the second negative voltage according to the second frequency. It is preferable that the back gate of the first transistor be a semiconductor device to which either a first negative voltage or a second negative voltage is applied.
　上記形態において、半導体装置は、動作モード制御回路を有している。第１トランジスタのバックゲートには、動作モード制御回路によって選択される第１負電圧、又は第２負電圧のいずれかが与えられる半導体装置が好ましい。 In the above embodiment, the semiconductor device includes an operation mode control circuit. It is preferable that the back gate of the first transistor be a semiconductor device to which either the first negative voltage or the second negative voltage selected by the operation mode control circuit is applied.
　上記形態において、半導体装置を有する記憶装置であって、記憶装置は、複数のメモリセルを有している。メモリセルは、それぞれ半導体層に金属酸化物を有する第２トランジスタを有している。第２トランジスタのバックゲートには、第１負電圧、又は第２負電圧のいずれかが与えられる記憶装置が好ましい。 In the above embodiment, the memory device includes a semiconductor device, and the memory device includes a plurality of memory cells. Each memory cell includes a second transistor having a metal oxide in the semiconductor layer. It is preferable that a memory device in which either the first negative voltage or the second negative voltage is supplied to the back gate of the second transistor.
　上記形態において、半導体装置を有する表示装置であって、表示装置は、記憶装置と、表示パネルとを有している。表示パネルは、複数の画素を有している。画素は、それぞれ半導体層に金属酸化物を有する第３トランジスタを有している。第３トランジスタのバックゲートには、第１負電圧、又は第２負電圧のいずれかが与えられる表示装置が好ましい。 In the above embodiment, the display device includes a semiconductor device, and the display device includes a memory device and a display panel. The display panel has a plurality of pixels. Each pixel has a third transistor having a metal oxide in the semiconductor layer. It is preferable that the back gate of the third transistor be provided with either the first negative voltage or the second negative voltage.
　上記形態において、負電圧生成回路は、第４トランジスタ、第５トランジスタ、第６トランジスタ、第７トランジスタ、第８トランジスタ、第１容量素子、第２容量素子、第１入力端子、第２入力端子、出力端子、第１配線、及び第２配線を有している。第４乃至第７トランジスタは、半導体層に金属酸化物を有している。第１入力端子は、第４トランジスタのゲート、第５トランジスタのゲート、及び第８トランジスタのゲートと電気的に接続される。第２入力端子は、第６トランジスタのゲート、及び第７トランジスタのゲートと電気的に接続される。第１配線は、第４トランジスタのソース又はドレインの一方と電気的に接続される。第２配線は、第５トランジスタのソース又はドレインの一方と電気的に接続される。第４のトランジスタのソース又はドレインの他方は、第６のトランジスタのソース又はドレインの一方、及び第１容量素子の電極の一方と電気的に接続される。第５のトランジスタのソース又はドレインの他方は、第７のトランジスタのソース又はドレインの一方、及び第１容量素子の電極の他方と電気的に接続される。第６のトランジスタのソース又はドレインの他方は、第８のトランジスタのソース又はドレインの一方、及び第２容量素子の電極の一方と電気的に接続される。第８のトランジスタのソース又はドレインの他方は、第２配線と電気的に接続される。第７のトランジスタのソース又はドレインの他方は、第２容量素子の電極の他方、第４乃至第８トランジスタのそれぞれのバックゲート、及び出力端子に接続される半導体装置が好ましい。 In the above embodiment, the negative voltage generation circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitive element, a second capacitive element, a first input terminal, a second input terminal, It has an output terminal, a first wiring, and a second wiring. The fourth to seventh transistors each include a metal oxide in the semiconductor layer. The first input terminal is electrically connected to the gate of the fourth transistor, the gate of the fifth transistor, and the gate of the eighth transistor. The second input terminal is electrically connected to the gate of the sixth transistor and the gate of the seventh transistor. The first wiring is electrically connected to one of the source and the drain of the fourth transistor. The second wiring is electrically connected to one of the source and the drain of the fifth transistor. The other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the sixth transistor and one of the electrodes of the first capacitive element. The other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the seventh transistor and the other of the electrode of the first capacitive element. The other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the eighth transistor and one of the electrodes of the second capacitor. The other of the source and the drain of the eighth transistor is electrically connected to the second wiring. It is preferable that the other of the source and the drain of the seventh transistor be a semiconductor device connected to the other of the electrodes of the second capacitor, the back gate of each of the fourth to eighth transistors, and the output terminal.
　上記形態において、第１配線には、第３電圧が与えられる。第２配線には、第３電圧より小さな第４電位が与えられる。第１入力端子には、第１周波数の信号が与えられる。第２入力端子には、第１周波数の反転信号が与えられることで第４乃至第８トランジスタのそれぞれのバックゲート、及び出力端子に負電圧を出力する半導体装置が好ましい。 In the above aspect, the third voltage is applied to the first wiring. A fourth potential smaller than the third voltage is applied to the second wiring. The first input terminal is supplied with a signal of the first frequency. It is preferable that the second input terminal be a semiconductor device which outputs a negative voltage to the back gate of each of the fourth to eighth transistors and the output terminal by receiving an inverted signal of the first frequency.
　本発明の一形態により、新規な半導体装置を提供することができる。また、発明の一形態により、温度変化に影響されずにデータが保持される半導体装置を提供することができる。また、本発明の一形態により、消費電力の増加が抑制された半導体装置を提供することができる。 According to one embodiment of the present invention, a novel semiconductor device can be provided. Further, according to one embodiment of the present invention, a semiconductor device in which data is held without being affected by a temperature change can be provided. According to one embodiment of the present invention, a semiconductor device in which an increase in power consumption is suppressed can be provided.
　なお、これらの効果の記載は、他の効果の存在を妨げるものではない。なお、本発明の一態様は、これらの効果の全てを有する必要はない。なお、これら以外の効果は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の効果を抽出することが可能である。 Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not have to have all of these effects. Note that effects other than these are naturally apparent from the description of the specification, drawings, claims and the like, and other effects can be extracted from the descriptions of the specification, drawings, claims and the like. It is.
半導体装置の構成例を示す回路図。FIG. 2 is a circuit diagram showing a configuration example of a semiconductor device. 半導体装置の構成例を示す回路図。FIG. 2 is a circuit diagram showing a configuration example of a semiconductor device. 半導体装置の構成例を示す回路図。FIG. 2 is a circuit diagram showing a configuration example of a semiconductor device. 表示装置の構成例を示すブロック図。FIG. 2 is a block diagram showing an example of the configuration of a display device. 画素の構成例を示す回路図。FIG. 2 is a circuit diagram showing a configuration example of a pixel. トランジスタの構成例を示す断面図。FIG. 7 is a cross-sectional view showing a configuration example of a transistor. トランジスタの構成例を示す断面図。FIG. 7 is a cross-sectional view showing a configuration example of a transistor. トランジスタの構成例を示す断面図。FIG. 7 is a cross-sectional view showing a configuration example of a transistor. トランジスタの構成例を示す断面図。FIG. 7 is a cross-sectional view showing a configuration example of a transistor. 記憶装置の構造例を示すブロック図。FIG. 2 is a block diagram showing an example of the structure of a storage device. メモリセルの構成例を示す回路図。FIG. 2 is a circuit diagram showing an example of the configuration of a memory cell. 半導体装置の動作例を示すタイミングチャート。5 is a timing chart showing an operation example of a semiconductor device. メモリセルアレイの構造例を示すブロック図。FIG. 2 is a block diagram showing an example of the structure of a memory cell array. メモリセルの構造例を示す回路図。FIG. 2 is a circuit diagram showing an example of the structure of a memory cell. メモリセルの構造例を示す回路図。FIG. 2 is a circuit diagram showing an example of the structure of a memory cell. メモリセルの構造例を示す回路図。FIG. 2 is a circuit diagram showing an example of the structure of a memory cell. 記憶装置の構成例を示す断面図。FIG. 7 is a cross-sectional view showing a configuration example of a memory device. トランジスタの構成例を示す断面図。FIG. 7 is a cross-sectional view showing a configuration example of a transistor. 記憶装置の構成例を示す断面図。FIG. 7 is a cross-sectional view showing a configuration example of a memory device. 記憶装置の構成例を示す上面模式図。The upper surface schematic diagram which shows the structural example of a memory | storage device. 抵抗素子の構成例を示す上面図。FIG. 5 is a top view showing an example of the configuration of a resistance element. 抵抗素子を有する記憶装置の構成例を示す断面図。FIG. 7 is a cross-sectional view showing a configuration example of a memory device having a resistance element. 金属酸化物の原子数比の範囲を説明する図。The figure explaining the range of the atomic ratio of a metal oxide. トランジスタの構成例を示す上面図及び断面図。7A and 7B are a top view and a cross-sectional view illustrating a configuration example of a transistor. トランジスタの構成例を示す上面図及び断面図。7A and 7B are a top view and a cross-sectional view illustrating a configuration example of a transistor. 半導体ウエハの上面図。The top view of a semiconductor wafer. 半導体装置の作製工程を示すフローチャート図及び斜視図。5A and 5B are a flowchart and a perspective view illustrating a manufacturing process of a semiconductor device. 電子機器の例を示す斜視図。FIG. 2 is a perspective view showing an example of an electronic device. 電子機器の例を示す斜視図。FIG. 2 is a perspective view showing an example of an electronic device.
　本発明の実施の形態について、図面を用いて詳細に説明する。但し、本発明は以下の説明に限定されず、本発明の趣旨及びその範囲から逸脱することなくその形態及び詳細を様々に変更し得ることは当業者であれば容易に理解される。従って、本発明は以下に示す実施の形態の記載内容に限定して解釈されるものではない。 Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that various changes can be made in the form and details without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.
　なお、以下に説明する発明の構成において、同一部分又は同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する。また、同様の機能を指す場合には、ハッチパターンを同じくし、特に符号を付さない場合がある。 Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description of such portions is not repeated. In addition, when referring to the same function, the hatch pattern may be the same and no reference numeral may be given.
　なお、本明細書で説明する各図において、各構成の大きさ、層の厚さ、又は領域は、明瞭化のために誇張されている場合がある。よって、必ずしもそのスケールに限定されない。 Note that in the drawings described herein, the size of each component, the thickness of a layer, or the area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale.
　なお、本明細書中において、高電源電圧をＨレベル（又はＶＤＤ）、低電源電圧をＬレベル（又はＧＮＤ）と呼ぶ場合がある。 In this specification, a high power supply voltage may be referred to as an H level (or V DD ), and a low power supply voltage may be referred to as an L level (or GND).
　また、本明細書は、以下の実施の形態を適宜組み合わせることが可能である。また、１つの実施の形態の中に、複数の構成例が示される場合は、構成例を適宜組み合わせることが可能である。 Further, in this specification, the following embodiments can be combined as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment, it is possible to appropriately combine the configuration examples.
　本明細書等において、金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）とは、広い意味での金属の酸化物である。金属酸化物は、酸化物絶縁体、酸化物導電体（透明酸化物導電体を含む）、酸化物半導体などに分類される。例えば、トランジスタの半導体層に金属酸化物を用いた場合、当該金属酸化物を酸化物半導体と呼称する場合がある。また、ＯＳトランジスタと記載する場合においては、金属酸化物又は酸化物半導体を有するトランジスタと換言することができる。また、本明細書等において、窒素を有する金属酸化物も金属酸化物と総称する場合がある。 In the present specification and the like, the metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, and the like. For example, in the case where a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In the case of describing an OS transistor, the transistor can be put in another way as a transistor having a metal oxide or an oxide semiconductor. In the present specification and the like, metal oxides having nitrogen may also be generically referred to as metal oxides.
（実施の形態１）
〈〈半導体装置１０〉〉
　図１は、本発明の一形態である半導体装置の構成例を示す回路図である。半導体装置１０は、記憶装置、表示装置、又は電子機器などの使用環境に合わせて、記憶装置、表示装置又は電子機器などが有するトランジスタの閾値電圧をフィードバックループによって制御することができる。 Embodiment 1
<< semiconductor device 10 >>
FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device which is an embodiment of the present invention. The semiconductor device 10 can control a threshold voltage of a transistor included in the memory device, the display device, the electronic device, or the like by a feedback loop in accordance with a use environment of the memory device, the display device, the electronic device, or the like.
　半導体装置１０は、バンドギャップリファレンス回路１１、電圧参照回路１２、選択回路１３、差分検出回路１４、電圧制御発振器１５、負電圧生成回路１６、及び動作モード制御回路１７を有する。 The semiconductor device 10 includes a band gap reference circuit 11, a voltage reference circuit 12, a selection circuit 13, a difference detection circuit 14, a voltage control oscillator 15, a negative voltage generation circuit 16, and an operation mode control circuit 17.
　バンドギャップリファレンス回路１１は、出力端子１１ａ、出力端子１１ｂ、及び出力端子１１ｃを有する。出力端子１１ａには、第１電流が出力され、出力端子１１ｂには、第１電位が出力され、出力端子１１ｃには、第２電位が出力される。 The band gap reference circuit 11 has an output terminal 11a, an output terminal 11b, and an output terminal 11c. The first current is output to the output terminal 11a, the first potential is output to the output terminal 11b, and the second potential is output to the output terminal 11c.
　電圧参照回路１２は、入力端子１２ａ、入力端子１２ｃ、入力端子１２ｄ、及び出力端子１２ｂを有する。電圧参照回路１２は、半導体層に金属酸化物を有する第１トランジスタを有する。第１トランジスタについては、図２（Ｂ）で詳細な説明をする。第１トランジスタは、バックゲートを有し、バックゲートは、入力端子１２ｃと電気的に接続される。第１トランジスタが入力端子１２ａから第１電流が与えられる場合、出力端子１２ｂは、第１トランジスタの閾値電圧を出力する。入力端子１２ｄは、配線ＲＳＴと電気的に接続される。配線ＲＳＴに与えられる信号が、第１トランジスタのバックゲート電位を初期化することができる。但し、入力端子１２ｄは、必ずしも設けなくてもよい。 The voltage reference circuit 12 has an input terminal 12a, an input terminal 12c, an input terminal 12d, and an output terminal 12b. The voltage reference circuit 12 includes a first transistor having a metal oxide in the semiconductor layer. The first transistor will be described in detail with reference to FIG. The first transistor has a back gate, and the back gate is electrically connected to the input terminal 12c. When the first transistor receives the first current from the input terminal 12a, the output terminal 12b outputs the threshold voltage of the first transistor. The input terminal 12 d is electrically connected to the wiring RST. The signal applied to the wiring RST can initialize the back gate potential of the first transistor. However, the input terminal 12d may not necessarily be provided.
　選択回路１３は、入力端子１３ａ、入力端子１３ｂ、入力端子１３ｄ、及び出力端子１３ｃを有する。入力端子１３ａは、出力端子１１ｂと電気的に接続され、入力端子１３ｂは、出力端子１１ｃと電気的に接続される。動作モード制御回路１７は、入力端子１３ｄと電気的に接続される。よって、選択回路１３は、動作モード制御回路１７が検知する温度に従い、入力端子１３ａに与えられる第１電位、又は入力端子１３ｂに与えられる第２電位のいずれかを出力端子１３ｃに出力する。なお、さらに細かく温度選択の条件を管理し、選択回路１３がそれぞれの温度に応じて異なる電位を出力してもよい。なお、動作モード制御回路１７は、温度を検知するための動作モード制御回路１７が温度センサを有する構成でもよい、又は、動作モード制御回路１７に温度センサが接続される構成でもよいし、又は、ＣＰＵなどから温度情報が与えられる構成でもよい。 The selection circuit 13 has an input terminal 13a, an input terminal 13b, an input terminal 13d, and an output terminal 13c. The input terminal 13a is electrically connected to the output terminal 11b, and the input terminal 13b is electrically connected to the output terminal 11c. The operation mode control circuit 17 is electrically connected to the input terminal 13d. Therefore, according to the temperature detected by the operation mode control circuit 17, the selection circuit 13 outputs either the first potential applied to the input terminal 13a or the second potential applied to the input terminal 13b to the output terminal 13c. The conditions for temperature selection may be managed more finely, and the selection circuit 13 may output different potentials according to the respective temperatures. Operation mode control circuit 17 may have a configuration in which operation mode control circuit 17 for detecting temperature has a temperature sensor, or a configuration in which a temperature sensor is connected to operation mode control circuit 17 may be used, or The configuration may be such that temperature information is given from a CPU or the like.
　差分検出回路１４は、第１トランジスタの閾値電圧、及び選択回路１３の出力電圧の電圧差を差分電圧として検出し出力する。差分検出回路１４は、アンプを用いることで容易に検出することができる。もしくは、差分検出回路１４は、アナログデジタル変換回路によって構成されてもよい。 The difference detection circuit 14 detects and outputs a difference between the threshold voltage of the first transistor and the output voltage of the selection circuit 13 as a difference voltage. The difference detection circuit 14 can be easily detected by using an amplifier. Alternatively, the difference detection circuit 14 may be configured by an analog-to-digital converter.
　電圧制御発振器１５は、入力される差分電圧を周波数に変換することができる。電圧制御発振器１５は、ＶＣＯ回路（Ｖｏｌｔａｇｅ　Ｃｏｎｔｒｏｌｌｅｄ　Ｏｓｃｉｌｌａｔｏｒ）などを用いて電圧から周波数に変換することが好ましい。電圧制御発振器１５の出力周波数は、入力される差分電圧の大きさに応じて出力周波数の大きさが制御される。 The voltage control oscillator 15 can convert the input differential voltage into a frequency. The voltage controlled oscillator 15 preferably converts voltage to frequency using a VCO circuit (Voltage Controlled Oscillator) or the like. The magnitude of the output frequency of the voltage control oscillator 15 is controlled in accordance with the magnitude of the input differential voltage.
　負電圧生成回路１６は、入力端子１６ａ、出力端子１６ｂ、レベルシフタ回路１６ｃ、及びチャージポンプ回路１６ｄを有する。レベルシフタ回路１６ｃには、入力端子１６ａを介して該出力周波数が入力周波数として与えられる。レベルシフタ回路１６ｃは、チャージポンプ回路１６ｄに与える入力周波数の振幅電圧を調整することができる。また、レベルシフタ回路１６ｃは、チャージポンプ回路１６ｄに与える正相信号、及び反転信号を生成することができる。チャージポンプ回路１６ｄは、与えられる入力周波数に応じて負電圧を生成することができる。 The negative voltage generation circuit 16 has an input terminal 16a, an output terminal 16b, a level shifter circuit 16c, and a charge pump circuit 16d. The output frequency is given as an input frequency to the level shifter circuit 16c via the input terminal 16a. The level shifter circuit 16c can adjust the amplitude voltage of the input frequency applied to the charge pump circuit 16d. Also, the level shifter circuit 16c can generate a positive phase signal and an inverted signal to be supplied to the charge pump circuit 16d. The charge pump circuit 16d can generate a negative voltage in accordance with the applied input frequency.
　チャージポンプ回路１６ｄが生成する負電圧は、電圧参照回路１２の入力端子１２ｃに与えることができる。よって、第１トランジスタの閾値電圧が選択回路１３の出力電圧と同じ電圧に収束するように、電圧参照回路１２が第１トランジスタのバックゲートに与える電圧を制御することができる。 The negative voltage generated by the charge pump circuit 16 d can be applied to the input terminal 12 c of the voltage reference circuit 12. Therefore, the voltage applied to the back gate of the first transistor can be controlled such that the threshold voltage of the first transistor converges to the same voltage as the output voltage of the selection circuit 13.
　一例として、記憶装置のメモリセル、又は表示装置の画素などに、半導体層が金属酸化物を有するトランジスタが用いられる場合、該トランジスタのバックゲートは、半導体装置１０が電圧で出力する信号ＶＢＧによって制御することができる。従って、記憶装置、又は表示装置が温度変化の大きな環境で使用される場合、該トランジスタのバックゲートに与えられる信号ＶＢＧは、動作モード制御回路１７によって選択された閾値電圧になるように該トランジスタの閾値電圧が調整される。よって、該トランジスタのオフ電流が低く保たれる。また、記憶装置が高温の環境で使用される場合に発生するデータの劣化、又は表示装置が高温の環境で使用される場合に発生する画素の表示不良を低減することができる。また、記憶装置、又は表示装置が、高温の環境で使用される場合に発生する消費電力、又は待機電力の増大を抑制することができる。 As an example, in the case where a transistor whose semiconductor layer includes a metal oxide is used for a memory cell of a memory device or a pixel of a display device, a back gate of the transistor is controlled by a signal VBG output from the semiconductor device 10 by voltage. can do. Therefore, when the storage device or the display device is used in a large temperature change environment, signal VBG applied to the back gate of the transistor is set to the threshold voltage selected by operation mode control circuit 17. The threshold voltage is adjusted. Thus, the off-state current of the transistor is kept low. In addition, deterioration of data which occurs when the storage device is used in a high temperature environment or display defects of pixels which occur when the display device is used in a high temperature environment can be reduced. In addition, it is possible to suppress an increase in power consumption or standby power generated when the storage device or the display device is used in a high temperature environment.
　図２（Ａ）は、バンドギャップリファレンス回路１１の構成例を示す回路図である。バンドギャップリファレンス回路１１は、バンドギャップリファレンス回路１１ｄ、及び基準電圧電流生成回路１１ｅを有する。バンドギャップリファレンス回路１１ｄは、出力端子に任意の電圧を出力することができる。一例として、バンドギャップリファレンス回路１１ｄは公知の回路を用いてもよい。また任意の電圧とは、一例として、常温（２５℃）における第１トランジスタの閾値電圧になるように設定されることが好ましい。但し、任意の電圧は限定されるものではなく、記憶装置、表示装置、又は電子機器などの使用環境に合わせて設定されることが好ましい。 FIG. 2A is a circuit diagram showing a configuration example of the band gap reference circuit 11. The band gap reference circuit 11 includes a band gap reference circuit 11 d and a reference voltage / current generation circuit 11 e. The band gap reference circuit 11d can output an arbitrary voltage to the output terminal. As an example, the band gap reference circuit 11d may use a known circuit. Further, it is preferable that the arbitrary voltage is set to be, for example, the threshold voltage of the first transistor at normal temperature (25 ° C.). However, the arbitrary voltage is not limited and is preferably set in accordance with the use environment of a storage device, a display device, an electronic device, or the like.
　基準電圧電流生成回路１１ｅは、アンプ３０、トランジスタ３１ａ乃至３１ｄ、抵抗素子３２ａ乃至３２ｃを有する。トランジスタ３１ａ乃至３１ｄはｐ型トランジスタを用いることが好ましい。また、アンプ３０は、ボルテージフォロワ接続を有していることが好ましい。アンプ３０の非反転入力端子には、バンドギャップリファレンス回路１１ｄの出力端子が電気的に接続される。反転入力端子には、アンプ３０の出力端子が電気的に接続される。 The reference voltage / current generation circuit 11e includes an amplifier 30, transistors 31a to 31d, and resistance elements 32a to 32c. The transistors 31a to 31d are preferably p-type transistors. The amplifier 30 preferably has a voltage follower connection. The output terminal of the band gap reference circuit 11 d is electrically connected to the non-inverted input terminal of the amplifier 30. The output terminal of the amplifier 30 is electrically connected to the inverting input terminal.
　アンプ３０の出力端子は、トランジスタ３１ａ乃至３１ｄのそれぞれのゲートと電気的に接続される。トランジスタ３１ａ乃至３１ｄのそれぞれのソースは配線ＶＤＤ１と接続され、カレントミラー回路を形成する。トランジスタ３１ａのドレインは、直列に接続された抵抗素子３２ａ乃至３２ｃと電気的に接続される。トランジスタ３１ｂのドレインは、直列に接続された抵抗素子３２ｂ及び３２ｃと電気的に接続される。トランジスタ３１ｃのドレインは、抵抗素子３２ｃと電気的に接続される。但し、カレントミラー回路はｎ型トランジスタで形成されてもよい。なお、同じ符号を有する抵抗素子は、同じ大きさの抵抗素子を表している。 The output terminal of the amplifier 30 is electrically connected to the gate of each of the transistors 31a to 31d. The sources of the transistors 31a to 31d are connected to the wiring VDD1 to form a current mirror circuit. The drain of the transistor 31a is electrically connected to the resistance elements 32a to 32c connected in series. The drain of the transistor 31b is electrically connected to the resistance elements 32b and 32c connected in series. The drain of the transistor 31c is electrically connected to the resistance element 32c. However, the current mirror circuit may be formed of an n-type transistor. In addition, the resistive element which has the same code represents the resistive element of the same magnitude | size.
　トランジスタ３１ａ乃至３１ｄは、同じチャネル長を有していることが好ましい。トランジスタ３１ａ乃至３１ｃは、さらに同じチャネル幅を有することでトランジスタ３１ａ乃至３１ｃに流れる電流の大きさを同じにすることができる。従って、抵抗値を変えることで任意の電圧を容易に生成することができる。 The transistors 31a to 31d preferably have the same channel length. The transistors 31a to 31c can have the same channel width to make the magnitudes of the currents flowing to the transistors 31a to 31c the same. Therefore, any voltage can be easily generated by changing the resistance value.
　一例として、トランジスタ３１ａが、直列に接続される抵抗素子３２ａ乃至３２ｃに電流を流すことでリファレンス電圧を生成することができる。該リファレンス電圧を反転入力端子に与えることでアンプ３０がボルテージフォロワとして機能する。異なる例として、トランジスタ３１ｂが、直列に接続された抵抗素子３２ｂ、及び３２ｃに電流を流すことで第１電圧を生成することができる。第１電圧は、出力端子１１ｂに出力される。さらに、異なる例として、トランジスタ３１ｃが、抵抗素子３２ｃに電流を流すことで第２電圧を生成することができる。第２電圧は、出力端子１１ｃに出力される。 As one example, the reference voltage can be generated by causing the transistor 31a to flow a current to the resistance elements 32a to 32c connected in series. The amplifier 30 functions as a voltage follower by applying the reference voltage to the inverting input terminal. As another example, the first voltage can be generated by causing the transistor 31 b to flow a current through the resistance elements 32 b and 32 c connected in series. The first voltage is output to the output terminal 11b. Furthermore, as another example, the transistor 31c can generate the second voltage by causing a current to flow through the resistor element 32c. The second voltage is output to the output terminal 11c.
　基準電圧電流生成回路１１ｅは、さらに、第１電流を生成するトランジスタ３１ｄを有する。但し、トランジスタ３１ｄのチャネル幅は、トランジスタ３１ａ乃至３１ｃと同じでもよいし、異なっていてもよい。トランジスタ３１ｄに流れる第１電流は、出力端子１１ａに出力される。 The reference voltage / current generation circuit 11e further includes a transistor 31d that generates a first current. However, the channel width of the transistor 31 d may be the same as or different from that of the transistors 31 a to 31 c. The first current flowing to the transistor 31 d is output to the output terminal 11 a.
　よって、基準電圧電流生成回路１１ｅでは、第１電圧が第２電圧よりも大きな電圧を出力する例を示している。異なる例として、カレントミラーの段数を増やし、抵抗の組み合わせを細かく設定することで、第１トランジスタの閾値電圧をさらに細かく制御してもよい。 Therefore, in the reference voltage current generation circuit 11e, an example is shown in which the first voltage outputs a voltage larger than the second voltage. As another example, the threshold voltage of the first transistor may be more finely controlled by increasing the number of stages of the current mirror and finely setting the combination of the resistors.
　図２（Ｂ）は、電圧参照回路１２の構成を示す回路図である。電圧参照回路１２は、トランジスタ３３、抵抗素子３４、及びトランジスタ３５を有している。トランジスタ３３、及びトランジスタ３５は、半導体層に金属酸化物を有するトランジスタである。トランジスタ３３は、電圧参照回路１２が有する第１のトランジスタに相当する。 FIG. 2B is a circuit diagram showing a configuration of voltage reference circuit 12. The voltage reference circuit 12 includes a transistor 33, a resistive element 34, and a transistor 35. The transistors 33 and 35 are transistors each including a metal oxide in a semiconductor layer. The transistor 33 corresponds to a first transistor included in the voltage reference circuit 12.
　トランジスタ３３のドレイン及びゲートは、入力端子１２ａ、及び出力端子１２ｂと電気的に接続される。トランジスタ３３のソースは、配線ＧＮＤと電気的に接続される。また、トランジスタ３３のバックゲートは、抵抗素子３４の電極の一方、トランジスタ３５のソース又はドレインの一方、トランジスタ３５のバックゲート、及び入力端子１２ｃと電気的に接続される。抵抗素子３４の電極の他方は、配線ＶＤＤ１と電気的に接続される。また、トランジスタ３５のソース又はドレインの他方は、配線ＧＮＤと電気的に接続される。 The drain and gate of the transistor 33 are electrically connected to the input terminal 12a and the output terminal 12b. The source of the transistor 33 is electrically connected to the wiring GND. The back gate of the transistor 33 is electrically connected to one of the electrodes of the resistance element 34, one of the source or drain of the transistor 35, the back gate of the transistor 35, and the input terminal 12 c. The other of the electrodes of the resistance element 34 is electrically connected to the wiring VDD1. Further, the other of the source and the drain of the transistor 35 is electrically connected to the wiring GND.
　トランジスタ３３のドレイン及びゲートには、入力端子１２ａを介して第１電流が与えられる。よって、出力端子１２ｂは、トランジスタ３３の閾値電圧を出力する。なお、トランジスタ３３は、トランジスタ３３のバックゲートに与えられる電圧により閾値電圧がシフトすることが知られている。従って、トランジスタ３３のバックゲートには、入力端子１２ｃを介して負電圧生成回路１６で生成される負電圧が与えられる。つまり、電圧参照回路１２、選択回路１３、差分検出回路１４、電圧制御発振器１５、負電圧生成回路１６は、トランジスタ３３を中心としたフィードバックループを形成することができる。なお、選択回路１３は、動作モード制御回路１７が検知する温度によって、出力端子１３ｃに出力する電位を、第１電位、又は第２電位のいずれか一から選択することができる。フィードバックループは、電圧参照回路１２の出力端子１２ｂの出力電圧が出力端子１３ｃに出力する電位と同じになるとフィードバック調整が収束し、調整が終了する。 The drain and gate of the transistor 33 are supplied with the first current through the input terminal 12a. Thus, the output terminal 12 b outputs the threshold voltage of the transistor 33. It is known that the threshold voltage of the transistor 33 is shifted by the voltage applied to the back gate of the transistor 33. Therefore, the negative voltage generated by the negative voltage generation circuit 16 is given to the back gate of the transistor 33 through the input terminal 12c. That is, the voltage reference circuit 12, the selection circuit 13, the difference detection circuit 14, the voltage control oscillator 15, and the negative voltage generation circuit 16 can form a feedback loop centered on the transistor 33. The selection circuit 13 can select the potential to be output to the output terminal 13c from either the first potential or the second potential according to the temperature detected by the operation mode control circuit 17. In the feedback loop, when the output voltage of the output terminal 12b of the voltage reference circuit 12 becomes equal to the potential output to the output terminal 13c, the feedback adjustment converges, and the adjustment ends.
　トランジスタ３５は、トランジスタ３３のバックゲート電位を初期化することができる。抵抗素子３４は、配線ＶＤＤ１に与えられる電圧を基準にトランジスタ３３のバックゲート電位を生成することができる。抵抗素子３４の代わりに、容量素子、又はダイオード等を用いてもよい。後述する負電圧生成回路１６は、チャージポンプ回路１６ｄを用いて負電圧を生成するため、トランジスタ３３のバックゲートに与える負電圧の微調整ができることが好ましい。よって抵抗を介して電流を流すことで、トランジスタ３３のバックゲートに与える負電圧の微調整をすることができる。 The transistor 35 can initialize the back gate potential of the transistor 33. The resistive element 34 can generate the back gate potential of the transistor 33 based on the voltage applied to the wiring VDD1. Instead of the resistive element 34, a capacitive element or a diode may be used. Since the negative voltage generation circuit 16 described later generates a negative voltage using the charge pump circuit 16 d, it is preferable that the negative voltage applied to the back gate of the transistor 33 can be finely adjusted. Therefore, by flowing a current through the resistor, the negative voltage applied to the back gate of the transistor 33 can be finely adjusted.
　図３は、負電圧生成回路１６の構成を示す回路図である。負電圧生成回路１６は、入力端子１６ａ、出力端子１６ｂ、レベルシフタ回路１６ｃ、及びチャージポンプ回路１６ｄを有する。レベルシフタ回路１６ｃは、レベルシフタ３６ａ、及びレベルシフタ３６ｂを有する。レベルシフタ回路１６ｃは、チャージポンプ回路１６ｄに与える信号の振幅電圧を調整することができる。一例として、レベルシフタ３６ａは正電圧側に電圧を拡張することができる。一例として、レベルシフタ３６ｂは負電圧側に電圧を拡張することができる。一例として、配線ＶＤＤ１に与えられる電圧が、正電圧側の最大電圧となる。一例として、チャージポンプ回路１６ｄが生成する負電圧が、負電圧側の最小電圧となる。 FIG. 3 is a circuit diagram showing a configuration of negative voltage generation circuit 16. The negative voltage generation circuit 16 has an input terminal 16a, an output terminal 16b, a level shifter circuit 16c, and a charge pump circuit 16d. The level shifter circuit 16 c includes a level shifter 36 a and a level shifter 36 b. The level shifter circuit 16c can adjust the amplitude voltage of the signal supplied to the charge pump circuit 16d. As one example, the level shifter 36a can expand the voltage to the positive voltage side. As one example, the level shifter 36 b can extend the voltage to the negative voltage side. As an example, the voltage applied to the wiring VDD1 is the maximum voltage on the positive voltage side. As an example, the negative voltage generated by the charge pump circuit 16 d is the minimum voltage on the negative voltage side.
　レベルシフタ回路１６ｃには、入力端子１６ａを介して入力周波数が与えられる。また、レベルシフタ３６ａは、チャージポンプ回路１６ｄに与える正相信号を生成し、レベルシフタ３６ｂは、チャージポンプ回路１６ｄに与える反転信号を生成することができる。 An input frequency is given to the level shifter circuit 16c via the input terminal 16a. The level shifter 36a can generate a positive phase signal to be supplied to the charge pump circuit 16d, and the level shifter 36b can generate an inversion signal to be supplied to the charge pump circuit 16d.
　チャージポンプ回路１６ｄは、トランジスタ３７ａ、トランジスタ３７ｂ、容量素子３７ｃ、トランジスタ３８ａ、トランジスタ３８ｂ、容量素子３８ｃ、トランジスタ３９、入力端子１６ｅ、入力端子１６ｆ、出力端子１６ｂ、配線ＶＤＤ２、及び配線ＧＮＤを有する。トランジスタ３７ａ、トランジスタ３７ｂ、トランジスタ３８ａ、トランジスタ３８ｂ、及びトランジスタ３９は、半導体層に金属酸化物を有していることが好ましい。 The charge pump circuit 16d includes a transistor 37a, a transistor 37b, a capacitor 37c, a transistor 38a, a transistor 38b, a capacitor 38c, a transistor 39, an input terminal 16e, an input terminal 16f, an output terminal 16b, a wiring VDD2, and a wiring GND. The transistors 37a, 37b, 38a, 38b, and 39 preferably each include a metal oxide in a semiconductor layer.
　入力端子１６ｅは、トランジスタ３７ａのゲート、トランジスタ３７ｂのゲート、及びトランジスタ３９のゲートと電気的に接続される。入力端子１６ｆは、トランジスタ３８ａのゲート、及びトランジスタ３８ｂのゲートと電気的に接続される。配線ＶＤＤ２は、トランジスタ３７ａのソース又はドレインの一方と電気的に接続される。配線ＧＮＤは、トランジスタ３７ｂのソース又はドレインの一方と電気的に接続される。トランジスタ３７ａのソース又はドレインの他方は、３８ａのトランジスタのソース又はドレインの一方、及び容量素子３７ｃの電極の一方と電気的に接続される。トランジスタ３７ｂのソース又はドレインの他方は、トランジスタ３８ｂのソース又はドレインの一方、及び容量素子３７ｃの電極の他方と電気的に接続される。トランジスタ３８ａのソース又はドレインの他方は、トランジスタ３９のソース又はドレインの一方、及び容量素子３８ｃの電極の一方と電気的に接続される。トランジスタ３９のソース又はドレインの他方は、配線ＧＮＤと電気的に接続される。トランジスタ３８ｂのソース又はドレインの他方は、出力端子１６ｂ、レベルシフタ３６ａ、レベルシフタ３６ｂ、容量素子３８ｃの電極の他方、トランジスタ３７ａ、トランジスタ３７ｂ、トランジスタ３８ａ、トランジスタ３８ｂ、及びトランジスタ３９のそれぞれのバックゲートと電気的に接続される。 The input terminal 16 e is electrically connected to the gate of the transistor 37 a, the gate of the transistor 37 b, and the gate of the transistor 39. The input terminal 16f is electrically connected to the gate of the transistor 38a and the gate of the transistor 38b. The wiring VDD2 is electrically connected to one of the source and the drain of the transistor 37a. The wiring GND is electrically connected to one of the source and the drain of the transistor 37b. The other of the source and the drain of the transistor 37a is electrically connected to one of the source and the drain of the transistor 38a and one of the electrodes of the capacitor 37c. The other of the source and the drain of the transistor 37b is electrically connected to one of the source and the drain of the transistor 38b and the other of the electrodes of the capacitor 37c. The other of the source and the drain of the transistor 38a is electrically connected to one of the source and the drain of the transistor 39 and one of the electrodes of the capacitor 38c. The other of the source and the drain of the transistor 39 is electrically connected to the wiring GND. The other of the source or drain of the transistor 38b is the output terminal 16b, the level shifter 36a, the level shifter 36b, the other of the electrodes of the capacitor 38c, the transistor 37a, the transistor 37b, the transistor 38a, the transistor 38b, and the transistor 39 Connected.
　配線ＶＤＤ２には、正の電圧が与えられる。配線ＧＮＤには、配線ＶＤＤ２に与えられた正の電圧より小さな電圧が与えられる。但し、配線ＧＮＤには、回路の基準電位が与えられることが好ましい。以降では、一例としてグランド電位の０Ｖが与えられる場合について説明する。配線ＶＤＤ２は、配線ＶＤＤ１に与えられる電圧以下の電圧であることが好ましい。より好ましくは、配線ＶＤＤ２は、配線ＶＤＤ１に与えられる電圧よりも小さな電圧であることが好ましい。 A positive voltage is applied to the wiring VDD2. A voltage smaller than the positive voltage applied to the wiring VDD2 is applied to the wiring GND. However, preferably, the reference potential of the circuit is supplied to the wiring GND. Hereinafter, the case where 0 V of the ground potential is applied will be described as an example. The wiring VDD2 is preferably a voltage lower than or equal to the voltage supplied to the wiring VDD1. More preferably, the wiring VDD2 is preferably a voltage smaller than the voltage applied to the wiring VDD1.
　レベルシフタ３６ａの出力は、トランジスタ３７ａ、トランジスタ３７ｂ、及びトランジスタ３９をオン状態にする。この場合、レベルシフタ３６ｂの出力は、レベルシフタ３６ａの出力の反転状態であり、従って、トランジスタ３８ａ、及びトランジスタ３８ｂはオフ状態になる。よって、容量素子３７ｃの電極の一方には配線ＶＤＤ２から正の電圧が与えられ、容量素子３７ｃの電極の他方には配線ＧＮＤから一例として０Ｖが与えられる。従って、容量素子３７ｃには、配線ＶＤＤ２と、０Ｖとの電位差に相当する電圧が保持される。 The output of the level shifter 36a turns on the transistor 37a, the transistor 37b, and the transistor 39. In this case, the output of the level shifter 36b is the inverted state of the output of the level shifter 36a, and therefore the transistor 38a and the transistor 38b are turned off. Therefore, a positive voltage is applied to the one of the electrodes of the capacitive element 37c from the wiring VDD2, and 0 V is applied to the other of the electrodes of the capacitive element 37c as an example from the wiring GND. Accordingly, a voltage corresponding to a potential difference between the wiring VDD2 and 0 V is held in the capacitor 37c.
　続いて、レベルシフタ３６ａの出力が反転し、トランジスタ３７ａ、トランジスタ３７ｂ、及びトランジスタ３９は、オフ状態になる。この場合、レベルシフタ３６ｂの出力は、レベルシフタ３６ａの出力の反転状態であり、トランジスタ３８ａ、及びトランジスタ３８ｂはオン状態になる。よって、容量素子３７ｃと容量素子３８ｃとは合成容量となり、容量素子３７ｃに保持された電圧は、平滑化された電位になる。この場合、容量素子３７ｃの電極の他方、及び容量素子３８ｃの電極の他方がトランジスタ３８ｂを介して形成されたノードはフローティングノードになるため、フローティングノードが該平滑化された電位の基準電位となる。 Subsequently, the output of the level shifter 36a is inverted, and the transistors 37a, 37b, and 39 are turned off. In this case, the output of the level shifter 36b is the inverted state of the output of the level shifter 36a, and the transistor 38a and the transistor 38b are turned on. Thus, the capacitive element 37c and the capacitive element 38c form a combined capacitance, and the voltage held by the capacitive element 37c becomes a smoothed potential. In this case, since the other of the electrodes of the capacitor 37c and the other of the electrodes of the capacitor 38c is formed through the transistor 38b becomes a floating node, the floating node becomes a reference potential of the smoothed potential. .
　続いて、レベルシフタ３６ａの出力は、トランジスタ３７ａ、トランジスタ３７ｂ、及びトランジスタ３９をオン状態にする。この場合、レベルシフタ３６ｂの出力は、レベルシフタ３６ａの出力の反転状態であり、トランジスタ３８ａ、及びトランジスタ３８ｂはオフ状態になる。 Subsequently, the output of the level shifter 36a turns on the transistor 37a, the transistor 37b, and the transistor 39. In this case, the output of the level shifter 36b is the inverted state of the output of the level shifter 36a, and the transistor 38a and the transistor 38b are turned off.
　ここでは、容量素子３８ｃに着目して説明する。容量素子３８ｃには、該平滑化された電位が保持されている。続いて、容量素子３８ｃの電極の一方が配線ＧＮＤに与えられる０Ｖに変化する場合、容量素子３８ｃの電極の一方が基準電位になり、容量素子３８ｃの電極の他方には、該平滑化された電位が負電圧として生成される。生成された負電圧は、出力端子１６ｂに与えられ、さらに、トランジスタ３７ａ、トランジスタ３７ｂ、トランジスタ３８ａ、トランジスタ３８ｂ、及びトランジスタ３９のそれぞれのバックゲートに与えられる。さらに、生成された負電圧は、レベルシフタ３６ａ、レベルシフタ３６ｂの負電源として与えられる。 Here, description will be given focusing on the capacitive element 38c. The smoothed potential is held in the capacitive element 38c. Subsequently, when one of the electrodes of the capacitive element 38c changes to 0 V applied to the wiring GND, one of the electrodes of the capacitive element 38c becomes a reference potential, and the other of the electrodes of the capacitive element 38c is smoothed. The potential is generated as a negative voltage. The generated negative voltage is applied to the output terminal 16b, and is further applied to the back gates of the transistor 37a, the transistor 37b, the transistor 38a, the transistor 38b, and the transistor 39. Furthermore, the generated negative voltage is given as a negative power supply of the level shifter 36a and the level shifter 36b.
　以上、本実施の形態に示す半導体装置１０を用いることで、記憶装置、表示装置、又は電子機器などの使用環境に合わせてトランジスタの閾値電圧がフィードバックループによって制御され、温度変化に影響されずにデータが保持される半導体装置を提供することができる。また、消費電力の増加を抑制することができる。 As described above, by using the semiconductor device 10 described in this embodiment, the threshold voltage of the transistor is controlled by the feedback loop in accordance with the use environment of the memory device, the display device, the electronic device, or the like, and the temperature change is not affected. A semiconductor device in which data is held can be provided. In addition, an increase in power consumption can be suppressed.
　本実施の形態は、他の実施の形態と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the other embodiments.
（実施の形態２）
〈〈表示装置２０〉〉
　本実施の形態では、温度変化の影響を抑制する表示装置の構成例について図４乃至図９を用いて説明する。なお、本実施の形態においては、実施の形態１で説明した半導体装置１０の動作、機能については説明を省略する。 Second Embodiment
<< display device 20 >>
In this embodiment, configuration examples of a display device which suppresses the influence of temperature change will be described with reference to FIGS. In the present embodiment, description of the operation and function of the semiconductor device 10 described in the first embodiment will be omitted.
　図４（Ａ）は、表示装置の構成例を示すブロック図である。表示装置２０は、制御部２１、及び表示パネル２６を有する。制御部２１は、半導体装置１０、ディスプレイコントローラ２２、フレームメモリ２３、ソースドライバ２４、及びゲートドライバ２５を有する。フレームメモリ２３は、記憶装置１００を有する。フレームメモリ２３は、例えば、複数の記憶装置１００ａ、及び記憶装置１００ｂを有することで、表示データが静止画と動画を区別するための比較処理、画質改善のためのフィルタリング処理、画像と文字情報などを重ね合わせるための画像データ合成処理、異なる画像を重ね合わせるための画像データ合成処理などに使用することができる。なお、フレームメモリ２３には、ＣＰＵ２７などから画像データが与えられることが好ましい。ＣＰＵ２７は、表示装置、又は記憶装置などの構成部品、さらに表示装置が使用されている環境温度などの温度情報を温度センサ１８などから収集し半導体装置１０に与えることができる。 FIG. 4A is a block diagram illustrating a configuration example of a display device. The display device 20 includes a control unit 21 and a display panel 26. The control unit 21 includes a semiconductor device 10, a display controller 22, a frame memory 23, a source driver 24, and a gate driver 25. The frame memory 23 has a storage device 100. The frame memory 23 includes, for example, a plurality of storage devices 100a and 100b, so that display data can be compared to distinguish still images from moving images, filtering to improve image quality, images and text information, etc. Can be used for image data combining processing for overlapping, and image data combining processing for overlapping different images. Preferably, the frame memory 23 is provided with image data from the CPU 27 or the like. The CPU 27 can collect, from the temperature sensor 18 or the like, temperature information such as components such as a display device or a storage device, and an environmental temperature at which the display device is used, and give the semiconductor device 10.
　記憶装置１００は、ＤＲＡＭ（Ｄｙｎａｍｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、又はＳＲＡＭ（Ｓｔａｔｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）などの記憶回路を用いてもよい。なお、記憶回路には、オフ電流の小さなトランジスタを用いることで、静止画などを長い期間保持することを可能にする。なお、オフ電流の小さなトランジスタを有する記憶装置として、ＤＯＳＲＡＭ（登録商標）「Ｄｙｎａｍｉｃ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　ＲＡＭ」、ＮＯＳＲＡＭ（登録商標）「Ｎｏｎｖｏｌａｔｉｌｅ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　ＲＡＭ」などがある。オフ電流の小さなトランジスタについては、実施の形態８に詳細な説明をする。また、オフ電流の小さなトランジスタを用いた記憶装置１００については、実施の形態３に詳細な説明をする。 The storage device 100 may use a storage circuit such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). Note that a still image or the like can be held for a long time by using a transistor with small off current in the memory circuit. Note that as a memory device including a transistor with a small off current, there is a DOSRAM (registered trademark) “Dynamic Oxide Semiconductor RAM”, a NOSRAM (registered trademark) “Nonvolatile Oxide Semiconductor RAM”, and the like. A transistor with a small off current is described in detail in Embodiment 8. A memory device 100 using a transistor with a small off current is described in detail in Embodiment 3.
　表示パネル２６は、表示領域を有し、表示領域は、アレイ状に配列される画素群を有し、それぞれの画素は、トランジスタを有している。以降では、アレイ状に配列される画素群を、画素２６ａと言い換えて説明する。 The display panel 26 has a display area, and the display area has pixel groups arranged in an array, and each pixel has a transistor. Hereinafter, the pixel group arranged in an array will be described in other words as the pixel 26a.
　画素２６ａが有する該トランジスタは、半導体層に金属酸化物を有することでオフ電流を小さくすることができる。該トランジスタを用いることで、表示データの劣化を抑え表示の更新間隔を長くすることができる。特に表示パネルに静止画を表示している場合は、フレームメモリ２３、及び画素２６ａが有するトランジスタからのオフ電流の増大を抑制することで表示データの劣化を抑え表示期間を長くすることができる。 The transistor included in the pixel 26 a can reduce off current by including a metal oxide in the semiconductor layer. By using the transistor, deterioration of display data can be suppressed and a display update interval can be lengthened. In particular, when a still image is displayed on the display panel, deterioration of display data can be suppressed and a display period can be extended by suppressing an increase in off current from the transistors included in the frame memory 23 and the pixels 26a.
　但し、高温の環境で表示装置２０が使用される場合、該トランジスタのオフ電流がさらに大きくなることで、画素２６ａが有する該トランジスタのオフ電流の増大によって表示データが劣化する。実施の形態１で説明した半導体装置１０を用いて該トランジスタのバックゲートを制御することで、該トランジスタの閾値電圧の変化を制御することができる。つまり、高温の環境で使用される場合においても、画素２６ａが有するトランジスタは、オフ電流の増大を抑制することができる。また、フレームメモリ２３が有する記憶装置１００が高温の環境で使用される場合、記憶装置１００が有する該トランジスタは、オフ電流の増大を抑制することができる。 However, in the case where the display device 20 is used in a high temperature environment, the off current of the transistor is further increased, so that the off current of the transistor included in the pixel 26 a is increased to deteriorate display data. By controlling the back gate of the transistor using the semiconductor device 10 described in Embodiment 1, a change in threshold voltage of the transistor can be controlled. That is, even when used in a high temperature environment, the transistor included in the pixel 26a can suppress an increase in off current. Further, when the storage device 100 included in the frame memory 23 is used in a high temperature environment, the transistor included in the storage device 100 can suppress an increase in off current.
　図４（Ｂ）では、図４（Ａ）と異なる構成の表示装置２０について説明する。図４（Ｂ）に示す表示装置２０は、ゲートドライバ２５ａが半導体層に金属酸化物を有するトランジスタによって形成されている点が異なっている。ゲートドライバ２５ａ、及び画素２６ａが同じ該トランジスタで形成されることで、該トランジスタの閾値電圧は、該トランジスタのバックゲートに与える電圧によって制御することができる。よって、ゲートドライバ２５ａ、及び画素２６ａで用いる該トランジスタが同じため、画素２６ａへの表示データ書き込みタイミングをゲートドライバ２５ａによって適切に管理することができる。また高温の環境で使用される場合、表示パネル２６の消費電力の増大を抑制することができる。 In FIG. 4B, the display device 20 having a configuration different from that of FIG. 4A will be described. The display device 20 shown in FIG. 4B is different in that the gate driver 25a is formed of a transistor having a metal oxide in a semiconductor layer. By forming the gate driver 25a and the pixel 26a with the same transistor, the threshold voltage of the transistor can be controlled by the voltage applied to the back gate of the transistor. Therefore, since the gate driver 25a and the transistor used in the pixel 26a are the same, the timing of writing display data to the pixel 26a can be appropriately managed by the gate driver 25a. In addition, when used in a high temperature environment, an increase in power consumption of the display panel 26 can be suppressed.
〈〈画素〉〉
　図５は、図４（Ａ）の画素２６ａの構成例を示す画素回路の回路図である。各構成において説明が重複する内容については、説明を省略する。 << pixel >>
FIG. 5 is a circuit diagram of a pixel circuit showing a configuration example of the pixel 26a of FIG. 4 (A). The description of the same contents in each configuration will be omitted.
　図５（Ａ１）は、液晶素子を表示素子として用いた画素回路を示している。画素回路は、トランジスタ４１ａ、容量素子４２ａ、表示素子４３、配線ＧＬ１、配線ＳＬ１、配線ＣＯＭ、及び配線ＢＧＬを有している。トランジスタ４１ａのゲートは、配線ＧＬ１と電気的に接続される。トランジスタ４１ａのソース又はドレインの一方は、配線ＳＬ１と電気的に接続される。トランジスタ４１ａのソース又はドレインの他方は、容量素子４２ａの電極の一方、及び表示素子４３の一方と電気的に接続される。配線ＣＯＭは、容量素子４２ａの電極の他方、及び表示素子４３の他方と電気的に接続される。トランジスタ４１ａのバックゲートは、配線ＢＧＬと電気的に接続される。配線ＢＧＬは、アレイ状に配列される画素に共通に接続されることが好ましい。なお、表示領域を複数の表示領域に分割し、分割されたそれぞれの表示領域配線が異なるＢＧＬと接続されてもよい。配線ＢＧＬには、実施の形態１の半導体装置１０の出力電圧が与えられる。 FIG. 5A1 illustrates a pixel circuit in which a liquid crystal element is used as a display element. The pixel circuit includes a transistor 41a, a capacitor 42a, a display element 43, a wiring GL1, a wiring SL1, a wiring COM, and a wiring BGL. The gate of the transistor 41a is electrically connected to the wiring GL1. One of the source and the drain of the transistor 41a is electrically connected to the wiring SL1. The other of the source and the drain of the transistor 41 a is electrically connected to one of the electrodes of the capacitor 42 a and one of the display elements 43. The wiring COM is electrically connected to the other of the electrodes of the capacitor 42 a and the other of the display element 43. The back gate of the transistor 41a is electrically connected to the wiring BGL. The wiring BGL is preferably connected in common to the pixels arranged in an array. The display area may be divided into a plurality of display areas, and the divided display area wirings may be connected to different BGLs. The output voltage of the semiconductor device 10 of the first embodiment is applied to the wiring BGL.
　図５（Ａ２）では、図５（Ａ１）と異なる画素回路について説明する。図５（Ａ２）に示す画素回路は、さらに、トランジスタ４１ｂ、容量素子４２ｂ、配線ＧＬ２、及び配線ＳＬ２を有している点が異なっている。トランジスタ４１ｂのゲートは、配線ＧＬ２と電気的に接続される。トランジスタ４１ｂのソース又はドレインの一方は、配線ＳＬ２と電気的に接続される。トランジスタ４１ｂのソース又はドレインの他方は、容量素子４２ｂの電極の一方と電気的に接続される。容量素子４２ｂの電極の他方は、トランジスタ４１ａのソース又はドレインの他方、容量素子４２ａの電極の一方、及び表示素子４３の一方と電気的に接続される。トランジスタ４１ｂのバックゲートは、配線ＢＧＬと電気的に接続される。配線ＢＧＬには、実施の形態１の半導体装置１０の出力電圧が与えられる。 In FIG. 5A2, a pixel circuit different from that in FIG. 5A1 is described. The pixel circuit illustrated in FIG. 5A2 further includes a transistor 41b, a capacitor 42b, a wiring GL2, and a wiring SL2. The gate of the transistor 41 b is electrically connected to the wiring GL2. One of the source and the drain of the transistor 41 b is electrically connected to the wiring SL2. The other of the source and the drain of the transistor 41 b is electrically connected to one of the electrodes of the capacitor 42 b. The other of the electrodes of the capacitor 42 b is electrically connected to the other of the source and the drain of the transistor 41 a, one of the electrodes of the capacitor 42 a, and one of the display elements 43. The back gate of the transistor 41 b is electrically connected to the wiring BGL. The output voltage of the semiconductor device 10 of the first embodiment is applied to the wiring BGL.
　なお、図５（Ａ２）の画素回路では、容量素子４２ｂを有することで、容量素子４２ａに与える第１表示データに、容量素子４２ｂを介して第２表示データを加えることができる。例えば、表示素子４３に与える第１表示データは第１データ電圧として与えられ、第２表示データは、第２データ電圧として与えられる。つまり、表示データは、第１データ電圧に第２データ電圧を加えることができるため、ソースドライバの出力電圧を低減することができる。なお、図示はしていないが、第１表示データには、複数の表示データを加えることもできる。一例として、トランジスタ４１ｃ、容量素子４２ｃ、配線ＧＬ３、及び配線ＳＬ３を有することで、第１表示データに第３表示データを加えることができる。従って、加える表示データの数は、限定されない。 Note that in the pixel circuit in FIG. 5A2, by including the capacitor 42b, second display data can be added to the first display data supplied to the capacitor 42a through the capacitor 42b. For example, the first display data given to the display element 43 is given as a first data voltage, and the second display data is given as a second data voltage. That is, since the display data can add the second data voltage to the first data voltage, the output voltage of the source driver can be reduced. Although not shown, a plurality of display data can be added to the first display data. As an example, the third display data can be added to the first display data by including the transistor 41c, the capacitor 42c, the wiring GL3, and the wiring SL3. Therefore, the number of display data to be added is not limited.
　図５（Ｂ１）は、ＥＬ（Ｅｌｅｃｔｒｏｌｕｍｉｎｅｓｃｅｎｃｅ）素子を表示素子として用いた画素回路を示している。該画素回路は、トランジスタ４４ａ、トランジスタ４５、容量素子４６ａ、表示素子４７、配線ＧＬ１、配線ＳＬ１、配線ＡＮＯ、配線ＣＡＴＨ、及び配線ＢＧＬを有する。トランジスタ４４ａのゲートは、配線ＧＬ１と電気的に接続される。トランジスタ４４ａのソース又はドレインの一方は、配線ＳＬ１と電気的に接続される。トランジスタ４４ａのソース又はドレインの他方は、トランジスタ４５のゲート、トランジスタ４５のバックゲート、及び容量素子４６ａの電極の一方と電気的に接続される。トランジスタ４５のソース又はドレインの一方は、配線ＡＮＯと電気的に接続される。トランジスタ４５のソース又はドレインの他方は、表示素子４７の電極の一方、及び容量素子４６ａの電極の他方と電気的に接続される。表示素子４７の電極の他方は、配線ＣＡＴＨと電気的に接続される。トランジスタ４４ａのバックゲートは、配線ＢＧＬと電気的に接続される。配線ＢＧＬは、アレイ状に配列される画素に共通に接続されることが好ましい。但し、表示領域を複数の表示領域に分割し、分割されたそれぞれの表示領域配線が異なるＢＧＬと接続されてもよい。なお、トランジスタ４５のバックゲートは、トランジスタ４５のソース又はドレインの他方と電気的に接続されてもよい。配線ＢＧＬには、実施の形態１の半導体装置１０の出力電圧が与えられる。 FIG. 5B1 illustrates a pixel circuit in which an EL (Electroluminescence) element is used as a display element. The pixel circuit includes a transistor 44a, a transistor 45, a capacitor 46a, a display element 47, a wiring GL1, a wiring SL1, a wiring ANO, a wiring CATH, and a wiring BGL. The gate of the transistor 44a is electrically connected to the wiring GL1. One of the source and the drain of the transistor 44a is electrically connected to the wiring SL1. The other of the source and the drain of the transistor 44a is electrically connected to one of the gate of the transistor 45, the back gate of the transistor 45, and the electrode of the capacitor 46a. One of the source and the drain of the transistor 45 is electrically connected to the wiring ANO. The other of the source and the drain of the transistor 45 is electrically connected to one of the electrodes of the display element 47 and the other of the electrodes of the capacitor 46a. The other of the electrodes of the display element 47 is electrically connected to the wiring CATH. The back gate of the transistor 44a is electrically connected to the wiring BGL. The wiring BGL is preferably connected in common to the pixels arranged in an array. However, the display area may be divided into a plurality of display areas, and the divided display area wirings may be connected to different BGLs. Note that the back gate of the transistor 45 may be electrically connected to the other of the source and the drain of the transistor 45. The output voltage of the semiconductor device 10 of the first embodiment is applied to the wiring BGL.
　図５（Ｂ２）では、図５（Ｂ１）と異なる画素回路について説明する。図５（Ｂ２）に示す画素回路は、さらに、トランジスタ４８、及び配線ＧＬ２を有している点が異なっている。トランジスタ４８のゲートは、配線ＧＬ２と電気的に接続される。トランジスタ４８のソース又はドレインの一方は、配線ＭＮと電気的に接続される。トランジスタ４８のソース又はドレインの他方は、トランジスタ４５のソース又はドレインの他方、容量素子４６ａの電極の他方、及び表示素子４７の一方の電極と電気的に接続される。トランジスタ４８のバックゲートは、配線ＢＧＬと電気的に接続される。配線ＢＧＬには、実施の形態１の半導体装置１０の出力電圧が与えられる。 In FIG. 5 (B2), a pixel circuit which is different from that in FIG. 5 (B1) is described. The pixel circuit illustrated in FIG. 5B2 is further different in that the transistor 48 and the wiring GL2 are included. The gate of the transistor 48 is electrically connected to the wiring GL2. One of the source and the drain of the transistor 48 is electrically connected to the wiring MN. The other of the source and the drain of the transistor 48 is electrically connected to the other of the source and the drain of the transistor 45, the other of the electrode of the capacitor 46a, and one of the electrodes of the display element 47. The back gate of the transistor 48 is electrically connected to the wiring BGL. The output voltage of the semiconductor device 10 of the first embodiment is applied to the wiring BGL.
　図５（Ｂ２）の画素回路の構成では、トランジスタ４８を有することで、トランジスタ４５の表示データの書き込みを保証することができる。また、トランジスタ４５の閾値電圧は、トランジスタ４８を介して配線ＭＮから読み出すことができる。トランジスタ４５の経時的な閾値電圧の変化を補正値とすることで、画素に書き込む表示データは、補正値を用いて閾値電圧の変化を補正することができる。 In the configuration of the pixel circuit in FIG. 5 (B2), writing of display data of the transistor 45 can be guaranteed by including the transistor 48. In addition, the threshold voltage of the transistor 45 can be read out from the wiring MN through the transistor 48. By using the change in threshold voltage of the transistor 45 with time as a correction value, the display data written to the pixel can correct the change in threshold voltage using the correction value.
　図５（Ｂ３）では、図５（Ｂ２）と異なる画素回路について説明する。図５（Ｂ３）で示す画素回路は、さらに、トランジスタ４４ｂ、容量素子４６ｂ、配線ＧＬ３、及び配線ＳＬ２を有している点が異なっている。トランジスタ４４ｂのゲートは、配線ＧＬ３と電気的に接続される。トランジスタ４４ｂのソース又はドレインの一方は、配線ＳＬ２と電気的に接続される。トランジスタ４４ｂのソース又はドレインの他方は、容量素子４６ｂの電極の一方と電気的に接続される。容量素子４６ｂの電極の他方は、トランジスタ４４ａのソース又はドレインの他方、トランジスタ４５のゲート、トランジスタ４５のバックゲート、及び容量素子４６ａの電極の一方と電気的に接続される。トランジスタ４４ｂのバックゲートは、配線ＢＧＬと電気的に接続される。配線ＢＧＬは、アレイ状に配列される画素に共通に接続されることが好ましい。配線ＢＧＬには、実施の形態１の半導体装置１０の出力電圧が与えられる。 In FIG. 5 (B3), a pixel circuit different from that in FIG. 5 (B2) is described. The pixel circuit illustrated in FIG. 5B3 further includes a transistor 44b, a capacitor 46b, a wiring GL3, and a wiring SL2. The gate of the transistor 44b is electrically connected to the wiring GL3. One of the source and the drain of the transistor 44b is electrically connected to the wiring SL2. The other of the source and the drain of the transistor 44b is electrically connected to one of the electrodes of the capacitor 46b. The other of the electrodes of the capacitor 46b is electrically connected to the other of the source and the drain of the transistor 44a, the gate of the transistor 45, the back gate of the transistor 45, and one of the electrodes of the capacitor 46a. The back gate of the transistor 44 b is electrically connected to the wiring BGL. The wiring BGL is preferably connected in common to the pixels arranged in an array. The output voltage of the semiconductor device 10 of the first embodiment is applied to the wiring BGL.
　図５（Ｂ３）の画素回路では、容量素子４６ｂを有することで、容量素子４６ａに与える第１表示データに、容量素子４６ｂを介して第２表示データを加えることができる。例えば、表示素子４３に与える第１表示データは第１データ電圧として与えられ、第２表示データは、第２データ電圧として与えられる。つまり、表示データは、第１データ電圧に第２データ電圧を加えることができるため、ソースドライバの出力電圧を低減することができる。なお、図示はしていないが、第１表示データには、複数の表示データを加えることもできる。一例として、トランジスタ４４ｃ、容量素子４６ｃ、配線ＧＬ４、及び配線ＳＬ３を有することで、第１表示データに第３表示データを加えることができる。従って、加える表示データの数は、限定されない。 In the pixel circuit in FIG. 5 (B3), by including the capacitor 46b, the second display data can be added to the first display data given to the capacitor 46a via the capacitor 46b. For example, the first display data given to the display element 43 is given as a first data voltage, and the second display data is given as a second data voltage. That is, since the display data can add the second data voltage to the first data voltage, the output voltage of the source driver can be reduced. Although not shown, a plurality of display data can be added to the first display data. As an example, the third display data can be added to the first display data by including the transistor 44c, the capacitor 46c, the wiring GL4, and the wiring SL3. Therefore, the number of display data to be added is not limited.
　上述した各トランジスタに置き換えて用いることのできるトランジスタの一例について、図面を用いて説明する。 An example of a transistor that can be used in place of the above-described transistors is described with reference to the drawings.
　表示パネル２６は、ボトムゲート型のトランジスタや、トップゲート型トランジスタなどの様々な形態のトランジスタを用いて作製することができる。よって、既存の製造ラインに合わせて、使用する半導体層の材料やトランジスタ構造を容易に置き換えることができる。 The display panel 26 can be manufactured using various types of transistors such as a bottom gate transistor and a top gate transistor. Therefore, according to the existing manufacturing line, the material of the semiconductor layer to be used and the transistor structure can be easily replaced.
〔ボトムゲート型トランジスタ〕
　図６（Ａ１）は、ボトムゲート型のトランジスタの一種であるチャネル保護型のトランジスタ８１０のチャネル長方向の断面図である。図６（Ａ１）において、トランジスタ８１０は基板８６０上に形成されている。また、トランジスタ８１０は、基板８６０上に絶縁層８６１を介して電極８５８を有する。また、電極８５８上に絶縁層８５２を介して半導体層８５６を有する。電極８５８はゲート電極として機能できる。絶縁層８５２はゲート絶縁層として機能できる。 Bottom-gate transistor
FIG. 6A1 is a cross-sectional view in the channel length direction of a channel protective transistor 810 which is a kind of bottom gate transistor. In FIG. 6A 1, the transistor 810 is formed over a substrate 860. The transistor 810 also includes an electrode 858 over the substrate 860 with the insulating layer 861 interposed therebetween. In addition, the semiconductor layer 856 is provided over the electrode 858 with the insulating layer 852 interposed therebetween. The electrode 858 can function as a gate electrode. The insulating layer 852 can function as a gate insulating layer.
　また、半導体層８５６のチャネル形成領域上に絶縁層８５５を有する。また、半導体層８５６の一部と接して、絶縁層８５２上に電極８５７ａ及び電極８５７ｂを有する。電極８５７ａは、ソース電極又はドレイン電極の一方として機能できる。電極８５７ｂは、ソース電極又はドレイン電極の他方として機能できる。電極８５７ａの一部、及び電極８５７ｂの一部は、絶縁層８５５上に形成される。 In addition, the insulating layer 855 is provided over the channel formation region of the semiconductor layer 856. In addition, an electrode 857 a and an electrode 857 b are provided over the insulating layer 852 in contact with part of the semiconductor layer 856. The electrode 857a can function as one of a source electrode and a drain electrode. The electrode 857 b can function as the other of the source electrode and the drain electrode. A portion of the electrode 857a and a portion of the electrode 857b are formed over the insulating layer 855.
　絶縁層８５５は、チャネル保護層として機能できる。チャネル形成領域上に絶縁層８５５を設けることで、電極８５７ａ及び電極８５７ｂの形成時に生じる半導体層８５６の露出を防ぐことができる。よって、電極８５７ａ及び電極８５７ｂの形成時に、半導体層８５６のチャネル形成領域がエッチングされることを防ぐことができる。本発明の一態様によれば、電気特性の良好なトランジスタを実現することができる。 The insulating layer 855 can function as a channel protective layer. By providing the insulating layer 855 over the channel formation region, exposure of the semiconductor layer 856 which is generated at the time of formation of the electrodes 857a and 857b can be prevented. Thus, the channel formation region of the semiconductor layer 856 can be prevented from being etched when the electrode 857a and the electrode 857b are formed. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.
　また、トランジスタ８１０は、電極８５７ａ、電極８５７ｂ及び絶縁層８５５上に絶縁層８５３を有し、絶縁層８５３の上に絶縁層８５４を有する。 In addition, the transistor 810 includes the insulating layer 853 over the electrode 857a, the electrode 857b, and the insulating layer 855, and the insulating layer 854 over the insulating layer 853.
　半導体層８５６に酸化物半導体を用いる場合、電極８５７ａ及び電極８５７ｂの、少なくとも半導体層８５６と接する部分に、半導体層８５６の一部から酸素を奪い、酸素欠損を生じさせることが可能な材料を用いることが好ましい。半導体層８５６中の酸素欠損が生じた領域はキャリア濃度が増加し、当該領域はｎ型化し、ｎ型領域（ｎ＋層）となる。従って、当該領域はソース領域又はドレイン領域として機能することができる。半導体層８５６に酸化物半導体を用いる場合、半導体層８５６から酸素を奪い、酸素欠損を生じさせることが可能な材料の一例として、タングステン、チタン等を挙げることができる。 In the case where an oxide semiconductor is used for the semiconductor layer 856, a material capable of generating oxygen vacancies by removing oxygen from part of the semiconductor layer 856 is used in at least a portion of the electrode 857a and the electrode 857b in contact with the semiconductor layer 856. Is preferred. The region of the semiconductor layer 856 in which oxygen vacancies occur has an increased carrier concentration, and the region becomes n-type to be an n-type region (n + layer). Thus, the region can function as a source region or a drain region. In the case of using an oxide semiconductor for the semiconductor layer 856, tungsten, titanium, or the like can be given as an example of a material that can deprive the semiconductor layer 856 of oxygen and cause oxygen vacancies.
　半導体層８５６にソース領域及びドレイン領域が形成されることにより、電極８５７ａ及び電極８５７ｂと半導体層８５６の接触抵抗を低減することができる。よって、電界効果移動度や、閾値電圧などの、トランジスタの電気特性を良好なものとすることができる。 With the source region and the drain region formed in the semiconductor layer 856, the contact resistance between the electrode 857a and the electrode 857b and the semiconductor layer 856 can be reduced. Accordingly, electric characteristics of the transistor such as field effect mobility and threshold voltage can be improved.
　半導体層８５６にシリコンなどの半導体を用いる場合は、半導体層８５６と電極８５７ａの間、及び半導体層８５６と電極８５７ｂの間に、ｎ型半導体又はｐ型半導体として機能する層を設けることが好ましい。ｎ型半導体又はｐ型半導体として機能する層は、トランジスタのソース領域又はドレイン領域として機能することができる。 In the case where a semiconductor such as silicon is used for the semiconductor layer 856, a layer functioning as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 856 and the electrode 857a and between the semiconductor layer 856 and the electrode 857b. A layer functioning as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of a transistor.
　絶縁層８５４は、外部からのトランジスタへの不純物の拡散を防ぐ、又は低減する機能を有する材料を用いて形成することが好ましい。なお、必要に応じて絶縁層８５４を省略することもできる。 The insulating layer 854 is preferably formed using a material having a function of preventing or reducing diffusion of impurities into the transistor from the outside. Note that the insulating layer 854 can be omitted as needed.
　図６（Ａ２）に示すトランジスタ８１１は、絶縁層８５４上にバックゲート電極として機能できる電極８５０を有する点が、トランジスタ８１０と異なる。電極８５０は、電極８５８と同様の材料及び方法で形成することができる。 A transistor 811 illustrated in FIG. 6A2 is different from the transistor 810 in that an electrode 850 that can function as a back gate electrode is provided over the insulating layer 854. The electrode 850 can be formed with the same material and method as the electrode 858.
　一般に、バックゲート電極は導電層で形成され、ゲート電極とバックゲート電極で半導体層のチャネル形成領域を挟むように配置される。よって、バックゲート電極は、ゲート電極と同様に機能させることができる。バックゲート電極の電位は、ゲート電極と同電位としてもよいし、接地電位（ＧＮＤ電位）や、任意の電位としてもよい。また、バックゲート電極の電位をゲート電極と連動させず独立して変化させることで、トランジスタの閾値電圧を変化させることができる。例えば、バックゲート電極には、図１の半導体装置１０の出力電圧が与えられることが好ましい。 In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode are disposed so as to sandwich the channel formation region of the semiconductor layer. Thus, the back gate electrode can function similarly to the gate electrode. The potential of the back gate electrode may be the same as that of the gate electrode, or may be the ground potential (GND potential) or any potential. In addition, the threshold voltage of the transistor can be changed by independently changing the potential of the back gate electrode without interlocking with the gate electrode. For example, it is preferable that the back gate electrode be supplied with the output voltage of the semiconductor device 10 of FIG.
　また、電極８５８及び電極８５０は、どちらもゲート電極として機能することができる。よって、絶縁層８５２、絶縁層８５３、及び絶縁層８５４は、それぞれがゲート絶縁層として機能することができる。なお、電極８５０は、絶縁層８５３と絶縁層８５４の間に設けてもよい。 Further, the electrode 858 and the electrode 850 can both function as a gate electrode. Thus, each of the insulating layer 852, the insulating layer 853, and the insulating layer 854 can function as a gate insulating layer. Note that the electrode 850 may be provided between the insulating layer 853 and the insulating layer 854.
　なお、電極８５８又は電極８５０の一方を、「ゲート電極」という場合、他方を「バックゲート電極」という。例えば、トランジスタ８１１において、電極８５０を「ゲート電極」と言う場合、電極８５８を「バックゲート電極」と言う。また、電極８５０を「ゲート電極」として用いる場合は、トランジスタ８１１をトップゲート型のトランジスタの一種と考えることができる。また、電極８５８及び電極８５０のどちらか一方を、「第１のゲート電極」といい、他方を「第２のゲート電極」という場合がある。 Note that when one of the electrode 858 or the electrode 850 is referred to as a “gate electrode”, the other is referred to as a “back gate electrode”. For example, in the transistor 811, when the electrode 850 is referred to as a “gate electrode”, the electrode 858 is referred to as a “back gate electrode”. In the case where the electrode 850 is used as a “gate electrode”, the transistor 811 can be considered as a kind of top gate transistor. Further, one of the electrode 858 and the electrode 850 may be referred to as a “first gate electrode”, and the other may be referred to as a “second gate electrode”.
　半導体層８５６を挟んで電極８５８及び電極８５０を設けることで、更には、電極８５８及び電極８５０を同電位とすることで、半導体層８５６においてキャリアの流れる領域が膜厚方向においてより大きくなるため、キャリアの移動量が増加する。この結果、トランジスタ８１１のオン電流が大きくなると共に、電界効果移動度が高くなる。 By providing the electrode 858 and the electrode 850 with the semiconductor layer 856 interposed, and by setting the electrode 858 and the electrode 850 to the same potential, the region in which the carrier flows in the semiconductor layer 856 becomes larger in the film thickness direction. The amount of carrier movement increases. As a result, the on current of the transistor 811 is increased, and the field effect mobility is increased.
　従って、トランジスタ８１１は、占有面積に対して大きいオン電流を有するトランジスタである。すなわち、求められるオン電流に対して、トランジスタ８１１の占有面積を小さくすることができる。本発明の一態様によれば、トランジスタの占有面積を小さくすることができる。よって、本発明の一態様によれば、集積度の高い半導体装置を実現することができる。 Accordingly, the transistor 811 is a transistor having a large on current with respect to the occupied area. That is, the area occupied by the transistor 811 can be reduced with respect to the on current required. According to one embodiment of the present invention, the area occupied by the transistor can be reduced. Thus, according to one embodiment of the present invention, a semiconductor device with a high degree of integration can be realized.
　また、ゲート電極とバックゲート電極は導電層で形成されるため、トランジスタの外部で生じる電界が、チャネルが形成される半導体層に作用しないようにする機能（特に静電気などに対する電界遮蔽機能）を有する。なお、バックゲート電極を半導体層よりも大きく形成し、バックゲート電極で半導体層を覆うことで、電界遮蔽機能を高めることができる。 In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they have a function to prevent an electric field generated outside the transistor from acting on the semiconductor layer in which a channel is formed (in particular, an electric field shielding function against static electricity). . Note that the electric field shielding function can be enhanced by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode.
　また、バックゲート電極を、遮光性を有する導電膜で形成することで、バックゲート電極側から半導体層に光が入射することを防ぐことができる。よって、半導体層の光劣化を防ぎ、トランジスタの閾値電圧がシフトするなどの電気特性の劣化を防ぐことができる。 In addition, when the back gate electrode is formed using a light-shielding conductive film, light can be prevented from entering the semiconductor layer from the back gate electrode side. Accordingly, light deterioration of the semiconductor layer can be prevented, and deterioration of electrical characteristics such as a shift in threshold voltage of a transistor can be prevented.
　本発明の一態様によれば、信頼性の良好なトランジスタを実現することができる。また、信頼性の良好な半導体装置を実現することができる。 According to one embodiment of the present invention, a highly reliable transistor can be realized. In addition, a highly reliable semiconductor device can be realized.
　図６（Ｂ１）は、図６（Ａ１）とは異なる構成のチャネル保護型のトランジスタ８２０のチャネル長方向の断面図である。トランジスタ８２０は、トランジスタ８１０とほぼ同様の構造を有しているが、絶縁層８５５が半導体層８５６の端部を覆っている点が異なる。また、半導体層８５６と重なる絶縁層８５５の一部を選択的に除去して形成した開口部において、半導体層８５６と電極８５７ａが電気的に接続している。また、半導体層８５６と重なる絶縁層８５５の一部を選択的に除去して形成した他の開口部において、半導体層８５６と電極８５７ｂが電気的に接続している。絶縁層８５５の、チャネル形成領域と重なる領域は、チャネル保護層として機能できる。 6B1 is a cross-sectional view in the channel length direction of a channel protective transistor 820 having a different structure from that in FIG. 6A1. The transistor 820 has substantially the same structure as the transistor 810, except that the insulating layer 855 covers an end portion of the semiconductor layer 856. The semiconductor layer 856 and the electrode 857a are electrically connected to each other in an opening portion which is formed by selectively removing part of the insulating layer 855 overlapping with the semiconductor layer 856. In addition, the semiconductor layer 856 and the electrode 857 b are electrically connected to each other in another opening which is formed by selectively removing part of the insulating layer 855 overlapping with the semiconductor layer 856. The region of the insulating layer 855 overlapping with the channel formation region can function as a channel protective layer.
　図６（Ｂ２）に示すトランジスタ８２１は、絶縁層８５４上にバックゲート電極として機能できる電極８５０を有する点が、トランジスタ８２０と異なる。 A transistor 821 illustrated in FIG. 6B2 is different from the transistor 820 in that an electrode 850 that can function as a back gate electrode is provided over the insulating layer 854.
　絶縁層８５５を設けることで、電極８５７ａ及び電極８５７ｂの形成時に生じる半導体層８５６の露出を防ぐことができる。よって、電極８５７ａ及び電極８５７ｂの形成時に半導体層８５６の薄膜化を防ぐことができる。 With the insulating layer 855, the exposure of the semiconductor layer 856 which is generated at the time of formation of the electrodes 857a and 857b can be prevented. Thus, thinning of the semiconductor layer 856 can be prevented at the time of formation of the electrodes 857a and 857b.
　また、トランジスタ８２０及びトランジスタ８２１は、トランジスタ８１０及びトランジスタ８１１よりも、電極８５７ａと電極８５８の間の距離と、電極８５７ｂと電極８５８の間の距離が長くなる。よって、電極８５７ａと電極８５８の間に生じる寄生容量を小さくすることができる。また、電極８５７ｂと電極８５８の間に生じる寄生容量を小さくすることができる。本発明の一態様によれば、電気特性の良好なトランジスタを実現できる。 Further, in the transistors 820 and 821, the distance between the electrode 857a and the electrode 858 and the distance between the electrode 857b and the electrode 858 are longer than those in the transistors 810 and 811. Thus, parasitic capacitance generated between the electrode 857a and the electrode 858 can be reduced. In addition, parasitic capacitance generated between the electrode 857 b and the electrode 858 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.
　図６（Ｃ１）に示すトランジスタ８２５は、ボトムゲート型のトランジスタの１つであるチャネルエッチング型のトランジスタ８２５のチャネル長方向の断面図である。トランジスタ８２５は、絶縁層８５４を用いずに電極８５７ａ及び電極８５７ｂを形成する。このため、電極８５７ａ及び電極８５７ｂの形成時に露出する半導体層８５６の一部がエッチングされる場合がある。一方、絶縁層８５５を設けないため、トランジスタの生産性を高めることができる。 A transistor 825 illustrated in FIG. 6C1 is a cross-sectional view in the channel length direction of a channel-etched transistor 825 which is one of bottom-gate transistors. The transistor 825 forms the electrode 857a and the electrode 857b without using the insulating layer 854. Therefore, part of the semiconductor layer 856 exposed when forming the electrode 857a and the electrode 857b may be etched. On the other hand, since the insulating layer 855 is not provided, productivity of the transistor can be increased.
　図６（Ｃ２）に示すトランジスタ８２６は、絶縁層８５４上にバックゲート電極として機能できる電極８５０を有する点が、トランジスタ８２５と異なる。 A transistor 826 illustrated in FIG. 6C2 is different from the transistor 825 in that an electrode 850 that can function as a back gate electrode is provided over the insulating layer 854.
　図７（Ａ１）乃至（Ｃ２）にトランジスタ８１０、８１１、８２０、８２１、８２５、８２６のチャネル幅方向の断面図をそれぞれ示す。 7A1 to 7C2 are cross-sectional views in the channel width direction of the transistors 810, 811, 820, 821, 825, and 826, respectively.
　図７（Ｂ２）、（Ｃ２）に示す構造では、ゲート電極とバックゲート電極とが接続され、ゲート電極とバックゲート電極との電位が同電位となる。また、半導体層８５６は、ゲート電極とバックゲート電極と挟まれている。 In the structures shown in FIGS. 7B2 and 7C2, the gate electrode and the back gate electrode are connected, and the potentials of the gate electrode and the back gate electrode are the same. In addition, the semiconductor layer 856 is sandwiched between the gate electrode and the back gate electrode.
　ゲート電極及びバックゲート電極のそれぞれのチャネル幅方向の長さは、半導体層８５６のチャネル幅方向の長さよりも長く、半導体層８５６のチャネル幅方向全体は、絶縁層８５２、８５５、８５３、８５４を間に挟んでゲート電極又はバックゲート電極に覆われた構成である。 The length in the channel width direction of each of the gate electrode and the back gate electrode is longer than the length in the channel width direction of the semiconductor layer 856, and the entire channel width direction of the semiconductor layer 856 is the insulating layer 852, 855, 853, 854. It is the structure covered by the gate electrode or the back gate electrode on both sides.
　当該構成とすることで、トランジスタに含まれる半導体層８５６を、ゲート電極及びバックゲート電極の電界によって電気的に取り囲むことができる。 With this structure, the semiconductor layer 856 included in the transistor can be electrically surrounded by the electric field of the gate electrode and the back gate electrode.
　トランジスタ８２１又はトランジスタ８２６のように、ゲート電極及びバックゲート電極の電界によって、チャネル形成領域が形成される半導体層８５６を電気的に取り囲むトランジスタのデバイス構造をＳｕｒｒｏｕｎｄｅｄ　ｃｈａｎｎｅｌ（Ｓ−ｃｈａｎｎｅｌ）構造と呼ぶことができる。 A device structure of a transistor electrically surrounding a semiconductor layer 856 in which a channel formation region is formed by an electric field of a gate electrode and a back gate electrode, such as the transistor 821 or the transistor 826, is referred to as a surrounded channel (S-channel) structure. Can.
　Ｓ−ｃｈａｎｎｅｌ構造とすることで、ゲート電極及びバックゲート電極の一方又は双方によってチャネルを誘起させるための電界を効果的に半導体層８５６に印加することができるため、トランジスタの電流駆動能力が向上し、高いオン電流特性を得ることが可能となる。また、オン電流を高くすることが可能であるため、トランジスタを微細化することが可能となる。また、Ｓ−ｃｈａｎｎｅｌ構造とすることで、トランジスタの機械的強度を高めることができる。 With the S-channel structure, an electric field for inducing a channel can be effectively applied to the semiconductor layer 856 by one or both of the gate electrode and the back gate electrode, so that the current drive capability of the transistor is improved. It is possible to obtain high on-current characteristics. In addition, since the on current can be increased, the transistor can be miniaturized. In addition, with the S-channel structure, mechanical strength of the transistor can be increased.
〔トップゲート型トランジスタ〕
　図８（Ａ１）に例示するトランジスタ８４２は、トップゲート型のトランジスタの１つである。トランジスタ８４２は、絶縁層８５４を形成した後に電極８５７ａ及び電極８５７ｂを形成する点がトランジスタ８１０やトランジスタ８２０と異なる。電極８５７ａ及び電極８５７ｂは、絶縁層８５３及び絶縁層８５４に形成した開口部において半導体層８５６と電気的に接続する。 [Top gate type transistor]
The transistor 842 illustrated in FIG. 8A1 is one of top-gate transistors. The transistor 842 is different from the transistor 810 and the transistor 820 in that the electrode 857 a and the electrode 857 b are formed after the insulating layer 854 is formed. The electrode 857 a and the electrode 857 b are electrically connected to the semiconductor layer 856 in an opening formed in the insulating layer 853 and the insulating layer 854.
　また、電極８５８と重ならない絶縁層８５２の一部を除去し、電極８５８と残りの絶縁層８５２をマスクとして用いて不純物を半導体層８５６に導入することで、半導体層８５６中に自己整合（セルフアライメント）的に不純物領域を形成することができる。トランジスタ８４２は、絶縁層８５２が電極８５８の端部を越えて延伸する領域を有する。半導体層８５６の絶縁層８５２を介して不純物が導入された領域の不純物濃度は、絶縁層８５２を介さずに不純物が導入された領域よりも小さくなる。よって、半導体層８５６は、電極８５８と重ならない領域にＬＤＤ（Ｌｉｇｈｔｌｙ　Ｄｏｐｅｄ　Ｄｒａｉｎ）領域が形成される。 In addition, a portion of the insulating layer 852 which does not overlap with the electrode 858 is removed, and an impurity is introduced into the semiconductor layer 856 by using the electrode 858 and the remaining insulating layer 852 as a mask; Alignment) can form an impurity region. The transistor 842 has a region where the insulating layer 852 extends beyond the end of the electrode 858. The impurity concentration of the region into which the impurity is introduced through the insulating layer 852 of the semiconductor layer 856 is smaller than that of the region into which the impurity is introduced without the insulating layer 852. Thus, in the semiconductor layer 856, a lightly doped drain (LDD) region is formed in a region which does not overlap with the electrode 858.
　図８（Ａ２）に示すトランジスタ８４３は、電極８５０を有する点がトランジスタ８４２と異なる。トランジスタ８４３は、基板８６０の上に形成された電極８５０を有する。電極８５０は、絶縁層８６１を介して半導体層８５６と重なる領域を有する。電極８５０は、バックゲート電極として機能することができる。 A transistor 843 illustrated in FIG. 8A2 is different from the transistor 842 in having an electrode 850. The transistor 843 has an electrode 850 formed on a substrate 860. The electrode 850 has a region overlapping with the semiconductor layer 856 through the insulating layer 861. The electrode 850 can function as a back gate electrode.
　また、図８（Ｂ１）に示すトランジスタ８４４及び図８（Ｂ２）に示すトランジスタ８４５のように、電極８５８と重ならない領域の絶縁層８５２を全て除去してもよい。また、図８（Ｃ１）に示すトランジスタ８４６及び図８（Ｃ２）に示すトランジスタ８４７のように、絶縁層８５２を残してもよい。 Alternatively, as in the transistor 844 illustrated in FIG. 8B1 and the transistor 845 illustrated in FIG. 8B2, all the insulating layer 852 in a region which does not overlap with the electrode 858 may be removed. Alternatively, as in the transistor 846 illustrated in FIG. 8C1 and the transistor 847 illustrated in FIG. 8C2, the insulating layer 852 may be left.
　トランジスタ８４２乃至トランジスタ８４７も、電極８５８を形成した後に、電極８５８をマスクとして用いて不純物を半導体層８５６に導入することで、半導体層８５６中に自己整合的に不純物領域を形成することができる。本発明の一態様によれば、電気特性の良好なトランジスタを実現することができる。また、本発明の一態様によれば、集積度の高い半導体装置を実現することができる。 The transistors 842 to 847 can also form impurity regions in the semiconductor layer 856 in a self-aligned manner by introducing an impurity into the semiconductor layer 856 using the electrode 858 as a mask after the electrodes 858 are formed. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. Further, according to one embodiment of the present invention, a semiconductor device with a high degree of integration can be realized.
　図９（Ａ１）乃至（Ｃ２）にトランジスタ８４２、８４３、８４４、８４５、８４６、８４７のチャネル幅方向の断面図をそれぞれ示す。 9A1 to 9C2 are cross-sectional views in the channel width direction of the transistors 842, 843, 844, 845, 846, and 847, respectively.
　トランジスタ８４３、トランジスタ８４５、及びトランジスタ８４７は、それぞれ先に説明したＳ−ｃｈａｎｎｅｌ構造である。但し、これに限定されず、トランジスタ８４３、トランジスタ８４５、及びトランジスタ８４７をＳ−ｃｈａｎｎｅｌ構造としなくてもよい。 The transistor 843, the transistor 845, and the transistor 847 each have the S-channel structure described above. However, without limitation thereto, the transistor 843, the transistor 845, and the transistor 847 may not have an S-channel structure.
　本実施の形態は、他の実施の形態と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the other embodiments.
（実施の形態３）
　本実施の形態では、実施の形態１に記載の半導体装置１０を用いた記憶装置について説明する。 Third Embodiment
In this embodiment, a memory device using the semiconductor device 10 described in Embodiment 1 will be described.
〈〈記憶装置１００〉〉
　図１０は記憶装置の構成例を示すブロック図である。図１０に示す記憶装置１００は、メモリセルアレイ（Ｍｅｍｏｒｙ　Ｃｅｌｌ　Ａｒｒａｙ）１１０、周辺回路１１１、コントロール回路（Ｃｏｎｔｒｏｌ　Ｃｉｒｃｕｉｔ）１１２、半導体装置１０、パワースイッチ（ＰＳＷ）１４１、１４２を有する。 << storage device 100 >>
FIG. 10 is a block diagram showing a configuration example of a storage device. A memory device 100 illustrated in FIG. 10 includes a memory cell array (Memory Cell Array) 110, a peripheral circuit 111, a control circuit (Control Circuit) 112, the semiconductor device 10, and power switches (PSW) 141 and 142.
　記憶装置１００において、各回路、各信号及び各電圧は、必要に応じて、適宜取捨することができる。あるいは、他の回路又は他の信号を追加してもよい。信号ＢＷ、ＣＥ、ＧＷ、ＣＬＫ、ＷＡＫＥ、ＡＤＤＲ、ＷＤＡ、ＰＯＮ１、ＰＯＮ２は外部からの入力信号であり、信号ＲＤＡは外部への出力信号である。信号ＣＬＫはクロック信号である。信号ＣＥ、ＧＷ、及び信号ＢＷは制御信号である。信号ＣＥはチップイネーブル信号であり、信号ＧＷはグローバル書き込みイネーブル信号であり、信号ＢＷはバイト書き込みイネーブル信号である。信号ＡＤＤＲはアドレス信号である。信号ＷＤＡは書き込みデータであり、信号ＲＤＡは読み出しデータである。信号ＰＯＮ１、ＰＯＮ２は、パワーゲーティング制御用信号である。なお、信号ＰＯＮ１、ＰＯＮ２は、コントロール回路１１２で生成してもよい。 In the storage device 100, each circuit, each signal, and each voltage can be appropriately discarded as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1 and PON2 are input signals from the outside, and signal RDA is an output signal to the outside. The signal CLK is a clock signal. The signals CE, GW and the signal BW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. Signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. Signals PON1 and PON2 are power gating control signals. The signals PON1 and PON2 may be generated by the control circuit 112.
　コントロール回路１１２は、記憶装置１００の動作全般を制御する機能を有するロジック回路である。例えば、コントロール回路は、信号ＣＥ、信号ＧＷ及び信号ＢＷを論理演算して、記憶装置１００の動作モード（例えば、書き込み動作、読み出し動作）を決定する。又は、コントロール回路１１２は、この動作モードが実行されるように、周辺回路１１１の制御信号を生成する。 The control circuit 112 is a logic circuit having a function of controlling the overall operation of the storage device 100. For example, the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine an operation mode (for example, a write operation or a read operation) of the storage device 100. Alternatively, control circuit 112 generates a control signal of peripheral circuit 111 such that this operation mode is performed.
　メモリセルアレイ１１０は、複数のメモリセル（ＭＣ）１３０、及び複数の配線ＷＬ、ＮＷＬ、ＢＬ、ＢＬＢを有する。複数のメモリセル１３０は行列状に配置されている。 The memory cell array 110 includes a plurality of memory cells (MC) 130 and a plurality of wirings WL, NWL, BL, and BLB. The plurality of memory cells 130 are arranged in a matrix.
　同じ行のメモリセル１３０は、その行の配線ＷＬ、ＮＷＬに電気的に接続される。配線ＷＬ、ＮＷＬはそれぞれワード線であり、配線ＢＬ、ＢＬＢは相補データを伝送するためのビット線対である。配線ＢＬＢは、ＢＬの論理を反転したデータが入力されるビット線であり、ビット補線や、反転ビット線と呼ばれる場合がある。メモリセル１３０は、２種類のメモリＳＭＣ及びメモリＮＶＭを有する。ＳＭＣは１ビットの相補データを記憶することができるメモリ回路である。ＮＶＭはｎビット（ｎは１よりも大きい整数）の相補データを記憶することができるメモリ回路であり、電源オフ状態でも長期間データを保持することが可能である。 The memory cells 130 in the same row are electrically connected to the wirings WL, NWL in the row. The wirings WL and NWL are respectively word lines, and the wirings BL and BLB are a pair of bit lines for transmitting complementary data. The wiring BLB is a bit line to which data obtained by inverting the logic of BL is input, and may be referred to as a complementary bit line or an inverted bit line. The memory cell 130 has two types of memory SMC and memory NVM. The SMC is a memory circuit capable of storing 1-bit complementary data. The NVM is a memory circuit capable of storing complementary data of n bits (n is an integer larger than 1), and can hold data for a long time even in a power-off state.
　半導体装置１０は負電圧（ＶＢＧ）を生成し配線ＢＧＬを介してメモリセルアレイ１１０に与える機能を有する。ＶＢＧはＮＶＭに用いられるトランジスタのバックゲートに印加される。ＷＡＫＥは、ＣＬＫの半導体装置１０への入力を制御する機能を有する。例えば、ＷＡＫＥにＨレベルの信号が与えられると、信号ＣＬＫが半導体装置１０へ入力され、半導体装置１０はＶＢＧを生成する。半導体装置１０の詳細は実施の形態１の記載を参酌すればよい。 The semiconductor device 10 has a function of generating a negative voltage (V BG ) and applying it to the memory cell array 110 through the wiring BGL. V BG is applied to the back gate of the transistor used for NVM. WAKE has a function of controlling the input of CLK to the semiconductor device 10. For example, when a signal at H level is supplied to WAKE, the signal CLK is input to the semiconductor device 10, and the semiconductor device 10 generates V BG . The description of Embodiment 1 can be referred to for the details of the semiconductor device 10.
　ＳＭＣとＮＶＭとはローカルビット線対（配線ＬＢＬ、ＬＢＬＢ）により電気的に接続されている。配線ＬＢＬは、配線ＢＬに対するローカルビット線であり、配線ＬＢＬＢは、配線ＢＬＢに対するローカルビット線である。配線ＬＢＬ、ＬＢＬＢによって、ＳＭＣとＮＶＭとは電気的に接続されている。メモリセル１３０は回路ＬＰＣを有する。ＬＰＣは、配線ＬＢＬ及び配線ＬＢＬＢをプリチャージするためのローカルプリチャージ回路である。ＬＰＣの制御信号は、周辺回路１１１で生成される。 The SMC and NVM are electrically connected by a local bit line pair (wiring LBL, LBLB). The wiring LBL is a local bit line for the wiring BL, and the wiring LBLB is a local bit line for the wiring BLB. The SMC and the NVM are electrically connected by the lines LBL and LBLB. Memory cell 130 has a circuit LPC. The LPC is a local precharge circuit for precharging the line LBL and the line LBLB. The LPC control signal is generated by the peripheral circuit 111.
　周辺回路１１１は、メモリセルアレイ１１０に対するデータの書き込み及び読み出しをするための回路である。周辺回路１１１は、配線ＷＬ、ＮＷＬ、ＢＬ、ＢＬＢを駆動する機能を有する。周辺回路１１１は、行デコーダ（Ｒｏｗ　Ｄｅｃｏｒｄｅｒ）１２１、列デコーダ（Ｃｏｌｕｍｎ　Ｄｅｃｏｒｄｅｒ）１２２、行ドライバ（Ｒｏｗ　Ｄｒｉｖｅｒ）１２３、列ドライバ（Ｃｏｌｕｍｎ　Ｄｒｉｖｅｒ）１２４、入力回路（Ｉｎｐｕｔ　Ｃｉｒ．）１２５、及び出力回路（Ｏｕｔｐｕｔ　Ｃｉｒｃｕｉｔ）１２６を有する。 Peripheral circuit 111 is a circuit for writing data to and reading data from memory cell array 110. The peripheral circuit 111 has a function of driving the wirings WL, NWL, BL, and BLB. The peripheral circuit 111 includes a row decoder (Row Decorder) 121, a column decoder (Column Decorder) 122, a row driver (Row Driver) 123, a column driver (Column Driver) 124, an input circuit (Input Cir.) 125, and an output circuit Output Circuit 126.
　行デコーダ１２１及び列デコーダ１２２は、信号ＡＤＤＲをデコードする機能を有する。行デコーダ１２１は、アクセスする行を指定するための回路であり、列デコーダ１２２は、アクセスする列を指定するための回路である。行ドライバ１２３は、行デコーダ１２１が指定する行の配線ＷＬ、ＮＷＬを選択する機能を有する。具体的には、行ドライバ１２３は、配線ＷＬ、ＮＷＬを選択するための信号を生成する機能を有する。列ドライバ１２４は、データをメモリセルアレイ１１０に書き込む機能、メモリセルアレイ１１０からデータを読み出す機能、読み出したデータを保持する機能、配線ＢＬ及び配線ＢＬＢをプリチャージする機能等を有する。 The row decoder 121 and the column decoder 122 have a function of decoding the signal ADDR. The row decoder 121 is a circuit for specifying a row to be accessed, and the column decoder 122 is a circuit for specifying a column to be accessed. The row driver 123 has a function of selecting the wirings WL and NWL of the row designated by the row decoder 121. Specifically, the row driver 123 has a function of generating a signal for selecting the wirings WL and NWL. The column driver 124 has a function of writing data to the memory cell array 110, a function of reading data from the memory cell array 110, a function of holding the read data, a function of precharging the wiring BL and the wiring BLB, and the like.
　入力回路１２５は、信号ＷＤＡを保持する機能を有する。入力回路１２５が保持するデータは、列ドライバ１２４に出力される。入力回路１２５の出力データが、メモリセルアレイ１１０に書き込むデータである。列ドライバ１２４がメモリセルアレイ１１０から読み出したデータ（Ｄｏｕｔ）は、出力回路１２６に出力される。出力回路１２６は、Ｄｏｕｔを保持する機能を有する。出力回路１２６は、保持しているデータを記憶装置１００外部に出力する。出力されるデータが信号ＲＤＡである。 The input circuit 125 has a function of holding the signal WDA. The data held by the input circuit 125 is output to the column driver 124. The output data of the input circuit 125 is data to be written to the memory cell array 110. Data (Dout) read from the memory cell array 110 by the column driver 124 is output to the output circuit 126. The output circuit 126 has a function of holding Dout. The output circuit 126 outputs the held data to the outside of the storage device 100. The data to be output is the signal RDA.
　ＰＳＷ１４１はメモリセルアレイ１１０以外の回路（周辺回路１１５）へのＶＤＤの供給を制御する機能を有する。ＰＳＷ１４２は、行ドライバ１２３へのＶＨＭの供給を制御する機能を有する。ここでは、記憶装置１００の高電源電圧がＶＤＤであり、低電源電圧はＧＮＤ（接地電位）である。また、ＶＨＭは、配線ＮＷＬを高レベルにするために用いられる高電源電圧であり、ＶＤＤよりも高い。信号ＰＯＮ１によってＰＳＷ１４１のオン・オフが制御され、信号ＰＯＮ２によってＰＳＷ１４２のオン・オフが制御される。図１０では、周辺回路１１５において、ＶＤＤが供給される電源ドメインの数を１としているが、複数にすることもできる。この場合、各電源ドメインに対してパワースイッチを設ければよい。 The PSW 141 has a function of controlling the supply of VDD to circuits (peripheral circuits 115) other than the memory cell array 110. The PSW 142 has a function of controlling the supply of the VHM to the row driver 123. Here, the high power supply voltage of the storage device 100 is VDD, and the low power supply voltage is GND (ground potential). Also, VHM is a high power supply voltage used to make the wiring NWL high, and is higher than VDD. The signal PON1 controls the on / off of the PSW 141, and the signal PON2 controls the on / off of the PSW 142. In FIG. 10, in the peripheral circuit 115, the number of power supply domains to which VDD is supplied is one, but it may be plural. In this case, a power switch may be provided for each power supply domain.
〈〈メモリセル１３０〉〉
　図１１に、メモリセル１３０の回路構成例を示す。 << memory cell 130 >>
FIG. 11 shows a circuit configuration example of the memory cell 130.
〈ＳＭＣ〉
　ＳＭＣは、配線ＢＬ、配線ＢＬＢ、配線ＬＢＬ、配線ＬＢＬＢ、配線ＶＨＨ、及び配線ＶＬＬと電気的に接続されている。 <SMC>
The SMC is electrically connected to the wiring BL, the wiring BLB, the wiring LBL, the wiring LBLB, the wiring VHH, and the wiring VLL.
　ＳＭＣは、ＣＭＯＳ型（６トランジスタ型）のＳＲＡＭセルと同様の回路構成であり、トランジスタＴｌｄ１、Ｔｌｄ２、Ｔｄｒ１、Ｔｄｒ２、Ｔａｃ１、Ｔａｃ２を有する。トランジスタＴｌｄ１、Ｔｌｄ２はロードトランジスタ（プルアップトランジスタ）であり、トランジスタＴｄｒ１、Ｔｄｒ２は駆動トランジスタ（プルダウントランジスタ）であり、トランジスタＴａｃ１、Ｔａｃ２はアクセストランジスタ（トランスファトランジスタ）である。 SMC has a circuit configuration similar to that of a CMOS type (6-transistor type) SRAM cell, and has transistors Tld1, Tld2, Tdr1, Tdr2, Tac1, Tac2. The transistors Tld1 and Tld2 are load transistors (pull-up transistors), the transistors Tdr1 and Tdr2 are drive transistors (pull-down transistors), and the transistors Tac1 and Tac2 are access transistors (transfer transistors).
　トランジスタＴａｃ１により配線ＢＬと配線ＬＢＬとの間の導通状態が制御される。トランジスタＴａｃ２により配線ＢＬＢと配線ＬＢＬＢとの間の導通状態が制御される。トランジスタＴａｃ１、Ｔａｃ２のオン・オフは配線ＷＬの電位によって制御される。トランジスタＴｌｄ１、Ｔｄｒ１によりインバータが構成され、トランジスタＴｌｄ２、Ｔｄｒ２によりインバータが構成されている。これら２個のインバータの入力端子は、それぞれ、他方の出力端子に電気的に接続されており、ラッチ回路が構成される。２個のインバータには、配線ＶＨＨ、ＶＬＬによって電源電圧が供給される。 The conduction state between the wiring BL and the wiring LBL is controlled by the transistor Tac1. The conduction state between the wiring BLB and the wiring LBLB is controlled by the transistor Tac2. The on / off of the transistors Tac1 and Tac2 is controlled by the potential of the wiring WL. The transistors Tld1 and Tdr1 constitute an inverter, and the transistors Tld2 and Tdr2 constitute an inverter. The input terminals of these two inverters are respectively electrically connected to the other output terminal, and a latch circuit is configured. Power supply voltages are supplied to the two inverters by the wires VHH and VLL.
〈ＮＶＭ〉
　図１１に示すＮＶＭは、ｎ個（ｎは２以上の偶数）のＮＭＣを有する。ｎ個のＮＭＣは互いに異なる配線ＮＷＬに電気的に接続されている。また、ｎ個のＮＭＣは１本の配線ＶＣＳと電気的に接続されている。ｎ個のＮＭＣを区別するために、［０］、［１］等の符号を用い、ｎ本の配線ＮＷＬを区別するために、＿０、＿１等の符号を用いることとする。 <NVM>
The NVM shown in FIG. 11 has n (n is an even number of 2 or more) NMC. The n NMCs are electrically connected to different interconnects NWL. In addition, n NMCs are electrically connected to one wiring VCS. In order to distinguish n NMCs, codes such as [0] and [1] are used, and in order to distinguish n wires NWL, codes such as _0 and _1 are used.
　ＮＭＣは１ビットのデータを保持することができるメモリ回路（メモリセルと呼ぶこともできる。）である。ＮＭＣは１つのトランジスタ、及び１つの容量素子を有するダイナミック・ランダム・アクセス・メモリ（ＤＲＡＭ）のメモリセルと同様の回路構成である。ＮＭＣはトランジスタＴｒ１及び容量素子Ｃｓを有する。容量素子ＣｓはＮＭＣの保持容量として機能する。配線ＶＣＳは、ＮＭＣの保持容量用の電源線であり、ここではＧＮＤが入力される。 The NMC is a memory circuit (also referred to as a memory cell) capable of holding 1-bit data. The NMC has a circuit configuration similar to that of a dynamic random access memory (DRAM) memory cell having one transistor and one capacitive element. The NMC has a transistor Tr1 and a capacitive element Cs. The capacitive element Cs functions as a storage capacitor of the NMC. The wiring VCS is a power supply line for the storage capacitance of the NMC, and GND is input here.
　トランジスタＴｒ１のゲート（第１ゲート）は、配線ＮＷＬと電気的に接続されている。トランジスタＴｒ１のソース又はドレインの一方は配線ＬＢＬ（または配線ＬＢＬＢ）と電気的に接続されている。容量素子Ｃｓの第１端子はトランジスタＴｒ１のソース又はドレインの他方と電気的に接続され、容量素子Ｃｓの第２端子はＶＣＳと電気的に接続されている。 The gate (first gate) of the transistor Tr1 is electrically connected to the wiring NWL. One of the source and the drain of the transistor Tr1 is electrically connected to the wiring LBL (or the wiring LBLB). The first terminal of the capacitive element Cs is electrically connected to the other of the source and the drain of the transistor Tr1, and the second terminal of the capacitive element Cs is electrically connected to the VCS.
　トランジスタＴｒ１は第２ゲートを有する。トランジスタＴｒ１の第２ゲートは配線ＢＧＬに電気的に接続されている。配線ＢＧＬは、トランジスタＴｒ１の第２ゲートの電位を制御するための信号が入力される信号線、あるいは一定電位が入力される電源線である。配線ＢＧＬの電位によって、トランジスタＴｒ１の閾値電圧を制御することができる。その結果、トランジスタＴｒ１がノーマリーオンになることを防ぐことができる。 The transistor Tr1 has a second gate. The second gate of the transistor Tr1 is electrically connected to the wiring BGL. The wiring BGL is a signal line to which a signal for controlling the potential of the second gate of the transistor Tr1 is input, or a power supply line to which a constant potential is input. The threshold voltage of the transistor Tr1 can be controlled by the potential of the wiring BGL. As a result, the transistor Tr1 can be prevented from being normally on.
　ＮＭＣ［０］乃至ＮＭＣ［ｎ−１］のうち半数は配線ＬＢＬに接続され、残りの半数は配線ＬＢＬＢに接続されている。図１１に示すＮＶＭは、メモリセルのレイアウト方式として折り返し型を適用した場合の回路図である。なお、折り返し型のメモリセルに関しては、後述の図１４で再び説明を行う。 Half of NMC [0] to NMC [n-1] are connected to the wiring LBL, and the other half are connected to the wiring LBLB. NVM shown in FIG. 11 is a circuit diagram in the case where a folding type is applied as a layout method of memory cells. The folded memory cell will be described again with reference to FIG. 14 described later.
　トランジスタＴｒ１としてＯＳトランジスタを用いることが好ましい。ＯＳトランジスタを用いることで、トランジスタＴｒ１のオフ電流を極めて小さくできる。 It is preferable to use an OS transistor as the transistor Tr1. By using the OS transistor, the off current of the transistor Tr1 can be extremely reduced.
　トランジスタＴｒ１のオフ電流を小さくすることで、ＮＭＣの保持時間を長くすることができる。オフ電流が極めて小さいとは、例えば、チャネル幅１μｍあたりのオフ電流が１００ｚＡ（ゼプトアンペア）以下であることをいう。なお、オフ電流は小さいほど好ましいため、この規格化されたオフ電流が１０ｚＡ／μｍ以下、あるいは１ｚＡ／μｍ以下とすることが好ましく、１０ｙＡ（ヨクトアンペア）／μｍ以下であることがより好ましい。１ｚＡは１×１０−２１Ａであり、１ｙＡは１×１０−２４Ａである。 By reducing the off-state current of the transistor Tr1, the retention time of the NMC can be extended. The extremely low off-state current means, for example, that the off-state current per 1 μm of the channel width is 100 zA (zepto amps) or less. The smaller the off-state current, the more preferable. Therefore, the standardized off-state current is preferably 10 zA / μm or less, or 1 zA / μm or less, and more preferably 10 yA (yoctamps) / μm or less. 1zA is 1 × 10 −21 A, and 1yA is 1 × 10 −24 A.
　トランジスタＴｒ１にＯＳトランジスタを用いることで、ＮＭＣの保持時間を長くすることができ、ＮＭＣを不揮発性メモリ回路として用いることができる。 By using an OS transistor for the transistor Tr1, the retention time of the NMC can be extended, and the NMC can be used as a non-volatile memory circuit.
　なお、ＮＭＣの数（ｎ）は８の倍数であることが好ましい。すなわち、ＮＶＭが保持できるデータのビット数は、８の倍数であることが好ましい。ＮＭＣを８の倍数とすることで、メモリセル１３０は、例えば１バイト（８ビット）、１ワード（３２ビット）、ハーフワード（１６ビット）など、それぞれの単位ごとにデータを扱うことができる。 The number (n) of NMCs is preferably a multiple of eight. That is, the number of bits of data that can be held by NVM is preferably a multiple of eight. By setting NMC to a multiple of 8, the memory cell 130 can handle data in units of one byte (8 bits), one word (32 bits), half words (16 bits), and the like.
〈ＬＰＣ〉
　ＬＰＣは、配線ＰＣＬ及び配線ＶＰＣと電気的に接続されている。配線ＰＣＬは、配線ＬＢＬ、ＬＢＬＢのプリチャージ動作制御用の信号を供給するための信号線である。配線ＶＰＣはプリチャージ電圧を供給するための電源線である。ＬＰＣは、トランジスタＴｅｑ１、Ｔｐｃ１、Ｔｐｃ２を有する。トランジスタＴｅｑ１、Ｔｐｃ１、Ｔｐｃ２のゲートは配線ＰＣＬに電気的に接続されている。トランジスタＴｅｑ１は配線ＬＢＬとＬＢＬＢと間の導通状態を制御する。トランジスタＴｐｃ１は配線ＬＢＬと配線ＶＰＣと間の導通状態を制御する。トランジスタＴｐｃ２は配線ＬＢＬＢと配線ＶＰＣと間の導通状態を制御する。 <LPC>
The LPC is electrically connected to the line PCL and the line VPC. The line PCL is a signal line for supplying a signal for controlling the precharge operation of the lines LBL and LBLB. The wiring VPC is a power supply line for supplying a precharge voltage. The LPC includes transistors Teq1, Tpc1, and Tpc2. Gates of the transistors Teq1, Tpc1, and Tpc2 are electrically connected to the wiring PCL. The transistor Teq1 controls conduction between the lines LBL and LBLB. The transistor Tpc1 controls a conduction state between the wiring LBL and the wiring VPC. The transistor Tpc2 controls conduction between the wiring LBLB and the wiring VPC.
　図１１の例では、トランジスタＴｅｑ１、Ｔｐｃ１、Ｔｐｃ２はｎチャネル型トランジスタであるが、これらをｐチャネル型トランジスタとしてもよい。あるいは、ＬＰＣにＴｅｑ１を設けなくてもよい。この場合、トランジスタＴｐｃ１、Ｔｐｃ２は、ｎチャネル型トランジスタ、ｐチャネル型トランジスタの何れでもよい。あるいは、ＬＰＣをトランジスタＴｅｑ１のみで構成することもできる。この場合もトランジスタＴｅｑ１はｎチャネル型トランジスタでも、ｐチャネル型トランジスタでもよい。トランジスタＴｅｑ１でなるＬＰＣは、配線ＬＢＬと配線ＬＢＬＢとの電位を平滑化することで、配線ＬＢＬと配線ＬＢＬＢのプリチャージを行う。 In the example of FIG. 11, the transistors Teq1, Tpc1, and Tpc2 are n-channel transistors, but they may be p-channel transistors. Alternatively, it is not necessary to provide Teq1 in the LPC. In this case, the transistors Tpc1 and Tpc2 may be either n-channel transistors or p-channel transistors. Alternatively, LPC can be configured with only the transistor Teq1. Also in this case, the transistor Teq1 may be an n-channel transistor or a p-channel transistor. The LPC including the transistor Teq1 performs precharging of the wiring LBL and the wiring LBLB by smoothing the potentials of the wiring LBL and the wiring LBLB.
　周辺回路１１１は、メモリセルアレイ１１０に設けられる各種の電源線（配線ＶＨＨ、ＶＬＬ、ＶＰＣ）への電位を供給する機能を有する。そのため、ＰＳＷ１４１がオフとなって、周辺回路１１１へのＶＤＤの供給が停止すると、これら電源線への電位の供給も停止することとなる。 Peripheral circuit 111 has a function of supplying a potential to various power supply lines (interconnects VHH, VLL, and VPC) provided in memory cell array 110. Therefore, when the PSW 141 is turned off and the supply of the VDD to the peripheral circuit 111 is stopped, the supply of the potential to the power supply lines is also stopped.
〈〈記憶装置１００の動作例〉〉 << Operation Example of Storage Device 100 >>
　図１２のタイミングチャートを用いて、記憶装置１００の動作例を説明する。図１２は、データの書き込み方式がライトスルー方式である動作例を示している。ここでは、データの読み出し動作には、ＮＶＭの何れか１のＮＭＣを選択し、選択されたＮＭＣのデータをＳＭＣで増幅して、ＢＬ、ＢＬＢに書き込む方式が採用されている。 An operation example of the storage device 100 will be described using the timing chart of FIG. FIG. 12 shows an operation example in which the data writing method is the write-through method. Here, in the data read operation, a method is selected in which one NMC in NVM is selected, data of the selected NMC is amplified by SMC, and the data is written in BL and BLB.
　図１２において、ｔ０、ｔ１等は時刻を表している。波形間に付された矢印は、記憶装置１００の動作の理解を容易にするためのものである。ＶＤＤＭは、記憶装置１００に設けられたＶＤＤ供給用の電源線である。ＰＳＷ１４１によって、ＶＤＤＭへのＶＤＤの供給が制御される。また、ＶＤＤＭ、ＶＰＣ、ＶＨＨ等について、点線で表されている波形は、電位が不確定であることを示している。また、ＶＤＤＭ等の配線の低レベル（Ｌレベル）はＧＮＤである。信号線のうち、ＰＣＬ、ＷＬの高レベル（Ｈレベル）はＶＤＤであり、ＮＷＬ＿０−ＮＷＬ＿［ｎ−１］の高レベルはＶＨＭである。 In FIG. 12, t0, t1, etc. represent time. The arrows between the waveforms are to facilitate the understanding of the operation of the storage device 100. VDDM is a power supply line provided in the storage device 100 for VDD supply. The PSW 141 controls the supply of VDD to VDDM. Also, with respect to VDDM, VPC, VHH, etc., the waveforms represented by dotted lines indicate that the potential is indeterminate. Also, the low level (L level) of the wiring such as VDDM is GND. Among the signal lines, the high level (H level) of PCL and WL is VDD, and the high level of NWL_0-NWL_ [n-1] is VHM.
　なお、ＮＷＬ＿０−ＮＷＬ＿［ｎ−１］の高レベルがＶＨＭであるのは、トランジスタＴｒ１の閾値電圧がトランジスタＴａｃ１等の他のトランジスタよりも高い場合を想定しているからである。ＮＷＬ＿０−ＮＷＬ＿［ｎ−１］にＶＤＤを印加することで、ＮＶＭのデータの書き込み及び読み出しが可能であれば、ＮＷＬ＿０−ＮＷＬ＿［ｎ−１］の高レベルをＶＤＤとすることができる。この場合、記憶装置１００にＶＨＭ用のＰＳＷ１４２は設けなくてもよい（図１０参照）。 Note that the high level of NWL_0-NWL_ [n-1] is VHM because it is assumed that the threshold voltage of the transistor Tr1 is higher than that of the other transistors such as the transistor Tac1. By applying VDD to NWL_0-NWL_ [n-1], the high level of NWL_0-NWL_ [n-1] can be VDD, as long as writing and reading of NVM data are possible. In this case, the storage device 100 may not have the PSW 142 for VHM (see FIG. 10).
（パワーゲーティング）
　まず、記憶装置１００のパワーゲーティング動作について説明する。ｔ０−ｔ１では、記憶装置１００は、ＶＤＤの供給が遮断されている電源オフ（ＰＯＷＥＲ　ＯＦＦ）期間である。ｔ１以降は、記憶装置１００は、ＶＤＤが供給されている電源オン（ＰＯＷＥＲ　ＯＮ）期間である。 (Power gating)
First, the power gating operation of the storage device 100 will be described. At t0 to t1, the storage device 100 is in a power off period during which the supply of VDD is cut off. After t1, the storage device 100 is a power on period during which VDD is supplied.
　ｔ０でＰＳＷ１４１がオフになると、ＶＤＤＭの電位は下がり、やがてＧＮＤとなる。周辺回路１１１へのＶＤＤの供給が遮断されるためＷＬ、ＮＷＬ＿０−ＮＷＬ＿［ｎ−１］、ＰＣＬ、ＶＰＣもＧＮＤとなる。ｔ１でＰＳＷ１４１がオンとなると、ＶＤＤＭが充電され、やがて、その電位はＶＤＤまで上昇する。ｔ１−ｔ２が電源復帰に要する時間である。またＰＳＷ１４１をオン、オフするのと連動して、ＰＳＷ１４２もオン、オフするとよい。 When the PSW 141 is turned off at t0, the potential of the VDDM falls and eventually becomes GND. Since the supply of VDD to the peripheral circuit 111 is cut off, WL, NWL_0-NWL_ [n-1], PCL, and VPC also become GND. When PSW 141 is turned on at t1, VDDM is charged, and eventually its potential rises to VDD. t1-t2 is the time required for power supply recovery. Further, in conjunction with turning on and off the PSW 141, the PSW 142 may also be turned on and off.
（初期化（ＩＮＴＩＡＬＩＺＡＴＩＯＮ））
　ｔ２−ｔ３では、記憶装置１００を初期状態にするための初期化動作が行われる。具体的には、ＶＰＣ、ＶＨＨ及びＶＬＬはＶＤＤ／２とされる。ビット線対（ＢＬ、ＢＬＢ）及びローカルビット線対（ＬＢＬ、ＬＢＬＢ）はそれぞれプリチャージされ、ＶＤＤ／２とする。ビット線対のプリチャージは列ドライバ１２４によって行われ、ローカルビット線対のプリチャージはＬＰＣによって行われる。ＰＣＬを高レベル（Ｈレベル）にすることで、トランジスタＴｅｑ１、Ｔｐｃ１、Ｔｐｃ２がオンとなり、ＬＢＬ、ＬＢＬＢのプリチャージと電位の平滑化が行われる。 (Initialization (INTIALIZATION))
At t2-t3, an initialization operation for initializing the storage device 100 is performed. Specifically, VPC, VHH and VLL are set to VDD / 2. The bit line pair (BL, BLB) and the local bit line pair (LBL, LBLB) are each precharged to VDD / 2. Precharging of the bit line pair is performed by the column driver 124, and precharging of the local bit line pair is performed by the LPC. By setting PCL to a high level (H level), the transistors Teq1, Tpc1, and Tpc2 are turned on, and precharging of LBL and LBLB and smoothing of the potential are performed.
（書き込み（ＷＲＩＴＥ））
　書き込みアクセスがあると、列ドライバ１２４によってビット線対をプリチャージ状態から浮遊状態にする。また、ＬＰＣによって、ローカルビット線対をプリチャージ状態から浮遊状態にする。これはＰＣＬをＨレベルからＬレベルにすることで行われる。 (WRITE (WRITE))
When there is a write access, the column driver 124 brings the bit line pair into the floating state from the precharged state. Further, the local bit line pair is brought from the precharged state to the floating state by LPC. This is done by changing PCL from H level to L level.
　次に、列ドライバ１２４によって、データＤＡ１がビット線対に書き込まれる。ここで、ＢＬがＶＤＤであれば、ＢＬＢはＧＮＤである。行デコーダ１２１によって行アドレスがデコードされたタイミングで、書き込み対象行のＮＷＬ＿０−ＮＷＬ＿［ｎ−１］の何れか１本をＨレベルにする。ここでは、ＮＷＬ＿１をＨレベルにして、ＮＭＣ［１］のトランジスタＴｒ１をオンにする。また、ＮＷＬ＿１が選択された後、ＶＨＨはＶＤＤとされ、ＶＬＬはＧＮＤとされるため、ＳＭＣはアクティブとなる。また、ＮＷＬ＿１が選択された後、書き込み対象行のＷＬをＨレベルにして、トランジスタＴａｃ１、Ｔａｃ２をオンにする。なお、ＮＷＬ＿１をＨレベルにするタイミングでＷＬをＨレベルにしてもよい。 Next, data DA1 is written to the bit line pair by column driver 124. Here, if BL is VDD, BLB is GND. At the timing when the row address is decoded by the row decoder 121, one of NWL_0-NWL_ [n-1] of the write target row is set to H level. Here, NWL_1 is set to H level to turn on the transistor Tr1 of NMC [1]. Further, after NWL_1 is selected, VHH is set to VDD and VLL is set to GND, so that SMC becomes active. Further, after NWL_1 is selected, the WL of the write target row is set to the H level to turn on the transistors Tac1 and Tac2. Note that WL may be set to H level at the timing of setting NWL_1 to H level.
　トランジスタＴａｃ１、Ｔａｃ２がオンになることで、ローカルビット線対にデータＤＡ１が書き込まれる。このとき、ＳＭＣはアクティブであるので、ＳＭＣにデータＤＡ１が書き込まれる。かつ、ＮＶＭにおいて書き込み対象となっているＮＭＣ［１］のトランジスタＴｒ１はオンであるので、ＮＭＣ［１］にもデータＤＡ１が書き込まれることとなる。一定期間ＷＬをＨレベルにした後にＬレベルにする。ＷＬがＬレベルになることで、ＳＭＣとビット線対との間は非導通状態となる。この状態になったら、ＮＷＬ＿１をＬレベルにして、ＮＭＣ［１］を非選択状態に戻す。ＮＷＬ＿１をＬレベルにした後、ＶＨＨ、ＶＬＬの電位をＶＤＤ／２に戻し、ＳＭＣを非アクティブにする。ＳＭＣを非アクティブにすることで、ＳＭＣからはデータＤＡ１は消失するが、データＤＡ１はＮＭＣ［１］で長時間保持できるので、問題はない。 When the transistors Tac1 and Tac2 are turned on, the data DA1 is written to the local bit line pair. At this time, since SMC is active, data DA1 is written to SMC. In addition, since the transistor Tr1 of the NMC [1] to be written in the NVM is on, the data DA1 is also written to the NMC [1]. After WL is at H level for a predetermined period, L level is set. With WL at L level, the SMC and the bit line pair become nonconductive. When this state is reached, NWL_1 is set to L level, and NMC [1] is returned to the non-selected state. After setting NWL_1 to L level, the potentials of VHH and VLL are returned to VDD / 2, and SMC is inactivated. Deactivating the SMC causes the data DA1 to disappear from the SMC, but there is no problem since the data DA1 can be held for a long time by the NMC [1].
　ＮＷＬ＿１をＬレベルにした後、ビット線対及びローカルビット線対のプリチャージ動作を開始し、これらをＶＤＤ／２にプリチャージしている。 After setting NWL_1 to L level, the precharge operation of the bit line pair and the local bit line pair is started, and these are precharged to VDD / 2.
（非アクセス（ＮＯＮ−ＡＣＣＥＳＳ））
　ｔ４−ｔ５では、記憶装置１００は、ホスト装置からアクセス要求がない非アクセス状態である。ＰＣＬはＨレベルであり、ＷＬ及びＮＷＬ＿０−ＮＷＬ＿［ｎ−１］はＬレベルである。ＶＰＣ、ＶＨＨ及びＶＬＬはＶＤＤ／２である。ビット線対及びローカルビット線対はＶＤＤ／２にプリチャージされている。ｔ４−ｔ５では、ＳＭＣは動作させる必要がないので、ＶＨＨ、ＶＬＬをＶＤＤ／２にしておくことで、ＳＭＣのリーク電流を低減することができる。よって、記憶装置１００全体の消費電力を効果的に低減することができる。 (Non-Access (NON-ACCESS))
At t4-t5, the storage device 100 is in the non-access state where there is no access request from the host device. PCL is at H level, and WL and NWL_0-NWL_ [n-1] are at L level. VPC, VHH and VLL are VDD / 2. The bit line pair and the local bit line pair are precharged to VDD / 2. At t4-t5, SMC does not need to be operated, so by setting VHH and VLL to VDD / 2, the leakage current of SMC can be reduced. Thus, the power consumption of the entire storage device 100 can be effectively reduced.
（読み出し（ＲＥＡＤ））
　ｔ５−ｔ６では、記憶装置１００は、ホスト装置の読み出しアクセス要求に対する動作を行っている。ここでは、ＮＶＭのＮＭＣ［１］に、ホスト装置の処理に必要なデータが記憶されていることとする。 (Read (READ))
At t5 to t6, the storage device 100 performs an operation for the read access request of the host device. Here, it is assumed that data necessary for processing of the host device is stored in NMC [1] of NVM.
　読み出しアクセスがあると、列ドライバ１２４により、ビット線対はプリチャージ状態から浮遊状態とされ、ＬＰＣにより、ローカルビット線対はプリチャージ状態から浮遊状態とされる。次に、ＮＷＬ＿１をＨレベルにして、ＮＭＣ［１］のトランジスタＴｒ１をオンにする。ローカルビット線対には、データＤＡ１が書き込まれる。ＮＷＬ＿１をＨレベルした後、ＶＨＨをＶＤＤにし、かつＶＬＬをＧＮＤにして、ＳＭＣをアクティブにする。このとき、ＳＭＣは差動増幅回路として機能し、ローカルビット線対のデータＤＡ１を増幅する。ＳＭＣをアクティブにした後、ＷＬをＨレベルにして、ローカルビット線対のデータＤＡ１をビット線対に書き込む。ビット線対に書き込まれたデータＤＡ１は列ドライバ１２４によって読み出される。 When there is a read access, the column driver 124 brings the bit line pair to the floating state from the precharged state, and the LPC brings the local bit line pair to the floating state from the precharged state. Next, NWL_1 is set to H level to turn on the transistor Tr1 of NMC [1]. Data DA1 is written to the local bit line pair. After NWL_1 is at H level, VHH is set to VDD and VLL is set to GND to activate SMC. At this time, SMC functions as a differential amplifier circuit to amplify data DA1 of the local bit line pair. After activating SMC, WL is set to H level to write data DA1 of the local bit line pair to the bit line pair. The data DA1 written to the bit line pair is read by the column driver 124.
　読み出し動作の終了動作は、書き込み動作の場合と同様であり、初期化動作と非アクセス状態にするための動作である。まず、ＷＬをＬレベルにする。次にＮＷＬ＿１をＬレベルにする。次にＶＨＨ及びＶＬＬをＶＤＤ／２にして、ＳＭＣを非アクティブにする。また、ＮＷＬ＿１をＬレベルにした後、ビット線対及びローカルビット線対のプリチャージを開始する。 The end operation of the read operation is the same as that of the write operation, and is an operation for setting the initialization operation and the non-access state. First, set WL to L level. Next, set NWL_1 to the L level. Next, set VHH and VLL to VDD / 2 to deactivate SMC. Also, after setting NWL_1 to L level, precharging of the bit line pair and the local bit line pair is started.
　図１２の例では、書き込み動作、読み出し動作の最後に、ＰＣＬをＨレベルに遷移させてローカルビット線対のプリチャージを開始しているが、このタイミングは図１２の例に限定されない。ＮＷＬ＿１がＬレベルになったときからＷＬをＨレベルにするときまでの間に、ＰＣＬを立ち上げて、ローカルビット線対のプリチャージを開始すればよい。 In the example of FIG. 12, at the end of the write operation and the read operation, PCL is transited to H level to start precharging of the local bit line pair, but this timing is not limited to the example of FIG. In a period from when NWL_1 goes to L level to when WL goes to H level, PCL may be raised to start precharging of the local bit line pair.
　また、図１２の例では、非アクセス状態では、ＰＣＬをＨレベルに維持することで、ローカルビット線対をＶＤＤ／２に固定しているが、ＰＣＬをＬレベルにして、ローカルビット線対を浮遊状態にしておいてもよい。この場合、書き込み動作、及び読み出し動作の開始時に、まず、ＰＣＬをＬレベルからＨレベルにして、ローカルビット線対のプリチャージを行えばよい。 Further, in the example of FIG. 12, the local bit line pair is fixed at VDD / 2 by keeping the PCL at the H level in the non-access state, but the PCL is set to the L level to set the local bit line pair. It may be in a floating state. In this case, at the start of the write operation and the read operation, first, PCL may be changed from the L level to the H level to precharge the local bit line pair.
〈〈メモリセルアレイのデバイス構造〉〉
　記憶装置１００において、ＮＶＭのトランジスタＴｒ１はＯＳトランジスタとし、他のトランジスタは、例えば、Ｓｉトランジスタ等とすることができる。この場合、メモリセルアレイ１１０を、Ｓｉトランジスタで構成される回路上に、ＯＳトランジスタで構成される回路が積層されているデバイス構造とすることができる。図１３に、メモリセルアレイ１１０のデバイス構造例を模式的に示す。 <Device Structure of Memory Cell Array>
In the storage device 100, the NVM transistor Tr1 can be an OS transistor, and the other transistors can be, for example, a Si transistor or the like. In this case, the memory cell array 110 can have a device structure in which a circuit including an OS transistor is stacked on a circuit including an Si transistor. An example of the device structure of the memory cell array 110 is schematically shown in FIG.
〈メモリセルアレイ〉
　図１３の例では、メモリセルアレイ１１０Ａ上に、メモリセルアレイ１１０Ｂが積層されている。メモリセルアレイ１１０ＡにはＳＭＣ及びＬＰＣがマトリクス状に設けられている。メモリセルアレイ１１０ＢにはＮＶＭがマトリクス状に設けられている。メモリセルアレイ１１０Ａは応答速度が速いメモリ部Ａを構成し、メモリセルアレイ１１０Ｂはデータの長期貯蔵用のメモリ部Ｂを構成する。メモリセルアレイ１１０Ｂをメモリセルアレイ１１０Ａに積層することで、記憶装置１００の大容量化と小型化を効果的に行える。 <Memory cell array>
In the example of FIG. 13, the memory cell array 110B is stacked on the memory cell array 110A. The memory cell array 110A is provided with SMC and LPC in a matrix. NVMs are provided in a matrix on the memory cell array 110B. The memory cell array 110A constitutes a memory unit A having a high response speed, and the memory cell array 110B constitutes a memory unit B for long-term storage of data. By stacking the memory cell array 110B on the memory cell array 110A, the capacity and size of the storage device 100 can be effectively increased.
　メモリセルアレイ１１０Ｂをメモリセルアレイ１１０Ａに積層することで、メモリセルアレイ１１０の大容量化と小型化が可能となる。ＣＭＯＳ型ＳＲＡＭのメモリセルと比較した場合、メモリセル１３０のビット当たりの面積をより小さくすることができる。 By stacking the memory cell array 110B on the memory cell array 110A, the capacity and size of the memory cell array 110 can be increased. The area per bit of the memory cell 130 can be further reduced as compared with the memory cell of the CMOS type SRAM.
　ＮＶＭで構成されるメモリセルアレイ１１０Ｂはフラッシュメモリ、ＭＲＡＭ（磁気抵抗ランダムアクセスメモリ）、ＰＲＡＭ（相変化ランダムアクセスメモリ）などの他の不揮発性メモリと比較して、ＣＭＯＳ回路との親和性に非常に優れている。フラッシュメモリは駆動に高電圧が必要である。ＭＲＡＭ、ＰＲＡＭは電流駆動型メモリであるため、電流駆動用の素子や回路が必要となる。これに対して、ＮＶＭは、トランジスタＴｒ１のオン、オフの制御によって動作する。つまり、ＮＶＭはＣＭＯＳ回路と同じように電圧駆動型のトランジスタで構成される回路であり、また、低電圧で駆動することができる。そのため、１つのチップにプロセッサと記憶装置１００とを組み込むことが容易である。また、記憶装置１００は、性能を低下させずに、ビット当たりの面積を低減することができる。また、記憶装置１００は消費電力を低減することができる。また、記憶装置１００は電源オフ状態でもデータを記憶することが可能であるので、記憶装置１００のパワーゲーティングが可能である。 The memory cell array 110B configured by NVM is highly compatible with CMOS circuits as compared to other nonvolatile memories such as flash memory, MRAM (magnetoresistive random access memory) and PRAM (phase change random access memory). Are better. Flash memory requires a high voltage to drive. Since the MRAM and PRAM are current driven memories, elements and circuits for current driving are required. On the other hand, the NVM operates by on / off control of the transistor Tr1. That is, NVM is a circuit composed of voltage-driven transistors in the same manner as a CMOS circuit, and can be driven at a low voltage. Therefore, it is easy to incorporate the processor and the storage device 100 into one chip. Also, the storage device 100 can reduce the area per bit without degrading the performance. In addition, the storage device 100 can reduce power consumption. Further, since the storage device 100 can store data even in the power-off state, power gating of the storage device 100 is possible.
　ＳＲＡＭは高速であるため、標準的なプロセッサのオンチップ・キャッシュメモリに使用されている。ＳＲＡＭは待機時でも電力を消費してしまうということ、また大容量化が難しいという短所がある。例えば、モバイル機器用のプロセッサでは、オンチップ・キャッシュメモリの待機時の消費電力がプロセッサ全体の平均消費電力に占める割合の８０％に達するといわれている。これに対して、記憶装置１００は、読み出し、書き込みが速いというＳＲＡＭの長所を生かしつつ、ＳＲＡＭの短所が解消されているＲＡＭである。そのため、オンチップ・キャッシュメモリに記憶装置１００を適用することは、プロセッサ全体の消費電力の低減に有用である。記憶装置１００はビット当たりの面積が小さいため、大容量化が容易であるので、キャッシュメモリ等に好適である。 Because of their high speed, SRAMs are used for standard processor on-chip cache memories. SRAM has the disadvantages that it consumes power even during standby and that it is difficult to increase the capacity. For example, in processors for mobile devices, it is said that the standby power consumption of on-chip cache memory reaches 80% of the ratio of the average power consumption of the entire processor. On the other hand, the storage device 100 is a RAM in which the disadvantages of the SRAM are eliminated while taking advantage of the advantage of the SRAM that reading and writing are fast. Therefore, applying the storage device 100 to the on-chip cache memory is useful for reducing the power consumption of the entire processor. The storage device 100 is suitable for a cache memory or the like because the storage device 100 has a small area per bit and can easily be increased in capacity.
　次に、ＮＶＭのレイアウト方式（折り返し型、ツインセル型、開放型）について、図１４乃至図１５を用いて説明を行う。なお、図１４乃至図１５はＮＶＭが８ビットのデータを記憶する（ＮＶＭはＮＭＣ［０］乃至ＮＭＣ［７］を有する）例を示している。 Next, an NVM layout method (folded type, twin cell type, open type) will be described using FIGS. 14 to 15. FIG. 14 to 15 show an example in which NVM stores 8-bit data (NVM has NMC [0] to NMC [7]).
〈折り返し型〉
　図１４に示す回路図は、メモリセル１３０のレイアウト方式として折り返し型を適用した例である。ＳＭＣ及びＬＰＣが形成されている領域上に、ＮＭＣ［０］乃至ＮＭＣ［７］が設けられている。折り返し型のメモリセル１３０において、ＮＭＣは配線ＬＢＬに接続されるものと、配線ＬＢＬＢに接続されるものに分類される。折り返し型を適用することで、メモリセル１３０は、配線ＮＷＬの電位の変化によって配線ＬＢＬ又は配線ＬＢＬＢにデータを出力する。例えば、配線ＬＢＬに読み出しデータが出力される場合、配線ＬＢＬＢが配線ＬＢＬから距離を設けることで、配線ＬＢＬに与えられる読み出しデータが、配線ＬＢＬＢに対するノイズになることを低減することができる。 <Fold type>
The circuit diagram shown in FIG. 14 is an example in which a folded type is applied as a layout method of the memory cell 130. NMC [0] to NMC [7] are provided on the region where SMC and LPC are formed. In the folded memory cell 130, the NMC is classified into one connected to the wiring LBL and one connected to the wiring LBLB. By applying the folded type, the memory cell 130 outputs data to the wiring LBL or the wiring LBLB in accordance with the change in the potential of the wiring NWL. For example, in the case where read data is output to the wiring LBL, the distance between the wiring LBL and the wiring LBL can be reduced, whereby the read data to be supplied to the wiring LBL can be reduced as noise to the wiring LBLB.
〈開放型〉
　図１５に示す回路図は、メモリセル１３０のレイアウト方式として開放型を適用した例である。折り返し型と同様に、ＮＭＣは１つのトランジスタと１つの容量素子で構成されている。開放型のメモリセル１３０において、ＮＭＣは配線ＬＢＬに接続されるものと、配線ＬＢＬＢに接続されるものに分類される。図１５において、１つの配線ＮＷＬに２つのＮＭＣが接続されているように見えるが、２つのＮＭＣのうち１つは隣り合うメモリセル１３０に接続されたものである。開放型はＮＭＣを高集積化することが可能で、他のレイアウト方式に比べて、記憶装置１００が記憶できるデータの容量を大きくすることができる。 <Open type>
The circuit diagram shown in FIG. 15 is an example in which an open type is applied as a layout method of the memory cell 130. Like the folded type, the NMC is composed of one transistor and one capacitive element. In the open memory cell 130, the NMC is classified into one connected to the wiring LBL and one connected to the wiring LBLB. In FIG. 15, two NMCs appear to be connected to one interconnect NWL, but one of the two NMCs is connected to an adjacent memory cell 130. In the open type, the NMC can be highly integrated, and the capacity of data that can be stored in the storage device 100 can be increased compared to other layout methods.
〈ツインセル型〉
　図１６に示す回路図は、はメモリセル１３０のレイアウト方式としてツインセル型を適用した例である。図１６において、ＮＭＣは２つのトランジスタと２つの容量素子で構成されている。すなわち、ＮＭＣは相補的な２つのメモリセルを有する。ツインセル型のメモリセル１３０は、２つのメモリセルに保持された相補データを１ビットとして扱う。 <Twin cell type>
The circuit diagram shown in FIG. 16 is an example in which a twin cell type is applied as a layout method of the memory cell 130. In FIG. 16, NMC is composed of two transistors and two capacitive elements. That is, the NMC has two complementary memory cells. The twin-cell memory cell 130 treats complementary data held in two memory cells as one bit.
　ＮＭＣは、一対のメモリセルを備えることで相補データを長時間保持することができる。ＮＭＣが相補データを保持していることで、ＮＭＣで保持している相補データを読み出すときには、ＳＭＣは差動増幅回路として機能することができる。このため、ツインセル型は、一対のメモリセルの一方が保持している電圧と、一対のメモリセルの他方が保持している電圧との電圧差が小さくとも、信頼性の高い読み出し動作ができる。 The NMC can hold complementary data for a long time by providing a pair of memory cells. Since the NMC holds the complementary data, the SMC can function as a differential amplifier circuit when reading the complementary data held by the NMC. Therefore, the twin-cell type can perform highly reliable read operation even if the voltage difference between the voltage held by one of the pair of memory cells and the voltage held by the other of the pair of memory cells is small.
〈記憶装置１００の断面図〉
　図１７は、記憶装置１００の断面図の一例を示している。図１７に示す記憶装置１００は、下から順に積層された層Ｌ１、層Ｌ２、層Ｌ３、層Ｌ４を有する。 <Cross-sectional view of storage device 100>
FIG. 17 illustrates an example of a cross-sectional view of the storage device 100. The memory device 100 illustrated in FIG. 17 includes a layer L1, a layer L2, a layer L3, and a layer L4 stacked in order from the bottom.
　層Ｌ１は、トランジスタＭ１と、基板３００と、素子分離層３０１と、絶縁体３０２と、プラグ３１０などを有する。 The layer L1 includes the transistor M1, the substrate 300, the element isolation layer 301, the insulator 302, the plug 310, and the like.
　層Ｌ２は、絶縁体３０３と、配線３２０と、絶縁体３０４と、プラグ３１１などを有する。 The layer L2 includes an insulator 303, a wiring 320, an insulator 304, a plug 311, and the like.
　層Ｌ３は、絶縁体２１４と、絶縁体２１６と、トランジスタＴｒ１と、プラグ３１２と、絶縁体２８２と、配線３２１などを有する。トランジスタＴｒ１の第１ゲートは配線ＮＷＬとしての機能を有し、トランジスタＴｒ１の第２ゲートは配線ＢＧＬとしての機能を有する。図２２は、トランジスタＴｒ１としてＯＳトランジスタを用いた例を示している。 The layer L3 includes an insulator 214, an insulator 216, a transistor Tr1, a plug 312, an insulator 282, a wiring 321, and the like. The first gate of the transistor Tr1 has a function as a wiring NWL, and the second gate of the transistor Tr1 has a function as a wiring BGL. FIG. 22 shows an example in which an OS transistor is used as the transistor Tr1.
　層Ｌ４は、容量素子Ｃｓと、プラグ３１３と、配線ＬＢＬなどを有する。容量素子Ｃｓは導電体３２２と、導電体３２３と、絶縁体３０５で成る。 The layer L4 includes a capacitor Cs, a plug 313, a wiring LBL, and the like. The capacitive element Cs includes the conductor 322, the conductor 323, and the insulator 305.
　次に図１８を用いてトランジスタＭ１の詳細について説明を行う。図１８（Ａ）左側はトランジスタＭ１のチャネル長方向の断面図であり、図１８（Ａ）の右側はトランジスタＭ１のチャネル幅方向の断面図を示している。 Next, details of the transistor M1 will be described with reference to FIG. 18A is a cross-sectional view of the transistor M1 in the channel length direction, and the right side of FIG. 18A is a cross-sectional view of the transistor M1 in the channel width direction.
　トランジスタＭ１は基板３００上に設けられ、素子分離層３０１によって隣接する他のトランジスタと分離されている。素子分離層３０１として、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン等を用いることができる。なお、本明細書において、酸化窒化物とは、窒素よりも酸素の含有量が多い化合物をいい、窒化酸化物とは、酸素よりも窒素の含有量が多い化合物をいう。 The transistor M1 is provided over the substrate 300 and is separated from other adjacent transistors by the element separation layer 301. As the element isolation layer 301, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like can be used. In the present specification, oxynitride refers to a compound having a higher content of oxygen than nitrogen, and nitrided oxide refers to a compound having a higher content of nitrogen than oxygen.
　基板３００としては、シリコンや炭化シリコンからなる単結晶半導体基板、多結晶半導体基板、シリコンゲルマニウムからなる化合物半導体基板や、ＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板などを用いることができる。また、基板３００として、例えば、ガラス基板、石英基板、プラスチック基板、金属基板、貼り合わせフィルム、繊維状の材料を含む紙、又は基材フィルム、などを用いてもよい。また、ある基板を用いて半導体素子を形成し、その後、別の基板に半導体素子を転置してもよい。 As the substrate 300, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI (Silicon On Insulator) substrate, or the like can be used. In addition, as the substrate 300, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a bonded film, a paper containing a fibrous material, a base film, or the like may be used. Alternatively, a semiconductor element may be formed using a certain substrate and then transferred to another substrate.
　また、基板３００として、可とう性基板を用いてもよい。なお、可とう性基板上にトランジスタを設ける方法としては、非可とう性の基板上にトランジスタを作製した後、トランジスタを剥離し、可とう性基板である基板３００に転置する方法もある。その場合には、非可とう性基板とトランジスタとの間に剥離層を設けるとよい。なお、基板３００として、繊維を編みこんだシート、フィルム又は箔などを用いてもよい。また、基板３００が伸縮性を有してもよい。また、基板３００は、折り曲げや引っ張りをやめた際に、元の形状に戻る性質を有してもよい。又は、元の形状に戻らない性質を有してもよい。基板３００の厚さは、例えば、５μｍ以上７００μｍ以下、好ましくは１０μｍ以上５００μｍ以下、さらに好ましくは１５μｍ以上３００μｍ以下とする。基板３００を薄くすると、半導体装置を軽量化することができる。また、基板３００を薄くすることで、ガラスなどを用いた場合にも伸縮性を有する場合や、折り曲げや引っ張りをやめた際に、元の形状に戻る性質を有する場合がある。そのため、落下などによって基板３００上の半導体装置に加わる衝撃などを緩和することができる。即ち、丈夫な半導体装置を提供することができる。可とう性基板である基板３００としては、例えば、金属、合金、樹脂もしくはガラス、又はそれらの繊維などを用いることができる。可とう性基板である基板３００は、線膨張率が低いほど環境による変形が抑制されて好ましい。可とう性基板である基板３００としては、例えば、線膨張率が１×１０−３／Ｋ以下、５×１０−５／Ｋ以下、または１×１０−５／Ｋ以下である材質を用いればよい。樹脂としては、例えば、ポリエステル樹脂、ポリオレフィン樹脂、ポリアミド（ナイロン、アラミドなど）樹脂、ポリイミド樹脂、ポリカーボネート樹脂、アクリル樹脂、ポリテトラフルオロエチレン（ＰＴＦＥ）樹脂などがある。特に、アラミド樹脂は、線膨張率が低いため、可とう性基板である基板３００として好適である。 Alternatively, a flexible substrate may be used as the substrate 300. Note that as a method for providing a transistor on a flexible substrate, there is a method in which the transistor is peeled off after being manufactured on a non-flexible substrate and transposed to the substrate 300 which is a flexible substrate. In that case, a release layer may be provided between the non-flexible substrate and the transistor. Note that as the substrate 300, a sheet, a film, a foil, or the like in which fibers are woven may be used. In addition, the substrate 300 may have stretchability. In addition, the substrate 300 may have a property of returning to the original shape when bending or pulling is stopped. Or you may have the property which does not return to an original shape. The thickness of the substrate 300 is, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, further preferably 15 μm to 300 μm. When the substrate 300 is thinned, the weight of the semiconductor device can be reduced. In addition, when the substrate 300 is made thin, it may have elasticity even when glass or the like is used, or may return to its original shape when bending or pulling is stopped. Therefore, an impact or the like applied to the semiconductor device over the substrate 300 due to a drop or the like can be alleviated. That is, a robust semiconductor device can be provided. As the substrate 300 which is a flexible substrate, for example, a metal, an alloy, a resin or glass, or a fiber thereof can be used. As the substrate 300 which is a flexible substrate has a lower coefficient of linear expansion, deformation due to the environment is preferably suppressed. As the substrate 300 which is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 −3 / K or less, 5 × 10 −5 / K or less, or 1 × 10 −5 / K or less is used. Good. Examples of the resin include polyester resin, polyolefin resin, polyamide (nylon, aramid etc.) resin, polyimide resin, polycarbonate resin, acrylic resin, polytetrafluoroethylene (PTFE) resin and the like. In particular, since an aramid resin has a low coefficient of linear expansion, it is suitable as the substrate 300 which is a flexible substrate.
　本実施の形態では、一例として、基板３００に単結晶シリコンウェハを用いた例を示している。 In this embodiment, an example in which a single crystal silicon wafer is used as the substrate 300 is shown as an example.
　トランジスタＭ１は、ウェル３５１に設けられたチャネル形成領域３５２、不純物領域３５３及び不純物領域３５４と、該不純物領域に接して設けられた導電性領域３５５及び導電性領域３５６と、チャネル形成領域３５２上に設けられたゲート絶縁体３５８と、ゲート絶縁体３５８上に設けられたゲート電極３５７とを有する。なお、導電性領域３５５、３５６には、金属シリサイド等を用いてもよい。 The transistor M1 includes a channel formation region 352, an impurity region 353 and an impurity region 354 provided in the well 351, a conductive region 355 and a conductive region 356 provided in contact with the impurity region, and the channel formation region 352. A gate insulator 358 provided and a gate electrode 357 provided on the gate insulator 358 are provided. Note that for the conductive regions 355 and 356, metal silicide or the like may be used.
　図１８（Ａ）において、トランジスタＭ１はチャネル形成領域３５２が凸形状を有し、その側面及び上面に沿ってゲート絶縁体３５８及びゲート電極３５７が設けられている。このような形状を有するトランジスタをＦＩＮ型トランジスタと呼ぶ。本実施の形態では、半導体基板の一部を加工して凸部を形成する場合を示したが、ＳＯＩ基板を加工して凸形状を有する半導体層を形成してもよい。 In FIG. 18A, in the transistor M1, the channel formation region 352 has a convex shape, and the gate insulator 358 and the gate electrode 357 are provided along the side surface and the top surface. A transistor having such a shape is called a FIN transistor. In this embodiment mode, a case where a convex portion is formed by processing a part of a semiconductor substrate is described; however, a semiconductor layer having a convex shape may be formed by processing an SOI substrate.
　本実施の形態では、一例として、トランジスタＭ１としてＳｉトランジスタを適用した例を示している。トランジスタＭ１は、ｎチャネル型のトランジスタ又はｐチャネル型のトランジスタのいずれでもよく、回路によって適切なトランジスタを用いればよい。 In this embodiment, an example in which a Si transistor is applied as the transistor M1 is shown as an example. The transistor M1 may be either an n-channel transistor or a p-channel transistor, and a suitable transistor may be used depending on the circuit.
　なお、トランジスタＭ１として、プレーナー型のトランジスタを用いてもよい。その場合の例を図１８（Ｂ）に示す。図１８（Ｂ）左側はトランジスタＭ１のチャネル長方向の断面図であり、図１８（Ｂ）の右側はトランジスタＭ１のチャネル幅方向の断面図を示している。 Note that a planar transistor may be used as the transistor M1. An example in that case is shown in FIG. The left side of FIG. 18B is a cross-sectional view of the transistor M1 in the channel length direction, and the right side of FIG. 18B is a cross-sectional view of the transistor M1 in the channel width direction.
　図１８（Ｂ）に示すトランジスタＭ１は、ウェル３６１に設けられたチャネル形成領域３６２、低濃度不純物領域３７１及び低濃度不純物領域３７２と、高濃度不純物領域３６３及び高濃度不純物領域３６４と、該高濃度不純物領域に接して設けられた導電性領域３６５及び導電性領域３６６と、チャネル形成領域３６２上に設けられたゲート絶縁体３６８と、ゲート絶縁体３６８上に設けられたゲート電極３６７と、ゲート電極３６７の側壁に設けられた側壁絶縁層３６９及び側壁絶縁層３７０を有する。なお、導電性領域３６５、３６６には、金属シリサイド等を用いてもよい。 A transistor M1 illustrated in FIG. 18B includes a channel formation region 362, a low concentration impurity region 371, a low concentration impurity region 372, a high concentration impurity region 363, and a high concentration impurity region 364 provided in the well 361; A conductive region 365 and a conductive region 366 provided in contact with the concentration impurity region, a gate insulator 368 provided on the channel formation region 362, a gate electrode 367 provided on the gate insulator 368, and a gate Side wall insulating layers 369 and 370 provided on the side walls of the electrode 367 are provided. Note that for the conductive regions 365 and 366, metal silicide or the like may be used.
　再び図１７に戻る。絶縁体３０２は、層間絶縁体としての機能を有する。トランジスタＭ１にＳｉトランジスタを用いた場合、絶縁体３０２は水素を含むことが好ましい。絶縁体３０２が水素を含むことで、シリコンのダングリングボンドを終端し、トランジスタＭ１の信頼性を向上させる効果がある。絶縁体３０２として、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン等を用いることが好ましい。 It returns to FIG. 17 again. The insulator 302 has a function as an interlayer insulator. In the case where a Si transistor is used for the transistor M1, the insulator 302 preferably contains hydrogen. The insulator 302 containing hydrogen has an effect of terminating a dangling bond of silicon and improving the reliability of the transistor M1. As the insulator 302, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like is preferably used.
　絶縁体３０３には、基板３００又はトランジスタＭ１などから、トランジスタＴｒ１が設けられる領域に、水素や不純物が拡散しないようなバリア膜を用いることが好ましい。例えば、ＣＶＤ法で形成した窒化シリコンを用いることができる。ここで、トランジスタＴｒ１が有する金属酸化物に水素が拡散することで、該金属酸化物の特性が低下する場合がある。従って、トランジスタＭ１と、トランジスタＴｒ１との間に、水素の拡散を抑制する膜を用いることが好ましい。 As the insulator 303, it is preferable to use a barrier film to which hydrogen or an impurity is not diffused from the substrate 300, the transistor M1, or the like to the region where the transistor Tr1 is provided. For example, silicon nitride formed by a CVD method can be used. Here, the diffusion of hydrogen into the metal oxide of the transistor Tr1 may reduce the characteristics of the metal oxide. Therefore, it is preferable to use a film which suppresses the diffusion of hydrogen between the transistor M1 and the transistor Tr1.
　水素の拡散を抑制する膜とは、水素の脱離量が少ない膜のことを言う。水素の脱離量は、例えば、昇温脱離ガス分析法（ＴＤＳ（Ｔｈｅｒｍａｌ　Ｄｅｓｏｒｐｔｉｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ））などを用いて分析することができる。例えば、絶縁体３２４の水素の脱離量は、ＴＤＳ分析において、膜の表面温度が５０℃から５００℃の範囲において、水素原子に換算した脱離量が、絶縁体３０３の面積当たりに換算して、１０×１０１５ａｔｏｍｓ／ｃｍ２以下、好ましくは５×１０１５ａｔｏｍｓ／ｃｍ２以下であればよい。 The film that suppresses the diffusion of hydrogen refers to a film with a small amount of desorption of hydrogen. The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS) or the like. For example, in TDS analysis, the amount of desorption of hydrogen in the insulator 324 is equivalent to the amount of desorption of hydrogen atoms per area of the insulator 303 in the range of 50 ° C. to 500 ° C. of the film surface temperature. In this case, it is 10 × 10 15 atoms / cm 2 or less, preferably 5 × 10 15 atoms / cm 2 or less.
　また、絶縁体３０４、２１４、２８２は、銅の拡散を抑制する、又は、酸素、及び水素に対するバリア性を有する絶縁体を用いることが好ましい。例えば、銅の拡散を抑制する膜の一例として、窒化シリコンを用いることができる。また、酸化アルミニウムなどの金属酸化物を用いてもよい。 In addition, as the insulators 304, 214, and 282, it is preferable to use an insulator that suppresses copper diffusion or has a barrier property to oxygen and hydrogen. For example, silicon nitride can be used as an example of a film which suppresses diffusion of copper. Alternatively, a metal oxide such as aluminum oxide may be used.
　絶縁体２１６は、例えば、酸化シリコン膜や酸化窒化シリコン膜などを用いることができる。 For the insulator 216, a silicon oxide film, a silicon oxynitride film, or the like can be used, for example.
　絶縁体２８０、トランジスタＴｒ１の詳細については後述の実施の形態３で説明を行う。 Details of the insulator 280 and the transistor Tr1 will be described in a third embodiment described later.
　絶縁体３０５には例えば酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化アルミニウム、酸化窒化アルミニウム、窒化酸化アルミニウム、窒化アルミニウム、酸化ハフニウム、酸化窒化ハフニウム、窒化酸化ハフニウム、窒化ハフニウムなどを用いればよい。 For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxide oxynitride, hafnium oxide oxynitride, hafnium oxide nitride, etc. are used for the insulator 305 Just do it.
　また、絶縁体３０５は上記絶縁体の積層構造としてもよい。例えば、酸化窒化シリコンなどの絶縁破壊耐性が大きい材料と、酸化アルミニウムなどの高誘電率（ｈｉｇｈ−ｋ）材料の積層構造としてもよい。当該構成により、容量素子Ｃｓは、十分な容量を確保でき、且つ、静電破壊を抑制することができる。 In addition, the insulator 305 may have a stacked structure of the above insulators. For example, a stacked structure of a material having high dielectric breakdown resistance such as silicon oxynitride and a high dielectric constant (high-k) material such as aluminum oxide may be used. With this configuration, the capacitive element Cs can secure a sufficient capacitance and can suppress electrostatic breakdown.
　図１７に示す導電体、配線及びプラグとして、銅（Ｃｕ）、タングステン（Ｗ）、モリブデン（Ｍｏ）、金（Ａｕ）、アルミニウム（Ａｌ）、マンガン（Ｍｎ）、チタン（Ｔｉ）、タンタル（Ｔａ）、ニッケル（Ｎｉ）、クロム（Ｃｒ）、鉛（Ｐｂ）、錫（Ｓｎ）、鉄（Ｆｅ）、コバルト（Ｃｏ）、ルテニウム（Ｒｕ）、白金（Ｐｔ）、イリジウム（Ｉｒ）、ストロンチウム（Ｓｒ）の低抵抗材料からなる単体、合金、又はこれらを主成分とする化合物を含む導電体の単層又は積層とすることが好ましい。特に、耐熱性と導電性を両立するタングステンやモリブデンなどの高融点材料を用いることが好ましい。また、アルミニウムや銅などの低抵抗導電性材料で形成することが好ましい。 As the conductors, wirings, and plugs shown in FIG. 17, copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta) ), Nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr) It is preferable to set it as the single | mono layer or lamination | stacking of the conductor containing the single-piece | unit which consists of a low resistance material of the above, an alloy, or the compound which has these as a main component. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity. Moreover, it is preferable to form with low resistance conductive materials, such as aluminum and copper.
　図１７の記憶装置１００は、トランジスタＴｒ１を容量素子Ｃｓの上に形成してもよい。その場合の断面図を図１９に示す。図１９に示す断面図は、層Ｌ３と層Ｌ４が図１７の断面図が異なる。 In the memory device 100 of FIG. 17, the transistor Tr1 may be formed on the capacitive element Cs. A cross-sectional view in that case is shown in FIG. In the cross-sectional view shown in FIG. 19, the cross-sectional view in FIG. 17 is different between the layer L3 and the layer L4.
　図１９において、層Ｌ３は、配線３４１、容量素子Ｃｓを有する。 In FIG. 19, the layer L3 includes a wiring 341 and a capacitor Cs.
　図１９において、層Ｌ４は、プラグ３３１、プラグ３３２、プラグ３３３、プラグ３３４、配線３４２、配線３４３、配線ＬＢＬ、絶縁体２１４、絶縁体２１６、絶縁体２８０、絶縁体２８２、トランジスタＴｒ１を有する。 In FIG. 19, the layer L4 includes a plug 331, a plug 332, a plug 333, a plug 334, a wiring 342, a wiring 343, a wiring LBL, an insulator 214, an insulator 216, an insulator 280, an insulator 282, and a transistor Tr1.
　容量素子ＣｓをトランジスタＴｒ１の下に設けることで、容量素子Ｃｓを形成する際に生じるプロセスダメージ又は水素の影響から、トランジスタＴｒ１を防ぐことができる。 By providing the capacitive element Cs under the transistor Tr1, the transistor Tr1 can be prevented from the process damage or the influence of hydrogen which is generated when the capacitive element Cs is formed.
　図１７及び図１９において、符号及びハッチングパターンが与えられていない領域は、絶縁体で構成されている。上記絶縁体には、酸化アルミニウム、窒化酸化アルミニウム、酸化マグネシウム、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウム、酸化タンタルなどから選ばれた一種以上の材料を含む絶縁体を用いることができる。また、当該領域には、ポリイミド樹脂、ポリアミド樹脂、アクリル樹脂、シロキサン樹脂、エポキシ樹脂、フェノール樹脂等の有機樹脂を用いることもできる。 In FIG. 17 and FIG. 19, regions where reference numerals and hatching patterns are not given are made of an insulator. As the above insulator, aluminum oxide, aluminum nitride oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide An insulator containing one or more materials selected from tantalum oxide and the like can be used. In addition, in the region, an organic resin such as a polyimide resin, a polyamide resin, an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resin can also be used.
　図２０は記憶装置１００の上面模式図である。記憶装置１００は複数のサブアレイ（Ｓｕｂ　Ａｒｒａｙ）１５０を有する。それぞれのサブアレイ１５０は、メモリセルアレイ１１０、行ドライバ１２３及び列ドライバ１２４を有する。また、複数のサブアレイ１５０を囲むように、電源線１５１が配置されている。 FIG. 20 is a schematic top view of the storage device 100. As shown in FIG. The storage device 100 has a plurality of sub arrays 150. Each subarray 150 includes a memory cell array 110, a row driver 123 and a column driver 124. Further, power supply lines 151 are arranged so as to surround the plurality of subarrays 150.
　記憶装置１００において、半導体装置１０はメモリセルの外側に配置することができる。例えば、図２０の電源線１５１の下に配置することができる。そうすることで、記憶装置１００の面積オーバーヘッドを少なくすることができる。 In the storage device 100, the semiconductor device 10 can be disposed outside the memory cell. For example, it can be disposed under the power supply line 151 of FIG. By doing so, the area overhead of the storage device 100 can be reduced.
　本実施の形態は、他の実施の形態と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the other embodiments.
（実施の形態４）
　本実施の形態では、図１の動作モード制御回路１７に与える温度情報を検出する温度センサに用いることが可能な抵抗素子について説明を行う。 Embodiment 4
In this embodiment, a resistive element that can be used for a temperature sensor that detects temperature information given to the operation mode control circuit 17 of FIG. 1 will be described.
　図２１は抵抗素子４００の上面図である。抵抗素子４００は、金属酸化物４０１、導電体４０２及び導電体４０３を有する。また、金属酸化物４０１はその上面図において蛇行部を有する。 FIG. 21 is a top view of the resistance element 400. FIG. The resistive element 400 includes a metal oxide 401, a conductor 402, and a conductor 403. In addition, the metal oxide 401 has a serpentine portion in the top view.
　金属酸化物４０１は温度によって抵抗率が変化する性質を有する。抵抗素子４００は、導電体４０２と導電体４０３の間に電流を流し、金属酸化物４０１の抵抗値を測定することで温度を検出することができる。 The metal oxide 401 has a property that the resistivity changes with temperature. The resistance element 400 can detect a temperature by flowing a current between the conductor 402 and the conductor 403 and measuring the resistance value of the metal oxide 401.
　図２２は図１７に示す記憶装置１００の断面図に、抵抗素子４００を組み込んだ場合の断面模式図である。ＯＳトランジスタであるトランジスタＴｒ１と同じ層Ｌ３に、抵抗素子４００が設けられている。 FIG. 22 is a schematic cross-sectional view of the case where the resistance element 400 is incorporated in the cross-sectional view of the memory device 100 shown in FIG. A resistive element 400 is provided in the same layer L3 as the transistor Tr1 which is an OS transistor.
　抵抗素子４００に用いられる金属酸化物４０１は、トランジスタＴｒ１に用いられる金属酸化物２３０ｂと同じ金属酸化物によって構成される。金属酸化物４０１は、そのままでは抵抗率が高すぎて、抵抗素子として充分な機能を果たさない。そのため、金属酸化物４０１は、図２１に示す形状にエッチングされた後、抵抗率を下げるための処理が施されることが好ましい。 The metal oxide 401 used for the resistance element 400 is made of the same metal oxide as the metal oxide 230b used for the transistor Tr1. The metal oxide 401 has too high resistivity as it is and does not function sufficiently as a resistance element. Therefore, after the metal oxide 401 is etched into the shape shown in FIG. 21, it is preferable that a process for lowering the resistivity be performed.
　上述の抵抗率を下げるための処理として、例えば、Ｈｅ、Ａｒ、Ｋｒ、Ｘｅなどの希ガスによるプラズマ処理が挙げられる。また、先述の希ガスに、酸化窒素、アンモニア、窒素又は水素を導入し、混合ガスとしてプラズマ処理を行ってもよい。これら、プラズマ処理によって、金属酸化物４０１は酸素欠損が形成され、抵抗率を下げることができる。 Examples of the above-described treatment for reducing the resistivity include plasma treatment with a rare gas such as He, Ar, Kr, or Xe. In addition, nitrogen oxide, ammonia, nitrogen, or hydrogen may be introduced into the above-described rare gas, and plasma treatment may be performed as a mixed gas. By these plasma treatments, oxygen vacancies are formed in the metal oxide 401, whereby the resistivity can be reduced.
　また、上述の抵抗率を下げるための処理として、窒化シリコンなど、水素を多量に含む膜を金属酸化物４０１と接するように設ける処理が挙げられる。金属酸化物４０１は水素を添加されることで、抵抗率を下げることができる。 Further, as the above-described treatment for reducing the resistivity, treatment in which a film containing a large amount of hydrogen such as silicon nitride is provided in contact with the metal oxide 401 can be given. The resistivity of the metal oxide 401 can be reduced by the addition of hydrogen.
　これら抵抗率を下げる処理によって、金属酸化物４０１は、室温による抵抗率を１×１０−３Ωｃｍ以上、１×１０４Ωｃｍ以下とすることができる。 By the treatment for reducing the resistivity, the metal oxide 401 can have a resistivity at room temperature of 1 × 10 −3 Ωcm or more and 1 × 10 4 Ωcm or less.
　図２２に示すように、抵抗素子４００をトランジスタＴｒ１と同じ層に形成することで、抵抗素子４００はトランジスタＴｒ１の温度を正確に検出することができる。また、抵抗素子４００とトランジスタＴｒ１を、同じ工程で形成することができるため、それぞれ別の工程で形成する場合よりも、工程を短縮することができる。 As shown in FIG. 22, by forming the resistive element 400 in the same layer as the transistor Tr1, the resistive element 400 can accurately detect the temperature of the transistor Tr1. Further, since the resistance element 400 and the transistor Tr1 can be formed in the same step, the steps can be shortened as compared to the case where they are formed in separate steps.
　なお、抵抗素子４００の金属酸化物４０１と、トランジスタＴｒ１の金属酸化物２３０ｂを異なる金属酸化物で形成する場合、抵抗素子４００は層Ｌ４よりも上層に形成してもよい。 Note that in the case where the metal oxide 401 of the resistance element 400 and the metal oxide 230b of the transistor Tr1 are formed using different metal oxides, the resistance element 400 may be formed over the layer L4.
　本実施の形態は、他の実施の形態と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the other embodiments.
（実施の形態５）
　本実施の形態では、上記実施の形態で用いたＯＳトランジスタの構造について説明を行う。 Fifth Embodiment
In this embodiment mode, a structure of the OS transistor used in the above embodiment mode will be described.
〈〈金属酸化物〉〉
　まず、ＯＳトランジスタに用いられる金属酸化物について説明する。 << metal oxide >>
First, metal oxides used for the OS transistor will be described.
　金属酸化物は、少なくともインジウム又は亜鉛を含むことが好ましい。特にインジウム及び亜鉛を含むことが好ましい。また、それらに加えて、アルミニウム、ガリウム、イットリウム又はスズなどが含まれていることが好ましい。また、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、又はマグネシウムなどから選ばれた一種、又は複数種が含まれていてもよい。 The metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium or tin is contained. In addition, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.
　ここでは、金属酸化物が、インジウム、元素Ｍ及び亜鉛を有するＩｎ−Ｍ−Ｚｎ酸化物である場合を考える。なお、元素Ｍは、アルミニウム、ガリウム、イットリウム又はスズなどとする。そのほかの元素Ｍに適用可能な元素としては、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、マグネシウムなどがある。但し、元素Ｍとして、前述の元素を複数組み合わせても構わない場合がある。 Here, it is assumed that the metal oxide is an In-M-Zn oxide containing indium, an element M and zinc. The element M is aluminum, gallium, yttrium, tin or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like. However, as the element M, a plurality of the aforementioned elements may be combined in some cases.
　次に、図２３（Ａ）、図２３（Ｂ）、及び図２３（Ｃ）を用いて、本発明に係る金属酸化物が有するインジウム、元素Ｍ及び亜鉛の原子数比の好ましい範囲について説明する。なお、図２３（Ａ）、図２３（Ｂ）、及び図２３（Ｃ）には、酸素の原子数比については記載しない。また、金属酸化物が有するインジウム、元素Ｍ、及び亜鉛の原子数比のそれぞれの項を［Ｉｎ］、［Ｍ］、及び［Ｚｎ］とする。 Next, with reference to FIGS. 23A, 23B, and 23C, a preferable range of the atomic ratio of indium, the element M, and zinc contained in the metal oxide according to the present invention will be described. . The atomic ratio of oxygen is not described in FIGS. 23 (A), 23 (B), and 23 (C). The terms of the atomic ratio of indium to the element M to zinc contained in the metal oxide are denoted by [In], [M] and [Zn].
　図２３（Ａ）、図２３（Ｂ）、及び図２３（Ｃ）において、破線は、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝（１＋α）：（１−α）：１の原子数比（−１≦α≦１）となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝（１＋α）：（１−α）：２の原子数比となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝（１＋α）：（１−α）：３の原子数比となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝（１＋α）：（１−α）：４の原子数比となるライン、及び［Ｉｎ］：［Ｍ］：［Ｚｎ］＝（１＋α）：（１−α）：５の原子数比となるラインを表す。 In FIG. 23A, FIG. 23B, and FIG. 23C, the broken line indicates an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1. A line with (−1 ≦ α ≦ 1), a line with an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 2, [In]: [M] A line having an atomic ratio of [Zn] = (1 + α) :( 1-α): 3, an atomic number of [In]: [M]: [Zn] = (1 + α) :( 1-α): 4 The line which becomes a ratio, and the line which becomes atomic number ratio of [In]: [M]: [Zn] = (1+ (alpha)) :( 1- (alpha)): 5 is represented.
　また、一点鎖線は、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝５：１：βの原子数比（β≧０）となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝２：１：βの原子数比となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝１：１：βの原子数比となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝１：２：βの原子数比となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝１：３：βの原子数比となるライン、及び［Ｉｎ］：［Ｍ］：［Ｚｎ］＝１：４：βの原子数比となるラインを表す。 Moreover, the dashed-dotted line is a line where the atomic ratio (β ≧ 0) of [In]: [M]: [Zn] = 5: 1: β, [In]: [M]: [Zn] = 2: A line with an atomic ratio of 1: β, [In]: [M]: [Zn] = 1: 1: A line with an atomic ratio of β, [In]: [M]: [Zn] = 1: A line with an atomic ratio of 2: β, a line with an atomic ratio of [In]: [M]: [Zn] = 1: 3: β, and [In]: [M]: [Zn] = 1 : 4: represents a line having an atomic ratio of β.
　また、図２３（Ａ）、図２３（Ｂ）、及び図２３（Ｃ）に示す、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝０：２：１の原子数比、及びその近傍値の金属酸化物は、スピネル型の結晶構造をとりやすい。 23A, 23B, and 23C, the atomic ratio of [In]: [M]: [Zn] = 0: 2: 1, and its neighboring value Metal oxides tend to have a spinel crystal structure.
　また、金属酸化物中に複数の相が共存する場合がある（二相共存、三相共存など）。例えば、原子数比が［Ｉｎ］：［Ｍ］：［Ｚｎ］＝０：２：１の近傍値である場合、スピネル型の結晶構造と層状の結晶構造との二相が共存しやすい。また、原子数比が［Ｉｎ］：［Ｍ］：［Ｚｎ］＝１：０：０の近傍値である場合、ビックスバイト型の結晶構造と層状の結晶構造との二相が共存しやすい。金属酸化物中に複数の相が共存する場合、異なる結晶構造の間において、結晶粒界が形成される場合がある。 In addition, a plurality of phases may coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is in the vicinity of [In]: [M]: [Zn] = 0: 2: 1, two phases of the spinel crystal structure and the layered crystal structure easily coexist. In addition, when the atomic ratio is in the vicinity of [In]: [M]: [Zn] = 1: 0: 0, two phases of the bixbite-type crystal structure and the layered crystal structure easily coexist. When a plurality of phases coexist in a metal oxide, grain boundaries may be formed between different crystal structures.
　図２３（Ａ）に示す領域Ａは、金属酸化物が有する、インジウム、元素Ｍ、及び亜鉛の原子数比の好ましい範囲の一例について示している。 A region A illustrated in FIG. 23A illustrates an example of a preferable range of the atomic ratio of indium to the element M to zinc contained in the metal oxide.
　金属酸化物は、インジウムの含有率を高くすることで、金属酸化物のキャリア移動度（電子移動度）を高くすることができる。従って、インジウムの含有率が高い金属酸化物はインジウムの含有率が低い金属酸化物と比較してキャリア移動度が高くなる。 The metal oxide can increase the carrier mobility (electron mobility) of the metal oxide by increasing the indium content. Therefore, a metal oxide having a high indium content has higher carrier mobility than a metal oxide having a low indium content.
　一方、金属酸化物中のインジウム及び亜鉛の含有率が低くなると、キャリア移動度が低くなる。従って、原子数比が［Ｉｎ］：［Ｍ］：［Ｚｎ］＝０：１：０、及びその近傍値である場合（例えば図２３（Ｃ）に示す領域Ｃ）は、絶縁性が高くなる。 On the other hand, the lower the indium and zinc content in the metal oxide, the lower the carrier mobility. Therefore, when the atomic ratio is [In]: [M]: [Zn] = 0: 1: 0, and in the vicinity thereof (for example, in the region C shown in FIG. 23C), the insulating property is high. .
　従って、本発明の一態様の金属酸化物は、キャリア移動度が高く、かつ、結晶粒界が少ない層状構造となりやすい、図２３（Ａ）の領域Ａで示される原子数比を有することが好ましい。 Therefore, the metal oxide of one embodiment of the present invention preferably has an atomic ratio represented by a region A in FIG. 23A, which is likely to have a layered structure with high carrier mobility and few crystal grain boundaries. .
　特に、図２３（Ｂ）に示す領域Ｂでは、領域Ａの中でも、ＣＡＡＣ（ｃ−ａｘｉｓ　ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ）−ＯＳとなりやすく、キャリア移動度も高い優れた金属酸化物が得られる。 In particular, in the region B illustrated in FIG. 23B, a c-axis aligned crystalline (CAAC) -OS is easily formed in the region A, and an excellent metal oxide with high carrier mobility can be obtained.
　ＣＡＡＣ−ＯＳは、ｃ軸配向性を有し、かつａ−ｂ面方向において複数のナノ結晶が連結し、歪みを有した結晶構造である。なお、歪みとは、複数のナノ結晶が連結する領域において、格子配列の揃った領域と、別の格子配列の揃った領域と、の間で格子配列の向きが変化している箇所を指す。 The CAAC-OS has a c-axis orientation, and has a strained crystal structure in which a plurality of nanocrystals are connected in the a-b plane direction. Note that distortion refers to a portion where the orientation of the lattice arrangement changes between the region in which the lattice arrangement is aligned and the region in which another lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.
　ナノ結晶は、六角形を基本とするが、正六角形状とは限らず、非正六角形状である場合がある。また、歪みにおいて、五角形、及び七角形などの格子配列を有する場合がある。なお、ＣＡＡＣ−ＯＳにおいて、歪み近傍においても、明確な結晶粒界（グレインバウンダリーともいう）を確認することはできない。即ち、格子配列の歪みによって、結晶粒界の形成が抑制されていることがわかる。これは、ＣＡＡＣ−ＯＳが、ａ−ｂ面方向において酸素原子の配列が稠密でないことや、金属元素が置換することで原子間の結合距離が変化することなどによって、歪みを許容することができるためと考えられる。 The nanocrystals are based on hexagons, but may not be regular hexagons and may be non-hexagonal. Moreover, distortion may have a lattice arrangement such as pentagon and heptagon. In the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) can not be confirmed near the strain. That is, it is understood that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, or that the bonding distance between atoms is changed due to metal element substitution. It is thought that it is for.
　ＣＡＡＣ−ＯＳは結晶性の高い金属酸化物である。一方、ＣＡＡＣ−ＯＳは、明確な結晶粒界を確認することはできないため、結晶粒界に起因する電子移動度の低下が起こりにくいといえる。また、金属酸化物の結晶性は不純物の混入や欠陥の生成などによって低下する場合があるため、ＣＡＡＣ−ＯＳは不純物や欠陥（酸素欠損など）の少ない金属酸化物ともいえる。従って、ＣＡＡＣ−ＯＳを有する金属酸化物は、物理的性質が安定する。そのため、ＣＡＡＣ−ＯＳを有する金属酸化物は熱に強く、信頼性が高い。 CAAC-OS is a highly crystalline metal oxide. On the other hand, CAAC-OS can not confirm clear crystal grain boundaries, so that it can be said that the decrease in electron mobility due to crystal grain boundaries does not easily occur. In addition, since the crystallinity of the metal oxide may be lowered due to the mixing of impurities, generation of defects, or the like, CAAC-OS can also be said to be a metal oxide with few impurities or defects (such as oxygen vacancies). Therefore, the metal oxide having a CAAC-OS has stable physical properties. Therefore, a metal oxide having a CAAC-OS is resistant to heat and has high reliability.
　なお、領域Ｂは、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝４：２：３から４．１、及びその近傍値を含む。近傍値には、例えば、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝５：３：４が含まれる。また、領域Ｂは、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝５：１：６、及びその近傍値、及び［Ｉｎ］：［Ｍ］：［Ｚｎ］＝５：１：７、及びその近傍値を含む。 Region B includes [In]: [M]: [Zn] = 4: 2: 3 to 4.1, and their neighboring values. The neighborhood value includes, for example, [In]: [M]: [Zn] = 5: 3: 4. Region B has [In]: [M]: [Zn] = 5: 1: 6 and their neighboring values, and [In]: [M]: [Zn] = 5: 1: 7, and Includes neighborhood values.
　なお、金属酸化物が有する性質は、原子数比によって一義的に定まらない。同じ原子数比であっても、形成条件により、金属酸化物の性質が異なる場合がある。例えば、金属酸化物をスパッタリング装置にて成膜する場合、ターゲットの原子数比からずれた原子数比の膜が形成される。また、成膜時の基板温度によっては、ターゲットの［Ｚｎ］よりも、膜の［Ｚｎ］が小さくなる場合がある。従って、図示する領域は、金属酸化物が特定の特性を有する傾向がある原子数比を示す領域であり、領域Ａ乃至領域Ｃの境界は厳密ではない。 Note that the properties of the metal oxide can not be uniquely determined by the atomic ratio. Even with the same atomic ratio, the properties of the metal oxide may differ depending on the forming conditions. For example, in the case of forming a metal oxide film by a sputtering apparatus, a film having an atomic ratio different from the atomic ratio of the target is formed. Further, depending on the substrate temperature at the time of film formation, the [Zn] of the film may be smaller than the [Zn] of the target. Therefore, the illustrated region is a region showing an atomic ratio in which the metal oxide tends to have specific characteristics, and the boundaries of the regions A to C are not strict.
＜半導体装置の構成例１＞
　以下では、本発明の一態様に係るトランジスタＴｒ１を有する半導体装置の一例について説明する。 <Structure Example 1 of Semiconductor Device>
Hereinafter, an example of a semiconductor device including the transistor Tr1 according to one embodiment of the present invention will be described.
　図２４（Ａ）は、トランジスタＴｒ１トランジスタＴｒ１を有する半導体装置の上面図である。また、図２４（Ｂ）は、図２４（Ａ）にＡ１−Ａ２の一点鎖線で示す部位の断面図であり、トランジスタＴｒ１のチャネル長方向の断面図でもある。また、図２４（Ｃ）は、図２４（Ａ）にＡ３−Ａ４の一点鎖線で示す部位の断面図であり、トランジスタＴｒ１のチャネル幅方向の断面図でもある。図２４（Ａ）の上面図では、図の明瞭化のために一部の要素を省いて図示している。 FIG. 24A is a top view of a semiconductor device having a transistor Tr1 and a transistor Tr1. FIG. 24B is a cross-sectional view of a portion indicated by an alternate long and short dash line A1-A2 in FIG. 24A, and also a cross-sectional view of the transistor Tr1 in the channel length direction. FIG. 24C is a cross-sectional view of a portion indicated by an alternate long and short dash line A3-A4 in FIG. 24A, and also a cross-sectional view in the channel width direction of the transistor Tr1. In the top view of FIG. 24A, some elements are omitted for clarity of the drawing.
　本発明の一態様の半導体装置は、基板２１３と、基板２１３上の絶縁体２１５と、絶縁体２１５上のトランジスタＴｒ１と、トランジスタＴｒ１上の、絶縁体２８０と、絶縁体２８０上の絶縁体２８２と、を有する。但し、基板２１３は、絶縁体２１４でもよい。 The semiconductor device of one embodiment of the present invention includes a substrate 213, an insulator 215 over the substrate 213, a transistor Tr1 over the insulator 215, an insulator 280 over the transistor Tr1, and an insulator 282 over the insulator 280. And. However, the substrate 213 may be the insulator 214.
　トランジスタＴｒ１は、絶縁体２１５上の導電体２０５及び絶縁体２１６と、導電体２０５上及び絶縁体２１６上の絶縁体２２０と、絶縁体２２０上の絶縁体２２２と、絶縁体２２２上の絶縁体２２４と、絶縁体２２４上の金属酸化物２３０ａと、金属酸化物２３０ａ上の金属酸化物２３０ｂと、金属酸化物２３０ｂの上面と接する領域を有する導電体２４０ａ１及び導電体２４０ａ２と、導電体２４０ａ１上のバリア膜２４０ｂ１と、導電体２４０ａ２上のバリア膜２４０ｂ２と、導電体２４０ａ１の側面、導電体２４０ａ２の側面、バリア膜２４０ｂ１の側面、バリア膜２４０ｂ２の側面及び金属酸化物２３０ｂの上面と接する領域を有する金属酸化物２３０ｃと、金属酸化物２３０ｃ上の絶縁体２５０と、金属酸化物２３０ｂの上面と金属酸化物２３０ｃ及び絶縁体２５０を介して互いに重なる領域を有する導電体２６０と、導電体２６０上の絶縁体２４１と、を有する。また、絶縁体２１６は、開口部を有していて、開口部内に導電体２０５ａ及び導電体２０５ｂが配置される。 The transistor Tr1 includes the conductor 205 and the insulator 216 on the insulator 215, the insulator 220 on the conductor 205 and the insulator 216, the insulator 222 on the insulator 220, and the insulator on the insulator 222. 224, a metal oxide 230a on the insulator 224, a metal oxide 230b on the metal oxide 230a, a conductor 240a1 and a conductor 240a2 having a region in contact with the top surface of the metal oxide 230b, and the conductor 240a1 Of the barrier film 240b1, the barrier film 240b2 on the conductor 240a2, the side surface of the conductor 240a1, the side surface of the conductor 240a2, the side surface of the barrier film 240b1, the side surface of the barrier film 240b2, and the region in contact with the top surface of the metal oxide 230b Metal oxide 230c, an insulator 250 on the metal oxide 230c, and an upper surface of the metal oxide 230b It has a conductor 260 which has a region overlapping with each other through the metal oxide 230c and the insulator 250, the insulator 241 on the conductor 260. The insulator 216 has an opening, and the conductor 205a and the conductor 205b are disposed in the opening.
　図２４（Ｂ）および（Ｃ）において、絶縁体２４１の端部、絶縁体２５０の端部及び金属酸化物２３０ｃの端部は面一であり、チャネル長方向においては、バリア膜２４０ｂ１上及びバリア膜２４０ｂ２上に配置され、チャネル幅方向の一方においては、絶縁体２２４上に配置される。 In FIGS. 24B and 24C, the end of the insulator 241, the end of the insulator 250, and the end of the metal oxide 230c are flush with each other, and the barrier film 240b1 and the barrier in the channel length direction. It is disposed on the film 240 b 2 and on the insulator 224 in one of the channel width directions.
　トランジスタＴｒ１において、導電体２６０は第１のゲート電極としての機能を有する。導電体２６０は、導電体２６０ａ及び導電体２６０ｂの積層構造とすることができる。さらに、導電体２６０は、３層以上の積層構造とすることもできる。例えば、酸素の透過を抑制する機能を有する導電体２６０ａを導電体２６０ｂの下層に成膜することで導電体２６０ｂの酸化を防ぐことができる。又は、例えば、導電体２６０が酸化耐性を有する金属を有することが好ましい。又は、例えば、金属酸化物導電体などを用いてもよい。又は、例えば、導電性を有する金属酸化物を含む多層構造としてもよい。絶縁体２５０は第１のゲート絶縁体としての機能を有する。 In the transistor Tr1, the conductor 260 has a function as a first gate electrode. The conductor 260 can have a stacked structure of the conductor 260a and the conductor 260b. Furthermore, the conductor 260 can also have a stacked structure of three or more layers. For example, oxidation of the conductor 260b can be prevented by forming the conductor 260a having a function of suppressing permeation of oxygen under the conductor 260b. Alternatively, for example, the conductor 260 preferably includes a metal having oxidation resistance. Alternatively, for example, a metal oxide conductor or the like may be used. Alternatively, for example, a multilayer structure including a conductive metal oxide may be used. The insulator 250 has a function as a first gate insulator.
　また、導電体２４０ａ１及び導電体２４０ａ２は、ソース電極又はドレイン電極としての機能を有する。また、導電体２４０ａ１及び導電体２４０ａ２は、酸素の透過を抑制する機能を有する導電体と積層構造とすることができる。例えば酸素の透過を抑制する機能を有する導電体を上層に成膜することで導電体２４０ａ１及び導電体２４０ａ２の酸化を防ぐことができる。又は、導電体２４０ａ１及び導電体２４０ａ２が酸化耐性を有する金属を有することが好ましい。又は、金属酸化物導電体などを用いてもよい。 The conductor 240a1 and the conductor 240a2 also function as a source electrode or a drain electrode. The conductor 240a1 and the conductor 240a2 can have a stacked structure with a conductor having a function of suppressing permeation of oxygen. For example, oxidation of the conductor 240a1 and the conductor 240a2 can be prevented by forming a conductor with a function of suppressing permeation of oxygen over the upper layer. Alternatively, it is preferable that the conductor 240a1 and the conductor 240a2 include a metal having oxidation resistance. Alternatively, a metal oxide conductor or the like may be used.
　また、バリア膜２４０ｂ１及びバリア膜２４０ｂ２は、水素や水などの不純物及び酸素の透過を抑制する機能を有する。バリア膜２４０ｂ１は、導電体２４０ａ１上にあって、導電体２４０ａ１への酸素の拡散を防止する。バリア膜２４０ｂ２は、導電体２４０ａ２上にあって、導電体２４０ａ２への酸素の拡散を防止する。 The barrier film 240b1 and the barrier film 240b2 have a function of suppressing permeation of impurities such as hydrogen and water and oxygen. The barrier film 240b1 is on the conductor 240a1, and prevents the diffusion of oxygen to the conductor 240a1. The barrier film 240 b 2 is on the conductor 240 a 2 to prevent diffusion of oxygen to the conductor 240 a 2.
　トランジスタＴｒ１において、金属酸化物２３０ｂ及び金属酸化物２３０ｃはチャネル形成領域を有する。即ちトランジスタＴｒ１は、導電体２６０に印加する電位によって、金属酸化物２３０ｂ及び金属酸化物２３０ｃの抵抗を制御することができる。即ち、導電体２６０に印加する電位によって、導電体２４０ａ１と導電体２４０ａ２との間の導通・非導通を制御することができる。 In the transistor Tr1, the metal oxide 230b and the metal oxide 230c have a channel formation region. That is, the transistor Tr1 can control the resistances of the metal oxide 230b and the metal oxide 230c by the potential applied to the conductor 260. That is, by the potential applied to the conductor 260, conduction / nonconduction between the conductor 240a1 and the conductor 240a2 can be controlled.
　図２４（Ｃ）に示すように、第１のゲート電極の機能を有する導電体２６０は、第１のゲート絶縁体の機能を有する絶縁体２５０を介して金属酸化物２３０ｂの全体及び金属酸化物２３０ｃの一部を覆うように配される。従って、第１のゲート電極としての機能を有する導電体２６０の電界によって、金属酸化物２３０ｂの全体及び金属酸化物２３０ｃの一部を電気的に取り囲むことができる。第１のゲート電極の電界によって、チャネル形成領域を電気的に取り囲むトランジスタの構造を、ｓｕｒｒｏｕｎｄｅｄ　ｃｈａｎｎｅｌ（ｓ−ｃｈａｎｎｅｌ）構造とよぶ。 As shown in FIG. 24C, the conductor 260 having the function of the first gate electrode is the whole of the metal oxide 230b and the metal oxide through the insulator 250 having the function of the first gate insulator. It is arranged to cover a part of 230c. Therefore, the whole of the metal oxide 230 b and a part of the metal oxide 230 c can be electrically surrounded by the electric field of the conductor 260 having a function as the first gate electrode. The structure of the transistor that electrically surrounds the channel formation region by the electric field of the first gate electrode is referred to as a surrounded channel (s-channel) structure.
　さらに、図２４（Ｂ）に示すように、金属酸化物２３０ｂ、及び金属酸化物２３０ｃで、ソース電極又はドレイン電極としての機能を有する導電体２４０ａ１及び導電体２４０ａ２を挟み込む形状とすることで、ソース電極又はドレイン電極と接触する面積を大きくすることができる。従って、金属酸化物２３０ｂ及び金属酸化物２３０ｃと、導電体２４０ａ１及び導電体２４０ａ２と、の接触面積が大きくなり、コンタクト抵抗が下げられて好ましい。 Further, as shown in FIG. 24B, the metal oxide 230b and the metal oxide 230c sandwich the conductor 240a1 and the conductor 240a2 each having a function as a source electrode or a drain electrode, thereby forming a source. The area in contact with the electrode or drain electrode can be increased. Accordingly, the contact area between the metal oxide 230b and the metal oxide 230c, and the conductor 240a1 and the conductor 240a2 is increased, which is preferable because the contact resistance is lowered.
　金属酸化物２３０は、金属酸化物半導体として機能する金属酸化物（以下、金属酸化物半導体ともいう）を用いることが好ましい。但し、金属酸化物の代わりに、シリコン（歪シリコン含む）、ゲルマニウム、シリコンゲルマニウム、炭化シリコン、ガリウムヒ素、アルミニウムガリウムヒ素、インジウムリン、窒化ガリウム又は有機半導体などを用いても構わない場合がある。 As the metal oxide 230, a metal oxide which functions as a metal oxide semiconductor (hereinafter, also referred to as a metal oxide semiconductor) is preferably used. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium indium, an organic semiconductor, or the like may be used instead of the metal oxide.
　金属酸化物半導体を用いたトランジスタは、非導通状態において極めてリーク電流が小さいため、低消費電力の半導体装置が提供できる。また、金属酸化物半導体は、スパッタリング法などを用いて成膜できるため、高集積型の半導体装置を構成するトランジスタに用いることができる。 A transistor using a metal oxide semiconductor has extremely low leakage current in a non-conduction state; thus, a semiconductor device with low power consumption can be provided. In addition, since a metal oxide semiconductor can be formed by a sputtering method or the like, the metal oxide semiconductor can be used for a transistor included in a highly integrated semiconductor device.
　一方で、金属酸化物半導体を用いたトランジスタは、金属酸化物半導体中の不純物及び酸素欠損によって、その電気特性が変動しやすく、信頼性が悪くなる場合がある。また、金属酸化物半導体に含まれる水素は、金属原子と結合する酸素と反応して水になるため、酸素欠損を形成する場合がある。該酸素欠損に水素が入ることで、キャリアである電子が生成される場合がある。従って、酸素欠損が含まれている金属酸化物半導体を用いたトランジスタはノーマリーオン特性となりやすい。このため、金属酸化物半導体中の酸素欠損はできる限り低減されていることが好ましい。 On the other hand, in a transistor using a metal oxide semiconductor, the electrical characteristics thereof are likely to fluctuate due to impurities and oxygen vacancies in the metal oxide semiconductor, which may deteriorate reliability. Further, hydrogen contained in a metal oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancies, electrons which are carriers may be generated. Therefore, a transistor including a metal oxide semiconductor which contains oxygen vacancies is likely to be normally on. Therefore, it is preferable that oxygen vacancies in the metal oxide semiconductor be reduced as much as possible.
　金属酸化物半導体は、少なくともインジウム又は亜鉛を含むことが好ましい。特にインジウム及び亜鉛を含むことが好ましい。また、それらに加えて、アルミニウム、ガリウム、イットリウム又はスズなどが含まれていることが好ましい。また、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、又はマグネシウムなどから選ばれた一種、又は複数種が含まれていてもよい。 The metal oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium or tin is contained. In addition, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.
　ここでは、金属酸化物半導体が、インジウム、元素Ｍ及び亜鉛を有するＩｎ−Ｍ−Ｚｎ金属酸化物である場合を考える。なお、元素Ｍは、アルミニウム、ガリウム、イットリウム又はスズなどとする。それ以外の元素Ｍに適用可能な元素としては、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、マグネシウムなどがある。但し、元素Ｍとして、前述の元素を複数組み合わせても構わない場合がある。 Here, it is considered that the metal oxide semiconductor is an In-M-Zn metal oxide containing indium, an element M, and zinc. The element M is aluminum, gallium, yttrium, tin or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like. However, as the element M, a plurality of the aforementioned elements may be combined in some cases.
　なお、本明細書等において、窒素を有する金属酸化物も金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）と総称する場合がある。また、窒素を有する金属酸化物を、金属酸窒化物（ｍｅｔａｌ　ｏｘｙｎｉｔｒｉｄｅ）と呼称してもよい。 In the present specification and the like, metal oxides having nitrogen may also be collectively referred to as metal oxides. In addition, a metal oxide having nitrogen may be referred to as metal oxynitride.
　ここで、金属酸化物２３０ｂ及び金属酸化物２３０ｃに用いるＩｎ−Ｍ−Ｚｎ金属酸化物は、それぞれＩｎの方が元素Ｍより多くの原子を含むことが好ましい。このような金属酸化物とすることでトランジスタＴｒ１の移動度が上がり、キャリア密度も高くなる。また、ゲート電極としての機能を有する導電体２６０側に該金属酸化物を配置することで、チャネル形成領域の制御性が高くなり好ましい。 Here, in the In-M-Zn metal oxide used for the metal oxide 230 b and the metal oxide 230 c, each of In preferably contains more atoms than the element M. With such a metal oxide, the mobility of the transistor Tr1 is increased, and the carrier density is also increased. Further, by disposing the metal oxide on the side of the conductor 260 having a function as a gate electrode, controllability of the channel formation region is preferably high.
　ここで、例えば、金属酸化物２３０ｂと、金属酸化物２３０ｃとは、等しい組成の金属酸化物半導体か、又は近傍の組成の金属酸化物半導体を用いると好ましい。又は、例えば、金属酸化物２３０ｂと、金属酸化物２３０ｃとは、同じスパッタリングターゲット部材を用いて成膜することが好ましい。又は、例えば、金属酸化物２３０ｂと、金属酸化物２３０ｃとは、概ね同じ組成を有するスパッタリングターゲット部材を用いて成膜することが好ましい。又は、例えば、金属酸化物２３０ｂと、金属酸化物２３０ｃとは、概ね同じプロセス条件（例えば、成膜温度、酸素ガスの比率など）で成膜することが好ましい。 Here, for example, as the metal oxide 230b and the metal oxide 230c, it is preferable to use a metal oxide semiconductor of the same composition or a metal oxide semiconductor of a nearby composition. Alternatively, for example, the metal oxide 230 b and the metal oxide 230 c are preferably deposited using the same sputtering target member. Alternatively, for example, the metal oxide 230 b and the metal oxide 230 c are preferably deposited using a sputtering target member having substantially the same composition. Alternatively, for example, the metal oxide 230 b and the metal oxide 230 c are preferably deposited under substantially the same process conditions (e.g., a deposition temperature, a ratio of oxygen gas, and the like).
　又は、例えば、金属酸化物２３０ｂと、金属酸化物２３０ｃとは、異なる組成を有するスパッタリングターゲット部材を用いて成膜してもよい。例えば、金属酸化物２３０ｂと、金属酸化物２３０ｃとの、プロセス条件（例えば、成膜温度、酸素ガスの比率など）を適宜調整することで、金属酸化物２３０ｂと、金属酸化物２３０ｃとは、等しい組成の金属酸化物半導体か、又は近傍の組成の金属酸化物半導体を成膜することができる場合がある。金属酸化物２３０ｂ及び金属酸化物２３０ｃに組成の近い金属酸化物半導体を用いるほど好ましい場合があるが、要求される厚さや機能が異なるため、最適な成膜条件も異なってくる場合がある。従って、異なる組成を有するスパッタリングターゲット部材を用いて、金属酸化物２３０ｂと、金属酸化物２３０ｃと、を成膜することで、等しいか、又は近傍の組成のスパッタリングターゲット部材を用いた場合よりも、金属酸化物２３０ｂと金属酸化物２３０ｃとの組成を近付けることができて好ましい場合がある。 Alternatively, for example, the metal oxide 230 b and the metal oxide 230 c may be deposited using sputtering target members having different compositions. For example, the metal oxide 230b and the metal oxide 230c can be obtained by appropriately adjusting the process conditions (for example, the film formation temperature, the ratio of oxygen gas, and the like) between the metal oxide 230b and the metal oxide 230c. It may be possible to deposit a metal oxide semiconductor of the same composition or a metal oxide semiconductor of a nearby composition. It may be preferable to use a metal oxide semiconductor having a composition close to that of the metal oxide 230b and the metal oxide 230c, but since the required thickness and function are different, the optimum film formation conditions may also be different. Therefore, by depositing the metal oxide 230b and the metal oxide 230c using sputtering target members having different compositions, it is possible to use a sputtering target member of the same or a neighboring composition, In some cases, the compositions of the metal oxide 230b and the metal oxide 230c can be made close to each other.
　金属酸化物２３０ｂと、金属酸化物２３０ｃと、を等しいか、又は近傍の組成とすることで、金属酸化物２３０ｂの電子親和力と、金属酸化物２３０ｃの電子親和力と、は等しいか、差が小さくなる。特に、組成だけでなく、プロセス条件も概ね同じであれば、金属酸化物２３０ｂの電子親和力と、金属酸化物２３０ｃの電子親和力と、は等しいか、差が小さくなる。従って、金属酸化物２３０ｂと、金属酸化物２３０ｃと、の界面準位密度を低減することができる。界面準位密度を低減することで、トランジスタＴｒ１のオン電流の低下を防止することができる。尚、電子親和力は、伝導帯下端のエネルギー値Ｅｃと言い換えることができる。金属酸化物２３０ｂのＥｃと、金属酸化物２３０ｃのＥｃと、の差は小さい方が好ましく、０ｅＶ以上０．１５ｅＶ以下、より好ましくは、０Ｖ以上０．０７ｅＶとする。 By making the metal oxide 230b and the metal oxide 230c equal or close in composition, the electron affinity of the metal oxide 230b and the electron affinity of the metal oxide 230c are equal or the difference is small. Become. In particular, if not only the composition but also the process conditions are substantially the same, the electron affinity of the metal oxide 230b and the electron affinity of the metal oxide 230c are equal to or smaller than each other. Accordingly, the interface state density of the metal oxide 230 b and the metal oxide 230 c can be reduced. By reducing the interface state density, it is possible to prevent the decrease in the on current of the transistor Tr1. The electron affinity can be rephrased as the energy value Ec at the lower end of the conduction band. The difference between Ec of the metal oxide 230b and Ec of the metal oxide 230c is preferably small, and is 0 eV or more and 0.15 eV or less, more preferably 0 V or more and 0.07 eV.
　電子親和力又はＥｃは、真空準位と価電子帯上端のエネルギーＥｖとの差であるイオン化ポテンシャルＩｐと、エネルギーギャップＥｇから求めることができる。イオン化ポテンシャルＩｐは、例えば、紫外線光電子分光分析（ＵＰＳ：Ｕｌｔｒａｖｉｏｌｅｔ　Ｐｈｏｔｏｅｌｅｃｔｒｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）装置を用いて測定することができる。エネルギーギャップＥｇは、例えば、分光エリプソメータを用いて測定することができる。 The electron affinity or Ec can be obtained from the ionization potential Ip, which is the difference between the vacuum level and the energy Ev at the top of the valence band, and the energy gap Eg. The ionization potential Ip can be measured, for example, using an ultraviolet photoelectron spectroscopy (UPS) device. The energy gap Eg can be measured, for example, using a spectroscopic ellipsometer.
　また、トランジスタＴｒ１の構成において、金属酸化物２３０ｂの上面、及び側面に、ソース電極又はドレイン電極を形成する際の加工ダメージが生じる場合がある。つまり、金属酸化物２３０ｂと、金属酸化物２３０ｃとの界面近傍に加工ダメージによる欠陥が生じる場合がある。金属酸化物２３０ｂと、金属酸化物２３０ｃとは、等しい組成の金属酸化物半導体か、又は近傍の組成の金属酸化物半導体を用いることで、金属酸化物２３０ｂのＥｃと、金属酸化物２３０ｃとのＥｃ差が同じか小さいので、チャネルが形成される領域は、金属酸化物２３０ｂと、金属酸化物２３０ｃとの界面近傍だけではなく、金属酸化物２３０ｃと、第１のゲート絶縁体としての機能を有する絶縁体２５０と、の界面近傍にも形成される。 Further, in the configuration of the transistor Tr1, processing damage may occur when the source electrode or the drain electrode is formed on the upper surface and the side surface of the metal oxide 230b. That is, defects due to processing damage may occur in the vicinity of the interface between the metal oxide 230b and the metal oxide 230c. The metal oxide 230b and the metal oxide 230c may be metal oxide semiconductors having the same composition or metal oxide semiconductors having a composition nearby, so that the Ec of the metal oxide 230b and the metal oxide 230c can be used. Since the Ec difference is the same or smaller, the region in which the channel is formed is not only in the vicinity of the interface between the metal oxide 230b and the metal oxide 230c, but also functions as the metal oxide 230c and the first gate insulator. It is also formed in the vicinity of the interface with the insulator 250.
　よって、加工ダメージを有する金属酸化物２３０ｂと、金属酸化物２３０ｃとの界面近傍の影響を小さくすることができる。さらに、金属酸化物２３０ｃとなる金属酸化物と、第１のゲート絶縁体としての機能を有する絶縁体２５０となる絶縁体を積層して成膜した後に、金属酸化物２３０ｃとなる金属酸化物と、絶縁体２５０となる絶縁体を加工し、金属酸化物２３０ｃと、絶縁体２５０と、を形成すれば、金属酸化物２３０ｃと、絶縁体２５０と、の界面近傍は、加工によるダメージの影響を受けず良好となる。 Thus, the influence of the vicinity of the interface between the metal oxide 230b having processing damage and the metal oxide 230c can be reduced. Further, after a metal oxide to be the metal oxide 230c and an insulator to be the insulator 250 having a function as a first gate insulator are stacked and formed, a metal oxide to be the metal oxide 230c and If the insulator to be the insulator 250 is processed to form the metal oxide 230c and the insulator 250, the vicinity of the interface between the metal oxide 230c and the insulator 250 is affected by the damage caused by the processing. It becomes good without receiving.
　以上により、トランジスタＴｒ１の信頼性を向上させることができる。また、金属酸化物２３０ｂの全体及び金属酸化物２３０ｃの一部が、導電体２６０の電界によって取り囲まれていることから非導通時の電流（オフ電流）を小さくすることができる。 Thus, the reliability of the transistor Tr1 can be improved. Further, since the whole of the metal oxide 230b and a part of the metal oxide 230c are surrounded by the electric field of the conductor 260, the current (off current) at the time of non-conduction can be reduced.
　また、トランジスタは、第１のゲート電極としての機能を有する導電体２６０と、ソース電極又はドレイン電極としての機能を有する導電体２４０ａ１及び導電体２４０ａ２と、は重なる領域を有することで、導電体２６０と、導電体２４０ａ１と、で形成される寄生容量及び、導電体２６０と、導電体２４０ａ２と、で形成される寄生容量を有する。 In addition, the transistor includes a region in which the conductor 260 having a function as a first gate electrode and the conductor 240a1 and the conductor 240a2 having a function as a source electrode or a drain electrode overlap with each other. And the conductor 240a1, and the parasitic capacitance formed by the conductor 260 and the conductor 240a2.
　トランジスタの構成は、導電体２６０と、導電体２４０ａ１と、の間には、絶縁体２５０、金属酸化物２３０ｃに加えて、バリア膜２４０ｂ１を有していることで、該寄生容量を小さくすることができる。同様に、導電体２６０と、導電体２４０ａ２と、の間には、絶縁体２５０、金属酸化物２３０ｃに加えて、バリア膜２４０ｂ２を有していることで、該寄生容量を小さくすることができる。よって、トランジスタは、周波数特性に優れたトランジスタとなる。 The transistor has a barrier film 240 b 1 in addition to the insulator 250 and the metal oxide 230 c between the conductor 260 and the conductor 240 a 1 to reduce the parasitic capacitance. Can. Similarly, in addition to the insulator 250 and the metal oxide 230c, the barrier film 240b2 is provided between the conductor 260 and the conductor 240a2, whereby the parasitic capacitance can be reduced. . Thus, the transistor is a transistor with excellent frequency characteristics.
　また、トランジスタを上記の構成とすることで、トランジスタの動作時、例えば、導電体２６０と、導電体２４０ａ１又は導電体２４０ａ２との間に電位差が生じたときに、導電体２６０と、導電体２４０ａ１又は導電体２４０ａ２と、の間のリーク電流を低減又は防止することができる。 In addition, when the transistor has the above-described structure, for example, when a potential difference occurs between the conductor 260 and the conductor 240a1 or 240a2 during operation of the transistor, the conductor 260 and the conductor 240a1 Alternatively, leakage current between the conductor 240a2 and the conductor 240a2 can be reduced or prevented.
　導電体２０５は、絶縁体２１６に形成された開口に設けられている。絶縁体２１６の開口の内壁に接して導電体２０５ａが形成され、さらに内側に導電体２０５ｂが形成されている。ここで、導電体２０５ａ及び導電体２０５ｂの上面の高さと、絶縁体２１６の上面の高さは同程度にできる。導電体２０５は、第２のゲート電極としての機能を有する。また、導電体２０５は、酸素の透過を抑制する機能を有する導電体を含む多層膜とすることもできる。例えば、導電体２０５ａを酸素の透過を抑制する機能を有する導電体とすることで、導電体２０５ｂの酸化による導電率の低下を防ぐことができる。 The conductor 205 is provided in an opening formed in the insulator 216. A conductor 205a is formed in contact with the inner wall of the opening of the insulator 216, and a conductor 205b is formed further inside. Here, the heights of the top surfaces of the conductors 205a and 205b and the top surface of the insulator 216 can be approximately the same. The conductor 205 has a function as a second gate electrode. The conductor 205 can also be a multilayer film including a conductor having a function of suppressing permeation of oxygen. For example, by using the conductor 205a as a conductor having a function of suppressing permeation of oxygen, a decrease in conductivity due to oxidation of the conductor 205b can be prevented.
　絶縁体２２０、絶縁体２２２及び絶縁体２２４は第２のゲート絶縁膜としての機能を有する。導電体２０５へ印加する電位によって、トランジスタの閾値電圧を制御することができる。 The insulator 220, the insulator 222, and the insulator 224 function as a second gate insulating film. The potential applied to the conductor 205 can control the threshold voltage of the transistor.
　図２５が、図２４と異なる構成を有するトランジスタＴｒ１を有する半導体装置の上面図である。図２５は、図２４（Ｂ）および（Ｃ）において、導電体２６０の端部が絶縁体２５０の端部、及び金属酸化物２３０ｃの端部と面一である。絶縁体２４１は、導電体２６０の上面と側面を覆うように配置され、さらに、絶縁体２５０の端部、及び金属酸化物２３０ｃの端部に接して配置される。さらに、絶縁体２４１は、バリア膜２４０ｂ１上及びバリア膜２４０ｂ２上に配置され、バリア膜２４０ｂ１の端部、導電体２４０ａ１の端部、バリア膜２４０ｂ２の端部、及び導電体２４０ａ２の端部に接して配置される。さらに、絶縁体２４１は、絶縁体２２４上に配置される。 FIG. 25 is a top view of a semiconductor device having a transistor Tr1 having a configuration different from that of FIG. In FIGS. 25B and 25C, the end of the conductor 260 is flush with the end of the insulator 250 and the end of the metal oxide 230c. The insulator 241 is disposed so as to cover the top and side surfaces of the conductor 260, and is disposed in contact with the end of the insulator 250 and the end of the metal oxide 230c. Furthermore, the insulator 241 is disposed on the barrier film 240b1 and the barrier film 240b2, and is in contact with the end of the barrier film 240b1, the end of the conductor 240a1, the end of the barrier film 240b2, and the end of the conductor 240a2. Will be placed. Furthermore, the insulator 241 is disposed on the insulator 224.
＜絶縁体＞
　絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。 <Insulator>
The insulator includes, for example, an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, and the like.
　トランジスタを、水素などの不純物及び酸素の透過を抑制する機能を有する絶縁体で囲うことによって、トランジスタの電気特性を安定にすることができる。例えば、絶縁体２０２、絶縁体２１５、絶縁体２４１、及び絶縁体２８２として、水素などの不純物を吸着、又は酸素の透過を抑制する機能を有する絶縁体を用いればよい。さらに、絶縁体２０２、絶縁体２１５、絶縁体２４１、及び絶縁体２８２は、酸素を供給する機能を有する絶縁体を用いればよい。 The electrical characteristics of the transistor can be stabilized by surrounding the transistor with an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen. For example, as the insulator 202, the insulator 215, the insulator 241, and the insulator 282, an insulator having a function of adsorbing an impurity such as hydrogen or suppressing permeation of oxygen may be used. Further, for the insulator 202, the insulator 215, the insulator 241, and the insulator 282, an insulator having a function of supplying oxygen may be used.
　水素などの不純物及び酸素の透過を抑制する機能を有する絶縁体としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウム又はタンタルを含む絶縁体を、単層で、又は積層で用いればよい。 As an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium An insulator containing lanthanum, neodymium, hafnium or tantalum may be used in a single layer or a stack.
　また、例えば、絶縁体２０２、絶縁体２１５、絶縁体２４１、及び絶縁体２８２としては、酸化アルミニウム、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウム又は酸化タンタルなどの金属酸化物、窒化酸化シリコン又は窒化シリコンなどを用いればよい。なお、絶縁体２０２、絶縁体２１５、絶縁体２４１、及び絶縁体２８２は、酸化アルミニウムを有することが好ましい。 For example, as the insulator 202, the insulator 215, the insulator 241, and the insulator 282, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like may be used. Note that the insulator 202, the insulator 215, the insulator 241, and the insulator 282 preferably include aluminum oxide.
　また、例えば、絶縁体２８２をスパッタリング法によって、酸素を有するプラズマを用いて成膜すると該絶縁体の下地層となる絶縁体へ酸素を添加することができる。 Alternatively, for example, when the insulator 282 is formed by sputtering using an oxygen-containing plasma, oxygen can be added to the insulator to be the base layer of the insulator.
　絶縁体２１６、絶縁体２２０、絶縁体２２４及び絶縁体２５０としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウム又はタンタルを含む絶縁体を、単層で、又は積層で用いればよい。例えば、絶縁体２１６、絶縁体２２０、絶縁体２２４及び絶縁体２５０としては、酸化シリコン、酸化窒化シリコン又は、窒化シリコンを有することが好ましい。 As the insulator 216, the insulator 220, the insulator 224, and the insulator 250, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, An insulator containing lanthanum, neodymium, hafnium or tantalum may be used in a single layer or a stack. For example, as the insulator 216, the insulator 220, the insulator 224, and the insulator 250, silicon oxide, silicon oxynitride, or silicon nitride is preferably included.
　特に絶縁体２２４及び絶縁体２５０は、比誘電率の高い絶縁体を有することが好ましい。例えば、絶縁体２２４及び絶縁体２５０は、酸化ガリウム、酸化ハフニウム、酸化ジルコニウム、アルミニウム及びハフニウムを有する酸化物、アルミニウム及びハフニウムを有する酸化窒化物、シリコン及びハフニウムを有する酸化物、シリコン及びハフニウムを有する酸化窒化物又はシリコン及びハフニウムを有する窒化物などを有することが好ましい。又は、絶縁体２２４及び絶縁体２５０は、酸化シリコン又は酸化窒化シリコンと、比誘電率の高い絶縁体と、の積層構造を有することが好ましい。酸化シリコン及び酸化窒化シリコンは、熱的に安定であるため、比誘電率の高い絶縁体と組み合わせることで、熱的に安定かつ比誘電率の高い積層構造とすることができる。例えば、絶縁体２２４及び絶縁体２５０において、酸化アルミニウム、酸化ガリウム又は酸化ハフニウムを酸化物２０３と接する構造とすることで、酸化シリコン又は酸化窒化シリコンに含まれるシリコンが、酸化物２０３に混入することを抑制することができる。また、例えば、絶縁体２２４及び絶縁体２５０において、酸化シリコン又は酸化窒化シリコンを酸化物２０３と接する構造とすることで、酸化アルミニウム、酸化ガリウム又は酸化ハフニウムと、酸化シリコン又は酸化窒化シリコンと、の界面にトラップセンターが形成される場合がある。該トラップセンターは、電子を捕獲することでトランジスタの閾値電圧をプラス方向に変動させることができる場合がある。 In particular, the insulator 224 and the insulator 250 preferably include an insulator with a high dielectric constant. For example, the insulator 224 and the insulator 250 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, silicon and hafnium It is preferable to have oxynitride or nitride including silicon and hafnium. Alternatively, the insulator 224 and the insulator 250 preferably have a stacked-layer structure of silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. Silicon oxide and silicon oxynitride are thermally stable, and thus, when combined with an insulator with a high dielectric constant, a stacked structure with a thermally stable high dielectric constant can be obtained. For example, in the insulator 224 and the insulator 250, silicon contained in silicon oxide or silicon oxynitride is mixed into the oxide 203 by providing aluminum oxide, gallium oxide, or hafnium oxide in contact with the oxide 203. Can be suppressed. In addition, for example, in the insulator 224 and the insulator 250, silicon oxide or silicon oxynitride is in contact with the oxide 203, whereby aluminum oxide, gallium oxide, or hafnium oxide, and silicon oxide or silicon oxynitride can be used. Trap centers may be formed at the interface. The trap center may be able to shift the threshold voltage of the transistor in the positive direction by capturing electrons.
　絶縁体２８０は、比誘電率の低い絶縁体を有することが好ましい。例えば、絶縁体２８０は、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素及び窒素を添加した酸化シリコン、空孔を有する酸化シリコン又は樹脂などを有することが好ましい。又は、絶縁体２８０は、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素及び窒素を添加した酸化シリコン又は空孔を有する酸化シリコンと、樹脂と、の積層構造を有することが好ましい。酸化シリコン及び酸化窒化シリコンは、熱的に安定であるため、樹脂と組み合わせることで、熱的に安定かつ比誘電率の低い積層構造とすることができる。樹脂としては、例えば、ポリイミド樹脂、ポリアミド（ナイロン、アラミドなど）樹脂、アクリル樹脂、シロキサン樹脂、エポキシ樹脂、フェノール樹脂、ポリカーボネート樹脂、ポリエステル樹脂、ポリオレフィン樹脂等の有機樹脂がある。 The insulator 280 preferably includes an insulator with a low relative dielectric constant. For example, the insulator 280 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having vacancies Alternatively, it is preferable to have a resin or the like. Alternatively, the insulator 280 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with carbon and nitrogen, or silicon oxide with voids. It is preferable to have a laminated structure of and a resin. Silicon oxide and silicon oxynitride are thermally stable, and thus, when combined with a resin, a stacked structure with a thermally stable and low dielectric constant can be obtained. Examples of the resin include organic resins such as polyimide resin, polyamide (nylon, aramid etc.) resin, acrylic resin, siloxane resin, epoxy resin, phenol resin, polycarbonate resin, polyester resin, polyolefin resin and the like.
　バリア膜２４０ｂ１及びバリア膜２４０ｂ２としては、水素などの不純物及び酸素の透過を抑制する機能を有する絶縁体を用いればよい。バリア膜２４０ｂ１、バリア膜２４０ｂ２、バリア膜２４０ｂ１及びバリア膜２４０ｂ２によって、絶縁体２８０中の過剰酸素が、導電体２４０ａ１、導電体２４０ａ２への拡散することを防止することができる。 As the barrier film 240b1 and the barrier film 240b2, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen can be used. The barrier film 240b1, the barrier film 240b2, the barrier film 240b1, and the barrier film 240b2 can prevent excess oxygen in the insulator 280 from diffusing into the conductor 240a1 and the conductor 240a2.
　バリア膜２４０ｂ１及びバリア膜２４０ｂ２としては、例えば、酸化アルミニウム、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウム又は酸化タンタルなどの金属酸化物、窒化酸化シリコン又は窒化シリコンなどを用いればよい。 As the barrier film 240b1 and the barrier film 240b2, for example, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, metal oxide such as hafnium oxide or tantalum oxide, silicon nitride oxide Alternatively, silicon nitride or the like may be used.
＜導電体＞
　導電体２６０ａ、導電体２６０ｂ、導電体２０５ａ、導電体２０５ｂ、導電体２４０ａ１及び導電体２４０ａ２としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を１種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。 <Conductor>
As the conductor 260a, the conductor 260b, the conductor 205a, the conductor 205b, the conductor 240a1, and the conductor 240a2, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, A material containing one or more metal elements selected from vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium and the like can be used. Alternatively, a semiconductor with high electrical conductivity, typically a polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
　また、酸化物２０３に適用可能な金属酸化物に含まれる金属元素及び酸素を含む導電性材料を用いてもよい。また、前述した金属元素及び窒素を含む導電性材料を用いてもよい。例えば、窒化チタン、窒化タンタルなどの窒素を含む導電性材料を用いてもよい。また、インジウム錫酸化物、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、シリコンを添加したインジウム錫酸化物を用いてもよい。また、窒素を含むインジウムガリウム亜鉛酸化物を用いてもよい。このような材料を用いることで、酸化物２０３に含まれる水素を捕獲することができる場合がある。又は、外方の絶縁体などから侵入する水素を捕獲することができる場合がある。 Alternatively, a conductive material containing a metal element contained in a metal oxide applicable to the oxide 203 and oxygen may be used. Alternatively, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added. Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide 203 may be captured in some cases. Alternatively, it may be possible to capture hydrogen entering from an outer insulator or the like.
　また、上記の材料で形成される導電層を複数積層して用いてもよい。例えば、前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料と、窒素を含む導電性材料と、を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料と、酸素を含む導電性材料と、窒素を含む導電性材料と、を組み合わせた積層構造としてもよい。 Alternatively, a plurality of conductive layers formed of the above materials may be stacked. For example, a stacked structure in which a material containing a metal element described above and a conductive material containing oxygen are combined may be used. Alternatively, a stacked structure in which the material containing the metal element described above and the conductive material containing nitrogen are combined may be used. Alternatively, a stacked structure in which the above-described material containing a metal element, the conductive material containing oxygen, and the conductive material containing nitrogen are combined may be used.
　なお、トランジスタのチャネル形成領域に酸化物を用いる場合は、ゲート電極として前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造を用いることが好ましい。この場合は、酸素を含む導電性材料をチャネル形成領域側に設けるとよい。酸素を含む導電性材料をチャネル形成領域側に設けることで、当該導電性材料から離脱した酸素がチャネル形成領域に供給されやすくなる。 Note that in the case where an oxide is used for a channel formation region of a transistor, a stacked structure in which a material containing a metal element described above as the gate electrode and a conductive material containing oxygen are preferably used. In this case, a conductive material containing oxygen may be provided on the channel formation region side. By providing the conductive material containing oxygen in the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region.
　本実施の形態は、他の実施の形態と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the other embodiments.
（実施の形態６）
　本実施の形態では、上記実施の形態に示した記憶装置又は半導体装置を有する半導体ウエハ、ＩＣチップ及び電子部品の例について、図２６及び図２８を用いて説明する。 Sixth Embodiment
In this embodiment, examples of a semiconductor wafer, an IC chip, and an electronic component including the memory device or the semiconductor device described in the above embodiments will be described with reference to FIGS.
〔半導体ウエハ、チップ〕
　図２６（Ａ）は、ダイシング処理が行われる前の基板６１１の上面図を示している。基板６１１としては、例えば、半導体基板（「半導体ウエハ」ともいう。）を用いることができる。基板６１１上には、複数の回路領域６１２が設けられている。回路領域６１２には、上記実施の形態に示す半導体装置などを設けることができる。 [Semiconductor wafer, chip]
FIG. 26A shows a top view of the substrate 611 before the dicing process is performed. As the substrate 611, for example, a semiconductor substrate (also referred to as a "semiconductor wafer") can be used. A plurality of circuit regions 612 are provided on the substrate 611. The circuit region 612 can be provided with the semiconductor device described in the above embodiment or the like.
　複数の回路領域６１２は、それぞれが分離領域６１３に囲まれている。分離領域６１３と重なる位置に分離線（「ダイシングライン」ともいう。）６１４が設定される。分離線６１４に沿って基板６１１を切断することで、回路領域６１２を含むチップ６１５を基板６１１から切り出すことができる。図２６（Ｂ）にチップ６１５の拡大図を示す。 Each of the plurality of circuit areas 612 is surrounded by the separation area 613. A separation line (also referred to as a “dicing line”) 614 is set at a position overlapping with the separation region 613. By cutting the substrate 611 along the separation line 614, the chip 615 including the circuit region 612 can be cut from the substrate 611. An enlarged view of the chip 615 is shown in FIG.
　また、分離領域６１３に導電層や半導体層を設けてもよい。分離領域６１３に導電層や半導体層を設けることで、ダイシング工程時に生じうるＥＳＤを緩和し、ダイシング工程の歩留まり低下を防ぐことができる。また、一般にダイシング工程は、基板の冷却、削りくずの除去、帯電防止などを目的として、炭酸ガスなどを含有させて比抵抗を下げた純水を切削部に流しながら行われる。分離領域６１３に導電層や半導体層を設けることで、当該純水の使用量を削減することができる。よって、半導体装置の生産コストを低減することができる。また、半導体装置の生産性を高めることができる。 In addition, a conductive layer or a semiconductor layer may be provided in the separation region 613. By providing a conductive layer or a semiconductor layer in the separation region 613, ESD that may occur in the dicing step can be alleviated and yield reduction in the dicing step can be prevented. In general, the dicing step is carried out while flowing pure water having a reduced specific resistance into the cutting portion for the purpose of cooling the substrate, removing shavings, preventing charging, etc. By providing a conductive layer or a semiconductor layer in the separation region 613, the amount of pure water used can be reduced. Thus, the production cost of the semiconductor device can be reduced. In addition, the productivity of the semiconductor device can be enhanced.
　分離領域６１３に設ける半導体層としては、バンドギャップが２．５ｅＶ以上４．２ｅＶ以下、好ましくは２．７ｅＶ以上３．５ｅＶ以下の材料を用いることが好ましい。このような材料を用いると、蓄積された電荷をゆっくりと放電することができるため、ＥＳＤによる電荷の急激な移動が抑えられ、静電破壊を生じにくくすることができる。 As a semiconductor layer provided in the separation region 613, a material having a band gap of 2.5 eV or more and 4.2 eV or less, preferably 2.7 eV or more and 3.5 eV or less is preferably used. When such a material is used, the accumulated charge can be discharged slowly, so that rapid movement of the charge due to ESD can be suppressed and electrostatic breakdown can be made less likely to occur.
〔電子部品〕
　チップ６１５を電子部品に適用する例について、図２７を用いて説明する。なお、電子部品は、半導体パッケージ、又はＩＣ用パッケージともいう。電子部品は、端子取り出し方向や、端子の形状に応じて、複数の規格や名称が存在する。 [Electronic parts]
An example in which the chip 615 is applied to an electronic component is described with reference to FIG. Note that the electronic component is also referred to as a semiconductor package or a package for an IC. The electronic component has a plurality of standards and names depending on the terminal extraction direction and the shape of the terminal.
　電子部品は、組み立て工程（後工程）において、上記実施の形態に示した半導体装置と該半導体装置以外の部品が組み合わされて完成する。 The electronic component is completed by combining the semiconductor device described in the above embodiment and components other than the semiconductor device in an assembly process (post process).
　図２７（Ａ）に示すフローチャートを用いて、後工程について説明する。前工程において上記実施の形態に示した半導体装置を有する素子基板が完成した後、該素子基板の裏面（半導体装置などが形成されていない面）を研削する「裏面研削工程」を行う（ステップＳ１）。研削により素子基板を薄くすることで、素子基板の反りなどを低減し、電子部品の小型化を図ることができる。 The subsequent steps will be described using the flowchart shown in FIG. After the element substrate having the semiconductor device described in the above embodiment is completed in the previous step, a “back surface grinding step” is performed to grind the back surface (the surface on which the semiconductor device and the like are not formed) of the element substrate (step S1) ). By thinning the element substrate by grinding, warpage or the like of the element substrate can be reduced, and miniaturization of the electronic component can be achieved.
　次に、素子基板を複数のチップに分離する「ダイシング工程」を行う（ステップＳ２）。そして、分離したチップを個々ピックアップしてリードフレーム上に接合する「ダイボンディング工程」を行う（ステップＳ３）。ダイボンディング工程におけるチップとリードフレームとの接合は、樹脂による接合や、テープによる接合など、適宜製品に応じて適した方法を選択する。なお、リードフレームに代えてインターポーザ基板上にチップを接合してもよい。 Next, a “dicing process” is performed to separate the element substrate into a plurality of chips (step S2). Then, a "die bonding step" is performed in which the separated chips are individually picked up and bonded onto the lead frame (step S3). The bonding between the chip and the lead frame in the die bonding step is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. The chip may be bonded onto the interposer substrate instead of the lead frame.
　次いで、リードフレームのリードとチップ上の電極とを、金属の細線（ワイヤー）で電気的に接続する「ワイヤーボンディング工程」を行う（ステップＳ４）。金属の細線には、銀線や金線を用いることができる。また、ワイヤーボンディングは、ボールボンディングや、ウェッジボンディングを用いることができる。 Next, a "wire bonding step" is performed to electrically connect the lead of the lead frame and the electrode on the chip with a metal thin wire (wire) (step S4). A silver wire or a gold wire can be used for the thin metal wire. Moreover, wire bonding can use ball bonding or wedge bonding.
　ワイヤーボンディングされたチップは、エポキシ樹脂などで封止される「封止工程（モールド工程）」が施される（ステップＳ５）。封止工程を行うことで電子部品の内部が樹脂で充填され、チップに内蔵される回路部やチップとリードを接続するワイヤーを機械的な外力から保護することができ、また水分や埃による特性の劣化（信頼性の低下）を低減することができる。 The wire-bonded chip is subjected to a “sealing process (molding process)” in which the chip is sealed with an epoxy resin or the like (step S5). By performing the sealing process, the inside of the electronic component is filled with a resin, and the circuit portion incorporated in the chip and the wire connecting the chip and the lead can be protected from mechanical external force, and characteristics due to moisture and dust Degradation (reliability degradation) can be reduced.
　次いで、リードフレームのリードをめっき処理する「リードめっき工程」を行なう（ステップＳ６）。めっき処理によりリードの錆を防止し、後にプリント基板に設ける際のはんだ付けをより確実に行うことができる。次いで、リードを切断及び成形加工する「成形工程」を行なう（ステップＳ７）。 Next, a “lead plating process” is performed to plate the leads of the lead frame (step S6). The plating process can prevent rusting of the leads, and can be more reliably soldered later when provided on a printed circuit board. Next, a "forming step" of cutting and forming the lead is performed (step S7).
　次いで、パッケージの表面に印字処理（マーキング）を施す「マーキング工程」を行なう（ステップＳ８）。そして外観形状の良否や動作不良の有無などを調べる「検査工程」（ステップＳ９）を経て、電子部品が完成する。 Next, a "marking process" is performed to print (mark) the surface of the package (step S8). Then, an electronic component is completed through an “inspection step” (step S9) for checking whether the appearance shape is good or bad, and the like.
　また、完成した電子部品の斜視模式図を図２７（Ｂ）に示す。図２７（Ｂ）では、電子部品の一例として、ＱＦＰ（Ｑｕａｄ　Ｆｌａｔ　Ｐａｃｋａｇｅ）の斜視模式図を示している。図２７（Ｂ）に示す電子部品６５０は、リード６５５及び半導体装置６５３を示している。半導体装置６５３としては、上記実施の形態に示した記憶装置又は半導体装置などを用いることができる。 Further, FIG. 27B is a schematic perspective view of the completed electronic component. FIG. 27B illustrates a schematic perspective view of a quad flat package (QFP) as an example of the electronic component. An electronic component 650 illustrated in FIG. 27B illustrates a lead 655 and a semiconductor device 653. As the semiconductor device 653, the memory device or the semiconductor device described in the above embodiment can be used.
　図２７（Ｂ）に示す電子部品６５０は、例えばプリント基板６５２に設けられる。このような電子部品６５０が複数組み合わされて、それぞれがプリント基板６５２上で電気的に接続されることで電子部品が設けられた基板６５４が完成する。完成した基板６５４は、電子機器などに用いられる。 The electronic component 650 illustrated in FIG. 27B is provided, for example, on a printed substrate 652. A plurality of such electronic components 650 are combined and electrically connected on the printed circuit board 652 to complete a substrate 654 provided with the electronic components. The completed substrate 654 is used for an electronic device or the like.
　本実施の形態は、他の実施の形態と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the other embodiments.
（実施の形態７）
　本実施の形態では、上記実施の形態で説明した半導体装置、表示装置、及び／又は記憶装置が搭載された電子機器の例について説明する。 Seventh Embodiment
In this embodiment, an example of an electronic device in which the semiconductor device, the display device, and / or the memory device described in any of the above embodiments is mounted will be described.
　本発明の一態様に係る半導体装置、表示装置、及び／又は記憶装置は、様々な電子機器に搭載することができる。電子機器の例としては、例えば、テレビジョン装置、デスクトップ型もしくはノート型のパーソナルコンピュータ、コンピュータ用などのモニタ、デジタルサイネージ（Ｄｉｇｉｔａｌ　Ｓｉｇｎａｇｅ：電子看板）、パチンコ機などの大型ゲーム機などの比較的大きな画面を備える電子機器の他、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、などが挙げられる。 The semiconductor device, the display device, and / or the memory device of one embodiment of the present invention can be mounted on various electronic devices. Examples of the electronic devices include, for example, television devices, desktop or notebook personal computers, monitors for computers, etc., large-sized game machines such as digital signage (Digital Signage), pachinko machines, etc. In addition to electronic devices equipped with screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound reproduction devices, etc. may be mentioned.
　本発明の一態様の電子機器は、アンテナを有していてもよい。アンテナで信号を受信することで、表示部で映像や情報等の表示を行うことができる。また、電子機器がアンテナ及び二次電池を有する場合、アンテナを、非接触電力伝送に用いてもよい。 The electronic device of one embodiment of the present invention may have an antenna. By receiving the signal with the antenna, display of images, information, and the like can be performed on the display portion. In addition, when the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.
　本発明の一態様の電子機器は、センサ（力、変位、位置、速度、加速度、角速度、回転数、距離、光、液、磁気、温度、化学物質、音声、時間、硬度、電場、電流、電圧、電力、放射線、流量、湿度、傾度、振動、におい又は赤外線を測定する機能を含むもの）を有していてもよい。 The electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow rate, humidity, inclination, vibration, smell or infrared light.
　本発明の一態様の電子機器は、様々な機能を有することができる。例えば、様々な情報（静止画、動画、テキスト画像など）を表示部に表示する機能、タッチパネル機能、カレンダー、日付又は時刻などを表示する機能、様々なソフトウェア（プログラム）を実行する機能、無線通信機能、記録媒体に記録されているプログラム又はデータを読み出す機能等を有することができる。図２８及び図２９に、電子機器の例を示す。 The electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function of displaying date or time, etc., a function of executing various software (programs), wireless communication A function, a function of reading a program or data recorded in a recording medium, or the like can be provided. 28 and 29 show an example of the electronic device.
　図２８（Ａ）に示すロボット２１００は、演算装置２１１０、照度センサ２１０１、マイクロフォン２１０２、上部カメラ２１０３、スピーカ２１０４、ディスプレイ２１０５、下部カメラ２１０６及び障害物センサ２１０７、移動機構２１０８を備える。なお、ここでは一例として、人型のロボットを示している。 The robot 2100 shown in FIG. 28A includes an arithmetic unit 2110, an illuminance sensor 2101, a microphone 2102, an upper camera 2103, a speaker 2104, a display 2105, a lower camera 2106, an obstacle sensor 2107, and a movement mechanism 2108. Here, a humanoid robot is shown as an example.
　ロボット２１００において、演算装置２１１０、照度センサ２１０１、上部カメラ２１０３、下部カメラ２１０６及び障害物センサ２１０７等に、上記半導体装置及び／又は上記記憶装置を使用することができる。 In the robot 2100, the semiconductor device and / or the storage device can be used for the arithmetic device 2110, the illuminance sensor 2101, the upper camera 2103, the lower camera 2106, the obstacle sensor 2107, and the like.
　マイクロフォン２１０２は、使用者の話し声及び環境音等を検知する機能を有する。また、スピーカ２１０４は、音声を発する機能を有する。ロボット２１００は、マイクロフォン２１０２及びスピーカ２１０４を用いて、使用者とコミュニケーションをとることが可能である。 The microphone 2102 has a function of detecting the user's speech and environmental sounds. In addition, the speaker 2104 has a function of emitting sound. The robot 2100 can communicate with the user using the microphone 2102 and the speaker 2104.
　ディスプレイ２１０５は、種々の情報の表示を行う機能を有する。ロボット２１００は、使用者の望みの情報をディスプレイ２１０５に表示することが可能である。なお、ディスプレイ２１０５には、上記表示装置を使用することができる。ディスプレイ２１０５は、タッチパネルを搭載していてもよい。 The display 2105 has a function of displaying various information. The robot 2100 can display information desired by the user on the display 2105. Note that the display device can be used for the display 2105. The display 2105 may have a touch panel.
　上部カメラ２１０３及び下部カメラ２１０６は、ロボット２１００の周囲を撮像する機能を有する。また、障害物センサ２１０７は、ロボット２１００が二足歩行で前進する際の進行方向における障害物の有無を察知することができる。ロボット２１００は、上部カメラ２１０３、下部カメラ２１０６及び障害物センサ２１０７を用いて、周囲の環境を認識し、安全に移動することが可能である。なお、温度変化の大きな環境でロボット２１００が使用される場合は、上記半導体装置、上記記憶装置、上記表示装置、及び／又は上記電子部品を使用することで消費電力の増大を抑制することができる。 The upper camera 2103 and the lower camera 2106 have a function of imaging the periphery of the robot 2100. Also, the obstacle sensor 2107 can detect the presence or absence of an obstacle in the traveling direction when the robot 2100 moves forward with bipedal walking. The robot 2100 can recognize the surrounding environment and move safely by using the upper camera 2103, the lower camera 2106 and the obstacle sensor 2107. In the case where the robot 2100 is used in a large temperature change environment, an increase in power consumption can be suppressed by using the semiconductor device, the memory device, the display device, and / or the electronic component. .
　図２８（Ｂ）は、自動車の一例を示す外観図である。自動車２９８０は、カメラ２９８１等を有する。また、自動車２９８０は、赤外線レーダー、ミリ波レーダー、レーザーレーダーなど各種センサなどを備える。自動車２９８０は、カメラ２９８１が撮影した画像を解析し、歩行者の有無など、周囲の交通状況を判断し、自動運転を行うことができる。 FIG. 28B is an external view showing an example of a car. The automobile 2980 has a camera 2981 and the like. In addition, the automobile 2980 includes various sensors such as an infrared radar, a millimeter wave radar, a laser radar, and the like. The automobile 2980 can analyze an image captured by the camera 2981, determine a surrounding traffic condition such as the presence or absence of a pedestrian, and perform automatic driving.
　自動車２９８０において、カメラ２９８１に上記半導体装置、上記記憶装置、上記表示装置、及び／又は上記電子部品を使用することで消費電力の増大を抑制することができる。 In the automobile 2980, an increase in power consumption can be suppressed by using the semiconductor device, the storage device, the display device, and / or the electronic component for the camera 2981.
　図２８（Ｃ）に、互いに別々の言語で話す複数の人間のコミュニケーションにおいて、携帯電子機器２１３０に同時通訳を行わせる状況を示す。 FIG. 28C shows a state in which the portable electronic device 2130 is caused to perform simultaneous interpretation in communication between a plurality of people who speak different languages from each other.
　携帯電子機器２１３０は、マイクロフォン及びスピーカ等を有し、使用者の話し声を認識してそれを話し相手の話す言語に翻訳する機能を有する。携帯電子機器２１３０の演算装置に、上記半導体装置、上記記憶装置、及び／又は上記電子部品を使用することができる。 The portable electronic device 2130 has a microphone, a speaker, and the like, and has a function of recognizing the user's speech and translating it into the language spoken by the other party. The semiconductor device, the storage device, and / or the electronic component can be used for the arithmetic device of the portable electronic device 2130.
　図２９（Ａ）は、飛行体２１２０を示す外観図である。飛行体２１２０は、演算装置２１２１と、プロペラ２１２３と、カメラ２１２２と、を有し、自律して飛行する機能を有する。 FIG. 29A is an external view showing an aircraft 2120. FIG. The flying body 2120 includes an arithmetic unit 2121, a propeller 2123, and a camera 2122, and has a function of autonomously flying.
　飛行体２１２０において、演算装置２１２１及びカメラ２１２２に上記半導体装置、上記記憶装置、及び／又は上記電子部品を用いることができる。なお、温度変化の大きな環境で飛行体２１２０が使用される場合は、上記半導体装置、上記記憶装置、及び／又は上記電子部品を使用することで消費電力の増大を抑制することができる。 In the aircraft 2120, the semiconductor device, the storage device, and / or the electronic component can be used for the arithmetic device 2121 and the camera 2122. In the case where the flying body 2120 is used in a large temperature change environment, an increase in power consumption can be suppressed by using the semiconductor device, the storage device, and / or the electronic component.
　図２９（Ｂ−１）及び図２９（Ｂ−２）に、飛行体２１２０の使用形態の例を示す。図２９（Ｂ−１）に示すように、飛行体２１２０は貨物２１２４の運搬に用いることができる。また、図２９（Ｂ−２）に示すように、飛行体２１２０に農薬を封入した容器２１２５を搭載し、飛行体２１２０を農薬の散布に用いることができる。 29 (B-1) and 29 (B-2) show examples of usage of the flying object 2120. FIG. As shown in FIG. 29 (B-1), the aircraft 2120 can be used to transport the cargo 2124. Further, as shown in FIG. 29 (B-2), a container 2125 in which a pesticide is sealed is mounted on a flying object 2120, and the flying object 2120 can be used for spraying a pesticide.
　本実施の形態は、他の実施の形態の記載と適宜組み合わせることができる。 This embodiment can be combined with the description of the other embodiments as appropriate.
（実施の形態８）
　本実施の形態では、上記実施の形態で述べたＯＳトランジスタに用いることができるＣＡＣ（Ｃｌｏｕｄ−Ａｌｉｇｎｅｄ　Ｃｏｍｐｏｓｉｔｅ）−ＯＳの構成について説明する。 Eighth Embodiment
In this embodiment mode, a structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the OS transistor described in the above embodiment modes will be described.
　ＣＡＣ−ＯＳとは、例えば、金属酸化物を構成する元素が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上２ｎｍ以下、又はその近傍のサイズで偏在した材料の一構成である。なお、以下では、金属酸化物において、一つあるいはそれ以上の金属元素が偏在し、該金属元素を有する領域が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上２ｎｍ以下、又はその近傍のサイズで混合した状態をモザイク状、又はパッチ状ともいう。 The CAC-OS is one configuration of a material in which, for example, an element constituting a metal oxide is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof. Note that, in the following, in the metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less The state in which they are mixed is also called a mosaic or patch.
　なお、金属酸化物は、少なくともインジウムを含むことが好ましい。特にインジウム及び亜鉛を含むことが好ましい。また、それらに加えて、アルミニウム、ガリウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、又はマグネシウムなどから選ばれた一種、又は複数種が含まれていてもよい。 Note that the metal oxide preferably contains at least indium. In particular, it is preferable to contain indium and zinc. In addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. One or more selected from may be included.
　例えば、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳ（ＣＡＣ−ＯＳの中でもＩｎ−Ｇａ−Ｚｎ酸化物を、特にＣＡＣ−ＩＧＺＯと呼称してもよい。）とは、インジウム酸化物（以下、ＩｎＯＸ１（Ｘ１は０よりも大きい実数）とする。）、又はインジウム亜鉛酸化物（以下、ＩｎＸ２ＺｎＹ２ＯＺ２（Ｘ２、Ｙ２、及びＺ２は０よりも大きい実数）とする。）と、ガリウム酸化物（以下、ＧａＯＸ３（Ｘ３は０よりも大きい実数）とする。）、又はガリウム亜鉛酸化物（以下、ＧａＸ４ＺｎＹ４ＯＺ４（Ｘ４、Ｙ４、及びＺ４は０よりも大きい実数）とする。）などと、に材料が分離することでモザイク状となり、モザイク状のＩｎＯＸ１、又はＩｎＸ２ＺｎＹ２ＯＺ２が、膜中に均一に分布した構成（以下、クラウド状ともいう。）である。 For example, CAC-OS in the In-Ga-Zn oxide (an In-Ga-Zn oxide among the CAC-OS may be particularly referred to as CAC-IGZO) is an indium oxide (hereinafter referred to as InO). X1 (X1 is a real number greater than 0)) or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0)) and gallium Oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)), or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 a real number greater than 0) to.) and the like, the material becomes mosaic by separate into, mosaic InO X1, or in X2 Zn Y2 O Z2 is configured uniformly distributed in the film (hereinafter, cloud Also referred to.) A.
　つまり、ＣＡＣ−ＯＳは、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域とが、混合している構成を有する複合金属酸化物である。なお、本明細書において、例えば、第１の領域の元素Ｍに対するＩｎの原子数比が、第２の領域の元素Ｍに対するＩｎの原子数比よりも大きいことを、第１の領域は、第２の領域と比較して、Ｉｎの濃度が高いとする。 That is, CAC-OS is a composite metal oxide having a structure in which a region in which GaO X3 is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component are mixed. Note that in this specification, for example, the ratio of the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region, It is assumed that the concentration of In is higher than that in the region 2.
　なお、ＩＧＺＯは通称であり、Ｉｎ、Ｇａ、Ｚｎ、及びＯによる１つの化合物をいう場合がある。代表例として、ＩｎＧａＯ３（ＺｎＯ）ｍ１（ｍ１は自然数）、又はＩｎ（１＋ｘ０）Ｇａ（１−ｘ０）Ｏ３（ＺｎＯ）ｍ０（−１≦ｘ０≦１、ｍ０は任意数）で表される結晶性の化合物が挙げられる。 Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. Representative examples are represented by InGaO 3 (ZnO) m1 (m1 is a natural number), or In (1 + x0) Ga ( 1-x0) O 3 (ZnO) m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number) Crystalline compounds are mentioned.
　上記結晶性の化合物は、単結晶構造、多結晶構造、又はＣＡＡＣ構造を有する。なお、ＣＡＡＣ構造とは、複数のＩＧＺＯのナノ結晶がｃ軸配向を有し、かつａ−ｂ面においては配向せずに連結した結晶構造である。 The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane.
　一方、ＣＡＣ−ＯＳは、金属酸化物の材料構成に関する。ＣＡＣ−ＯＳとは、Ｉｎ、Ｇａ、Ｚｎ、及びＯを含む材料構成において、一部にＧａを主成分とするナノ粒子状に観察される領域と、一部にＩｎを主成分とするナノ粒子状に観察される領域とが、それぞれモザイク状にランダムに分散している構成をいう。従って、ＣＡＣ−ＯＳにおいて、結晶構造は副次的な要素である。 On the other hand, CAC-OS relates to the material composition of metal oxides. The CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material configuration including In, Ga, Zn, and O, and nanoparticles composed mainly of In in some components. The area | region observed in shape says the structure currently disperse | distributed to mosaic shape at random, respectively. Therefore, in CAC-OS, the crystal structure is a secondary element.
　なお、ＣＡＣ−ＯＳは、組成の異なる二種類以上の膜の積層構造は含まないものとする。例えば、Ｉｎを主成分とする膜と、Ｇａを主成分とする膜との２層からなる構造は、含まない。 Note that CAC-OS does not include a stacked structure of two or more types of films different in composition. For example, a structure including two layers of a film containing In as a main component and a film containing Ga as a main component is not included.
　なお、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域とは、明確な境界が観察できない場合がある。 In some cases, a clear boundary can not be observed between the region in which GaO X3 is the main component and the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component.
　なお、ガリウムの代わりに、アルミニウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、又はマグネシウムなどから選ばれた一種、又は複数種が含まれている場合、ＣＡＣ−ＯＳは、一部に該金属元素を主成分とするナノ粒子状に観察される領域と、一部にＩｎを主成分とするナノ粒子状に観察される領域とが、それぞれモザイク状にランダムに分散している構成をいう。 In addition, it is selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium instead of gallium. In the case where one or more of the above components are contained, the CAC-OS is partially observed in the form of nanoparticles having the metal element as a main component, and partially having In as a main component. The area | region observed in particle form says the structure currently each disperse | distributed to mosaic form at random.
　ＣＡＣ−ＯＳは、例えば基板を加熱しない条件で、スパッタリング法により形成することができる。また、ＣＡＣ−ＯＳをスパッタリング法で形成する場合、成膜ガスとして、不活性ガス（代表的にはアルゴン）、酸素ガス、及び窒素ガスの中から選ばれたいずれか一つ又は複数を用いればよい。また、成膜時の成膜ガスの総流量に対する酸素ガスの流量比は低いほど好ましく、例えば酸素ガスの流量比を０％以上３０％未満、好ましくは０％以上１０％以下とすることが好ましい。 The CAC-OS can be formed, for example, by sputtering under the condition that the substrate is not heated. In addition, in the case of forming the CAC-OS by a sputtering method, one or more selected from an inert gas (typically, argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the film forming gas at the time of film formation is preferably as low as possible. For example, the flow rate ratio of the oxygen gas is 0% to 30%, preferably 0% to 10%. .
　ＣＡＣ−ＯＳは、Ｘ線回折（ＸＲＤ：Ｘ−ｒａｙ　ｄｉｆｆｒａｃｔｉｏｎ）測定法のひとつであるＯｕｔ−ｏｆ−ｐｌａｎｅ法によるθ／２θスキャンを用いて測定したときに、明確なピークが観察されないという特徴を有する。すなわち、Ｘ線回折測定から、測定領域のａ−ｂ面方向、及びｃ軸方向の配向は見られないことが分かる。 CAC-OS has a feature that a clear peak is not observed when it is measured using a θ / 2θ scan by the Out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. Have. That is, it is understood from the X-ray diffraction measurement that the orientation in the a-b plane direction and the c-axis direction of the measurement region can not be seen.
　またＣＡＣ−ＯＳは、プローブ径が１ｎｍの電子線（ナノビーム電子線ともいう。）を照射することで得られる電子線回折パターンにおいて、リング状に輝度の高い領域と、該リング領域に複数の輝点が観測される。従って、電子線回折パターンから、ＣＡＣ−ＯＳの結晶構造が、平面方向、及び断面方向において、配向性を有さないｎｃ（ｎａｎｏ−ｃｒｙｓｔａｌ）構造を有することがわかる。 Further, in an electron beam diffraction pattern obtained by irradiating an electron beam (also referred to as a nanobeam electron beam) having a probe diameter of 1 nm, the CAC-OS has a ring-like high luminance region and a plurality of bright spots in the ring region. A point is observed. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and in the cross-sectional direction.
　また例えば、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳでは、エネルギー分散型Ｘ線分光法（ＥＤＸ：Ｅｎｅｒｇｙ　Ｄｉｓｐｅｒｓｉｖｅ　Ｘ−ｒａｙ　ｓｐｅｃｔｒｏｓｃｏｐｙ）を用いて取得したＥＤＸマッピングにより、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域とが、偏在し、混合している構造を有することが確認できる。 In addition, for example, in the case of CAC-OS in In-Ga-Zn oxide, a region in which GaO X3 is a main component by EDX mapping acquired using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy) It can be confirmed that a structure in which the In X 2 Zn Y 2 O Z 2 or the region mainly containing In O X 1 is unevenly distributed and mixed is obtained.
　ＣＡＣ−ＯＳは、金属元素が均一に分布したＩＧＺＯ化合物とは異なる構造であり、ＩＧＺＯ化合物と異なる性質を有する。つまり、ＣＡＣ−ＯＳは、ＧａＯＸ３などが主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域と、に互いに相分離し、各元素を主成分とする領域がモザイク状である構造を有する。 The CAC-OS has a structure different from the IGZO compound in which the metal element is uniformly distributed, and has different properties from the IGZO compound. That is, CAC-OS is phase-separated into a region in which GaO X3 or the like is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component, and a region in which each element is a main component Has a mosaic-like structure.
　ここで、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域は、ＧａＯＸ３などが主成分である領域と比較して、導電性が高い領域である。つまり、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域を、キャリアが流れることにより、金属酸化物としての導電性が発現する。従って、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域が、金属酸化物中にクラウド状に分布することで、高い電界効果移動度（μ）が実現できる。 Here, the region whose main component is In X2 Zn Y2 O Z2 or InO X1 is a region whose conductivity is higher than the region whose main component is GaO X3 or the like. That is, when carriers flow in a region mainly containing In X 2 Zn Y 2 O Z 2 or InO X 1 , conductivity as a metal oxide is exhibited. Therefore, high field-effect mobility (μ) can be realized by distributing the region mainly containing In X 2 Zn Y 2 O Z 2 or InO X 1 in the form of a cloud in the metal oxide.
　一方、ＧａＯＸ３などが主成分である領域は、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域と比較して、絶縁性が高い領域である。つまり、ＧａＯＸ３などが主成分である領域が、金属酸化物中に分布することで、リーク電流を抑制し、良好なスイッチング動作を実現できる。 On the other hand, the region in which GaO X3 or the like is the main component is a region in which the insulating property is higher than the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component. That is, a region in which GaO X 3 or the like is a main component is distributed in the metal oxide, so that the leakage current can be suppressed and a good switching operation can be realized.
　従って、ＣＡＣ−ＯＳを半導体素子に用いた場合、ＧａＯＸ３などに起因する絶縁性と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１に起因する導電性とが、相補的に作用することにより、高いオン電流（Ｉｏｎ）、及び高い電界効果移動度（μ）を実現することができる。 Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO X3 and the like and the conductivity caused by In X 2 Zn Y 2 O Z 2 or InO X 1 act complementarily to achieve high results. The on current (I on ) and high field effect mobility (μ) can be realized.
　また、ＣＡＣ−ＯＳを用いた半導体素子は、信頼性が高い。従って、ＣＡＣ−ＯＳは、ディスプレイをはじめとするさまざまな半導体装置に最適である。 In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, CAC-OS is most suitable for various semiconductor devices including displays.
　本実施の形態は、他の実施の形態と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the other embodiments.
　本明細書において、特に断りがない場合、オン電流とは、トランジスタがオン状態にあるときのドレイン電流をいう。オン状態（オンと略す場合もある）とは、特に断りがない場合、ｎチャネル型トランジスタでは、ゲートとソースの間の電圧（ＶＧ）が閾値電圧（Ｖｔｈ）以上の状態、ｐチャネル型トランジスタでは、ＶＧがＶｔｈ以下の状態をいう。例えば、ｎチャネル型のトランジスタのオン電流とは、ＶＧがＶｔｈ以上のときのドレイン電流を言う。また、トランジスタのオン電流は、ドレインとソースの間の電圧（ＶＤ）に依存する場合がある。 In the present specification, unless otherwise specified, the on current refers to the drain current when the transistor is in the on state. The on state (sometimes abbreviated as on) is a state in which the voltage (V G ) between the gate and the source is equal to or higher than the threshold voltage (V th ) in the n-channel transistor unless otherwise noted. In a transistor, V G is lower than or equal to V th . For example, the on current of an n-channel transistor refers to the drain current when V G is greater than or equal to V th . In addition, the on current of the transistor may depend on the voltage (V D ) between the drain and the source.
　本明細書において、特に断りがない場合、オフ電流とは、トランジスタがオフ状態にあるときのドレイン電流をいう。オフ状態（オフと略す場合もある）とは、特に断りがない場合、ｎチャネル型トランジスタでは、ＶＧがＶｔｈよりも低い状態、ｐチャネル型トランジスタでは、ＶＧがＶｔｈよりも高い状態をいう。例えば、ｎチャネル型のトランジスタのオフ電流とは、ＶＧがＶｔｈよりも低いときのドレイン電流を言う。トランジスタのオフ電流は、ＶＧに依存する場合がある。従って、トランジスタのオフ電流が１０−２１Ａ未満である、とは、トランジスタのオフ電流が１０−２１Ａ未満となるＶＧの値が存在することを言う場合がある。 In the present specification, unless otherwise specified, the off current refers to the drain current when the transistor is in the off state. The OFF state (sometimes referred to as OFF), unless otherwise specified, the n-channel type transistor, V G is lower than V th state, the p-channel type transistor, V G is higher than V th state Say For example, the off-state current of an n-channel transistor refers to the drain current when V G is lower than V th . The off current of the transistor may depend on V G. Accordingly, the off current of the transistor is less than 10 -21 A, and may refer to the value of V G to off-current of the transistor is less than 10 -21 A are present.
　また、トランジスタのオフ電流は、ＶＤに依存する場合がある。本明細書において、オフ電流は、特に記載がない場合、ＶＤの絶対値が０．１Ｖ、０．８Ｖ、１Ｖ、１．２Ｖ、１．８Ｖ、２．５Ｖ、３Ｖ、３．３Ｖ、１０Ｖ、１２Ｖ、１６Ｖ、又は２０Ｖにおけるオフ電流を表す場合がある。又は、当該トランジスタが含まれる半導体装置等において使用されるＶＤにおけるオフ電流を表す場合がある。 In addition, the off-state current of the transistor may depend on V D. In the present specification, the off-state current, unless otherwise specified, has an absolute value of V D of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V. , 12 V, 16 V, or 20 V may represent an off current. Alternatively, the off current in V D used in a semiconductor device or the like including the transistor may be expressed.
　本明細書等において、ＸとＹとが接続されている、と明示的に記載されている場合は、ＸとＹとが電気的に接続されている場合と、ＸとＹとが直接接続されている場合とが、本明細書等に開示されているものとする。 In the present specification, when it is explicitly stated that X and Y are connected, X and Y are directly connected when X and Y are electrically connected, and X and Y are directly connected. Cases are disclosed in the present specification and the like.
　ここで、Ｘ、Ｙは、対象物（例えば、装置、素子、回路、配線、電極、端子、導電膜、層、など）であるとする。 Here, X and Y each denote an object (eg, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like).
　ＸとＹとが直接的に接続されている場合の一例としては、ＸとＹとの電気的な接続を可能とする素子（例えば、スイッチ、トランジスタ、容量素子、インダクタ、抵抗素子、ダイオード、表示素子、発光素子、負荷など）を介さずに、ＸとＹとが、接続されている場合である。 As an example in the case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, or the like) capable of electrically connecting X and Y This is the case where X and Y are connected without an element, a light emitting element, a load, etc.).
　ＸとＹとが電気的に接続されている場合の一例としては、ＸとＹとの電気的な接続を可能とする素子（例えば、スイッチ、トランジスタ、容量素子、インダクタ、抵抗素子、ダイオード、表示素子、発光素子、負荷など）が、ＸとＹとの間に１個以上接続されることが可能である。なお、スイッチは、導通状態（オン状態）、又は、非導通状態（オフ状態）になり、電流を流すか流さないかを制御する機能を有している。又は、スイッチは、電流を流す経路を選択して切り替える機能を有している。なお、ＸとＹとが電気的に接続されている場合は、ＸとＹとが直接的に接続されている場合を含むものとする。 As an example when X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, or the like) which enables electrical connection of X and Y One or more elements, light emitting elements, loads, etc.) can be connected between X and Y. Note that the switch is turned on (on) or turned off (off) and has a function of controlling whether current flows or not. Alternatively, the switch has a function of selecting and switching a path through which current flows. In addition, when X and Y are electrically connected, the case where X and Y are directly connected shall be included.
　ＧＬ１：配線、ＧＬ２：配線、ＧＬ３：配線、ＧＬ４：配線、Ｍ１：トランジスタ、ＰＯＮ１：信号、ＰＯＮ２：信号、ＳＬ１：配線、ＳＬ２：配線、ＳＬ３：配線、Ｔａｃ１：トランジスタ、Ｔａｃ２：トランジスタ、Ｔｄｒ１：トランジスタ、Ｔｅｑ１：トランジスタ、Ｔｌｄ１：トランジスタ、Ｔｌｄ２：トランジスタ、Ｔｐｃ１：トランジスタ、Ｔｐｃ２：トランジスタ、Ｔｒ１：トランジスタ、ＶＤＤ１：配線、ＶＤＤ２：配線、１０：半導体装置、１１：バンドギャップリファレンス回路、１１ａ：出力端子、１１ｂ：出力端子、１１ｃ：出力端子、１１ｄ：バンドギャップリファレンス回路、１１ｅ：基準電圧電流生成回路、１２：電圧参照回路、１２ａ：入力端子、１２ｂ：出力端子、１２ｃ：入力端子、１２ｄ：入力端子、１３：選択回路、１３ａ：入力端子、１３ｂ：入力端子、１３ｃ：出力端子、１３ｄ：入力端子、１４：差分検出回路、１５：電圧制御発振器、１６：負電圧生成回路、１６ａ：入力端子、１６ｂ：出力端子、１６ｃ：レベルシフタ回路、１６ｄ：チャージポンプ回路、１６ｅ：入力端子、１６ｆ：入力端子、１７：動作モード制御回路、１８：温度センサ、２０：表示装置、２１：制御部、２２：ディスプレイコントローラ、２３：フレームメモリ、２４：ソースドライバ、２５：ゲートドライバ、２５ａ：ゲートドライバ、２６：表示パネル、２６ａ：画素、２７：ＣＰＵ、３０：アンプ、３１ａ：トランジスタ、３１ｂ：トランジスタ、３１ｃ：トランジスタ、３１ｄ：トランジスタ、３２ａ：抵抗素子、３２ｂ：抵抗素子、３２ｃ：抵抗素子、３３：トランジスタ、３４：抵抗素子、３５：トランジスタ、３６ａ：レベルシフタ、３６ｂ：レベルシフタ、３７ａ：トランジスタ、３７ｂ：トランジスタ、３７ｃ：容量素子、３８ａ：トランジスタ、３８ｂ：トランジスタ、３８ｃ：容量素子、３９：トランジスタ、４１ａ：トランジスタ、４１ｂ：トランジスタ、４１ｃ：トランジスタ、４２ａ：容量素子、４２ｂ：容量素子、４２ｃ：容量素子、４３：表示素子、４４ａ：トランジスタ、４４ｂ：トランジスタ、４４ｃ：トランジスタ、４５：トランジスタ、４６ａ：容量素子、４６ｂ：容量素子、４６ｃ：容量素子、４７：表示素子、４８：トランジスタ、１００：記憶装置、１００ａ：記憶装置、１００ｂ：記憶装置、１１０：メモリセルアレイ、１１０Ａ：メモリセルアレイ、１１０Ｂ：メモリセルアレイ、１１１：周辺回路、１１２：コントロール回路、１１５：周辺回路、１２１：行デコーダ、１２２：列デコーダ、１２３：行ドライバ、１２４：列ドライバ、１２５：入力回路、１２６：出力回路、１３０：メモリセル、１４１：ＰＳＷ、１４２：ＰＳＷ、１５０：サブアレイ、１５１：電源線、２０２：絶縁体、２０３：酸化物、２０５：導電体、２０５ａ：導電体、２０５ｂ：導電体、２１３：基板、２１４：絶縁体、２１５：絶縁体、２１６：絶縁体、２２０：絶縁体、２２２：絶縁体、２２４：絶縁体、２３０：金属酸化物、２３０ａ：金属酸化物、２３０ｂ：金属酸化物、２３０ｃ：金属酸化物、２４０ａ１：導電体、２４０ａ２：導電体、２４０ｂ１：バリア膜、２４０ｂ２：バリア膜、２４１：絶縁体、２５０：絶縁体、２６０：導電体、２６０ａ：導電体、２６０ｂ：導電体、２８０：絶縁体、２８２：絶縁体、３００：基板、３０１：素子分離層、３０２：絶縁体、３０３：絶縁体、３０４：絶縁体、３０５：絶縁体、３１０：プラグ、３１１：プラグ、３１２：プラグ、３１３：プラグ、３２０：配線、３２１：配線、３２２：導電体、３２３：導電体、３２４：絶縁体、３３１：プラグ、３３２：プラグ、３３３：プラグ、３３４：プラグ、３４１：配線、３４２：配線、３４３：配線、３５１：ウェル、３５２：チャネル形成領域、３５３：不純物領域、３５４：不純物領域、３５５：導電性領域、３５６：導電性領域、３５７：ゲート電極、３５８：ゲート絶縁体、３６１：ウェル、３６２：チャネル形成領域、３６３：高濃度不純物領域、３６４：高濃度不純物領域、３６５：導電性領域、３６６：導電性領域、３６７：ゲート電極、３６８：ゲート絶縁体、３６９：側壁絶縁層、３７０：側壁絶縁層、３７１：低濃度不純物領域、３７２：低濃度不純物領域、４００：抵抗素子、４０１：金属酸化物、４０２：導電体、４０３：導電体、６１１：基板、６１２：回路領域、６１３：分離領域、６１４：分離線、６１５：チップ、６５０：電子部品、６５２：プリント基板、６５３：半導体装置、６５４：基板、６５５：リード、８１０：トランジスタ、８１１：トランジスタ、８２０：トランジスタ、８２１：トランジスタ、８２５：トランジスタ、８２６：トランジスタ、８４２：トランジスタ、８４３：トランジスタ、８４４：トランジスタ、８４５：トランジスタ、８４６：トランジスタ、８４７：トランジスタ、８５０：電極、８５２：絶縁層、８５３：絶縁層、８５４：絶縁層、８５５：絶縁層、８５６：半導体層、８５７ａ：電極、８５７ｂ：電極、８５８：電極、８６０：基板、８６１：絶縁層、２１００：ロボット、２１０１：照度センサ、２１０２：マイクロフォン、２１０３：上部カメラ、２１０４：スピーカ、２１０５：ディスプレイ、２１０６：下部カメラ、２１０７：障害物センサ、２１０８：移動機構、２１１０：演算装置、２１２０：飛行体、２１２１：演算装置、２１２２：カメラ、２１２３：プロペラ、２１２４：貨物、２１２５：容器、２１３０：携帯電子機器、２９８０：自動車、２９８１：カメラ GL1: wiring, GL2: wiring, GL3: wiring, GL4: wiring, M1: transistor, PON1: signal, PON2: signal, SL1: wiring, SL2: wiring, SL3: wiring, Tac1: transistor, Tac2: transistor, Tdr1: Transistor, Teq1: transistor, Tld1: transistor, Tld2: transistor, Tpc1: transistor, Tpc2: transistor, Tr1: transistor, VDD1: wiring, VDD2: wiring, 10: semiconductor device, 11: band gap reference circuit, 11a: output terminal , 11b: output terminal, 11c: output terminal, 11d: band gap reference circuit, 11e: reference voltage / current generating circuit, 12: voltage reference circuit, 12a: input terminal, 12b: output terminal, 12c: input terminal, 12d: input end , 13: selection circuit, 13a: input terminal, 13b: input terminal, 13c: output terminal, 13d: input terminal, 14: difference detection circuit, 15: voltage control oscillator, 16: negative voltage generation circuit, 16a: input terminal, 16b: output terminal, 16c: level shifter circuit, 16d: charge pump circuit, 16e: input terminal, 16f: input terminal, 17: operation mode control circuit, 18: temperature sensor, 20: display device, 21: control unit, 22: Display controller, 23: frame memory, 24: source driver, 25: gate driver, 25a: gate driver, 26: display panel, 26a: pixel, 27: CPU, 30: amplifier, 31a: transistor, 31b: transistor, 31c: Transistor, 31d: transistor, 32a: resistive element, 32b: resistive element, 32 A resistance element 33: a transistor 34: a resistance element 35: a transistor 36a: a level shifter 36b: a level shifter 37a: a transistor 37b: a transistor 37c: a capacitive element 38a: a transistor 38b: a transistor 38c: a capacitive element , 39: transistor 41a: transistor 41b: transistor 41c: transistor 42a: capacitive element 42b: capacitive element 42c: capacitive element 43: display element 44a: transistor 44b: transistor 44c: transistor 45 : Transistor, 46a: capacitive element, 46b: capacitive element, 46c: capacitive element, 47: display element, 48: transistor, 100: storage device, 100a: storage device, 100b: storage device, 110: memory cell array, 110A: memo Recell array 110B: memory cell array 111: peripheral circuit 112: control circuit 115: peripheral circuit 121: row decoder 122: column decoder 123: row driver 124: column driver 125: input circuit 126: output Circuit 130: memory cell 141: PSW 142: PSW 150: sub array 151: power supply line 202: insulator 203: oxide 205: conductor 205a: conductor 205b: conductor 213 Substrate: 214: insulator, 215: insulator, 216: insulator, 220: insulator, 222: insulator, 224: insulator, 230: metal oxide, 230a: metal oxide, 230b: metal oxide 230c: metal oxide 240a1: conductor 240a2: conductor 240b1: barrier film 240b2: burr Film, 241: insulator, 250: insulator, 260: conductor, 260a: conductor, 260b: conductor, 280: insulator, 282: insulator, 300: substrate, 301: element isolation layer, 302: insulation Body, 303: Insulator, 304: Insulator, 305: Insulator, 310: Plug, 311: Plug, 312: Plug, 313: Plug, 320: Wiring, 321: Wiring, 322: Conductor, 323: Conductor , 324: insulator, 331: plug, 332: plug, 333: plug, 334: wiring, 342: wiring, 343: wiring, 351: well, 352: channel formation region, 353: impurity region, 354 A: impurity region, 355: conductive region, 356: conductive region, 357: gate electrode, 358: gate insulator, 361: well, 362: channel formation Area, 363: high concentration impurity region, 364: high concentration impurity region, 365: conductive region, 366: conductive region, 367: gate electrode, 368: gate insulator, 369: sidewall insulating layer, 370: sidewall insulating layer , 371: low concentration impurity region, 372: low concentration impurity region, 400: resistance element, 401: metal oxide, 402: conductor, 403: conductor, 611: substrate, 612: circuit region, 613: isolation region, 614: separation line, 615: chip, 650: electronic component, 652: printed circuit board, 653: semiconductor device, 654: substrate, 655: lead, 810: transistor, 811: transistor, 820: transistor, 821: transistor, 825: Transistor, 826: Transistor, 842: Transistor, 843: Transistor, 844: Transistor Ta, 845: Transistor, 846: Transistor, 847: Transistor, 850: Electrode, 852: Insulating layer, 853: Insulating layer, 854: Insulating layer, 855: Insulating layer, 856: Semiconductor layer, 857a: Electrode, 857b: Electrode , 858: electrode, 860: substrate, 861: insulating layer, 2100: robot, 2101: illuminance sensor, 2102: microphone, 2103: upper camera, 2104: speaker, 2105: display, 2106: lower camera, 2107: obstacle sensor , 2108: moving mechanism, 2110: computing device, 2120: flying object, 2121: computing device, 2122: camera, 2123: propeller, 2124: cargo, 2125: container, 2130: portable electronic device, 2980: automobile, 2981: camera

Claims (5)

  1. 　バンドギャップリファレンス回路、電圧参照回路、電圧制御発振器、及び負電圧生成回路を有する半導体装置であって、
    　前記電圧参照回路は、半導体層に金属酸化物を有する第１トランジスタを有し、
    　前記バンドギャップリファレンス回路は、第１電圧、及び第１電流を出力する機能を有し、
    　前記第１トランジスタに前記第１電流を与えることで、前記第１トランジスタの閾値電圧を出力する機能を有し、
    　前記電圧制御発振器は、前記閾値電圧と、前記第１電圧との電位差を第１周波数に変換する機能を有し、
    　前記負電圧生成回路は、前記第１周波数によって第１負電圧を生成する機能を有し、
    　前記第１トランジスタのバックゲートには、前記第１負電圧が与えられることによって前記第１トランジスタの前記閾値電圧が前記第１電圧になるように調整する機能を有する半導体装置。     A semiconductor device having a band gap reference circuit, a voltage reference circuit, a voltage control oscillator, and a negative voltage generation circuit,
    The voltage reference circuit comprises a first transistor having a metal oxide in the semiconductor layer,
    The band gap reference circuit has a function of outputting a first voltage and a first current,
    It has a function of outputting a threshold voltage of the first transistor by supplying the first current to the first transistor,
    The voltage control oscillator has a function of converting a potential difference between the threshold voltage and the first voltage into a first frequency,
    The negative voltage generation circuit has a function of generating a first negative voltage according to the first frequency,
    A semiconductor device having a function of adjusting the threshold voltage of the first transistor to be the first voltage by applying the first negative voltage to a back gate of the first transistor.
  2. 　請求項１において、
    　前記バンドギャップリファレンス回路は、さらに第２電圧を出力する機能を有し、
    　前記電圧制御発振器は、前記閾値電圧と、前記第２電圧との電位差を第２周波数に変換する機能を有し、
    　前記負電圧生成回路は、前記第２周波数によって第２負電圧を生成する機能を有し、
    　前記第１トランジスタのバックゲートには、前記第１負電圧、又は前記第２負電圧のいずれかが与えられる半導体装置。     In claim 1,
    The band gap reference circuit further has a function of outputting a second voltage,
    The voltage controlled oscillator has a function of converting a potential difference between the threshold voltage and the second voltage into a second frequency,
    The negative voltage generation circuit has a function of generating a second negative voltage according to the second frequency,
    The semiconductor device to which either the said 1st negative voltage or the said 2nd negative voltage is given to the back gate of the said 1st transistor.
  3. 　請求項１又は請求項２において、
    　前記半導体装置は、動作モード制御回路を有し、
    　前記第１トランジスタのバックゲートには、前記動作モード制御回路によって選択される前記第１負電圧、又は前記第２負電圧のいずれかが与えられる半導体装置。     In claim 1 or claim 2,
    The semiconductor device has an operation mode control circuit,
    The semiconductor device to which either the said 1st negative voltage selected by the said operation mode control circuit or the said 2nd negative voltage is given to the back gate of a said 1st transistor.
  4. 　請求項１乃至請求項３のいずれか一において、
    　前記半導体装置を有する記憶装置であって、
    　前記記憶装置は、複数のメモリセルを有し、
    　前記メモリセルは、それぞれ半導体層に金属酸化物を有する第２トランジスタを有し、
    　前記第２トランジスタのバックゲートには、前記第１負電圧、又は前記第２負電圧のいずれかが与えられる記憶装置。     In any one of claims 1 to 3,
    A storage device having the semiconductor device, wherein
    The storage device has a plurality of memory cells,
    The memory cell comprises a second transistor each having a metal oxide in the semiconductor layer,
    A storage device to which either the first negative voltage or the second negative voltage is applied to a back gate of the second transistor.
  5. 　請求項１乃至請求項４のいずれか一において、
    　前記半導体装置を有する表示装置であって、
    　前記表示装置は、記憶装置と、表示パネルとを有し、
    　前記表示パネルは、複数の画素を有し、
    　前記画素は、それぞれ半導体層に金属酸化物を有する第３トランジスタを有し、
    　前記第３トランジスタのバックゲートには、前記第１負電圧、又は前記第２負電圧が与えられる表示装置。     In any one of claims 1 to 4,
    A display device having the semiconductor device;
    The display device includes a storage device and a display panel.
    The display panel has a plurality of pixels,
    The pixels each comprise a third transistor having a metal oxide in the semiconductor layer,
    A display device in which the first negative voltage or the second negative voltage is applied to a back gate of the third transistor.
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