WO2019109686A1 - 驱动调整电路及调整方法、显示装置 - Google Patents

驱动调整电路及调整方法、显示装置 Download PDF

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Publication number
WO2019109686A1
WO2019109686A1 PCT/CN2018/103975 CN2018103975W WO2019109686A1 WO 2019109686 A1 WO2019109686 A1 WO 2019109686A1 CN 2018103975 W CN2018103975 W CN 2018103975W WO 2019109686 A1 WO2019109686 A1 WO 2019109686A1
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Prior art keywords
values
driving
charging
voltage
drive
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PCT/CN2018/103975
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English (en)
French (fr)
Inventor
代弘伟
杨富成
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US16/331,433 priority Critical patent/US20210358444A1/en
Publication of WO2019109686A1 publication Critical patent/WO2019109686A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Definitions

  • Embodiments of the present disclosure relate to a drive adjustment circuit, an adjustment method, and a display device.
  • a thin film transistor liquid crystal display is a hold type electro-optical conversion device.
  • the gray scale voltage corresponding to a certain luminance is output from the data drive IC (Integrate Chip), and then written into the pixel electrode through the data line after the transistor (thin film transistor) is turned on.
  • the writing process of the gray scale voltage is the charging process of the pixel electrode of the pixel unit, and the gray scale voltage of the pixel electrode that needs to be written to the pixel unit is as close as possible to the value output by the data driving IC.
  • At least one embodiment of the present disclosure provides a method of adjusting driving, comprising: acquiring one or more charging error values of a group of pixels; determining an adjustment strategy of the driving based on the one or more charging error values; The adjusting policy to adjust the setting of the driving; wherein the determining an adjustment policy of the driving according to the one or more charging error values comprises: if the one or more charging error values satisfy the first The condition reduces the drive; and if the one or more charge error values satisfy the second condition, the drive is increased.
  • each pixel unit in the pixel group is connected to a same scan line, and the scan line is a gate line or a dummy gate line.
  • the pixel group includes N pixel units, and the N pixel units are respectively charged by N writing voltage values provided by N data lines, wherein N is a total number of the data lines, N is a positive integer greater than or equal to 1; and the one or more charging error values of the acquired pixel group includes: respectively reading N writes of the N pixel units a voltage value; measuring a voltage value on the pixel electrode of the N pixel units to obtain N charging voltage values; and subtracting the N writing voltage values from absolute values of the N charging voltage values, respectively The absolute value yields N differences, and the one or more charging error values are determined based on the N differences.
  • the N write voltage values are data voltage values or set fixed voltage values.
  • the scan line is connected to a gate of a driving transistor of each of the pixel units, and the driving transistor is under the control of an on-voltage provided by the scan line.
  • Turning on; and the obtaining the N charging voltage values includes reading the N charging voltage values before turning off the driving transistor.
  • the one charging error value includes an average error value
  • the average error value is an average value of the N difference values
  • the average error value is used for Characterizing the average charging error of the N data lines.
  • the determining, according to the one or more charging error values, the driving adjustment policy includes: if the average error value is greater than the first threshold, subtracting Driving the voltage from a small source, reducing the source drive current or decreasing the duty cycle of the clock signal; or increasing the source drive voltage, increasing the source drive current, or increasing the clock signal if the average error value is less than the second threshold a duty ratio; wherein the first threshold is a positive real number and the second threshold is a negative real number.
  • the multiple charging error values include N independent error values, and the N independent error values are the N differences, and the N independent values.
  • the error values are used to characterize the charging errors of the N data lines, respectively.
  • the determining an adjustment strategy for driving according to one or more charging error values includes: for each data line: if the corresponding independent error value is greater than the first a threshold, reducing a source driving voltage of the data line or decreasing a source driving current of the data line; or increasing a source driving voltage of the data line if a corresponding independent error value thereof is less than a second threshold Or increasing a source drive current of the data line; wherein the first threshold is a positive real number and the second threshold is a negative real number.
  • the using the absolute values of the N charging voltage values and the absolute values of the N writing voltage values respectively obtain N difference values, including : acquiring a time interval at which the host inputs the adjacent two frames of image data to the driving circuit; and calculating the N difference values in the time interval.
  • Embodiments of the present disclosure also provide a driving adjustment circuit, including: a processing sub-circuit configured to acquire one or more charging error values of a pixel group; a policy generation sub-circuit configured to be based on the one or more charging errors a value determining the adjustment policy of the driver; and setting a sub-circuit configured to adjust the setting of the driver according to the adjustment policy; wherein the policy generation sub-circuit is further configured to: if the one or The plurality of charging error values satisfy the first condition to reduce the driving; and if the one or more charging error values satisfy the second condition, increasing the driving.
  • the pixel group includes N pixel units, and the N pixel units are respectively charged by N writing voltage values provided by N data lines, wherein N is a total number of the data lines, N is a positive integer greater than or equal to 1; and the processing sub-circuit is further configured to: read N write voltage values of the N pixel units, respectively; N voltage values on the pixel electrodes of the N pixel units, and N charge voltage values are obtained; and N differential values are obtained by subtracting the absolute values of the N write voltage values from the absolute values of the N charge voltage values, respectively. Determining the one or more charging error values based on the N differences.
  • the policy generation sub-circuit is further configured to: compare the one or more charging error values with a set first threshold and a second threshold to obtain Comparing results; and generating an adjustment strategy for adjusting the drive based on the comparison result; wherein the first threshold is a positive real number and the second threshold is a negative real number.
  • each pixel unit in the pixel group is connected to a same scan line, and the scan line is a gate line or a dummy gate line.
  • the embodiment of the present disclosure further provides a display device comprising the adjustment circuit, the gate drive circuit and the source drive circuit of any of the above embodiments.
  • the source driving circuit is configured to configure a source driving voltage or a source driving current according to a setting of the driving
  • the gate driving circuit is configured to be configured according to the driving. Reduce or increase the time taken by the output gate drive signal.
  • FIG. 1 is a flowchart of a method for adjusting driving according to an embodiment of the present disclosure
  • FIG. 2 is a flowchart of acquiring one or more charging error values of the pixel group of step S200 in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 3 is a flowchart of a method for adjusting driving according to an embodiment of the present disclosure
  • FIG. 4 is a flowchart of a method for adjusting driving according to an embodiment of the present disclosure
  • FIG. 5 is a structural block diagram of a driving adjustment circuit according to an embodiment of the present disclosure.
  • 6A is a block diagram showing the composition of a display device according to an embodiment of the present disclosure.
  • FIG. 6B is a schematic diagram of connection between a display device and a host according to an embodiment of the present disclosure
  • 6C is a circuit diagram of a GOA unit according to an embodiment of the present disclosure.
  • 6D is a timing diagram of a GOA unit according to an embodiment of the present disclosure.
  • FIG. 6E is a schematic diagram of reading a charging voltage value of a pixel unit according to an embodiment of the present disclosure.
  • the driving circuit of the thin film transistor liquid crystal display does not feed back the actual charging voltage of the pixel unit to the driving circuit, the driving circuit cannot know the actual voltage value charged in each pixel unit.
  • the charging condition of the pixel unit on the display panel changes with the use time. If the driving control strategy provided by the driving circuit cannot detect these changes, the charging voltage of the pixel unit may be abnormal and an abnormal display may occur. At the same time, for a display panel having a large size, due to the problem of uniformity, the charging difference of the pixel unit at different positions along the gate line direction of the display panel is large, and the display effect is also affected.
  • Embodiments of the present disclosure provide a driving adjustment circuit, an adjustment method, and a display device.
  • Embodiments of the present disclosure may adjust the driving capability of all data lines as a whole by a source driving adjustment strategy based on the average error (for example, adjusting the driving capability may at least include adjusting one of a source driving voltage, a source driving current, or a clock signal, for example, Adjusting the timing control circuit to adjust the clock signal to adjust the time taken by the high level of the output of the gate driving circuit), effectively improving the overall deterioration of the driving capability of the display panel as the use time increases.
  • the embodiment of the present disclosure further adjusts the driving capability of each data line by using a source driving adjustment strategy based on independent error (for example, adjusting the driving capability to at least one of adjusting the source driving voltage or the source driving current), thereby effectively improving the size.
  • a source driving adjustment strategy based on independent error (for example, adjusting the driving capability to at least one of adjusting the source driving voltage or the source driving current), thereby effectively improving the size.
  • Large panels show unevenness in the direction of the grid lines.
  • the method 100 of adjusting the driving of the present disclosure, the driving adjustment circuit 10, and the display device 1 will be described below with reference to FIGS. 1 to 6E.
  • an embodiment of the present disclosure provides a method 100 of adjusting driving.
  • the method 100 of adjusting the driving may include: step S200, acquiring one or more charging error values of the pixel group; step S300, determining an adjustment strategy of the driving according to the one or more charging error values; and step S400, according to step S400
  • the adjustment strategy adjusts the settings of the drive.
  • the determining an adjustment policy of the driving according to the one or more charging error values may include decreasing the driving if the one or more charging error values satisfy a first condition; and if The one or more charging error values satisfy the second condition, and the driving is increased.
  • the driving includes at least one of a source driving (ie, a source driving circuit) or a gate driving (ie, a gate driving circuit).
  • the pixel group involved in step S200 may include one or more pixel units, each of which is connected to the same scan line, and the scan line is a gate line or a dummy gate line.
  • the gate line is located in an effective display area on the display panel, and the gate driving circuit turns on the driving transistor row by row by controlling the on-state voltages of the plurality of gate lines to sequentially output the driving transistors one by one.
  • the on-state voltage causes the drive transistor to turn on
  • a plurality of data lines write data voltage values to the pixel cells.
  • a plurality of gate lines may be arranged in a row or a row, or may be arranged in a column and a column. Embodiments of the present disclosure do not limit the wiring direction of the gate lines and the manner of wiring.
  • one or more virtual gate lines are set in the non-display area on the display panel, and the image output can be stabilized by setting one or more virtual grid lines.
  • the gate drive circuit drives the on-state voltage of the transistor by controlling one or more of the virtual gate line ordered outputs.
  • the on-state voltage causes the drive transistor to turn on
  • the plurality of data lines write a predetermined one or more fixed voltage values to the pixel unit. It should be noted that the embodiments of the present disclosure do not limit the wiring direction of the dummy gate lines and the manner of wiring.
  • the effect of acquiring one or more charging error values on the image display can be reduced.
  • step S200 may periodically acquire one or more charging error values of the pixel group, wherein the length of the time period for acquiring one or more charging error values of the pixel group may be dynamically adjusted. That is to say, the time period of acquiring one or more charging error values of the pixel group can be dynamically adjusted as the display panel usage time increases. For example, when the display panel is used for a short period of time, one or more charging error values may be acquired once during the period in which the multi-frame image data is displayed; when the usage time of the display panel increases, the acquisition may be shortened one or more times at a time. The time period of the charging error value (for example, one or more charging error values are acquired once during the period in which one frame of image is displayed).
  • the pixel group includes N pixel units that are respectively charged by N write voltage values provided by the N data lines, wherein N is the total number of the data lines, N Is a positive integer greater than or equal to 1.
  • Obtaining one or more charging error values for the pixel group in the corresponding step S200 may include sub-steps as shown in FIG. 2.
  • a pixel group includes one row or one column of pixel units.
  • the one or more charging error values of the acquiring pixel group in step S200 may include: step S201, respectively reading N writing voltage values of the N pixel units; and step S202, measuring the N The voltage values on the pixel electrodes of the pixel units obtain N charging voltage values; and in step S203, the absolute values of the N charging voltage values are subtracted from the absolute values of the N writing voltage values to obtain N difference values Determining the one or more charging error values based on the N differences.
  • the write voltage value in step S201 is a data voltage value.
  • N pixel cells in a pixel group are connected to a gate line of an effective display region through a driving transistor.
  • the driving transistor is turned on, and the N data lines write a data voltage value (for example, a gray voltage value) to the pixel electrode of the pixel unit via the driving transistor.
  • the N pixel units in the pixel group perform image display according to the data voltage value.
  • the write voltage value in step S201 is a set fixed voltage value.
  • N pixel cells in a pixel group are connected to a dummy gate line of a non-effective display area through a driving transistor.
  • the driving transistor is turned on, and the N data lines write a predetermined fixed voltage value to the pixel electrode of the pixel unit via the driving transistor.
  • the same fixed voltage value may be provided to the N pixel units, or a plurality of fixed voltage values may be provided to the N pixel units, and the fixed voltage value is independent of the displayed image.
  • the obtaining the N charging voltage values in step S202 may further include the step of reading the charging voltage value, wherein the N pixels are read when the charging of the N pixel units in the pixel group is completed. More accurate one or more charging error values can be obtained for N charging voltage values on the pixel electrodes of the cell.
  • the driving transistor is turned on under the control of the turn-on voltage provided by the scan line, so that the N data lines input a write voltage value to the pixel electrode of the pixel unit via the driving transistor.
  • the obtaining the N charging voltage values includes reading the N charging voltage values on the pixel electrodes of the N pixel units before turning off the driving transistor.
  • Reading the charging voltage value at the time of completion of charging can prevent the inaccurate charging voltage value due to the discharge process of the pixel unit, thereby affecting one or more charging error values of the obtained charging error.
  • the N differences of step 203 are calculated over a suitable period of time.
  • the time interval at which the host provides two frames of image data before and after the driver circuit is acquired and N difference values are calculated within the time interval.
  • the image data of the first and second frames includes the first frame image data and the second frame image data, whereby the time interval may indicate that the first frame image data is supplied from the host to the driving circuit, and then the host provides the second frame image data to the driving circuit.
  • the previous time period Since the driving circuit does not receive image data information from the host during this time interval and does not charge the pixel unit of the display panel, the computational load on the CPU of the driving circuit is minimally affected.
  • a charge error value in step S200 is an average error value that can be used to characterize the average charge error of the N data lines.
  • the average error value may be an average of the N difference values obtained in step S203.
  • the method 100 of adjusting the drive further includes receiving the next frame of image data; and driving the display of the next frame of image data using the settings of the drive.
  • determining the driving adjustment strategy according to a charging error value of the corresponding step S300 may include: if the average error value is greater than the first threshold, reducing the driving capability (eg, reducing the source drive voltage, reducing the source drive current, or reducing the duty cycle of the clock signal); or increasing the drive capability if the average error value is less than the second threshold (eg, increasing the source drive voltage) Increase the source drive current or increase the duty cycle of the clock signal).
  • the source drive voltage can be increased or decreased by adjusting the gray scale voltage of the source drive output.
  • the source drive current can be increased or decreased by adjusting the current of the source drive output.
  • the duty cycle of the clock signal can be increased or decreased by adjusting the duty cycle of the clock signal output by the timing control circuit.
  • the first threshold is a positive real number and the second threshold is a negative real number.
  • the one or more charging error values satisfying the first condition may indicate that the average error value is greater than a first threshold; and the one or more charging error values satisfying the second condition may represent the average The error value is less than the second threshold.
  • FIG. 3 details the process of obtaining an adjustment strategy based on the average error value and adjusting the settings of the drive based on the adjustment strategy.
  • the embodiment shown in FIG. 3 has two dummy gate lines disposed in the non-display area, wherein the N pixel units in the pixel group are connected to the second virtual gate line. It is assumed that the first threshold is D 1 and the second threshold is D 2 , where D 1 is a positive real number and D 2 is a negative real number.
  • the method 300 for adjusting driving provided by the embodiment shown in FIG. 3 may include:
  • Step S301 sequentially charging each row of pixel units of the display area.
  • Step S304 comparing the average error value D with the first threshold D 1 .
  • N differences are calculated using the following formula (1), and the average error value D is calculated according to the following formula (2), and then the average error value D and the first threshold D 1 are compared:
  • P2i indicates the charging voltage on the pixel electrode of the i-th pixel units
  • P1i represents fixed voltage value corresponding to the i-th pixel unit, if the average error value D is greater than a first threshold value D. 1, is performed step S305, the Otherwise, step S306 is performed.
  • Step S305 determining an adjustment strategy one, and adjusting the setting of the driving according to the adjustment strategy one.
  • Step S306 the comparing the average error value and the second threshold value D D 2, if the average error value D is smaller than the second threshold value D 2, proceed to step S307, otherwise no adjustment drive.
  • Step S307 determining an adjustment strategy 2, and adjusting the setting of the driving according to the adjustment strategy 2.
  • the adjustment strategy 1 can reduce the existing driving capability (for example, reducing the source driving voltage, reducing the source driving current, or reducing The duty cycle of the clock signal).
  • the adjustment strategy 2 can increase the existing driving capability (for example, increasing the source driving voltage, increasing the source driving current, or increasing the clock signal). Duty cycle).
  • One of the adjustment strategies may be: reducing the source drive voltage, reducing the source drive current, or reducing one of the duty cycles of the clock signal.
  • the adjustment strategy 2 needs to be adopted to adjust the setting of the driving.
  • the adjustment strategy 2 may be: increasing the source driving voltage, increasing the source driving current, or increasing one of the duty ratios of the clock signal. For example, if the calculated average error value D is greater than or equal to the second threshold D 2 and less than or equal to the first threshold D 1 , it indicates that the charging error value is within the allowable range, so the driving may not be adjusted.
  • the pixel unit of the TFT-LCD of the thin film transistor liquid crystal display changes with the use time, and this change causes the display voltage to be abnormal due to excessive or too small voltage being charged into the pixel unit through the data line.
  • the embodiment of the present disclosure obtains an adjustment strategy by averaging the error value, and can adjust the setting of the driving according to the dynamic change of the pixel unit on the display panel. Specifically, the source driving voltage or the source driving current of all the data lines is charged by the pixel unit. By maintaining the charging voltage of the pixel unit within a prescribed range, the display quality is effectively improved.
  • the plurality of charging error values may further include N independent error values for respectively characterizing charging error values of the N data lines, wherein the N independent errors The value is the N difference values obtained in step 203.
  • determining the driving adjustment strategy according to the plurality of charging error values of step S300 may include:
  • the ability to drive the data line is reduced (eg, reducing the source drive of the data line)
  • the voltage either reduces the source drive current of the data line); or, if its corresponding independent error value is less than the second threshold, indicating that the drive to the data line is too small, the ability to drive the data line is increased (eg, Increasing the source driving voltage of the data line or increasing the source driving current of the data line).
  • the source drive voltage can be increased or decreased by adjusting the gray scale voltage of the source drive output.
  • the source drive current can be increased or decreased by adjusting the current of the source drive output.
  • the first threshold is a positive real number and the second threshold is a negative real number.
  • the one or more charging error values satisfying the first condition may indicate that an independent error value corresponding to a certain data line is greater than a first threshold; and the one or more charging error values satisfy a second condition. Indicates that the independent error value corresponding to a certain data line is smaller than the second threshold.
  • FIG. 4 details the process of obtaining an adjustment strategy based on an independent error value and adjusting the settings of the driver based on the adjustment policy.
  • the embodiment shown in FIG. 4 sets two virtual gate lines in the non-display area, wherein the N pixel units in the pixel group are connected to the second virtual gate line. It is assumed that the first threshold is D 1 and the second threshold is D 2 , D 1 is a positive real number, and D 2 is a negative real number.
  • Step S401 sequentially charging each row of pixel units of the display area.
  • Step S402 charging the first virtual gate line and the second virtual gate line of the non-display area, and the write voltage value is a fixed voltage value P0 (
  • Di is the i-th error value of a pixel unit corresponding to the i-th pixel units corresponding to the i-th data line, when the individual error value Di is greater than a first threshold value D 1, the step of the i-th data line independent error S405, otherwise step S406 is performed.
  • Step S405 determining an adjustment strategy one, and adjusting a setting of, for example, the driving of the i-th data line according to the adjustment strategy one.
  • Step S406 when the individual error value Di is not greater than a first threshold value D 1, more independent error value Di and the second threshold value D 2, if the individual error value Di is smaller than the second threshold value D 2, the step of the i-th data line S407, otherwise the driving of the ith data line is not adjusted.
  • Step S407 determining an adjustment strategy 2, and adjusting a setting of, for example, the driving of the ith data line according to the adjustment strategy 2.
  • the adjustment strategy one may be to reduce the source driving voltage and reduce one of the source driving currents.
  • the adjustment strategy 2 may be to increase the source driving voltage and increase one of the source driving currents.
  • i denotes the serial number of the i-th data line
  • P1i is the write voltage value of the pixel unit connected to the i-th data line
  • P2i is the charge voltage value on the pixel electrode of the pixel unit connected to the i-th data line.
  • the adjustment strategy 1 can be used to adjust the source drive setting of the data line.
  • the adjustment strategy 2 can be used to adjust the driving setting of the data line. It should be noted that if the independent error value corresponding to a certain data line is greater than or equal to the second threshold D2 and less than or equal to the first threshold D1, it indicates that the charging error of the data line is within the allowable range, and the data line is not adjusted. Source drive.
  • the charging condition of the pixel unit at different positions in the direction of the gate line of the display panel is largely different due to the problem of uniformity of the display panel. Therefore, if the driving capability supplied to each data line is the same, display unevenness in the direction of the gate line may be caused.
  • the different adjustment strategies for each data line can be obtained based on the independent error values of the embodiments of the present disclosure, and the source driving is adaptively adjusted (for example, increasing or decreasing the source driving voltage of a certain data line, increasing or decreasing some The source driving current of the data line, etc.) solves the problem of uneven display along the gate line direction due to the large size of the display panel.
  • an embodiment of the present disclosure provides a driving adjustment circuit 10.
  • the adjustment circuit 10 may include: a processing sub-circuit 11 configured to acquire one or more charging error values of the pixel group; the policy generation sub-circuit 12 configured to determine a driving adjustment strategy based on the one or more charging error values; And setting the sub-circuit 13 configured to adjust the setting of the driving according to the adjustment policy; wherein determining the adjustment policy of the driving according to the one or more charging error values may include: if the one or The plurality of charging error values satisfy the first condition to reduce the driving; and if the one or more charging error values satisfy the second condition, increasing the driving.
  • the pixel group includes N pixel units, and the N pixel units are respectively charged by N write voltage values provided by the N data lines, wherein N is the total number of the data lines, and N is greater than or equal to a positive integer of 1; and the processing sub-circuit 11 is further configured to: respectively read N write voltage values of the N pixel units; measure voltage values on pixel electrodes of the N pixel units, to obtain N charging voltage values; and N values are obtained by subtracting absolute values of the N writing voltage values from absolute values of the N charging voltage values, respectively, and determining the one or Multiple charging error values.
  • the input terminals of the processing sub-circuit 11 are respectively connected to the pixel electrodes of the N pixel units to read the N charging voltage values on the pixel electrodes of the measured N pixel units.
  • the output of the processing sub-circuit 11 is connected to the policy generation sub-circuit 12.
  • N difference values may be calculated in a software programming manner, or N difference values may be calculated by an adder or a multiplier or the like.
  • the policy generation sub-circuit 12 is configured to: set the one or more charging error values (eg, an average error value or one or more independent error values) to the set first threshold and second The threshold is compared to obtain a comparison result; and an adjustment strategy for adjusting the driving is generated according to the comparison result; wherein the first threshold is a positive real number and the second threshold is a negative real number.
  • the one or more charging error values eg, an average error value or one or more independent error values
  • policy generation sub-circuit 12 can include a comparator.
  • the comparator may be configured to compare the one or more charging error values with the first threshold and the second threshold and output a comparison result.
  • the output of the policy generation sub-circuit 12 is used to output a comparison result.
  • the result of the comparison may be any one of the one or more charging error values being greater than the first threshold, less than the second threshold, and being located between the first threshold and the second threshold. It should be noted that, only if the comparison result is that one or more charging error values are greater than the first threshold or less than the second threshold, the policy generation sub-circuit 12 needs to generate a corresponding adjustment driving strategy.
  • the setting sub-circuit 13 is configured to receive an adjustment strategy generated by the policy generation sub-circuit and generate corresponding control signals in accordance with the adjustment strategy, after which the control signals are input to the drive circuit to adjust the settings of the drive.
  • an embodiment of the present disclosure provides a display device 1.
  • the display device 1 includes at least an adjustment circuit 10, a gate drive circuit 3, and a source drive circuit 4.
  • adjustment circuit 10 For the specific structure and implementation of the adjustment circuit 10, reference may be made to the related descriptions of FIG. 1 to FIG. 5, and details are not described herein.
  • the display device 1 may further include a display panel 5.
  • the adjustment circuit 10 can be located on the display panel 5.
  • a plurality of pixel units are distributed on the display panel 5 (the pixel units are located in a region defined between adjacent gate lines and adjacent data lines), wherein each pixel unit includes a driving transistor T1 and The pixel electrode 6 (refer to the two pixel units shown in FIG. 6A).
  • the first pole of the driving transistor T1 is connected to the data lines (S(1), S(2) ... S(i) ... S(N)), and the gate and gate lines (G(1), G(2) ... G(j) ... G(M-1), G(M)) are connected, and the second pole is connected to the pixel electrode 6.
  • the adjustment circuit 10 can be connected to the pixel electrode 6 to measure the charging voltage value of the pixel electrode 6.
  • the pixel group when the pixel group is connected to the first gate line G(1), that is, the pixel group includes N pixel units connected to the first gate line G(1), then the first gate line G(1) The pixel electrodes 6 of the connected N pixel units are connected to the adjustment circuit 10; when the pixel group is connected to the last gate line G(M), that is, the pixel group includes N pixel units connected to the last gate line G(M) Then, the pixel electrode 6 of the N pixel units connected to the last gate line G(M) is connected to the adjustment circuit 10.
  • the display device 1 can be connected to the host 7 through the timing control circuit 9 and the host system interface 8.
  • the host 7 is configured to provide multi-frame image data 71 to the display device 1.
  • the timing control circuit 9 is at least configured to input control signals to the gate drive circuit 3 and the source drive circuit 4.
  • the timing control circuit 9 can provide a clock signal to the gate drive circuit.
  • one or more charging error values required by the adjusting circuit 10 may be calculated within a time interval in which the host 7 inputs the adjacent two frames of image data to the display device 1.
  • the duty ratio and the like of the clock signal are adjusted by adjusting the timing control circuit 9.
  • the source drive circuit 4 can configure one of the source drive voltage or the source drive current in accordance with the settings of the drive obtained by the adjustment circuit 10.
  • the time occupied by the high level of the output of the gate driving circuit 3 can be adjusted by adjusting the duty ratio of the timing signal, thereby affecting the charging voltage value of the pixel.
  • the duty ratio of the timing signal can be adjusted by adjusting the timing control circuit (not shown in FIG. 6B).
  • the gate drive circuit 3 includes a multi-stage cascaded shift register (GOA) unit, wherein the circuit structure of each shift register unit can be as shown in FIG. 6C (ie, FIG. 6C is a level one GOA unit). .
  • GOA cascaded shift register
  • the function of the multi-level cascaded GOA unit is to sequentially map each gate line (G(1), G(2)...G(j)...G(M-1), G(M) in one frame time.
  • the output high-level square wave, the drive transistor T1 corresponding to the gate lines is turned on line by line, so that the data lines (S(1), S(2) ... S(i) ... S(N)) are on the display unit panel All pixel units are charged once.
  • Bilateral driving means that a GOA unit is placed on the left and right sides of a grid line to charge it. In this case, the design of the left GOA unit and the right GOA unit can be completely symmetrical.
  • the GOA unit shown in FIG. 6C includes: a storage capacitor C1, a first transistor M1, a second transistor M2, a third transistor M3, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth The transistor M9, the tenth transistor M10, and the eleventh transistor M11.
  • the first pole of the first transistor M1 is connected to the first voltage terminal VDD to receive the input first DC voltage signal, the second pole is connected to the pull-up node PU, and the control pole is connected to the input terminal INPUT to receive the input signal.
  • the first pole of the second transistor M2 is connected to the pull-up node PU, the second pole is connected to the second voltage terminal VSS to receive the input second DC voltage, and the control pole is connected to the reset signal terminal RESET to receive the reset signal.
  • the first transistor of the third transistor M3 is connected to the clock signal terminal CLK to receive the clock signal, the second electrode is connected to the output terminal OUTPUT, and the control electrode is connected to the pull-up node PU.
  • the first pole of the fifth transistor M5 is connected to the third voltage terminal GCH to receive the input third DC voltage, the second pole is connected to the pull-down node PD, and the control pole is connected to the pull-down control node PD-A.
  • the first pole of the sixth transistor M6 is connected to the pull-down node PD, the second pole is connected to the fourth voltage terminal VGL to receive the input fourth DC voltage, and the control pole is connected to the pull-up node PU.
  • the first transistor of the seventh transistor M7 is connected to the output terminal OUTPUT, the second electrode is connected to the fourth voltage terminal VGL to receive the input fourth DC voltage, and the control electrode is connected to the fifth voltage terminal GCL to receive the fifth DC voltage.
  • the fourth DC voltage can be, for example, a low voltage.
  • the first pole of the eighth transistor M8 is connected to the pull-down control node PD-A, the second pole is connected to the fourth voltage terminal VGL to receive the input fourth DC voltage, and the control pole is connected to the pull-up node PU.
  • the first pole of the ninth transistor M9 is connected to the third voltage terminal GCH to receive the input third DC voltage
  • the second pole is connected to the pull-down control node PD-A
  • the control pole is connected to the third voltage terminal GCH to receive the input third.
  • DC voltage can be, for example, a high voltage.
  • the first pole of the tenth transistor M10 is connected to the pull-up node PU, the second pole is connected to the fourth voltage terminal VGL to receive the input fourth DC voltage, and the control pole is connected to the pull-down node PD.
  • the first electrode of the eleventh transistor M11 is connected to the output terminal OUTPUT, the second electrode is connected to the fourth voltage terminal VGL to receive the input fourth DC voltage, and the control electrode is connected to the pull-down node PD.
  • the first end of the storage capacitor C1 is connected to the pull-up node PU, and the second end is connected to the output terminal OUTPUT.
  • the output terminal OUTPUT of the GOA unit shown in Fig. 6C is connected to the gate line shown in Fig. 6A.
  • GOA unit shown in FIG. 6C is only one example of the embodiment of the present disclosure, and the embodiments of the present disclosure include but are not limited to the case shown in FIG. 6C.
  • the operation of the gate driving circuit 3 in which the GOA cells of FIG. 6C are cascaded in multiple stages is: after the start of one frame, the first trigger signal and the clock signal are input to the first stage GOA unit, and the first level GOA The unit receives the first trigger signal, and outputs a high-level square wave signal when the corresponding clock signal CLK is high level.
  • the output high-level square wave signal is used not only for the opening of the corresponding gate line but also as an input signal.
  • the next level of GOA unit Starting from the second-stage GOA unit, the subsequent GOA unit receives the input signal provided by the GOA unit of the previous stage, and outputs a high-level square wave signal when the corresponding CLK level is high.
  • the output high-level square wave signal is not only used.
  • the opening of the corresponding gate line also acts as an input signal on the next stage GOA unit, and also acts as a reset signal on the upper level GOA unit.
  • the last stage GOA unit does not need to output the high-level square wave signal as the input signal of the next stage.
  • Each level of the GOA unit will turn off the output signal of the GOA unit of the previous line when the line starts to output.
  • the next level of the GOA unit will also start outputting and turn off the output signal of the line after the end of the output of the line.
  • the GOA unit can sequentially output a high-level square wave signal, realizing the function of shift register.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching devices having the same characteristics.
  • the control of the transistor is extremely the gate of the transistor.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • one of the first poles and the other pole are directly described, so the first pole of all or part of the transistors in the embodiment of the present disclosure
  • the second pole is interchangeable as needed.
  • the first pole of the transistor of the embodiment of the present disclosure may be a source, and the second pole may be a drain; or the first extreme drain of the transistor and the second source of the second.
  • the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors.
  • the turn-on voltage is a low level voltage (eg, 0V, -5V, or other value)
  • the turn-off voltage is a high level voltage (eg, 5V, 10V, or other value)
  • the turn-on voltage is a high level voltage (for example, 5V, 10V, or other value)
  • the turn-off voltage is a low level voltage (for example, 0V, -5V, or other values).
  • each transistor is an N-type transistor.
  • those skilled in the art can realize the implementation of the P-type transistor or the combination of the N-type and P-type transistors in the embodiments of the present disclosure without creative efforts. Therefore, these Implementations are also within the scope of the present disclosure.
  • Fig. 6D is a driving timing chart. The operation of driving the GOA unit of FIG. 6C will be described below in conjunction with the timing diagram of FIG. 6D.
  • the first stage Q1 is an input stage.
  • the reset signal of the reset signal terminal RESET, the clock signal of the clock signal terminal CLK are set to a low level, and the input signal of the input terminal INPUT is a high level (the INPUT signal in FIG. 6D) High level square wave).
  • the second transistor M2 Since the reset signal is low level, the second transistor M2 is turned off; the input signal is high level, the first transistor M1 is turned on, and the storage capacitor C1 is charged by the first transistor M1, and the PU node of the pull-up node is at a high level.
  • the sixth transistor M6 and the eighth transistor M8 are turned on, thereby writing the fourth DC voltage of the fourth voltage terminal VGL to the pull-down node PD.
  • the PD point of the pull-down node is low, and the tenth transistor M10 and the eleventh transistor M11 are turned off to ensure normal input. Since the PU point of the pull-up node is high, the third transistor M3 is turned on, and since the clock signal is low, the output terminal OUTPUT outputs a low level.
  • the second stage Q2 is the output stage, the input signal and the reset signal are low level, and the clock signal is high level. Due to the holding function of the storage capacitor C1, the PU node of the pull-up node is at a high level, the third transistor M3 is turned on, and the clock signal is at a high level, and the output terminal OUTPUT outputs a high level. At this time, the potential of the pull-down node PD is low, and the tenth transistor M10 and the eleventh transistor M11 are turned off to ensure normal output.
  • the third stage Q3 is the reset phase. At this time, the clock signal and the input signal are at a low level, and the reset signal is at a high level. Since the reset signal is at a high level, the second transistor M2 is turned on, the pull-up node PU is at a low level, and the sixth transistor M6 and the eighth transistor M8 are turned off. The fifth transistor M5 and the ninth transistor are turned on, so that the third DC voltage of the third voltage terminal GCH is written to the pull-down node PD, the pull-down node PD is at a high level, and the tenth transistor M10 and the eleventh transistor M11 are turned on. The signals of the pull-up node PU and the output are all low.
  • the fourth stage Q4 is the hold phase, and the clock signal, the input signal, and the reset signal are all low. Since the clock signal, the input signal, and the reset signal are both low, the first transistor M1 and the second transistor M2 are turned off.
  • the pull-up node PU is at a low level, and the sixth transistor M6 and the eighth transistor M8 are turned off.
  • the pull-down node PD is at a high level, and the tenth transistor M10 and the eleventh transistor M11 are turned on, and the potentials of the pull-up node PU and the output terminal OUTPUT are kept at a low level.
  • the circuit of the above GOA unit will always operate in the fourth stage Q4 after entering the fourth stage Q4 and before the arrival of the next frame.
  • the non-display area on display panel 5 is provided with two dummy gate lines.
  • Figure 6E shows a schematic diagram of charging and reading the charging voltage values for the pixel cells connected to the two dummy gate lines. As shown in FIG. 6E, when the output of the first virtual gate line ends, a reset signal is provided to the first virtual gate line to reset the output of the first virtual gate line. Similarly, when the output of the second virtual gate line ends And providing a reset signal to the second virtual gate line to reset the output of the second virtual gate line. Referring to FIG. 6E, in the W1 period, the pixel unit connected to the first dummy gate line and the pixel unit connected to the second dummy gate line are in the charging phase.
  • the pixel electrode charging phase of the pixel cell connected to the first dummy gate line ends, and the charging phase of the pixel cell connected to the second dummy gate line will continue for a while.
  • the second virtual gate line is still in the period in which the charging is about to end.
  • an embodiment of the present disclosure may read a charging voltage value of a pixel group during a W2 period.

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Abstract

一种驱动的调整电路、调整方法及显示装置。调整驱动的方法（100）包括：获取像素组的一个或多个充电误差值（S200）；根据所述一个或多个充电误差值，确定所述驱动的调整策略（S300）；以及根据所述调整策略来调整所述驱动的设置（S400）；其中，所述根据所述一个或多个充电误差值，确定所述驱动的调整策略可以包括：如果所述一个或多个充电误差值满足第一条件，则减小所述驱动；以及如果所述一个或多个充电误差值满足第二条件，则增大所述驱动。

Description

驱动调整电路及调整方法、显示装置
本申请要求于2017年12月08日递交的中国专利申请第201711297125.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种驱动调整电路及调整方法、显示装置。
背景技术
薄膜晶体管液晶显示器(TFT-LCD)是保持型的电光转换器件。对应一定亮度的灰阶电压从数据驱动IC(Integrate Chip)输出后，通过数据线，在作为开关的晶体管(thin film transistor，TFT)打开后被写入像素电极。灰阶电压的写入过程就是像素单元的像素电极的充电过程，需要写入到像素单元的像素电极的灰阶电压尽可能地接近数据驱动IC输出的值。
发明内容
本公开的至少一个实施例提供一种调整驱动的方法，包括：获取像素组的一个或多个充电误差值；根据所述一个或多个充电误差值，确定所述驱动的调整策略；以及根据所述调整策略来调整所述驱动的设置；其中，所述根据所述一个或多个充电误差值，确定所述驱动的调整策略，包括：如果所述一个或多个充电误差值满足第一条件，则减小所述驱动；以及如果所述一个或多个充电误差值满足第二条件，则增大所述驱动。
例如，在本公开一实施例提供的调整驱动的方法中，所述像素组中的各像素单元均与同一条扫描线相连，所述扫描线为栅线或者虚栅线。
例如，在本公开一实施例提供的调整驱动的方法中，所述像素组包括N个像素单元，所述N个像素单元分别通过N条数据线提供的N个写入电压值进行充电，其中，N为所述数据线的总数目，N为大于等于1的正整数；以及所述获取像素组的一个或多个充电误差值，包括：分别读取所述N个像素单元的N个写入电压值；测量所述N个像素单元的像素电极上的电压值，得到N个充电电压值；以及分别利用所述N个充电电压值的绝对值减去所述N个写入 电压值的绝对值得到N个差值，基于所述N个差值确定所述一个或多个充电误差值。
例如，在本公开一实施例提供的调整驱动的方法中，所述N个写入电压值为数据电压值或者设定的固定电压值。
例如，在本公开一实施例提供的调整驱动的方法中，所述扫描线与各所述像素单元的驱动晶体管的栅极连接，所述驱动晶体管在所述扫描线提供的开启电压的控制下打开；以及所述得到N个充电电压值包括在关闭所述驱动晶体管之前读取所述N个充电电压值。
例如，在本公开一实施例提供的调整驱动的方法中，所述一个充电误差值包括平均误差值，所述平均误差值为所述N个差值的平均值，所述平均误差值用于表征所述N条数据线的平均充电误差。
例如，在本公开一实施例提供的调整驱动的方法中，所述根据所述一个或多个充电误差值，确定驱动的调整策略，包括：如果所述平均误差值大于第一阈值，则减小源驱动电压、减小源驱动电流或减小时钟信号的占空比；或者如果所述平均误差值小于第二阈值，则增大源驱动电压、增大源驱动电流或增大时钟信号的占空比；其中，所述第一阈值为正实数，所述第二阈值为负实数。
例如，在本公开一实施例提供的调整驱动的方法中，所述多个充电误差值包括N个独立误差值，所述N个独立误差值为所述N个差值，所述N个独立误差值分别用于表征所述N条数据线的充电误差。
例如，在本公开一实施例提供的调整驱动的方法中，所述根据一个或多个充电误差值，确定驱动的调整策略，包括：对于每条数据线：如果其对应的独立误差值大于第一阈值，则减小所述数据线的源驱动电压或者减小所述数据线的源驱动电流；或者如果其对应的独立误差值小于第二阈值，则增大所述数据线的源驱动电压或者增大所述数据线的源驱动电流；其中，所述第一阈值为正实数，所述第二阈值为负实数。
例如，在本公开一实施例提供的调整驱动的方法中，所述分别利用所述N个充电电压值的绝对值减去所述N个写入电压值的绝对值得到N个差值，包括：获取主机向驱动电路输入相邻两帧图像数据的时间间隔；以及在所述时间间隔内计算所述N个差值。
本公开实施例还提供一种驱动调整电路，包括，处理子电路，被配置为获取像素组的一个或多个充电误差值；策略生成子电路，被配置为根据所述一个 或多个充电误差值，确定所述驱动的调整策略；以及设置子电路，被配置为根据所述调整策略来调整所述驱动的设置；其中，所述策略生成子电路，还被配置为：如果所述一个或多个充电误差值满足第一条件，则减小所述驱动；以及如果所述一个或多个充电误差值满足第二条件，则增大所述驱动。
例如，在本公开一实施例提供的驱动调整电路中，所述像素组包括N个像素单元，所述N个像素单元分别通过N条数据线提供的N个写入电压值进行充电，其中，N为所述数据线的总数目，N为大于等于1的正整数；以及所述处理子电路还被配置为：分别读取所述N个像素单元的N个写入电压值；测量所述N个像素单元的像素电极上的电压值，得到N个充电电压值；以及分别利用所述N个充电电压值的绝对值减去所述N个写入电压值的绝对值得到N个差值，基于所述N个差值确定所述一个或多个充电误差值。
例如，在本公开一实施例提供的驱动调整电路中，所述策略生成子电路还被配置为：将所述一个或多个充电误差值与设定的第一阈值和第二阈值进行比较得到比较结果；以及根据所述比较结果生成用于调整所述驱动的调整策略；其中，所述第一阈值为正实数，所述第二阈值为负实数。
例如，在本公开一实施例提供的驱动调整电路中，所述像素组中的各像素单元均与同一条扫描线相连，所述扫描线为栅线或者虚栅线。
本公开实施例还提供一种显示装置，包含上述任一实施例的调整电路、栅驱动电路、源驱动电路。
例如，在本公开一实施例提供的显示装置中，所述源驱动电路被配置为依据驱动的设置来配置源驱动电压或源驱动电流，以及所述栅驱动电路被配置为依据驱动的设置来减小或增大输出的栅驱动信号所占的时间。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开实施例提供的一种调整驱动的方法流程图；
图2为本公开实施例提供的图1中的步骤S200的获取像素组的一个或多个充电误差值的流程图；
图3为本公开一实施例的提供的一种调整驱动的方法流程图；
图4为本公开一实施例的提供的一种调整驱动的方法流程图；
图5为本公开实施例提供的驱动调整电路的组成框图；
图6A为本公开实施例提供的显示装置的组成框图；
图6B为本公开实施例提供显示装置与主机的连接示意图；
图6C为本公开实施例提供的GOA单元的电路图；
图6D为本公开实施例提供的GOA单元的时序图；
图6E为本公开实施例提供的读取像素单元的充电电压值的示意图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。所给出的示例仅旨在有利于理解本公开实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。
当薄膜晶体管液晶显示器(thin film transistor liquid crystal display,TFT-LCD)的驱动电路不将像素单元的实际充电电压反馈给驱动电路时，驱动电路并不能获知充入各个像素单元的实际电压值。
显示面板上的像素单元的充电情况会随使用时间的增加而发生变化，如果驱动电路提供的驱动控制策略不能检测到这些变化，将导致像素单元的充电电压异常而出现异常显示等现象。同时，对于尺寸较大的显示面板，由于存在均一性的问题，在显示面板的沿着栅线方向的不同位置处像素单元的充电差别较大，也将影响显示效果。
本公开的实施例提供一种驱动调整电路及调整方法、显示装置。本公开的实施例通过基于平均误差得到的源驱动调整策略可以整体调整所有数据线的驱动能力(例如，调整驱动能力至少可以包括调整源驱动电压、源驱动电流或 者时钟信号之一，例如可以通过调整时序控制电路来调整时钟信号，进而达到调整栅驱动电路输出的高电平所占的时间)，有效改善显示面板随使用时间的增加而发生的驱动能力的整体恶化。本公开实施例还通过基于独立误差得到的源驱动调整策略来分别调整各条数据线的驱动能力(例如，调整驱动能力至少包括调整源驱动电压或者源驱动电流之一)，有效改善了尺寸较大的面板在栅线方向显示不均的问题。
下面结合图1-图6E介绍本公开的调整驱动的方法100、驱动调整电路10以及显示装置1。
如图1所示，本公开实施例提供一种调整驱动的方法100。调整驱动的方法100可以包括：步骤S200，获取像素组的一个或多个充电误差值；步骤S300，根据所述一个或多个充电误差值，确定所述驱动的调整策略；以及步骤S400，根据所述调整策略来调整所述驱动的设置。例如，所述根据所述一个或多个充电误差值，确定所述驱动的调整策略可以包括：如果所述一个或多个充电误差值满足第一条件，则减小所述驱动；以及如果所述一个或多个充电误差值满足第二条件，则增大所述驱动。例如，所述驱动包括源驱动(即源极驱动电路)或栅驱动(即栅极驱动电路)中的至少一个。
在一些实施例中，步骤S200涉及的像素组可以包括一或多个像素单元，各所述像素单元均与同一条扫描线相连，所述扫描线为栅线或者虚栅线。
例如，栅线位于显示面板上的有效显示区域中，栅驱动电路通过控制多条栅线一行一行地有序输出驱动晶体管的开态电压来逐行打开驱动晶体管。当开态电压使驱动晶体管打开时，多条数据线会向像素单元写入数据电压值。需要说明的是，多条栅线可以一行一行的排列，也可以一列一列的排列。本公开实施例并不对栅线的布线方向和布线的方式进行限定。
例如，在显示面板上的非显示区域设置一条或者多条虚栅线，通过设置一条或者多条虚栅线可以达到稳定图像输出的目的。在一些实施例中，栅驱动电路通过控制一或多条虚栅线有序输出驱动晶体管的开态电压。当开态电压使驱动晶体管打开时，多条数据线会向像素单元写入预先设定的一个或多个固定电压值。需要说明的是，本公开实施例并不对虚栅线的布线方向和布线的方式进行限定。
通过获取与虚栅线相连的像素组的一个或多个充电误差值，可以减少获取一个或多个充电误差值对图像显示的影响。
在一些实施例中，步骤S200可以周期性的获取像素组的一个或多个充电误差值，其中获取像素组的一个或多个充电误差值的时间周期的长短可以动态调整。也就是说，可以随着显示面板使用时间的增加，动态调整获取像素组的一个或多个充电误差值的时间周期。例如，在显示面板使用时间较短时，可以设置在显示多帧图像数据的时间段内获取一次一个或多个充电误差值；当随着显示面板使用时间的增加，可以缩短获取一次一个或多个充电误差值的时间周期(例如，在显示一帧图像的时间段内获取一次一个或多个充电误差值)。
在一些实施例中，像素组包括N个像素单元，所述N个像素单元分别通过N条数据线提供的N个写入电压值进行充电，其中，N为所述数据线的总数目，N为大于等于1的正整数。相应的步骤S200中获得像素组一个或多个充电误差值可以包括如图2所示的各子步骤。例如，像素组包括一行或一列像素单元。
如图2所示，步骤S200的获取像素组的一个或多个充电误差值可以包括：步骤S201，分别读取所述N个像素单元的N个写入电压值；步骤S202，测量所述N个像素单元的像素电极上的电压值，得到N个充电电压值；以及步骤S203，所述N个充电电压值的绝对值减去所述N个写入电压值的绝对值得到N个差值，基于所述N个差值确定所述一个或多个充电误差值。
在一些实施例中，步骤S201中的写入电压值为数据电压值。
例如，像素组中的N个像素单元通过驱动晶体管与有效显示区域的栅线相连。当栅线向驱动晶体管提供开启电压时，驱动晶体管开启，则N条数据线会经由驱动晶体管向像素单元的像素电极写入数据电压值(例如，灰度电压值)。之后，像素组中的N个像素单元会依据数据电压值进行图像显示。
在一些实施例中，步骤S201中的写入电压值为设定的固定电压值。
例如，像素组中的N个像素单元通过驱动晶体管与非有效显示区域的虚栅线相连。当虚栅线向驱动晶体管提供开启电压时，驱动晶体管开启，则N条数据线会经由驱动晶体管向像素单元的像素电极写入预先设定的固定电压值。需要说明的是，可以向N个像素单元提供一个相同的固定电压值，也可以向N个像素单元提供多个固定电压值，固定电压值与显示的图像无关。
在一些实施例中，步骤S202中的得到N个充电电压值还可以包括读取充电电压值的步骤，其中，当在像素组中的N个像素单元充电完成的时刻读取所述N个像素单元的像素电极上的N个充电电压值时，可以获得更准确的一个 或多个充电误差值。
例如，所述驱动晶体管在所述扫描线提供的开启电压的控制下打开，从而则N条数据线会经由驱动晶体管向像素单元的像素电极输入写入电压值。在步骤S202中，所述得到N个充电电压值包括在关闭所述驱动晶体管之前读取所述N个像素单元的像素电极上的所述N个充电电压值。
在充电完成的时刻读取充电电压值，可以防止因像素单元的放电过程导致读取的充电电压值不准确，进而影响获得的充电误差一个或多个充电误差值。
在一些实施例中，在合适的时间段内计算步骤203的N个差值。例如，获取主机向驱动电路提供前后两帧图像数据的时间间隔，在该时间间隔内计算N个差值。例如，前后两帧图像数据包括第一帧图像数据和第二帧图像数据，由此，时间间隔可以表示从主机向驱动电路提供第一帧图像数据后到主机向驱动电路提供第二帧图像数据之前的时间段。由于在该时间间隔内驱动电路不会接收来自主机的图像数据信息，也不会对显示面板的像素单元充电，因此对驱动电路的CPU的运算负担影响最小。
在一些实施例中，步骤S200中的一个充电误差值为平均误差值，该平均误差值可以用于表征N条数据线的平均充电误差。例如，平均误差值可以为步骤S203所得到的N个差值的平均值。
例如，调整驱动的方法100还包括，接收下一帧图像数据；以及采用所述驱动的设置来驱动显示下一帧图像数据。
例如，当步骤S200的一个充电误差值为平均误差值时，相应的步骤S300的根据一个充电误差值，确定驱动的调整策略可以包括：如果所述平均误差值大于第一阈值，则降低驱动能力(例如，减小源驱动电压、减小源驱动电流或减小时钟信号的占空比)；或者如果所述平均误差值小于第二阈值，则增大驱动能力(例如，增大源驱动电压、增大源驱动电流或增大时钟信号的占空比)。例如，可以通过调整源驱动输出的灰阶电压来增大或者减小源驱动电压。例如，可以通过调整源驱动输出的电流来增大或者减小源驱动电流。例如，可以通过调整时序控制电路输出的时钟信号的占空比来增大或者减小时钟信号的占空比。例如，第一阈值为正实数，第二阈值为负实数。
例如，在本公开中，所述一个或多个充电误差值满足第一条件可以表示所述平均误差值大于第一阈值；所述一个或多个充电误差值满足第二条件可以表示所述平均误差值小于第二阈值。
下面结合图3介绍本公开的一个实施例，详细说明根据平均误差值获得调整策略，并基于调整策略调整驱动的设置的过程。需要说明的是，图3所示的实施例在非显示区域设置了两条虚栅线，其中像素组中的N个像素单元与第二条虚栅线相连。假设第一阈值为D 1且第二阈值为D 2，其中D 1为正实数，D 2为负实数。
如图3所示，图3所示的实施例提供的调整驱动的方法300可以包括：
步骤S301，依次为显示区域的每一行像素单元充电。
步骤S302，为非显示区域的第一条虚栅线、第二条虚栅线充电，写入电压值为固定电压值P1i((i＝1,2,…N。N为数据线总数，|P1i|>0)。
步骤S303，读取与第二条虚栅线相连的N个像素单元的充电电压值，记为P2i(i＝1,2,…N。N为数据线总数)。
步骤S304，比较平均误差值D与第一阈值D 1。
例如，在步骤S304中，采用下述公式(1)计算N个差值，再根据下述公式(2)计算平均误差值D，然后比较平均误差值D与第一阈值D 1：
Di＝|P2i|-|P1i|    (1)
Figure PCTCN2018103975-appb-000001
其中，P2i表示第i个像素单元的像素电极上的充电电压值，P1i表示与第i个像素单元的对应的固定电压值，如果平均误差值D大于第一阈值D 1，则执行步骤S305，否则执行步骤S306。
步骤S305，确定调整策略一，以及根据所述调整策略一来调整驱动的设置。
步骤S306，比较平均误差值D与第二阈值D 2，如果平均误差值D小于第二阈值D 2，则执行步骤S307，否则不调整驱动。
步骤S307，确定调整策略二，以及根据所述调整策略二来调整驱动的设置。
例如，平均误差值D大于第一阈值D 1时，现有驱动能力过大，因此，调整策略一可以降低现有的驱动能力(例如，减小源驱动电压、减小源驱动电流或减小时钟信号的占空比)。平均误差值D小于第二阈值D2时，现有驱动能力过小，因此，调整策略二可以增大现有的驱动能力(例如，增大源驱动电压、增大源驱动电流或增大时钟信号的占空比)。
例如，假设在列翻转驱动方式下，各条数据线为与第二条虚栅线相连的N个像素单元写入的N个固定电压值分别为：P11＝5V，P12＝-5V，P13＝5V,… P1i＝5V…，P1N＝-5。当充电完成后从N个像素单元的像素电极上读取的N个充电电压值分别为P21＝5.1V，P22＝-5.09V，P23＝5.05V，…P2i＝5V…，P2N＝-5.09V。i表示第i条数据线的序号，P1i为与第i条数据线相连的像素单元的写入电压值，P2i为与第i条数据线相连的像素单元的像素电极上的充电电压值。利用公式(2)计算平均误差值D。假设计算得到的平均误差值D＝0.05，这就表示实际充到像素组中N个像素单元的充电电压值比写入的固定电压值平均增大了0.05V。假设第一阈值D 1取值为0.01，则可以得到D>D 1，表明实际数据线的源驱动电压过高，因此需要采用调整策略一来调整驱动的设置。调整策略一可以为：减小源驱动电压、减小源驱动电流或减小时钟信号的占空比之一。相应的，如果平均误差值D小于第二阈值D 2，则需要采取调整策略二来调整驱动的设置。调整策略二可以为：增大源驱动电压、增大源驱动电流或者增大时钟信号的占空比之一。例如，如果计算得到的平均误差值D大于等于第二阈值D 2且小于等于第一阈值D 1时，则表明充电误差值在允许的范围内，所以可以不对驱动进行调整。
薄膜晶体管液晶显示器TFT-LCD的像素单元会随使用时间的增加而发生变化，这种变化会造成通过数据线充入像素单元的电压过大或过小而造成显示异常。本公开实施例通过平均误差值，获得调整策略，可以根据显示面板上像素单元的动态变化来调整驱动的设置，具体地，通过整体调整所有数据线充入像素单元的源驱动电压或者源驱动电流等而将像素单元的充电电压维持在规定范围内，有效改善了显示质量。
在另一些实施例中，多个充电误差值还可以包括N个独立误差值，该N个独立误差值分别用于表征所述N条数据线的充电误差值，其中，所述N个独立误差值为步骤203得到的N个差值。
例如，当步骤200的多个充电误差值包括N个独立误差值时，步骤S300的根据多个充电误差值，确定驱动的调整策略可以包括：
对于每条数据线：如果其对应的独立误差值大于第一阈值，表明对该数据线的驱动过大，则降低对该数据线的驱动的能力(例如，减小所述数据线的源驱动电压或者减小所述数据线的源驱动电流)；或者，如果其对应的独立误差值小于第二阈值，表明对该数据线的驱动过小，则提高对该数据线的驱动的能力(例如，增大所述数据线的源驱动电压或者增大所述数据线的源驱动电流)。例如，可以通过调整源驱动输出的灰阶电压来增大或者减小源驱动电压。例如， 可以通过调整源驱动输出的电流来增大或者减小源驱动电流。例如，第一阈值为正实数，第二阈值为负实数。
例如，在本公开中，所述一个或多个充电误差值满足第一条件可以表示某一条数据线对应的独立误差值大于第一阈值；所述一个或多个充电误差值满足第二条件可以表示某一条数据线对应的独立误差值小于第二阈值。
下面结合图4介绍本公开的另一实施例，详细说明根据独立误差值获得调整策略，并基于调整策略调整驱动的设置的过程。需要说明的是，图4所示的实施例在非显示区域设置两条虚栅线，其中像素组中的N个像素单元与第二条虚栅线相连。假设第一阈值为D 1且第二阈值为D 2，D 1为正实数，D 2为负实数。
步骤S401，依次为显示区域的每一行像素单元充电。
步骤S402，为非显示区域的第一条虚栅线和第二条虚栅线充电，写入电压值为固定电压值P0(|P0|>0)。
步骤S403，读取与第二条虚栅线相连的N个像素单元的充电电压值，记为Pi(i＝1,2,…N，N为数据线总数)。
步骤S404，比较每个独立误差值Di(i＝1,2,…N)与第一阈值D 1。
例如，在步骤S404中，首先采用上述公式(1)逐一计算N个独立误差值Di(i＝1,2,…N)，之后再比较每个独立误差值Di(i＝1,2,…N)与第一阈值D 1。独立误差值Di为与第i个像素单元对应的误差值，第i个像素单元对应第i条数据线，当独立误差值Di大于第一阈值D 1时，则对第i条数据线执行步骤S405，否则执行步骤S406。
步骤S405，确定调整策略一，以及根据所述调整策略一来调整例如第i条数据线的驱动的设置。
步骤S406，当独立误差值Di不大于第一阈值D 1时，比较独立误差值Di与第二阈值D 2，如果独立误差值Di小于第二阈值D 2，则对第i条数据线执行步骤S407，否则不对该第i条数据线的驱动进行调整。
步骤S407，确定调整策略二，以及根据所述调整策略二来调整例如第i条数据线的驱动的设置。
例如，调整策略一可以为减小源驱动电压、减小源驱动电流之一。调整策略二可以为增大源驱动电压、增大源驱动电流之一。
例如，假设在列翻转驱动方式下，N条数据线为与第二条虚栅线相连的N个像素单元写入的N个固定电压值分别为：P11＝5V，P12＝-5V，P13＝5V,… P1i＝5V…，P1N＝-5。当充电完成后从N个像素单元的像素电极上读取的N个充电电压值分别为P21＝5.1V，P22＝-4.95V，P23＝4.90V，…P2i＝5V…，P2N＝-5.06V。i表示第i条数据线的序号，P1i为与第i条数据线相连的像素单元的写入电压值，P2i为与第i条数据线相连的像素单元的像素电极上的充电电压值。利用公式(1)计算N个独立误差值，分别得到：第一条数据线的独立误差值D1＝0.1，这就表示第一条数据线对像素单元的充电电压值比写入电压值高了0.1V；第二条数据线的独立误差D2＝-0.05，这表示第二条数据线对像素单元的充电电压值比写入电压值低了0.05V，其他各条数据线分析同理。如果某条数据线对应的独立误差值大于第一阈值，则可以使用调整策略一来调整这条数据线的源驱动设置。相应的，如果某条数据线对应的独立误差值小于第二阈值，则可以使用调整策略二来调整这条数据线的驱动设置。需要说明的是，如果某条数据线对应的独立误差值大于等于第二阈值D2且小于等于第一阈值D1时，则表明该数据线的充电误差在允许的范围内，不用调整该数据线的源驱动。
对于尺寸较大的模组，由于显示面板的均一性的问题，位于显示面板的栅线方向的不同位置的像素单元的充电情况差别较大。因此如果提供给每一条数据线的驱动能力都一样，则可能会造成沿栅线方向的显示不均。本公开实施例的基于独立误差值可以获得针对每一条数据线的不同调整策略，自适应地调整源驱动(例如，增大或者减小某条数据线的源驱动电压、增大或者减小某条数据线的源驱动电流等)，解决因显示面板尺寸较大造成的沿栅线方向的显示不均问题。
如图5所示，本公开实施例提供一种驱动的调整电路10。调整电路10可以包括：处理子电路11，被配置为获取像素组的一个或多个充电误差值；策略生成子电路12，被配置为根据一个或多个充电误差值，确定驱动的调整策略；以及设置子电路13，被配置为根据所述调整策略来调整驱动的设置；其中，所述根据所述一个或多个充电误差值，确定所述驱动的调整策略可以包括：如果所述一个或多个充电误差值满足第一条件，则减小所述驱动；以及如果所述一个或多个充电误差值满足第二条件，则增大所述驱动。
在一些实施例中，像素组包括N个像素单元N个像素单元分别通过N条数据线提供的N个写入电压值进行充电，其中，N为所述数据线的总数目，N为大于等于1的正整数；以及所述处理子电路11还被配置为：分别读取所述N 个像素单元的N个写入电压值；测量所述N个像素单元的像素电极上的电压值，得到N个充电电压值；以及分别利用所述N个充电电压值的绝对值减去所述N个写入电压值的绝对值得到N个差值，基于所述N个差值确定所述一个或多个充电误差值。
例如，处理子电路11的输入端分别与N个像素单元的像素电极相连接，来读取测量得到的N个像素单元的像素电极上的N个充电电压值。处理子电路11的输出端与策略生成子电路12相连。
例如，可以采用软件编程的方式计算N个差值，也可以通过加法器或者乘法器等计算N个差值。
在一些实施例中，策略生成子电路12被配置为：将所述一个或多个充电误差值(例如，平均误差值或者一个或多个独立误差值)与设定的第一阈值和第二阈值进行比较得到比较结果；以及根据所述比较结果生成用于调整所述驱动的调整策略；其中，所述第一阈值为正实数，所述第二阈值为负实数。
例如，策略生成子电路12可以包括比较器。比较器可以被配置为比较一个或多个充电误差值与第一阈值和第二阈值，并输出比较结果。例如，策略生成子电路12的输出端用于输出比较结果。比较结果可以为一个或多个充电误差值大于第一阈值、小于第二阈值和位于第一阈值与第二阈值之间中的任何一种情况。需要说明的是，只有比较结果为一个或多个充电误差值大于第一阈值或者小于第二阈值时，策略生成子电路12才需要生成相应的调整驱动的策略。
在一些实施例中，设置子电路13被配置为接收策略生成子电路生成的调整策略，并依据调整策略生成相应的控制信号，之后这些控制信号会被输入驱动电路来对驱动的设置进行调整。
另外，对于如何根据比较结果得到具体的调整策略可以参考调整驱动的方法部分的相关描述，在此不作赘述。
如图6A所示，本公开实施例提供一种显示装置1。显示装置1至少包括调整电路10、栅驱动电路3、源驱动电路4。调整电路10的具体结构和实现可以参考图1-图5的相关描述，在此不作赘述。
在一些实施例中，如图6A所示，显示装置1还可以包括显示面板5。
在一些实施例中，调整电路10可以位于显示面板5上。
在一些实施例中，显示面板5上分布多个像素单元(像素单元位于相邻的栅线和相邻的数据线之间所限定的区域中)，其中，每个像素单元包括驱动晶 体管T1和像素电极6(可以参考图6A示出的两个像素单元)。驱动晶体管T1的第一极与数据线(S(1),S(2)……S(i)……S(N))相连，控制极与栅线(G(1),G(2)……G(j)……G(M-1)，G(M))相连，第二极与像素电极6相连。调整电路10可以与像素电极6相连来测量像素电极6的充电电压值。需要说明的是，虽然图6A中示出的两个像素单元的像素电极6均与调整电路10相连，但这并不说明显示面板上所有的像素单元的像素电极6均需要与调整电路10相连。只有属于像素组中的像素单元的像素电极6才需要与调整电路10相连。例如，当像素组与第一条栅线G(1)相连时，即像素组包括与第一条栅线G(1)相连的N个像素单元，则与第一条栅线G(1)相连的N个像素单元的像素电极6与调整电路10相连；当像素组与最后一条栅线G(M)相连时，即像素组包括与最后一条栅线G(M)相连的N个像素单元，则与最后一条栅线G(M)相连的N个像素单元的像素电极6与调整电路10相连。
如图6B所示，显示装置1可以通过时序控制电路9以及主机系统接口8与主机7相连。主机7被配置为向显示装置1提供多帧图像数据71。时序控制电路9至少被配置为向栅驱动电路3和源驱动电路4输入控制信号。例如，时序控制电路9可以向栅驱动电路提供时钟信号。
例如，可以在主机7向显示装置1输入相邻两帧图像数据的时间间隔内计算调整电路10所需的一个或多个充电误差值。
例如，通过调整时序控制电路9来调整时钟信号的占空比等。
例如，源驱动电路4可以依据调整电路10得到的驱动的设置来配置源驱动电压或源驱动电流之一。
例如，可以通过调整时序信号的占空比来调整栅驱动电路3输出的高电平所占的时间，进而影响像素的充电电压值。具体地，可以通过调整时序控制电路(图6B中未示出)来调整时序信号的占空比。
在一些实施例中，栅驱动电路3包括多级级联的移位寄存器(GOA)单元，其中每个移位寄存器单元的电路结构可以如图6C所示(即图6C为一级GOA单元)。
多级级联的GOA单元的功能是在一帧时间内，顺序对各栅线(G(1),G(2)……G(j)……G(M-1)，G(M))输出高电平方波，将这些栅线对应的驱动晶体管T1逐行开启，以便数据线(S(1),S(2)……S(i)……S(N)) 对显示单元面板上所有像素单元完成一次充电。
在一些实施例中，对中大尺寸显示面板，由于栅线的负载较大，为了正常开启栅线，可以多采用双边驱动。双边驱动是指，在一条栅线的左边和右边均布置一个GOA单元对其进行充电，在此种情况下，左边的GOA单元和右边的GOA单元的设计可以完全对称。
图6C示出的GOA单元包括：存储电容C1、第一晶体管M1、第二晶体管M2，第三晶体管M3、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9，第十晶体管M10以及第十一晶体管M11。
第一晶体管M1的第一极与第一电压端VDD相连来接收输入的第一直流电压信号，第二极与上拉节点PU相连，控制极与输入端INPUT相连来接收输入信号。
第二晶体管M2的第一极与上拉节点PU相连，第二极与第二电压端VSS相连来接收输入的第二直流电压，控制极与复位信号端RESET相连以接收复位信号。
第三晶体管M3的第一极与时钟信号端CLK相连以接收时钟信号，第二极与输出端OUTPUT相连，控制极与上拉节点PU相连。
第五晶体管M5的第一极与第三电压端GCH相连来接收输入第三直流电压，第二极与下拉节点PD相连，控制极与下拉控制节点PD-A相连。
第六晶体管M6的第一极与下拉节点PD相连，第二极与第四电压端VGL相连来接收输入的第四直流电压，控制极与上拉节点PU相连。
第七晶体管M7的第一极与输出端OUTPUT相连，第二极与第四电压端VGL相连来接收输入的第四直流电压，控制极与第五电压端GCL相连以接收第五直流电压。第四直流电压例如可以为低电压。
第八晶体管M8的第一极与下拉控制节点PD-A相连，第二极与第四电压端VGL相连来接收输入的第四直流电压，控制极与上拉节点PU相连。
第九晶体管M9的第一极与第三电压端GCH相连来接收输入的第三直流电压，第二极与下拉控制节点PD-A相连，控制极与第三电压端GCH相连来接收输入第三直流电压。第三直流电压例如可以为高电压。
第十晶体管M10的第一极与上拉节点PU相连，第二极与第四电压端VGL相连来接收输入的第四直流电压，控制极与下拉节点PD相连。
第十一晶体管M11的第一极与输出端OUTPUT相连，第二极与第四电压 端VGL相连来接收输入的第四直流电压，控制极与下拉节点PD相连。
存储电容C1的第一端与上拉节点PU相连，第二端与输出端OUTPUT相连。
图6C示出的GOA单元的输出端OUTPUT与图6A示出的栅线相连。
需要说明的是，图6C所示的GOA单元仅为本公开实施例的一个示例，本公开的实施例包括但不局限于图6C所示的情形。
例如，将图6C的GOA单元多级级联后的栅驱动电路3的工作过程为：一帧开始后，对第一级GOA单元输入所需的第一触发信号和时钟信号，第一级GOA单元接收到第一触发信号，在其对应的时钟信号CLK高电平时，输出高电平方波信号，该输出的高电平方波信号不仅用于其对应栅线的开启，也作为输入信号作用于下一级GOA单元。从第二级GOA单元开始，后续GOA单元接收到其前一级GOA单元提供的输入信号，在各自对应的CLK高电平时，输出高电平方波信号，该输出的高电平方波信号不仅用于其对应栅线的开启，也作为输入信号作用于下一级GOA单元，还作为复位信号作用于上一级GOA单元。如此直至最后一级GOA单元输出结束为止(如上所述，最后一级GOA单元无需将输出的高电平方波信号作为下一级的输入信号)。每级GOA单元会在本行开始输出时，关闭上一行GOA单元的输出的信号，其下一级GOA单元，也将在本行输出结束之后开始输出并关闭本行输出的信号，如此，各GOA单元即可实现顺序输出高电平方波信号，实现了移位寄存的功能。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。晶体管的控制极为晶体管的栅极。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、或其他数值)，关闭电压为高电平电压(例如，5V、10V、或其他数值)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他数值)，关闭电压为低电平电压(例如，0V、-5V或其他数值)。
需要说明的是，本公开的实施例以各个晶体管均为N型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够想到本公开实施例采用P型晶体管或N型和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
图6D为一种驱动时序图。下面结合图6D的时序图说明驱动图6C的GOA单元的工作过程。
第一阶段Q1为输入阶段，在输入阶段时设置复位信号端RESET的复位信号、时钟信号端CLK的时钟信号为低电平，输入端INPUT的输入信号为高电平(图6D中INPUT信号上的高电平方波)。
由于复位信号为低电平，第二晶体管M2关断；输入信号为高电平，第一晶体管M1导通，存储电容C1通过第一晶体管M1充电，此时上拉节点PU点为高电平，第六晶体管M6和第八晶体管M8导通，从而将第四电压端VGL的第四直流电压写入下拉节点PD。下拉节点PD点为低电平，第十晶体管M10以及第十一晶体管M11关断，保证正常输入。由于上拉节点PU点为高电平，第三晶体管M3导通，由于时钟信号为低电平，所以输出端OUTPUT输出低电平。
第二阶段Q2为输出阶段，输入信号、复位信号为低电平，时钟信号为高电平。由于存储电容C1的保持作用，上拉节点PU点为高电平，第三晶体管M3导通，时钟信号为高电平，则输出端OUTPUT输出高电平。此时下拉节点PD的电位为低电平，第十晶体管M10以及第十一晶体管M11关断，保证正常输出。
第三阶段Q3为复位阶段，此时时钟信号、输入信号为低电平，复位信号为高电平。由于复位信号为高电平，第二晶体管M2导通，上拉节点PU为低电平，第六晶体管M6和第八晶体管M8关断。第五晶体管M5和第九晶体管开启，从而将第三电压端GCH的第三直流电压写入下拉节点PD，下拉节点PD为高电平，第十晶体管M10以及第十一晶体管M11导通。上拉节点PU以及输出端的信号均为低电平。
第四阶段Q4为保持阶段，时钟信号、输入信号以及复位信号均为低电平。由于时钟信号、输入信号以及复位信号均为低电平，则第一晶体管M1、第二晶体管M2关断。上拉节点PU为低电平，第六晶体管M6和第八晶体管M8关断。下拉节点PD为高电平，第十晶体管M10以及第十一晶体管M11导通， 将上拉节点PU和输出端OUTPUT的电位继续保持为低电平。
在进入第四阶段Q4之后以及下一帧到来之前的这段时间，上述GOA单元的电路将一直工作于第四阶段Q4。
在一些实施例中，显示面板5上的非显示区域设置两条虚栅线。图6E示出了为与这两条虚栅线相连的像素单元充电以及读取充电电压值的示意图。如图6E所示，当第一条虚栅线输出结束时，向第一条虚栅线提供复位信号来复位该第一条虚栅线的输出，同理当第二条虚栅线输出结束时，则向第二条虚栅线提供复位信号来复位该第二条虚栅线的输出。参考图6E可知，在W1时段，与第一条虚栅线相连的像素单元和与第二条虚栅线相连的像素单元均处于充电阶段。当W1时段结束，则与第一条虚栅线相连的像素单元的像素电极充电阶段结束，而与第二条虚栅线相连的像素单元的充电阶段还将持续一段时间。在W2时段，当第一条虚栅线开始处于复位阶段时，第二条虚栅线还处于充电即将结束的时段。例如，本公开实施例可以在W2时段读取像素组的充电电压值。
这是由于，在W2时段，第一条虚栅线虽然关闭了，但是由于像素单元中的电容的存在使得与第二条虚栅线相连的像素单元的充电电压值在这段时间(即W2时段内)保持不变，且由于距离充电阶段结束的时间很近，所以漏电很少，且在W2时段内读取的像素组的充电电压值最接近真实的充电电压值。
参照图1-5，对调整电路10的相似的描述在此不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种调整驱动的方法，包括：
    获取像素组的一个或多个充电误差值；
    根据所述一个或多个充电误差值，确定所述驱动的调整策略；以及
    根据所述调整策略来调整所述驱动的设置；
    其中，所述根据所述一个或多个充电误差值，确定所述驱动的调整策略，包括：
    如果所述一个或多个充电误差值满足第一条件，则减小所述驱动；以及
    如果所述一个或多个充电误差值满足第二条件，则增大所述驱动。
  2. 如权利要求1所述的调整驱动的方法，其中，所述像素组中的各像素单元均与同一条扫描线相连，所述扫描线为栅线或者虚栅线。
  3. 如权利要求2所述的调整驱动的方法，其中，
    所述像素组包括N个像素单元，所述N个像素单元分别通过N条数据线提供的N个写入电压值进行充电，其中，N为所述数据线的总数目，N为大于等于1的正整数；以及
    所述获取像素组的一个或多个充电误差值，包括：
    分别读取所述N个像素单元的N个写入电压值；
    测量所述N个像素单元的像素电极上的电压值，得到N个充电电压值；以及
    分别利用所述N个充电电压值的绝对值减去所述N个写入电压值的绝对值得到N个差值，基于所述N个差值确定所述一个或多个充电误差值。
  4. 如权利要求3所述的调整驱动的方法，其中，所述N个写入电压值为N个数据电压值或者N个设定的固定电压值。
  5. 如权利要求3或4所述的调整驱动的方法，其中，
    所述扫描线与各所述像素单元的驱动晶体管的栅极连接，所述驱动晶体管在所述扫描线提供的开启电压的控制下打开；以及
    所述得到N个充电电压值包括在关闭所述驱动晶体管之前读取所述N个充电电压值。
  6. 如权利要求3-5任一项所述的调整驱动的方法，其中，所述一个充电误差值为平均误差值，所述平均误差值为所述N个差值的平均值，所述平均误 差值用于表征所述N条数据线的平均充电误差。
  7. 如权利要求6所述的调整驱动的方法，其中，所述根据所述一个或多个充电误差值，确定所述驱动的调整策略，包括：
    如果所述平均误差值大于第一阈值，则减小源驱动电压或减小源驱动电流或减小时钟信号的占空比；或者
    如果所述平均误差值小于第二阈值，则增大源驱动电压或增大源驱动电流或增大时钟信号的占空比；
    其中，所述第一阈值为正实数，所述第二阈值为负实数。
  8. 如权利要求3-5任一项所述的调整驱动的方法，其中，所述多个充电误差值包括N个独立误差值，所述N个独立误差值为所述N个差值，所述N个独立误差值分别用于表征所述N条数据线的充电误差。
  9. 如权利要求8所述的调整驱动的方法，其中，所述根据所述一个或多个充电误差值，确定所述驱动的调整策略，包括：
    对于每条数据线：
    如果其对应的独立误差值大于第一阈值，则减小所述数据线的源驱动电压或者减小所述数据线的源驱动电流；或者
    如果其对应的独立误差值小于第二阈值，则增大所述数据线的源驱动电压或者增大所述数据线的源驱动电流；
    其中，所述第一阈值为正实数，所述第二阈值为负实数。
  10. 如权利要求3-5任一项所述的调整驱动的方法，其中，所述分别利用所述N个充电电压值的绝对值减去所述N个写入电压值的绝对值得到N个差值，包括：
    获取主机向驱动电路输入相邻两帧图像数据的时间间隔；以及
    在所述时间间隔内计算所述N个差值。
  11. 一种驱动调整电路，包括，
    处理子电路，被配置为获取像素组的一个或多个充电误差值；
    策略生成子电路，被配置为根据所述一个或多个充电误差值，确定所述驱动的调整策略；以及
    设置子电路，被配置为根据所述调整策略来调整所述驱动的设置；
    其中，所述策略生成子电路，还被配置为：如果所述一个或多个充电误差值满足第一条件，则减小所述驱动；以及如果所述一个或多个充电误差值满足 第二条件，则增大所述驱动。
  12. 如权利要求11所述的驱动调整电路，其中，所述像素组包括N个像素单元，所述N个像素单元分别通过N条数据线提供的N个写入电压值进行充电，其中，N为所述数据线的总数目，N为大于等于1的正整数；以及
    所述处理子电路还被配置为：
    分别读取所述N个像素单元的N个写入电压值；
    测量所述N个像素单元的像素电极上的电压值，得到N个充电电压值；以及
    分别利用所述N个充电电压值的绝对值减去所述N个写入电压值的绝对值得到N个差值，基于所述N个差值确定所述一个或多个充电误差值。
  13. 如权利要求11或12所述的驱动调整电路，其中，所述策略生成子电路还被配置为：将所述一个或多个充电误差值与设定的第一阈值和第二阈值进行比较得到比较结果；以及根据所述比较结果生成用于调整所述驱动的调整策略；其中，所述第一阈值为正实数，所述第二阈值为负实数。
  14. 如权利要求11-13任一项所述的驱动调整电路，其中，所述像素组中的各像素单元均与同一条扫描线相连，所述扫描线为栅线或者虚栅线。
  15. 一种显示装置，包含权利要求11-14任一项所述的调整电路、栅驱动电路以及源驱动电路，其中，
    所述源驱动电路被配置为依据所述驱动的设置来配置源驱动电压或源驱动电流；以及
    所述栅驱动电路被配置为依据所述驱动的设置来减小或增大输出的栅驱动信号所占的时间。
PCT/CN2018/103975 2017-12-08 2018-09-04 驱动调整电路及调整方法、显示装置 WO2019109686A1 (zh)

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