WO2019109441A1 - Method for fabricating polysilicon tft substrate and polysilicon tft substrate - Google Patents

Method for fabricating polysilicon tft substrate and polysilicon tft substrate Download PDF

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WO2019109441A1
WO2019109441A1 PCT/CN2018/070060 CN2018070060W WO2019109441A1 WO 2019109441 A1 WO2019109441 A1 WO 2019109441A1 CN 2018070060 W CN2018070060 W CN 2018070060W WO 2019109441 A1 WO2019109441 A1 WO 2019109441A1
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layer
region
polysilicon
ion
active layer
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PCT/CN2018/070060
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French (fr)
Chinese (zh)
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刘丹
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武汉华星光电半导体显示技术有限公司
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Publication of WO2019109441A1 publication Critical patent/WO2019109441A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to the field of display, and in particular to a method for fabricating a polysilicon TFT (Thin Film Transistor) substrate and a polysilicon TFT substrate.
  • a polysilicon TFT Thin Film Transistor
  • MOS metal oxide semiconductor
  • ILD interlayer insulating layer
  • the thermal diffusion process depends on the concentration gradient, and its concentration decreases from the surface layer to the inside of the polysilicon, and has a Gaussian distribution.
  • FIG. 1 a schematic diagram of the concentration-depth correspondence relationship of the thermal diffusion hydrogen in the prior art is shown;
  • the ion implantation has the highest concentration at the target depth.
  • the simulated 1E4 B+ ions are implanted into the polysilicon of 500A at 8Kev (kiloelectron volts), and the obtained ion concentration versus depth is shown in Fig. 2.
  • boron ions have the highest concentration at the targeted depth. Therefore, in polycrystalline silicon, hydrogen is supplemented by high temperature expansion, and it is impossible to achieve a good overlap between the hydrogen concentration and the boron concentration.
  • the technical problem to be solved by the present invention is to provide a method for fabricating a polysilicon TFT substrate and a corresponding polysilicon TFT substrate, which can improve the hydrogen replenishing effect in the fabrication of the polysilicon TFT substrate, and can accurately control the concentration and depth of hydrogen atom replenishment, and Improve the yield of polysilicon TFT substrates and improve their performance.
  • an aspect of an embodiment of the present invention provides a method for fabricating a polysilicon TFT substrate, including the following steps:
  • Step S10 depositing an amorphous silicon film layer on the substrate
  • Step S11 performing an excimer laser annealing on the amorphous silicon film layer to form a polysilicon active layer
  • Step S12 ion doping the channel region of the polysilicon active layer to form a channel doping region
  • Step S13 depositing a gate insulating layer on the polysilicon active layer
  • Step S14 using an ion implanter to control the injection of hydrogen ions into the channel region of the active layer polysilicon;
  • Step S15 depositing a gate layer on the gate insulating layer
  • Step S16 performing ion doping on the source region and the drain region of the polysilicon active layer to form a source doped region and a drain doped region;
  • Step S17 depositing an interlayer insulating layer on the gate layer
  • Step S18 forming a first via hole and a second via hole on the interlayer insulating layer facing the source doping region and the drain doping region, where the first via hole and the second via hole Forming a source electrode film layer and a drain electrode film layer respectively in the holes, and electrically connecting the source electrode film layer to the source doping region of the polysilicon active layer through the first via hole, so that the drain electrode The film layer is electrically connected to the drain doping region of the polysilicon active layer through the second via.
  • the step S12 further includes:
  • the boron-containing ion material is implanted into the channel region of the polysilicon active layer by an ion implanter to form a channel doped region, and the boron-containing ion material is B2H6 or BF3.
  • the step S12 specifically includes:
  • a first implant energy value and a boron ion concentration value are set in the ion implanter, and the boron-containing ion material is controlled to be implanted into the polysilicon active layer at the first implant angle at the first implant energy value.
  • the step S13 is specifically:
  • Step S19 forming a flat layer on the interlayer insulating layer, and forming a third via hole on the flat layer facing the position of the drain electrode film layer;
  • Step S190 forming a pixel electrode layer on the flat layer, extending the pixel electrode layer into the third via hole, and electrically connecting the drain electrode film layer.
  • the method further includes:
  • Ion doping is performed between a source region, a drain region and the channel region of the polysilicon active layer to form a doping buffer.
  • a method for fabricating a polysilicon TFT substrate which includes the following steps:
  • Step S10 depositing an amorphous silicon film layer on the substrate
  • Step S11 performing an excimer laser annealing on the amorphous silicon film layer to form a polysilicon active layer
  • Step S12 ion doping the channel region of the polysilicon active layer to form a channel doping region
  • Step S13 depositing a gate insulating layer on the polysilicon active layer
  • Step S14 using an ion implanter to control the injection of hydrogen ions into the channel region of the active layer polysilicon;
  • Step S15 depositing a gate layer on the gate insulating layer
  • Step S16 performing ion doping on the source region and the drain region of the polysilicon active layer to form a source doped region and a drain doped region;
  • Step S17 depositing an interlayer insulating layer on the gate layer
  • Step S18 forming a first via hole and a second via hole on the interlayer insulating layer facing the source doping region and the drain doping region, where the first via hole and the second via hole Forming a source electrode film layer and a drain electrode film layer respectively in the holes, and electrically connecting the source electrode film layer to the source doping region of the polysilicon active layer through the first via hole, so that the drain electrode The film layer is electrically connected to the drain doping region of the polysilicon active layer through the second via hole;
  • Step S19 forming a flat layer on the interlayer insulating layer, and forming a third via hole on the flat layer facing the position of the drain electrode film layer;
  • Step S190 forming a pixel electrode layer on the flat layer, extending the pixel electrode layer into the third via hole, and electrically connecting the drain electrode film layer.
  • the step S12 further includes:
  • Boron ions are implanted into the polysilicon active layer by an ion implanter to form a channel doped region, and the boron ion material is B2H6 or BF3.
  • the step S12 specifically includes:
  • the step S13 is specifically:
  • the method further includes:
  • Ion doping is performed between the source doped region, the drain doped region and the channel region of the polysilicon active layer to form a doping buffer.
  • another aspect of the embodiments of the present invention further provides a polysilicon TFT substrate, which is fabricated by the foregoing method, and the polysilicon TFT substrate includes:
  • a polysilicon active layer formed by depositing an amorphous silicon film layer on the substrate and performing excimer laser annealing;
  • the polysilicon active layer includes a channel doped region in the middle, and is doped in the channel a source-drain doping region on both sides of the region, wherein an ion implanter is used to implant hydrogen ions in the channel doping region;
  • An interlayer insulating layer is deposited on the gate layer, and a first via and a second via are formed on the interlayer insulating layer at positions adjacent to the source doping region and the drain doping region Forming, in the first via and the second via, an active electrode film layer and a drain electrode film layer, wherein the source electrode film layer passes through the first via hole and the polysilicon active layer The source doped regions are electrically connected, and the drain electrode film layer is electrically connected to the drain doping region of the polysilicon active layer through the second via.
  • a pixel electrode layer is disposed on the flat layer, and the pixel electrode layer extends into the third via hole and is electrically connected to the drain electrode film layer.
  • a doping buffer is formed by ion doping between the source doping region, the drain doping region and the channel region of the polysilicon active layer.
  • the hydrogen replenishing operation is completed before the gate layer (M1) process, and sufficient channel filling can be achieved.
  • Hydrogen ions at the same time, by controlling the value of the injected energy, the target depth and concentration of the hydrogen ions can be coincident with the target depth and concentration distribution of the boron ions to form a boron-hydrogen complex, thereby improving the channel.
  • the source of the hydrogen ions in the present invention is no longer dependent on the interlayer insulating layer (ILD), high temperature annealing is not required after the ILD film formation, the ILD is prevented from being broken, the performance of the thin film transistor is improved, and the product yield is improved;
  • ILD interlayer insulating layer
  • the hydrogen-filling operation is performed by means of ion implantation, and the depth and concentration of hydrogen atom filling can be precisely controlled, and the process is very simple and feasible.
  • 1 is a schematic diagram showing the relationship between the concentration and depth of thermal diffusion hydrogen in the prior art
  • FIG. 2 is a schematic diagram showing the relationship between ion concentration and depth obtained by implanting boron ions into silicon by ion implantation in an example of the prior art
  • FIG. 3 is a schematic diagram of a main flow of an embodiment of a method for fabricating a polysilicon TFT substrate provided by the present invention
  • FIG. 4 is a schematic diagram showing the relationship between the energy of injecting boron ions into crystalline silicon and the depth of interest in one embodiment
  • Figure 5 is a schematic diagram showing the relationship between the energy of injecting hydrogen ions into crystalline silicon and the depth of interest in one embodiment
  • Figure 6 is a graph showing the relationship between the energy of injecting hydrogen ions into silicon oxide (SiOx) and the depth of interest in one embodiment
  • FIG. 7 is a schematic diagram showing the relationship between ion concentration and depth obtained by injecting 1E4 hydrogen ions into 1300ASiO+500A Si with 8Kev energy in one embodiment
  • FIG. 8 is a schematic structural view of an embodiment of a polysilicon TFT substrate provided by the present invention.
  • FIG. 2 is a schematic diagram of a main flow of an embodiment of a method for fabricating a polysilicon TFT substrate provided by the present invention; in this embodiment, the method includes at least the following steps:
  • step S10 an amorphous silicon film layer is formed on the base substrate by an enhanced chemical vapor deposition method.
  • the base substrate may be a glass substrate or a flexible PI (polyimide resin) substrate.
  • step S11 the amorphous silicon film layer is subjected to excimer laser annealing to form a polysilicon active layer.
  • Step S12 performing ion doping of the channel region of the polysilicon active layer to form a channel doping region; specifically, applying a small amount of donor or acceptor impurity ions (such as boron ions) in the channel region by ion implantation technique Injecting therein for adjusting the magnitude of the threshold voltage of the device; specifically, in some examples, the step S12 may include controlling the implantation of boron ions (ie, boron ions) into the channel region of the active layer of the polysilicon by using an ion implanter. Material), forming a channel doping region, the boron ion material is B2H6 or BF3;
  • the step S12 sets a first implantation energy value (such as 8Kev) and a boron ion concentration value in the ion implanter, and controls the boron-containing ion material to be targeted at the first implantation energy value ( 90 degrees) is implanted into the channel region of the polysilicon active layer.
  • a first implantation energy value such as 8Kev
  • a boron ion concentration value in the ion implanter
  • Step S13 depositing a gate insulating layer (GI) on the polysilicon active layer.
  • GI gate insulating layer
  • Step S14 using an ion implanter to control the injection of hydrogen ions into the channel region of the active layer polysilicon; specifically, in an example, the step S13 is specifically:
  • a second implantation energy value such as 8Kev
  • a hydrogen ion concentration in the ion implanter and controlling the first implantation energy value to inject hydrogen ions into the groove of the polysilicon active layer at a targeting angle (90 degrees)
  • the hydrogen ions form a boron-hydrogen complex with the free boron ions.
  • the hydrogen ion material may be, for example, B 2 H 6 , PH 3 or the like.
  • the implantation of hydrogen ions (H+) is performed after deposition to form the gate insulating layer, and the principle thereof is as follows: because Si has a blocking ability against H+ than Si to boron ions (B+ ) Weakly much, theoretically, if 8Kev is used to inject B+ in the channel region, and only 2Kev for H+ can achieve the same target depth; as shown in Figure 4 and Figure 5, an example is shown respectively.
  • a schematic diagram showing the relationship between the energy of implanting boron ions into crystalline silicon and the depth of the target, and the relationship between the energy of injecting hydrogen ions into the crystalline silicon and the depth of the target.
  • the hydrogen ion implantation energy is smaller.
  • Ion Energy means injection energy value
  • Projected Range means projection range (target depth)
  • Longitudinal Straggling means longitudinal dispersion
  • lateral Straggling means lateral dispersion
  • -dE/dx means incident ion The nucleus and electrons block the energy loss at unit distance
  • Tiget Density indicates the target density
  • Ion Range indicates the ion range.
  • the current injection machine for panel owners is Nissin's iG6.
  • 2Kev is a working range that is easy to cause arcing of the electrode plate for the Acc power supply of the device. Therefore, in the embodiment of the present invention, the H+ implant process is placed after the gate insulating layer deposition process. At this time, when the active layer is H+ implanted, the gate insulating layer needs to be transmitted, so in one embodiment, The injection energy of H+ is controlled to be similar to the injection energy of B+. For example, when H+ is implanted, the injection energy of 8Kev can also be used to achieve the best coincidence of the concentration distribution of B+ and H+.
  • Step S15 depositing a gate layer (M1) on the gate insulating layer.
  • the source region and the drain region of the polysilicon active layer are ion doped to form a source/drain doping region.
  • the ion doped material in this step may be a PHx material.
  • the method further comprises: performing ion doping between the source region, the drain region and the channel region of the polysilicon active layer to form a doping buffer respectively.
  • the material forming the doping buffer can also be made of PHx material, except that the dose of the material used to form the doping buffer is smaller than the dose used to form the source and drain doping regions, and the doping buffer is used.
  • the zone is mainly concentrated on the side close to the channel zone.
  • Step S17 depositing an interlayer insulating layer (ILD) on the gate layer.
  • ILD interlayer insulating layer
  • Step S18 forming a first via hole and a second via hole in a position facing the source region and the drain doping region on the interlayer insulating layer, in the first via hole and the second via hole Depositing a source electrode film layer and a drain electrode film layer (M2), respectively, and electrically connecting the source electrode film layer to the source region of the polysilicon active layer through the first via hole to make the drain electrode film
  • the layer is electrically connected to the drain doping region of the polysilicon active layer through the second via.
  • Step S19 forming a flat layer on the interlayer insulating layer, and forming a third via hole on the flat layer facing the position of the drain electrode film layer;
  • Step S190 forming a pixel electrode layer on the flat layer, extending the pixel electrode layer into the third via hole, and electrically connecting the drain electrode film layer.
  • FIG. 6 a schematic diagram showing the relationship between the energy of injecting hydrogen ions into silicon oxide (SiOx) and the depth of penetration in one embodiment is shown, from which it can be seen that the relationship is shown in FIG. Very similar.
  • FIG. 7 a schematic diagram showing the relationship between the ion concentration and the depth obtained by injecting 1E4 hydrogen ions into 1300A SiO2+500A Si at 8Kev energy is shown in FIG. 7; it can be seen that the ion implantation is in the ion range.
  • the hydrogen ion has the highest concentration (Ion Range).
  • the concentration distribution after hydrogen ion implantation is similar to the distribution of boron ions in the channel (can be compared with FIG. 2), the hydrogen atom can be monitored and the dose can be monitored by the injection method. Maximize the action of hydrogen.
  • Ion Range indicates ion range
  • Straggle indicates discrete
  • Skewness indicates skewness
  • Kinurtosis indicates kurtosis
  • abscissa indicates injection depth (Target Depth)
  • ordinate indicates hydrogen ion concentration.
  • the polysilicon TFT substrate is formed by the method described above.
  • the polysilicon TFT substrate 10 includes:
  • a base substrate 10 which may be a glass substrate or a flexible PI (polyimide resin) substrate;
  • a polysilicon active layer 13 formed by depositing an amorphous silicon film layer on the substrate 10 and performing excimer laser annealing;
  • the polysilicon active layer 13 includes a channel doping region 130 located in the middle a source doping region 131 and a drain doping region 132 on both sides of the channel doping region 130, wherein an ion implanter is used to implant hydrogen ions in the channel doping region;
  • a source of the polysilicon active layer a doping buffer 133 is formed between the electrode doped region 131, the drain doping region 132 and the channel doping region 130 by ion doping;
  • a gate insulating layer 14 is deposited on the polysilicon active layer 13;
  • An interlayer insulating layer 16 is deposited on the gate layer 15 and a first surface is formed on the interlayer insulating layer 16 opposite to the source doping region 131 and the drain doping region 132.
  • the hole 160 and the second via 161 are respectively deposited in the first via 160 and the second via 161 to form an active electrode film layer 162 and a drain electrode film layer 163, and the source electrode film layer 162 passes through the
  • the first via 160 is electrically connected to the source doping region 131 of the polysilicon active layer, and the drain electrode film layer 163 passes through the second via 161 and the drain doping region of the polysilicon active layer 132 electrical connection;
  • the flat layer 17 is disposed on the interlayer insulating layer 16, and a third via hole 171 is formed on the flat layer 17 at a position facing the drain electrode film layer 163;
  • the pixel electrode layer 18 is disposed on the flat layer 17, and the pixel electrode layer 18 extends into the third via hole 171 and is electrically connected to the drain electrode film layer 163.
  • a buffer layer 12 may be further disposed between the base substrate 10 and the polysilicon active layer 13.
  • the buffer layer 12, the gate insulating layer 14, and the interlayer insulating layer 16 may each be a SiNx/SiO2 material
  • the flat layer 17 may be a SiNx or organic film material
  • the pixel electrode layer A metal oxide material (such as ITO) may be used, and the source electrode film layer 162 and the drain electrode film layer 163 may each be made of a metal material such as titanium metal or aluminum titanium alloy.
  • the hydrogen replenishing operation is completed before the gate layer (M1) process, and sufficient channel filling can be achieved.
  • Hydrogen ions at the same time, by controlling the value of the injected energy, the target depth and concentration of the hydrogen ions can be coincident with the target depth and concentration distribution of the boron ions to form a boron-hydrogen complex, thereby improving the channel.
  • the hydrogen-filling operation is performed by means of ion implantation, and the depth and concentration of hydrogen atom filling can be precisely controlled, and the process is very simple and feasible.

Abstract

A method for fabricating a polysilicon TFT substrate comprises: step S10, depositing an amorphous silicon film layer on a base substrate (10); step S11, performing excimer laser annealing on the amorphous silicon film layer to form a polysilicon active layer (13); step S12, ion doping a channel region of the polysilicon active layer (13) to form a channel doping region (130); step S13, performing deposition on the polysilicon active layer (13) to form a gate insulating layer (14); step S14, performing hydrogen ion implantation into the channel doping region (130) of the polysilicon active layer; step S15, performing deposition on the gate insulating layer (14) to form a gate layer (15); step S16, ion doping a source region and a drain region of the polysilicon active layer (13) to form a source doping region (131) and a drain doping region (132); step S17, performing deposition on the gate layer (15) to form an interlayer insulating layer (16); step S18, forming a first via hole (160) and a second via hole (161) on the interlayer insulating layer (16), and performing deposition to respectively form a source electrode film layer (162) and a drain electrode film layer (163) for electrical connection to the source doping region (131) and the drain doping region (132), respectively. A corresponding polysilicon TFT substrate is also disclosed. The invention can accurately control the concentration and depth of the added hydrogen atoms and improve TFT yield.

Description

一种多晶硅TFT基板的制作方法及多晶硅TFT基板Method for manufacturing polysilicon TFT substrate and polysilicon TFT substrate
本申请要求于2017年12月4日提交中国专利局、申请号为201711258888.9、发明名称为“一种多晶硅TFT基板的制作方法及多晶硅TFT基板”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。The present application claims the priority of the Chinese Patent Application entitled "A Polysilicon TFT Substrate Manufacturing Method and a Polycrystalline Silicon TFT Substrate", which is filed on Dec. 4, 2017, the entire contents of which are hereby incorporated by reference. This is incorporated herein by reference.
技术领域Technical field
本发明涉及显示领域，特别涉及一种多晶硅TFT(Thin Film Transistor，薄膜晶体管)基板的制作方法及多晶硅TFT基板。The present invention relates to the field of display, and in particular to a method for fabricating a polysilicon TFT (Thin Film Transistor) substrate and a polysilicon TFT substrate.
背景技术Background technique
在目前主流的多晶硅TFT制程中，一般采用离子注入的方式制作MOS(金属氧化物半导体)管，由于晶体本身会存在一些缺陷及杂质，并且注入的离子引入了新的能级，导致掺杂多晶硅(如掺硼)电学性能不能达到要求。现有技术中，通常解决方法是通过补氢来填补多晶硅晶体缺陷，钝化注入的硼离子，增加电子迁移率。常见的氢原子的补入都是以热扩散的方式进行，利用层间绝缘层(ILD)膜层中的氢元素，通过高温让其扩散到有源层多晶硅的表层。这种方式难以估算氢元素补入的深度及浓度(经常都是以经验值按照补氢的时间去衡量氢原子补入的量)，且补氢只能在ILD成膜后进行，受成膜前的有机物残留等影响，极易在高温后形成破洞。In the current mainstream polysilicon TFT process, MOS (metal oxide semiconductor) tubes are generally fabricated by ion implantation. Since the crystal itself has some defects and impurities, and the implanted ions introduce new energy levels, resulting in doped polysilicon. (such as boron doping) electrical performance can not meet the requirements. In the prior art, the usual solution is to fill the polysilicon crystal defects by hydrogen supplementation, passivate the implanted boron ions, and increase the electron mobility. The addition of a common hydrogen atom is carried out by means of thermal diffusion, and the hydrogen element in the interlayer insulating layer (ILD) film layer is diffused to the surface layer of the active layer polysilicon by a high temperature. In this way, it is difficult to estimate the depth and concentration of hydrogen enrichment (often the amount of hydrogen is added by empirical time according to the time of hydrogen supplementation), and hydrogen can only be formed after ILD film formation. The influence of the former organic matter residue is extremely easy to form a hole at a high temperature.
另外，有实验表明，掺硼硅在氢化后载流子浓度降低、迁移率升高，电阻率升高、电容减小。二次离子质谱的深度分布分析表明，氢与硼的分布存在对应关系，且只要没有形成更稳定的氢分子，无论晶格符合哪种模型，硼-氢(B-H)复合体中的氢总是对硼存在钝化作用。由此推断，在最影响TFT电性的沟道(Chanel)区，硼(B)与氢(H)的浓度分布如果完全重合(形成B-H复合体)，可以得到最佳电性。但事实上，热扩散过程依赖浓度梯度进行，其浓度由表层至多晶硅内部递减，呈高斯分布，如图1所示，示出了 现有技术中热扩散补氢的浓度-深度对应关系示意图；而离子注入在靶向深度上具有最高浓度，例如在一个例子中，模拟1E4个B+离子以8Kev(千电子伏特)能量注入500A的多晶硅中，获得的离子浓度与深度的关系图如图2所示，从图2中可以看出，硼离子在靶向深度上具有最高浓度。故在多晶硅中，通过高温扩展进行补氢，无法使氢浓度和硼浓度实现很好的重合。In addition, experiments have shown that after boronation, the carrier concentration decreases, the mobility increases, the resistivity increases, and the capacitance decreases. The depth distribution analysis of secondary ion mass spectrometry shows that there is a corresponding relationship between the distribution of hydrogen and boron, and as long as no more stable hydrogen molecules are formed, no matter which model the crystal lattice conforms to, the hydrogen in the boron-hydrogen (BH) complex is always There is a passivation effect on boron. From this, it is inferred that in the Chanel region which most affects the electrical conductivity of the TFT, if the concentration distribution of boron (B) and hydrogen (H) completely coincides (formation of the B-H composite), optimum electrical properties can be obtained. However, in fact, the thermal diffusion process depends on the concentration gradient, and its concentration decreases from the surface layer to the inside of the polysilicon, and has a Gaussian distribution. As shown in FIG. 1 , a schematic diagram of the concentration-depth correspondence relationship of the thermal diffusion hydrogen in the prior art is shown; The ion implantation has the highest concentration at the target depth. For example, in one example, the simulated 1E4 B+ ions are implanted into the polysilicon of 500A at 8Kev (kiloelectron volts), and the obtained ion concentration versus depth is shown in Fig. 2. As can be seen from Figure 2, boron ions have the highest concentration at the targeted depth. Therefore, in polycrystalline silicon, hydrogen is supplemented by high temperature expansion, and it is impossible to achieve a good overlap between the hydrogen concentration and the boron concentration.
发明内容Summary of the invention
本发明所要解决的技术问题在于，提供一种多晶硅TFT基板的制作方法及相应的及多晶硅TFT基板，可以改善多晶硅TFT基板制造中补氢效果，可以精确控制氢原子补入的浓度和深度，并提高多晶硅TFT基板的良率和改善其性能。The technical problem to be solved by the present invention is to provide a method for fabricating a polysilicon TFT substrate and a corresponding polysilicon TFT substrate, which can improve the hydrogen replenishing effect in the fabrication of the polysilicon TFT substrate, and can accurately control the concentration and depth of hydrogen atom replenishment, and Improve the yield of polysilicon TFT substrates and improve their performance.
为了解决上述技术问题，本发明的实施例的一方面提供一一种多晶硅TFT基板的制作方法，包括下述步骤：In order to solve the above technical problem, an aspect of an embodiment of the present invention provides a method for fabricating a polysilicon TFT substrate, including the following steps:
步骤S10，在衬底基板上沉积非晶硅膜层；Step S10, depositing an amorphous silicon film layer on the substrate;
步骤S11，对所述非晶硅膜层进行准分子激光退火，形成多晶硅有源层；Step S11, performing an excimer laser annealing on the amorphous silicon film layer to form a polysilicon active layer;
步骤S12，对所述多晶硅有源层的沟道区域进行离子掺杂，形成沟道掺杂区；Step S12, ion doping the channel region of the polysilicon active layer to form a channel doping region;
步骤S13，在所述多晶硅有源层上沉积形成栅极绝缘层；Step S13, depositing a gate insulating layer on the polysilicon active layer;
步骤S14，采用离子注入机控制向所述有源层多晶硅的沟道区域注入氢离子；Step S14, using an ion implanter to control the injection of hydrogen ions into the channel region of the active layer polysilicon;
步骤S15，在所述栅极绝缘层上沉积形成栅极层；Step S15, depositing a gate layer on the gate insulating layer;
步骤S16，对所述多晶硅有源层的源极区与漏极区进行离子掺杂，形成源极掺杂区和漏极掺杂区；Step S16, performing ion doping on the source region and the drain region of the polysilicon active layer to form a source doped region and a drain doped region;
步骤S17，在所述栅极层上沉积形成层间绝缘层；Step S17, depositing an interlayer insulating layer on the gate layer;
步骤S18，在所述层间绝缘层上正对所述源极掺杂区以及漏极掺杂区的位置形成第一过孔以及第二过孔，在所述第一过孔和第二过孔中分别沉积形成源电极膜层和漏电极膜层，使所述源电极膜层通过所述第一过孔与所述多晶硅有源层的源极掺杂区电连接，使所述漏电极膜层通过所述第二过孔与所述多晶硅有源层的漏极掺杂区电连接。Step S18, forming a first via hole and a second via hole on the interlayer insulating layer facing the source doping region and the drain doping region, where the first via hole and the second via hole Forming a source electrode film layer and a drain electrode film layer respectively in the holes, and electrically connecting the source electrode film layer to the source doping region of the polysilicon active layer through the first via hole, so that the drain electrode The film layer is electrically connected to the drain doping region of the polysilicon active layer through the second via.
其中，所述步骤S12进一步包括：The step S12 further includes:
采用离子注入机控制向所述多晶硅有源层的沟道区域中注入含硼离子材料，形成沟道掺杂区，所述含硼离子材料为B2H6或BF3。The boron-containing ion material is implanted into the channel region of the polysilicon active layer by an ion implanter to form a channel doped region, and the boron-containing ion material is B2H6 or BF3.
其中，所述步骤S12具体包括：The step S12 specifically includes:
在离子注入机中设置第一注入能量值以及硼离子浓度值，以所述第一注入能量值控制将所述含硼离子材料以所述第一注入角度注入至所述多晶硅有源层。A first implant energy value and a boron ion concentration value are set in the ion implanter, and the boron-containing ion material is controlled to be implanted into the polysilicon active layer at the first implant angle at the first implant energy value.
其中，所述步骤S13具体为：The step S13 is specifically:
在离子注入机中设置第二注入能量值以及氢离子浓度，以所述第一注入能量值控制将氢离子以所述第二注入角度注入至所述多晶硅有源层，使所述氢离子与所述硼离子形成硼-氢复合体。Setting a second implantation energy value and a hydrogen ion concentration in the ion implanter, and controlling, by the first implantation energy value, injecting hydrogen ions into the polysilicon active layer at the second implantation angle, so that the hydrogen ions The boron ions form a boron-hydrogen complex.
其中，进一步包括：Among them, further includes:
步骤S19，在所述层间绝缘层上形成平坦层，在所述平坦层上正对所述漏电极膜层的位置形成第三过孔；Step S19, forming a flat layer on the interlayer insulating layer, and forming a third via hole on the flat layer facing the position of the drain electrode film layer;
步骤S190，在所述平坦层上形成像素电极层，使所述像素电极层延伸至所述第三过孔中，并与所述漏电极膜层电连接。Step S190, forming a pixel electrode layer on the flat layer, extending the pixel electrode layer into the third via hole, and electrically connecting the drain electrode film layer.
其中，在所述步骤S16中进一步包括：Wherein, in the step S16, the method further includes:
对所述多晶硅有源层的源极区、漏极区与所述沟道区之间进行离子掺杂，分别形成一个掺杂缓冲区。Ion doping is performed between a source region, a drain region and the channel region of the polysilicon active layer to form a doping buffer.
相应地，本发明实施例的又一方面，还提供一种多晶硅TFT基板的制作方法，其中，包括下述步骤：Correspondingly, in another aspect of the embodiments of the present invention, a method for fabricating a polysilicon TFT substrate is further provided, which includes the following steps:
步骤S10，在衬底基板上沉积非晶硅膜层；Step S10, depositing an amorphous silicon film layer on the substrate;
步骤S11，对所述非晶硅膜层进行准分子激光退火，形成多晶硅有源层；Step S11, performing an excimer laser annealing on the amorphous silicon film layer to form a polysilicon active layer;
步骤S12，对所述多晶硅有源层的沟道区域进行离子掺杂，形成沟道掺杂区；Step S12, ion doping the channel region of the polysilicon active layer to form a channel doping region;
步骤S13，在所述多晶硅有源层上沉积形成栅极绝缘层Step S13, depositing a gate insulating layer on the polysilicon active layer
步骤S14，采用离子注入机控制向所述有源层多晶硅的沟道区域注入氢离子；Step S14, using an ion implanter to control the injection of hydrogen ions into the channel region of the active layer polysilicon;
步骤S15，在所述栅极绝缘层上沉积形成栅极层；Step S15, depositing a gate layer on the gate insulating layer;
步骤S16，对所述多晶硅有源层的源极区与漏极区进行离子掺杂，形成源极掺杂区和漏极掺杂区；Step S16, performing ion doping on the source region and the drain region of the polysilicon active layer to form a source doped region and a drain doped region;
步骤S17，在所述栅极层上沉积形成层间绝缘层；Step S17, depositing an interlayer insulating layer on the gate layer;
步骤S18，在所述层间绝缘层上正对所述源极掺杂区以及漏极掺杂区的位置形成第一过孔以及第二过孔，在所述第一过孔和第二过孔中分别沉积形成源电极膜层和漏电极膜层，使所述源电极膜层通过所述第一过孔与所述多晶硅有源层的源极掺杂区电连接，使所述漏电极膜层通过所述第二过孔与所述多晶硅有源层的漏极掺杂区电连接；Step S18, forming a first via hole and a second via hole on the interlayer insulating layer facing the source doping region and the drain doping region, where the first via hole and the second via hole Forming a source electrode film layer and a drain electrode film layer respectively in the holes, and electrically connecting the source electrode film layer to the source doping region of the polysilicon active layer through the first via hole, so that the drain electrode The film layer is electrically connected to the drain doping region of the polysilicon active layer through the second via hole;
步骤S19，在所述层间绝缘层上形成平坦层，在所述平坦层上正对所述漏电极膜层的位置形成第三过孔；Step S19, forming a flat layer on the interlayer insulating layer, and forming a third via hole on the flat layer facing the position of the drain electrode film layer;
步骤S190，在所述平坦层上形成像素电极层，使所述像素电极层延伸至所述第三过孔中，并与所述漏电极膜层电连接。Step S190, forming a pixel electrode layer on the flat layer, extending the pixel electrode layer into the third via hole, and electrically connecting the drain electrode film layer.
其中，所述步骤S12进一步包括：The step S12 further includes:
采用离子注入机控制向所述多晶硅有源层中注入硼离子，形成沟道掺杂区，所述硼离子材料为B2H6或BF3。Boron ions are implanted into the polysilicon active layer by an ion implanter to form a channel doped region, and the boron ion material is B2H6 or BF3.
其中，所述步骤S12具体包括：The step S12 specifically includes:
在离子注入机中设置第一注入能量值、第一注入角度以及硼离子浓度值，以所述第一注入能量值控制将所述含硼离子材料以所述第一注入角度注入至所述多晶硅有源层的沟道区域。Setting a first implantation energy value, a first implantation angle, and a boron ion concentration value in the ion implanter, and controlling, by the first implantation energy value, injecting the boron-containing ion material into the polysilicon at the first injection angle The channel region of the active layer.
其中，所述步骤S13具体为：The step S13 is specifically:
在离子注入机中设置第二注入能量值以及氢离子浓度，以所述第一注入能量值控制将氢离子注入至所述多晶硅有源层，使所述氢离子与所述硼离子形成硼-氢复合体。Setting a second implantation energy value and a hydrogen ion concentration in the ion implanter, and controlling the first implantation energy value to control hydrogen ion implantation into the polysilicon active layer, so that the hydrogen ion forms boron with the boron ion- Hydrogen complex.
其中，在所述步骤S16中进一步包括：Wherein, in the step S16, the method further includes:
对所述多晶硅有源层的源极掺杂区、漏极掺杂区与所述沟道区之间进行离子掺杂，分别形成一个掺杂缓冲区。Ion doping is performed between the source doped region, the drain doped region and the channel region of the polysilicon active layer to form a doping buffer.
相应地，本发明实施例的另一方面还提供一种多晶硅TFT基板，其通过前述方法制成，所述多晶硅TFT基板包括：Correspondingly, another aspect of the embodiments of the present invention further provides a polysilicon TFT substrate, which is fabricated by the foregoing method, and the polysilicon TFT substrate includes:
衬底基板；Substrate substrate;
多晶硅有源层，其通过在所衬底基板上沉积非晶硅膜层，并进行准分子激光退火所形成；所述多晶硅有源层包括位于中间的沟道掺杂区、位于沟道掺杂区两侧的源漏掺杂区，其中，在沟道掺杂区中采用离子注入机注入有氢离子；a polysilicon active layer formed by depositing an amorphous silicon film layer on the substrate and performing excimer laser annealing; the polysilicon active layer includes a channel doped region in the middle, and is doped in the channel a source-drain doping region on both sides of the region, wherein an ion implanter is used to implant hydrogen ions in the channel doping region;
栅极绝缘层，沉积形成于所述多晶硅有源层上；a gate insulating layer deposited on the polysilicon active layer;
栅极层，沉积形成于所述栅极绝缘层上；a gate layer formed on the gate insulating layer;
层间绝缘层，沉积形成于所述栅极层上，在所述层间绝缘层上正对所述源极掺杂区以及漏极掺杂区的位置形成有第一过孔以及第二过孔，在所述第一过孔和第二过孔中分别沉积形成有源电极膜层和漏电极膜层，所述源电极膜层通过所述第一过孔与所述多晶硅有源层的源极掺杂区电连接，所述漏电极膜层通过所述第二过孔与所述多晶硅有源层的漏极掺杂区电连接。An interlayer insulating layer is deposited on the gate layer, and a first via and a second via are formed on the interlayer insulating layer at positions adjacent to the source doping region and the drain doping region Forming, in the first via and the second via, an active electrode film layer and a drain electrode film layer, wherein the source electrode film layer passes through the first via hole and the polysilicon active layer The source doped regions are electrically connected, and the drain electrode film layer is electrically connected to the drain doping region of the polysilicon active layer through the second via.
其中，进一步包括：Among them, further includes:
平坦层，设置于所述层间绝缘层上，在所述平坦层上正对所述漏电极膜层的位置形成有第三过孔；a flat layer disposed on the interlayer insulating layer, wherein a third via hole is formed on the flat layer facing the drain electrode film layer;
像素电极层，设置于所述平坦层上，所述像素电极层延伸至所述第三过孔中，并与所述漏电极膜层电连接。a pixel electrode layer is disposed on the flat layer, and the pixel electrode layer extends into the third via hole and is electrically connected to the drain electrode film layer.
其中，在所述多晶硅有源层的源极掺杂区、漏极掺杂区与所述沟道区之间通过离子掺杂分别形成有一个掺杂缓冲区。Wherein, a doping buffer is formed by ion doping between the source doping region, the drain doping region and the channel region of the polysilicon active layer.
实施本发明实施例，具有如下有益效果：Embodiments of the present invention have the following beneficial effects:
在本发明的实施例中，由于将补氢的过程设置于栅极层(M1)制程之前，从而在栅极层(M1)制程之前即完成了补氢操作，可以实现对沟道补充足够的氢离子，同时，通过控制注入能量值的大小，可以使使氢离子的靶向深度和浓度与硼离子的靶向深度和浓度分布相重合，以形成硼-氢复合体，从而提高沟道中的电子的迁移率；In the embodiment of the present invention, since the hydrogen replenishing process is set before the gate layer (M1) process, the hydrogen replenishing operation is completed before the gate layer (M1) process, and sufficient channel filling can be achieved. Hydrogen ions, at the same time, by controlling the value of the injected energy, the target depth and concentration of the hydrogen ions can be coincident with the target depth and concentration distribution of the boron ions to form a boron-hydrogen complex, thereby improving the channel. Electronic mobility;
另外，由于本发明中氢离子的来源不再依赖于层间绝缘层(ILD)，故无需在ILD成膜后进行高温退火，可避免ILD破洞，改善薄膜晶体管性能，并提高产品良率；In addition, since the source of the hydrogen ions in the present invention is no longer dependent on the interlayer insulating layer (ILD), high temperature annealing is not required after the ILD film formation, the ILD is prevented from being broken, the performance of the thin film transistor is improved, and the product yield is improved;
再者，本发明实施例中，以离子注入的方式进行补氢操作，可精确控制氢原子补入的深度及浓度，工艺非常简单可行。Furthermore, in the embodiment of the present invention, the hydrogen-filling operation is performed by means of ion implantation, and the depth and concentration of hydrogen atom filling can be precisely controlled, and the process is very simple and feasible.
附图说明DRAWINGS
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.
图1是现有技术中热扩散补氢的浓度与深度对应关系示意图；1 is a schematic diagram showing the relationship between the concentration and depth of thermal diffusion hydrogen in the prior art;
图2是现有技术的一个例子中通过离子注入方式在硅中注入硼离子获得的离子浓度与深度的关系示意图；2 is a schematic diagram showing the relationship between ion concentration and depth obtained by implanting boron ions into silicon by ion implantation in an example of the prior art;
图3是本发明提供的一种多晶硅TFT基板的制作方法的一个实施例的主流程示意图；3 is a schematic diagram of a main flow of an embodiment of a method for fabricating a polysilicon TFT substrate provided by the present invention;
图4示出了一个实施例中模拟将硼离子注入晶体硅中的能量与靶向深度的关系示意图；4 is a schematic diagram showing the relationship between the energy of injecting boron ions into crystalline silicon and the depth of interest in one embodiment;
图5示出了一个实施例中模拟将氢离子注入晶体硅中的能量与靶向深度的关系示意图；Figure 5 is a schematic diagram showing the relationship between the energy of injecting hydrogen ions into crystalline silicon and the depth of interest in one embodiment;
图6示出了一个实施例中模拟将氢离子注入氧化硅(SiOx)中的能量与靶向深度的关系示意图；Figure 6 is a graph showing the relationship between the energy of injecting hydrogen ions into silicon oxide (SiOx) and the depth of interest in one embodiment;
图7示出了一个实施例中模拟以8Kev能量将1E4个氢离子注入1300ASiO+500A Si中获得的离子浓度与深度关系示意图；7 is a schematic diagram showing the relationship between ion concentration and depth obtained by injecting 1E4 hydrogen ions into 1300ASiO+500A Si with 8Kev energy in one embodiment;
图8是本发明提供的一种多晶硅TFT基板的一个实施例的结构示意图。FIG. 8 is a schematic structural view of an embodiment of a polysilicon TFT substrate provided by the present invention.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚完整地描述，显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省 略了与本发明关系不大的其他细节。In this context, it is also to be noted that in order to avoid obscuring the invention by unnecessary detail, only the structures and/or processing steps closely related to the solution according to the invention are shown in the drawings, and the Other details that are not relevant to the present invention.
如图3所示，示出了图2是本发明提供的一种多晶硅TFT基板的制作方法的一个实施例的主流程示意图；在该实施例中，该方法至少包括下述步骤：As shown in FIG. 3, FIG. 2 is a schematic diagram of a main flow of an embodiment of a method for fabricating a polysilicon TFT substrate provided by the present invention; in this embodiment, the method includes at least the following steps:
步骤S10，在衬底基板上采用增强化学气相沉积方法制作非晶硅膜层，可以理解的是，所述衬底基板可以是玻璃基板或柔性PI(聚酰亚胺树脂)基板。In step S10, an amorphous silicon film layer is formed on the base substrate by an enhanced chemical vapor deposition method. It can be understood that the base substrate may be a glass substrate or a flexible PI (polyimide resin) substrate.
步骤S11，对所述非晶硅膜层进行准分子激光退火，形成多晶硅有源层。In step S11, the amorphous silicon film layer is subjected to excimer laser annealing to form a polysilicon active layer.
步骤S12，进行所述多晶硅有源层的沟道区域离子掺杂，形成沟道掺杂区；具体地，在沟道区域通过离子注入技术把少量的施主或受主杂质离子(如硼离子)注入进去，以用来调整器件阈值电压的大小；具体地，在一些例子中，该步骤S12可包括采用离子注入机控制向所述多晶硅有源层的沟道区域中注入硼离子(即硼离子材料)，形成沟道掺杂区，所述硼离子材料为B2H6或BF3等；Step S12, performing ion doping of the channel region of the polysilicon active layer to form a channel doping region; specifically, applying a small amount of donor or acceptor impurity ions (such as boron ions) in the channel region by ion implantation technique Injecting therein for adjusting the magnitude of the threshold voltage of the device; specifically, in some examples, the step S12 may include controlling the implantation of boron ions (ie, boron ions) into the channel region of the active layer of the polysilicon by using an ion implanter. Material), forming a channel doping region, the boron ion material is B2H6 or BF3;
具体地，所述步骤S12在离子注入机中设置第一注入能量值(如8Kev)以及硼离子浓度值，以所述第一注入能量值控制将所述含硼离子材料以以靶向角度(90度)注入至所述多晶硅有源层的沟道区域。Specifically, the step S12 sets a first implantation energy value (such as 8Kev) and a boron ion concentration value in the ion implanter, and controls the boron-containing ion material to be targeted at the first implantation energy value ( 90 degrees) is implanted into the channel region of the polysilicon active layer.
步骤S13，在所述多晶硅有源层上沉积形成栅极绝缘层(GI)。Step S13, depositing a gate insulating layer (GI) on the polysilicon active layer.
步骤S14，采用离子注入机控制向所述有源层多晶硅的沟道区域注入氢离子；具体地，在一个例子中，所述步骤S13具体为：Step S14, using an ion implanter to control the injection of hydrogen ions into the channel region of the active layer polysilicon; specifically, in an example, the step S13 is specifically:
在离子注入机中设置第二注入能量值(如8Kev)以及氢离子浓度，以所述第一注入能量值控制将氢离子以靶向角度(90度)注入至所述多晶硅有源层的沟道区域，使所述氢离子与游离的硼离子形成硼-氢复合体。可以理解的是，通过在所述离子注入机中设置注入能量以及氢浓度，来控制向所述有源层多晶硅注入氢离子的靶向深度和浓度。所述氢离子材料可以是诸如B 2H 6、PH 3等等。 Setting a second implantation energy value (such as 8Kev) and a hydrogen ion concentration in the ion implanter, and controlling the first implantation energy value to inject hydrogen ions into the groove of the polysilicon active layer at a targeting angle (90 degrees) In the channel region, the hydrogen ions form a boron-hydrogen complex with the free boron ions. It will be appreciated that the depth of attack and concentration of hydrogen ions implanted into the active layer polysilicon is controlled by providing implant energy and hydrogen concentration in the ion implanter. The hydrogen ion material may be, for example, B 2 H 6 , PH 3 or the like.
可以理解的是，本发明的实施例中，将氢离子(H+)的注入设置在沉积形成栅极绝缘层之后，其原理说明如下：因为Si对H+的阻止能力要比Si对硼离子(B+)弱的多，理论推算若在沟道区域使用8Kev注入B+，而对H+的注入只需2Kev即可达到同样靶向深度；可以参照图4和图5所示，其 中分别示出了一个例子中模拟将硼离子注入晶体硅中的能量与靶向深度的关系示意图，以及模拟将氢离子注入晶体硅中的能量与靶向深度的关系示意图，从中可以看出，在类似的条件下，在达到相同的靶向深度，氢离子注入能量要小一些。其中，“Ion Energy”表示注入能量值，“Projected Range”表示投影射程(靶向深度)，“Longitudinal Straggling”表示纵向离散，“lateral Straggling”表示横向离散；“-dE/dx”表示入射离子受原子核和电子的阻止作用，在单位距离上的能量损失；“Target Density”表示目标密度，“Ion Range”表示离子射程。It can be understood that, in the embodiment of the present invention, the implantation of hydrogen ions (H+) is performed after deposition to form the gate insulating layer, and the principle thereof is as follows: because Si has a blocking ability against H+ than Si to boron ions (B+ ) Weakly much, theoretically, if 8Kev is used to inject B+ in the channel region, and only 2Kev for H+ can achieve the same target depth; as shown in Figure 4 and Figure 5, an example is shown respectively. A schematic diagram showing the relationship between the energy of implanting boron ions into crystalline silicon and the depth of the target, and the relationship between the energy of injecting hydrogen ions into the crystalline silicon and the depth of the target. It can be seen that under similar conditions, To achieve the same target depth, the hydrogen ion implantation energy is smaller. Among them, “Ion Energy” means injection energy value, “Projected Range” means projection range (target depth), “Longitudinal Straggling” means longitudinal dispersion, “lateral Straggling” means lateral dispersion; “-dE/dx” means incident ion The nucleus and electrons block the energy loss at unit distance; "Target Density" indicates the target density, and "Ion Range" indicates the ion range.
但是目前面板业主流的注入机为Nissin的iG6，2Kev对设备的Acc电源来说是一个容易造成电极板放电(Arcing)的工作范围。故在本发明的实施例中，将将H+注入制程放在栅绝缘层沉积制程之后，此时，对有源层进行H+注入时，需要透过栅绝缘层，故在一个实施例中，可将H+的注入能量控制在和B+的注入能量相近似，例如，在注入H+时，也可以采用8Kev的注入能量，可使B+与H+的浓度分布达到最佳重合。However, the current injection machine for panel owners is Nissin's iG6. 2Kev is a working range that is easy to cause arcing of the electrode plate for the Acc power supply of the device. Therefore, in the embodiment of the present invention, the H+ implant process is placed after the gate insulating layer deposition process. At this time, when the active layer is H+ implanted, the gate insulating layer needs to be transmitted, so in one embodiment, The injection energy of H+ is controlled to be similar to the injection energy of B+. For example, when H+ is implanted, the injection energy of 8Kev can also be used to achieve the best coincidence of the concentration distribution of B+ and H+.
步骤S15，在所述栅极绝缘层上沉积形成栅极层(M1)。Step S15, depositing a gate layer (M1) on the gate insulating layer.
步骤S16，对所述多晶硅有源层的源极区与漏极区进行离子掺杂，形成源漏掺杂区，可以理解的是，在该步骤中的离子掺杂的材料可以采用PHx材料。可以理解的是，在所述步骤S16中，进一步包括：对所述多晶硅有源层的源极区、漏极区与所述沟道区之间进行离子掺杂，分别形成一个掺杂缓冲区，可以理解的是，形成掺杂缓冲区的材料也可以采用PHx材料，只不过形成掺杂缓冲区所采用的材料剂量要比形成源漏掺杂区所采用的剂量小，且该掺杂缓冲区主要集中在靠近沟道区的一侧。In step S16, the source region and the drain region of the polysilicon active layer are ion doped to form a source/drain doping region. It is understood that the ion doped material in this step may be a PHx material. It is to be understood that, in the step S16, the method further comprises: performing ion doping between the source region, the drain region and the channel region of the polysilicon active layer to form a doping buffer respectively. It can be understood that the material forming the doping buffer can also be made of PHx material, except that the dose of the material used to form the doping buffer is smaller than the dose used to form the source and drain doping regions, and the doping buffer is used. The zone is mainly concentrated on the side close to the channel zone.
步骤S17，在所述栅极层上沉积形成层间绝缘层(ILD)。Step S17, depositing an interlayer insulating layer (ILD) on the gate layer.
步骤S18，在所述层间绝缘层上正对所述源极区以及漏极掺杂区的位置形成第一过孔以及第二过孔，在所述第一过孔和第二过孔中分别沉积形成源电极膜层和漏电极膜层(M2)，使所述源电极膜层通过所述第一过孔与所述多晶硅有源层的源极区电连接，使所述漏电极膜层通过所述第二过孔与所述多晶硅有源层的漏极掺杂区电连接。Step S18, forming a first via hole and a second via hole in a position facing the source region and the drain doping region on the interlayer insulating layer, in the first via hole and the second via hole Depositing a source electrode film layer and a drain electrode film layer (M2), respectively, and electrically connecting the source electrode film layer to the source region of the polysilicon active layer through the first via hole to make the drain electrode film The layer is electrically connected to the drain doping region of the polysilicon active layer through the second via.
步骤S19，在所述层间绝缘层上形成平坦层，在所述平坦层上正对所述 漏电极膜层的位置形成第三过孔；Step S19, forming a flat layer on the interlayer insulating layer, and forming a third via hole on the flat layer facing the position of the drain electrode film layer;
步骤S190，在所述平坦层上形成像素电极层，使所述像素电极层延伸至所述第三过孔中，并与所述漏电极膜层电连接。Step S190, forming a pixel electrode layer on the flat layer, extending the pixel electrode layer into the third via hole, and electrically connecting the drain electrode film layer.
如图6所示，示出了一个实施例中模拟将氢离子注入氧化硅(SiOx)中的能量与靶向深度的关系示意图，从中可以看出，其中的关系与图5示出的关系图非常近似。As shown in FIG. 6, a schematic diagram showing the relationship between the energy of injecting hydrogen ions into silicon oxide (SiOx) and the depth of penetration in one embodiment is shown, from which it can be seen that the relationship is shown in FIG. Very similar.
如图7所示，示出了一个实施例中模拟以8Kev能量将1E4个氢离子注入1300A SiO2+500A Si中得到的离子浓度与深度关系示意图；从中可以看出，通过该离子注入在离子射程(Ion Range)上氢离子具有最高浓度。且由于氢离子注入后的浓度分布与沟道中硼离子的分布情况类似(可以与图2进行对比)，故通过该注入方法可以使氢原子补入浓度及剂量实现可监控化，并做到补氢作用最大化。其中，“Ion Range”表示离子射程，“Straggle”表示离散，“Skewness”表求偏度，“Kurtosis”表示峰度，横坐标表示注入深度(Target Depth)，纵坐标表示氢离子浓度。As shown in FIG. 7, a schematic diagram showing the relationship between the ion concentration and the depth obtained by injecting 1E4 hydrogen ions into 1300A SiO2+500A Si at 8Kev energy is shown in FIG. 7; it can be seen that the ion implantation is in the ion range. The hydrogen ion has the highest concentration (Ion Range). And because the concentration distribution after hydrogen ion implantation is similar to the distribution of boron ions in the channel (can be compared with FIG. 2), the hydrogen atom can be monitored and the dose can be monitored by the injection method. Maximize the action of hydrogen. Among them, "Ion Range" indicates ion range, "Straggle" indicates discrete, "Skewness" indicates skewness, "Kurtosis" indicates kurtosis, abscissa indicates injection depth (Target Depth), and ordinate indicates hydrogen ion concentration.
如图8所示，示出了本发明提供的一种多晶硅TFT基板的一个实施例的结构示意图。在该实施例中，该多晶硅TFT基板是通过前面描述的方法所制成，具体地，所述多晶硅TFT基板10包括：As shown in FIG. 8, a schematic structural view of an embodiment of a polysilicon TFT substrate provided by the present invention is shown. In this embodiment, the polysilicon TFT substrate is formed by the method described above. Specifically, the polysilicon TFT substrate 10 includes:
衬底基板10，其可以是玻璃基板或柔性PI(聚酰亚胺树脂)基板；a base substrate 10, which may be a glass substrate or a flexible PI (polyimide resin) substrate;
多晶硅有源层13，其通过在所衬底基板10上沉积非晶硅膜层，并进行准分子激光退火所形成；所述多晶硅有源层13包括位于中间的沟道掺杂区130、位于沟道掺杂区130两侧的源极掺杂区131和漏极掺杂区132，其中，在沟道掺杂区中采用离子注入机注入有氢离子；在所述多晶硅有源层的源极掺杂区131、漏极掺杂区132与所述沟道掺杂区130之间通过离子掺杂分别形成有一个掺杂缓冲区133；a polysilicon active layer 13 formed by depositing an amorphous silicon film layer on the substrate 10 and performing excimer laser annealing; the polysilicon active layer 13 includes a channel doping region 130 located in the middle a source doping region 131 and a drain doping region 132 on both sides of the channel doping region 130, wherein an ion implanter is used to implant hydrogen ions in the channel doping region; a source of the polysilicon active layer a doping buffer 133 is formed between the electrode doped region 131, the drain doping region 132 and the channel doping region 130 by ion doping;
栅极绝缘层14，沉积形成于所述多晶硅有源层13上；a gate insulating layer 14 is deposited on the polysilicon active layer 13;
栅极层15，沉积形成于所述栅极绝缘层14上；a gate layer 15, deposited on the gate insulating layer 14;
层间绝缘层16，沉积形成于所述栅极层15上，在所述层间绝缘层16上正对所述源极掺杂区131以及漏极掺杂区132的位置形成有第一过孔160以及第二过孔161，在所述第一过孔160和第二过孔161中分别沉积形成有 源电极膜层162和漏电极膜层163，所述源电极膜层162通过所述第一过孔160与所述多晶硅有源层的源极掺杂区131电连接，所述漏电极膜层163通过所述第二过孔161与所述多晶硅有源层的漏极掺杂区132电连接；An interlayer insulating layer 16 is deposited on the gate layer 15 and a first surface is formed on the interlayer insulating layer 16 opposite to the source doping region 131 and the drain doping region 132. The hole 160 and the second via 161 are respectively deposited in the first via 160 and the second via 161 to form an active electrode film layer 162 and a drain electrode film layer 163, and the source electrode film layer 162 passes through the The first via 160 is electrically connected to the source doping region 131 of the polysilicon active layer, and the drain electrode film layer 163 passes through the second via 161 and the drain doping region of the polysilicon active layer 132 electrical connection;
平坦层17，设置于所述层间绝缘层16上，在所述平坦层17上正对所述漏电极膜层163的位置形成有第三过孔171；The flat layer 17 is disposed on the interlayer insulating layer 16, and a third via hole 171 is formed on the flat layer 17 at a position facing the drain electrode film layer 163;
像素电极层18，设置于所述平坦层17上，所述像素电极层18延伸至所述第三过孔171中，并与所述漏电极膜层163电连接。The pixel electrode layer 18 is disposed on the flat layer 17, and the pixel electrode layer 18 extends into the third via hole 171 and is electrically connected to the drain electrode film layer 163.
进一步地，在所述衬底基板10与所述多晶硅有源层13之间还可以设置缓冲层12。可以理解的是，在一个例子中，其中，缓冲层12、栅极绝缘层14、层间绝缘层16均可以采用SiNx/SiO2材料，而平坦层17可以采用SiNx或有机膜材料，像素电极层18可以采用金属氧化物材料(如ITO)，而源电极膜层162和漏电极膜层163均可以采用金属材料，如金属钛，或铝钛合金等。Further, a buffer layer 12 may be further disposed between the base substrate 10 and the polysilicon active layer 13. It can be understood that, in one example, the buffer layer 12, the gate insulating layer 14, and the interlayer insulating layer 16 may each be a SiNx/SiO2 material, and the flat layer 17 may be a SiNx or organic film material, and the pixel electrode layer. A metal oxide material (such as ITO) may be used, and the source electrode film layer 162 and the drain electrode film layer 163 may each be made of a metal material such as titanium metal or aluminum titanium alloy.
实施本发明实施例，具有如下有益效果：Embodiments of the present invention have the following beneficial effects:
在本发明的实施例中，由于将补氢的过程设置于栅极层(M1)制程之前，从而在栅极层(M1)制程之前即完成了补氢操作，可以实现对沟道补充足够的氢离子，同时，通过控制注入能量值的大小，可以使使氢离子的靶向深度和浓度与硼离子的靶向深度和浓度分布相重合，以形成硼-氢复合体，从而提高沟道中的电子的迁移率；In the embodiment of the present invention, since the hydrogen replenishing process is set before the gate layer (M1) process, the hydrogen replenishing operation is completed before the gate layer (M1) process, and sufficient channel filling can be achieved. Hydrogen ions, at the same time, by controlling the value of the injected energy, the target depth and concentration of the hydrogen ions can be coincident with the target depth and concentration distribution of the boron ions to form a boron-hydrogen complex, thereby improving the channel. Electronic mobility;
同时，本发明中，将补氢操作设置于在准分子激光退火(ELA)制程之后，可以避免现有技术中由于氢爆带来的晶化不良等现象；In the meantime, in the present invention, after the hydrogen-donating operation is set in the excimer laser annealing (ELA) process, the phenomenon of poor crystallization due to hydrogen explosion in the prior art can be avoided;
再者，本发明实施例中，以离子注入的方式进行补氢操作，可精确控制氢原子补入的深度及浓度，工艺非常简单可行。Furthermore, in the embodiment of the present invention, the hydrogen-filling operation is performed by means of ion implantation, and the depth and concentration of hydrogen atom filling can be precisely controlled, and the process is very simple and feasible.
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固 有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。It should be noted that, in this context, relational terms such as first and second are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply such entities or operations. There is any such actual relationship or order between them. Furthermore, the term "comprises" or "comprises" or "comprises" or any other variations thereof is intended to encompass a non-exclusive inclusion, such that a process, method, article, or device that comprises a plurality of elements includes not only those elements but also Other elements, or elements that are inherent to such a process, method, item, or device. An element that is defined by the phrase "comprising a ..." does not exclude the presence of additional equivalent elements in the process, method, item, or device that comprises the element.
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。The above description is only a specific embodiment of the present application, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present application. It should be considered as the scope of protection of this application.

Claims (14)

  1. 一种多晶硅TFT基板的制作方法，其中，包括下述步骤：A method for fabricating a polysilicon TFT substrate, comprising the steps of:
    步骤S10，在衬底基板上沉积非晶硅膜层；Step S10, depositing an amorphous silicon film layer on the substrate;
    步骤S11，对所述非晶硅膜层进行准分子激光退火，形成多晶硅有源层；Step S11, performing an excimer laser annealing on the amorphous silicon film layer to form a polysilicon active layer;
    步骤S12，对所述多晶硅有源层的沟道区域进行离子掺杂，形成沟道掺杂区；Step S12, ion doping the channel region of the polysilicon active layer to form a channel doping region;
    步骤S13，在所述多晶硅有源层上沉积形成栅极绝缘层；Step S13, depositing a gate insulating layer on the polysilicon active layer;
    步骤S14，采用离子注入机控制向所述有源层多晶硅的沟道区域注入氢离子；Step S14, using an ion implanter to control the injection of hydrogen ions into the channel region of the active layer polysilicon;
    步骤S15，在所述栅极绝缘层上沉积形成栅极层；Step S15, depositing a gate layer on the gate insulating layer;
    步骤S16，对所述多晶硅有源层的源极区与漏极区进行离子掺杂，形成源极掺杂区和漏极掺杂区；Step S16, performing ion doping on the source region and the drain region of the polysilicon active layer to form a source doped region and a drain doped region;
    步骤S17，在所述栅极层上沉积形成层间绝缘层；Step S17, depositing an interlayer insulating layer on the gate layer;
    步骤S18，在所述层间绝缘层上正对所述源极掺杂区以及漏极掺杂区的位置形成第一过孔以及第二过孔，在所述第一过孔和第二过孔中分别沉积形成源电极膜层和漏电极膜层，使所述源电极膜层通过所述第一过孔与所述多晶硅有源层的源极掺杂区电连接，使所述漏电极膜层通过所述第二过孔与所述多晶硅有源层的漏极掺杂区电连接。Step S18, forming a first via hole and a second via hole on the interlayer insulating layer facing the source doping region and the drain doping region, where the first via hole and the second via hole Forming a source electrode film layer and a drain electrode film layer respectively in the holes, and electrically connecting the source electrode film layer to the source doping region of the polysilicon active layer through the first via hole, so that the drain electrode The film layer is electrically connected to the drain doping region of the polysilicon active layer through the second via.
  2. 如权利要求1所述的方法，其中，所述步骤S12进一步包括：The method of claim 1 wherein said step S12 further comprises:
    采用离子注入机控制向所述多晶硅有源层中注入硼离子，形成沟道掺杂区，所述硼离子材料为B2H6或BF3。Boron ions are implanted into the polysilicon active layer by an ion implanter to form a channel doped region, and the boron ion material is B2H6 or BF3.
  3. 如权利要求2所述的方法，其中，所述步骤S12具体包括：The method of claim 2, wherein the step S12 comprises:
    在离子注入机中设置第一注入能量值、第一注入角度以及硼离子浓度值，以所述第一注入能量值控制将所述含硼离子材料以所述第一注入角度注入至所述多晶硅有源层的沟道区域。Setting a first implantation energy value, a first implantation angle, and a boron ion concentration value in the ion implanter, and controlling, by the first implantation energy value, injecting the boron-containing ion material into the polysilicon at the first injection angle The channel region of the active layer.
  4. 如权利要求3所述的方法，其中，所述步骤S13具体为：The method of claim 3, wherein the step S13 is specifically:
    在离子注入机中设置第二注入能量值以及氢离子浓度，以所述第一注入能量值控制将氢离子注入至所述多晶硅有源层，使所述氢离子与所述硼离子形成硼-氢复合体。Setting a second implantation energy value and a hydrogen ion concentration in the ion implanter, and controlling the first implantation energy value to control hydrogen ion implantation into the polysilicon active layer, so that the hydrogen ion forms boron with the boron ion- Hydrogen complex.
  5. 如权利要求4所述的方法，其中，进一步包括：The method of claim 4, further comprising:
    步骤S19，在所述层间绝缘层上形成平坦层，在所述平坦层上正对所述漏电极膜层的位置形成第三过孔；Step S19, forming a flat layer on the interlayer insulating layer, and forming a third via hole on the flat layer facing the position of the drain electrode film layer;
    步骤S190，在所述平坦层上形成像素电极层，使所述像素电极层延伸至所述第三过孔中，并与所述漏电极膜层电连接。Step S190, forming a pixel electrode layer on the flat layer, extending the pixel electrode layer into the third via hole, and electrically connecting the drain electrode film layer.
  6. 如权利要求5所述的方法，其中，在所述步骤S16中进一步包括：The method of claim 5, wherein the step S16 further comprises:
    对所述多晶硅有源层的源极掺杂区、漏极掺杂区与所述沟道区之间进行离子掺杂，分别形成一个掺杂缓冲区。Ion doping is performed between the source doped region, the drain doped region and the channel region of the polysilicon active layer to form a doping buffer.
  7. 一种多晶硅TFT基板的制作方法，其中，包括下述步骤：A method for fabricating a polysilicon TFT substrate, comprising the steps of:
    步骤S10，在衬底基板上沉积非晶硅膜层；Step S10, depositing an amorphous silicon film layer on the substrate;
    步骤S11，对所述非晶硅膜层进行准分子激光退火，形成多晶硅有源层；Step S11, performing an excimer laser annealing on the amorphous silicon film layer to form a polysilicon active layer;
    步骤S12，对所述多晶硅有源层的沟道区域进行离子掺杂，形成沟道掺杂区；Step S12, ion doping the channel region of the polysilicon active layer to form a channel doping region;
    步骤S13，在所述多晶硅有源层上沉积形成栅极绝缘层；Step S13, depositing a gate insulating layer on the polysilicon active layer;
    步骤S14，采用离子注入机控制向所述有源层多晶硅的沟道区域注入氢离子；Step S14, using an ion implanter to control the injection of hydrogen ions into the channel region of the active layer polysilicon;
    步骤S15，在所述栅极绝缘层上沉积形成栅极层；Step S15, depositing a gate layer on the gate insulating layer;
    步骤S16，对所述多晶硅有源层的源极区与漏极区进行离子掺杂，形成源极掺杂区和漏极掺杂区；Step S16, performing ion doping on the source region and the drain region of the polysilicon active layer to form a source doped region and a drain doped region;
    步骤S17，在所述栅极层上沉积形成层间绝缘层；Step S17, depositing an interlayer insulating layer on the gate layer;
    步骤S18，在所述层间绝缘层上正对所述源极掺杂区以及漏极掺杂区的位置形成第一过孔以及第二过孔，在所述第一过孔和第二过孔中分别沉积形成源电极膜层和漏电极膜层，使所述源电极膜层通过所述第一过孔与所述多 晶硅有源层的源极掺杂区电连接，使所述漏电极膜层通过所述第二过孔与所述多晶硅有源层的漏极掺杂区电连接；Step S18, forming a first via hole and a second via hole on the interlayer insulating layer facing the source doping region and the drain doping region, where the first via hole and the second via hole Forming a source electrode film layer and a drain electrode film layer respectively in the holes, and electrically connecting the source electrode film layer to the source doping region of the polysilicon active layer through the first via hole, so that the drain electrode The film layer is electrically connected to the drain doping region of the polysilicon active layer through the second via hole;
    步骤S19，在所述层间绝缘层上形成平坦层，在所述平坦层上正对所述漏电极膜层的位置形成第三过孔；Step S19, forming a flat layer on the interlayer insulating layer, and forming a third via hole on the flat layer facing the position of the drain electrode film layer;
    步骤S190，在所述平坦层上形成像素电极层，使所述像素电极层延伸至所述第三过孔中，并与所述漏电极膜层电连接。Step S190, forming a pixel electrode layer on the flat layer, extending the pixel electrode layer into the third via hole, and electrically connecting the drain electrode film layer.
  8. 如权利要求7所述的方法，其中，所述步骤S12进一步包括：The method of claim 7 wherein said step S12 further comprises:
    采用离子注入机控制向所述多晶硅有源层中注入硼离子，形成沟道掺杂区，所述硼离子材料为B2H6或BF3。Boron ions are implanted into the polysilicon active layer by an ion implanter to form a channel doped region, and the boron ion material is B2H6 or BF3.
  9. 如权利要求8所述的方法，其中，所述步骤S12具体包括：The method of claim 8 wherein said step S12 comprises:
    在离子注入机中设置第一注入能量值、第一注入角度以及硼离子浓度值，以所述第一注入能量值控制将所述含硼离子材料以所述第一注入角度注入至所述多晶硅有源层的沟道区域。Setting a first implantation energy value, a first implantation angle, and a boron ion concentration value in the ion implanter, and controlling, by the first implantation energy value, injecting the boron-containing ion material into the polysilicon at the first injection angle The channel region of the active layer.
  10. 如权利要求7所述的方法，其中，所述步骤S13具体为：The method of claim 7, wherein the step S13 is specifically:
    在离子注入机中设置第二注入能量值以及氢离子浓度，以所述第一注入能量值控制将氢离子注入至所述多晶硅有源层，使所述氢离子与所述硼离子形成硼-氢复合体。Setting a second implantation energy value and a hydrogen ion concentration in the ion implanter, and controlling the first implantation energy value to control hydrogen ion implantation into the polysilicon active layer, so that the hydrogen ion forms boron with the boron ion- Hydrogen complex.
  11. 如权利要求9所述的方法，其中，在所述步骤S16中进一步包括：The method of claim 9, further comprising in the step S16:
    对所述多晶硅有源层的源极掺杂区、漏极掺杂区与所述沟道区之间进行离子掺杂，分别形成一个掺杂缓冲区。Ion doping is performed between the source doped region, the drain doped region and the channel region of the polysilicon active layer to form a doping buffer.
  12. 一种多晶硅TFT基板，其中，所述多晶硅TFT基板包括：A polysilicon TFT substrate, wherein the polysilicon TFT substrate comprises:
    衬底基板；Substrate substrate;
    多晶硅有源层，其通过在所衬底基板上沉积非晶硅膜层，并进行准分子激光退火所形成；所述多晶硅有源层包括位于中间的沟道掺杂区、位于沟道 掺杂区两侧的源漏掺杂区，其中，在沟道掺杂区中采用离子注入机注入有氢离子；a polysilicon active layer formed by depositing an amorphous silicon film layer on the substrate and performing excimer laser annealing; the polysilicon active layer includes a channel doped region in the middle, and is doped in the channel a source-drain doping region on both sides of the region, wherein an ion implanter is used to implant hydrogen ions in the channel doping region;
    栅极绝缘层，沉积形成于所述多晶硅有源层上；a gate insulating layer deposited on the polysilicon active layer;
    栅极层，沉积形成于所述栅极绝缘层上；a gate layer formed on the gate insulating layer;
    层间绝缘层，沉积形成于所述栅极层上，在所述层间绝缘层上正对所述源极掺杂区以及漏极掺杂区的位置形成有第一过孔以及第二过孔，在所述第一过孔和第二过孔中分别沉积形成有源电极膜层和漏电极膜层，所述源电极膜层通过所述第一过孔与所述多晶硅有源层的源极掺杂区电连接，所述漏电极膜层通过所述第二过孔与所述多晶硅有源层的漏极掺杂区电连接。An interlayer insulating layer is deposited on the gate layer, and a first via and a second via are formed on the interlayer insulating layer at positions adjacent to the source doping region and the drain doping region Forming, in the first via and the second via, an active electrode film layer and a drain electrode film layer, wherein the source electrode film layer passes through the first via hole and the polysilicon active layer The source doped regions are electrically connected, and the drain electrode film layer is electrically connected to the drain doping region of the polysilicon active layer through the second via.
  13. 如权利要求12所述的多晶硅TFT基板，其中，进一步包括：The polysilicon TFT substrate of claim 12, further comprising:
    平坦层，设置于所述层间绝缘层上，在所述平坦层上正对所述漏电极膜层的位置形成有第三过孔；a flat layer disposed on the interlayer insulating layer, wherein a third via hole is formed on the flat layer facing the drain electrode film layer;
    像素电极层，设置于所述平坦层上，所述像素电极层延伸至所述第三过孔中，并与所述漏电极膜层电连接。a pixel electrode layer is disposed on the flat layer, and the pixel electrode layer extends into the third via hole and is electrically connected to the drain electrode film layer.
  14. 如权利要求13所述的多晶硅TFT基板，其中，在所述多晶硅有源层的源极掺杂区、漏极掺杂区与所述沟道区之间通过离子掺杂分别形成有一个掺杂缓冲区。The polysilicon TFT substrate according to claim 13, wherein a doping is formed by ion doping between the source doping region, the drain doping region and the channel region of the polysilicon active layer Buffer.
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