WO2019100693A1 - 控制se的系统、方法及芯片 - Google Patents

控制se的系统、方法及芯片 Download PDF

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Publication number
WO2019100693A1
WO2019100693A1 PCT/CN2018/090424 CN2018090424W WO2019100693A1 WO 2019100693 A1 WO2019100693 A1 WO 2019100693A1 CN 2018090424 W CN2018090424 W CN 2018090424W WO 2019100693 A1 WO2019100693 A1 WO 2019100693A1
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WO
WIPO (PCT)
Prior art keywords
power
processor
component
signal
shutdown
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PCT/CN2018/090424
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English (en)
French (fr)
Inventor
陈迎国
潘时林
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华为技术有限公司
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Publication of WO2019100693A1 publication Critical patent/WO2019100693A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/81—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07G—REGISTERING THE RECEIPT OF CASH, VALUABLES, OR TOKENS
    • G07G1/00—Cash registers
    • G07G1/12—Cash registers electronically operated
    • G07G1/14—Systems including one or more distant stations co-operating with a central processing unit

Definitions

  • the embodiments of the present invention relate to the field of chip technologies, and in particular, to a system, method, and chip for controlling a secure element (SE).
  • SE secure element
  • the SE is an encryption and decryption logic circuit independent of the main processor in the system, and includes a processor dedicated to security processing and various hardware circuits for encrypting and decrypting data exchanged between devices during data interaction. To improve the security of your data.
  • SE can be used to implement various types of security processing including mobile payment, bus card swipe or access card swiping.
  • the built-in SE solution refers to integrating the SE on the AP chip of the mobile terminal, that is, the SE is a part of the AP chip.
  • PMU power management unit
  • the PMU supplies power to the AP chip, the AP chip is in the power-on state, and the SE is also in the power-on state; when the mobile terminal is in the power-off state, the PMU stops supplying power to the AP chip, and the AP chip is in the power-off state, and the SE is also in the power-off state. It is in a power off state.
  • the embodiment of the present application provides a system, a method, and a chip for controlling the SE.
  • the SE is used for security processing.
  • an embodiment of the present application provides a system for controlling an SE, including an SE, a processor, a power-on component, a power management unit PMU, and a communication unit.
  • the SE, the processor, and the power-on component are located within the first semiconductor chip.
  • at least one of the PMU and the communication unit is located within the first semiconductor chip.
  • the PMU and the communication unit are located in other identical or different semiconductor chips than the first semiconductor chip.
  • the communication unit is configured to receive the communication signal that meets the preset condition, and output the first power-on signal to the power-on component according to the communication signal.
  • the power-on component is configured to acquire a first power-on signal from the communication unit and trigger the processor to be powered on.
  • the processor is configured to switch from the first power-off state to the first power-on state, and obtain the SE power-on indication information from the power-on component, and control the SE power-on according to the SE power-on indication information.
  • the SE is configured to switch from the second power-off state to the second power-on state under the control of the processor, interact with the communication unit to securely communicate data, and perform secure processing on the secure communication data.
  • PMU for powering the processor, SE, power-up components, and communication units.
  • the solution for the built-in SE outputs the first power-on signal to the upper power module when the communication unit detects the communication signal that meets the preset condition, thereby triggering the processor to be powered on, so as to be processed and processed.
  • the SE integrated on the same chip is powered on, and then communicates with the communication unit to securely communicate data and securely process the data. After the processor is powered off, the SE can be powered on for security processing, and the power consumption is saved as much as possible. The following does not affect the use of security features.
  • the power-on component is specifically configured to output a second power-on signal to the PMU in the aspect that the power-on component is used to trigger the processor to be powered on.
  • the PMU is configured to acquire a second power-on signal from the power-on component and supply power to the processor according to the second power-on signal.
  • the power-on component can be powered by the PMU trigger processor.
  • the processor is specifically configured to send a third power-on signal to the PMU in terms of the processor for controlling the power-on of the SE.
  • the PMU is configured to receive a third power-on signal from the processor and supply power to the SE according to the third power-on signal.
  • the processor is enabled to control the SE to power up.
  • the PMU is further configured to send a first shutdown signal to the processor when it is detected that the battery power is less than the first predetermined threshold.
  • the processor is further configured to receive a first shutdown signal from the PMU, and perform a first shutdown operation according to the first shutdown signal, where the first shutdown operation includes: controlling the processor and the SE to power off.
  • control processor and the SE are powered off by the first shutdown operation, so that the mobile terminal triggers the SE to be powered on for security processing by the power-off component that is not powered off.
  • the PMU is further configured to output a fourth power-on signal to the power-on component when the battery power is less than the second preset threshold, where the second preset threshold is less than the first preset threshold.
  • the power-on component is further configured to acquire a fourth power-on signal from the PMU and trigger the processor to be powered on.
  • the processor is further configured to switch from the first power-off state to the first power-on state triggered by the power-on component, and obtain the shutdown indication information from the power-on component, and perform the second shutdown operation according to the shutdown indication information, and the second shutdown The operation includes: controlling the processor, the SE, and the power-on component to be powered off.
  • the battery power is detected by the PMU.
  • the PMU When the battery power is lower than the second preset threshold, the PMU outputs a fourth power-on signal to the power module, so that the power-on component triggers the processor to be powered on, and is executed by the processor.
  • the second shutdown operation causes the mobile terminal to enter a normal shutdown state. In the above manner, the mobile terminal is prevented from consuming the power in the first shutdown state, so that a part of the power is reserved for subsequent use (such as making an emergency call, starting a shutdown alarm, etc.).
  • the power-on component is further configured to: start a timer after the processor performs the first shutdown operation; and trigger the processor to power up when the timer expires.
  • the processor is further configured to switch from the first power-off state to the first power-on state triggered by the power-on component, and obtain the shutdown indication information from the power-on component, and perform the second shutdown operation according to the shutdown indication information, and the second shutdown The operation includes: controlling the processor, the SE, and the power-on component to be powered off.
  • the power-on component controls the processor to be powered on, and the second shutdown operation is performed by the processor, so that the mobile terminal enters a normal shutdown state.
  • the length of time that the mobile terminal enters the first power-off state can be set according to the user's requirement, and the mobile terminal is prevented from remaining in the first power-off state for a long time, so that the mobile terminal consumes power in the first power-off state, so as to leave a part of power for subsequent use. (such as making an emergency call, starting a shutdown alarm, etc.).
  • the preset condition is that the communication signal includes a preset identifier, or the preset condition is that the frequency band of the communication signal is within the preset frequency band.
  • the communication unit is enabled to accurately recognize the communication signal related to the card swipe function provided by itself.
  • the processor is further configured to load the execution program of the SE from the memory outside the first semiconductor chip to the memory inside the first semiconductor chip after acquiring the SE power-on indication information from the power-on component.
  • the SE is further configured to load the execution program from the memory inside the first semiconductor chip to the memory inside the SE after the second power-off state is switched to the second power-on state under the control of the processor, and run the execution program to Realize the function of interacting with the communication unit to securely communicate data and securely process the secure communication data.
  • the execution program of the SE is stored in the memory outside the first semiconductor chip, which can save the storage space of the SE, so that the SE can be designed to be more light and thin.
  • the processor is further configured to perform a third shutdown operation after a predetermined time period after the SE is powered on; or, after the SE is powered on, start the timing clock, when receiving the reset command sent by the SE Resetting the timing clock, wherein the SE sends a reset command to the processor every time the signal from the communication unit is received, and when the timing clock times out, performing a third shutdown operation; wherein the third shutdown operation includes controlling the processor and The SE is powered down to maintain the powered component in an energized state.
  • the embodiment of the present application provides a method for controlling an SE, the method includes: the communication unit receives a communication signal that meets a preset condition, and outputs a first power-on signal to the power-on of the first semiconductor chip according to the communication signal.
  • a power-up component acquires a first power-on signal from the communication unit, and triggers a processor in the first semiconductor chip to be powered on; the processor switches from the first power-off state to the first power-on state triggered by the power-on component Obtaining SE power-on indication information from the power-on component, and controlling SE power-on in the first semiconductor chip according to the SE power-on indication information; the SE is switched from the second power-off state to the second power-on state under the control of the processor Communicate secure communication data with the communication unit and securely process the secure communication data; supply power to the processor, the SE, the power-on component, and the communication unit through the PMU.
  • an embodiment of the present application provides a chip, including an SE, a processor, and a power-on component.
  • a power-on component coupled to the communication unit and the PMU, configured to receive power from the PMU, receive a first power-on signal from the communication unit, and trigger a processor to power up
  • the processor is coupled to the power-on component, the SE, and the PMU, Receiving the power supply of the PMU and switching from the first power-off state to the first power-on state, and obtaining the SE power-on indication information from the power-on component, and controlling the SE power-on according to the SE power-on indication information
  • the SE is coupled to the communication unit, the processor, and the PMU, for receiving power of the PMU under the control of the processor, and switching from the second power-off state to the second power-on state, interacting with the communication unit to securely communicate data, and secure Communication data is processed securely.
  • the chip can also be implemented by various possible implementations or designs in the first aspect.
  • an embodiment of the present application provides a mobile terminal, where the mobile terminal includes the system for controlling an SE as described in the foregoing aspect.
  • an embodiment of the present application provides a computer program product for implementing the processor side method steps described in the above aspects when the computer program product is executed by a processor in a first semiconductor chip.
  • an embodiment of the present application provides a computer program product for implementing the method steps of the SE side described in the foregoing aspect when the computer program product is executed by an SE in a first semiconductor chip.
  • the solution for the built-in SE outputs the first power-on signal to the upper power module when the communication unit detects the communication signal that meets the preset condition, thereby triggering the processor.
  • Power-on so that the SE integrated with the processor on the same chip is powered on, and then communicates with the communication unit to securely communicate data and securely process the data, and can still trigger the SE to be powered on after the processor is powered off. It does not affect the use of security functions while minimizing power consumption.
  • FIG. 1 is a schematic diagram of an implementation environment provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a mobile terminal according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a first semiconductor chip according to an embodiment of the present application.
  • FIG. 4 is a flowchart of a method for controlling an SE provided by an embodiment of the present application.
  • FIG. 5 is a flowchart of a method for controlling an SE according to another embodiment of the present application.
  • FIG. 6 is a flowchart of entering a normal shutdown state from a first shutdown state according to an embodiment of the present application
  • FIG. 7 is a flowchart of a normal shutdown state from a first shutdown state according to another embodiment of the present application.
  • FIG. 8 is a flowchart of a method for controlling an SE according to another embodiment of the present application.
  • FIG. 1 shows a schematic diagram of an implementation environment provided by an embodiment of the present application.
  • the implementation environment includes a mobile terminal 10 and a card reading device 20.
  • the mobile terminal 10 may be a portable electronic device such as a cell phone, a tablet, a wearable device, or the like.
  • the card reading device 20 can be any electronic device having a card reading function, such as a Point Of Sales (POS) machine, a bus card reader, an access card reader, and the like.
  • POS Point Of Sales
  • the mobile terminal 10 can communicate with the card reading device 20 instead of the bank card to complete the card payment operation; when the card reading device 20 is a bus card reader, the mobile terminal 10 can communicate with the card reading device 20 instead of the bus card to complete the bus card swiping operation; when the card reading device 20 is the access card reader, the mobile terminal 10 can communicate with the card reading device 20 instead of the access card to complete the access control. Swipe operation.
  • the mobile terminal 10 and the card reading device 20 are equipped with an adapted communication unit, and the communication unit performs communication to complete the card swipe operation.
  • the card swipe operation can be completed by the short-range wireless communication technology between the mobile terminal 10 and the card reading device 20.
  • the communication unit may be a short-range communication chip, such as near field communication (Near Field Communication, NFC). )chip.
  • the communication unit can support various types of cellular communication, for example, Global System of Mobile communication (GSM) system, Code Division Multiple Access (CDMA) system, Wideband Code Division Multiple Access (Wideband Code) Division Multiple Access (WCDMA) system, General Packet Radio Service (GPRS), Long Term Evolution (LTE) system, LTE Frequency Division Duplex (FDD) system, LTE time division duplex (Time Division Duplex, TDD), Universal Mobile Telecommunication System (UMTS), and the like.
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • the mobile terminal 10 adopts a scheme of built-in SE.
  • the mobile terminal 10 includes a system for controlling an SE, and the system may include a first semiconductor chip 11, a communication unit 12, and a PMU 13.
  • a processor 11a, a power-on component 11b, and an SE 11c are integrated on the first semiconductor chip 11.
  • the processor 11a is coupled to the SE 11c and the PMU 13, respectively, and the SE 11c is coupled to the PMU 13 and the communication unit 12, respectively, and the power-on component 11b is coupled to the PMU 13 and the communication unit 12, respectively.
  • the SE 11c corresponds to performing security processing related to swiping.
  • the SE 11c corresponds to performing a security process related to the SIM of the cellular communication, such as a virtual SIM function or a SIM card security encryption or decryption or authentication function.
  • a security process related to the SIM of the cellular communication such as a virtual SIM function or a SIM card security encryption or decryption or authentication function.
  • the first semiconductor chip 11 is responsible for processing various operations of the mobile terminal 10, including power-on and power-off operations.
  • the first semiconductor chip 11 is an AP chip of the mobile terminal 10.
  • the AP chip includes an application processor and one or more devices other than the application processor to form a system on chip (SoC).
  • SoC system on chip
  • the first semiconductor chip 11 includes, in addition to the processor 11a, the power-on component 11b, and the SE 11c, at least one memory for storing a program temporarily loaded by the first semiconductor chip 11 and temporary data generated by the processor 11a running the program.
  • the at least one memory is a random access memory (RAM).
  • the processor 11a may be an application processor for running a general operating system of the mobile terminal 10, such as an Android operating system, an iOS operating system, a Windows operating system, or the like.
  • the processor 11a is a central processing unit (CPU) or a micro control unit (MCU) including an ARM (Advanced RISC Machine) processor.
  • the processor 11a can be used to run various application scenarios or other programs based on the above operating system.
  • the power-on component 11b is configured to trigger the processor 11a to power up when the shutdown card is swiped. Wherein, when the PMU 13 is in the power-on state, the power-on component 11b is also in an energized state.
  • the power-on component 11b includes a timer and a RAM placed in the power-on component 11b. The timer is used for timing, and when the timing expires, the power-on component 11b is caused to trigger the processor 11a to be powered on.
  • the RAM in the power-on component 11b is used to temporarily store data when the first semiconductor chip 11 is in a power-off state.
  • the power-on component 11b is used to be in an always-on state when at least one other portion of the first semiconductor chip 11, such as the processor 11a, is powered down.
  • the SE 11c is used for communicating with the communication unit 12, and is also used for securely processing the secure communication data exchanged between the mobile terminal 10 and the peer device (such as the card reading device 20 in the card swipe scene) to improve data security.
  • Security processing can include at least one of the following: data encryption, data integrity protection.
  • Security processing can also include various types of security drivers or security application processing.
  • the SE 11c can support secure operating system software processing, which can be various types of platform software, such as a Chip Operating System (COS).
  • COS Chip Operating System
  • a typical COS is an operating system that supports swipe operations.
  • SE 11c can support secure application processing.
  • a typical security application can make the card software based on the above COS.
  • the communication unit 12 is for communicating with the card reading device 20 to implement a card swipe operation.
  • the communication unit 12 is an NFC chip
  • the NFC chip of the mobile terminal 10 and the NFC chip of the card reading device 20 can communicate based on a Radio Frequency Identification (RFID) protocol to interactively signal in the card application.
  • RFID Radio Frequency Identification
  • communication unit 12 may support other types of communications, such as cellular communications.
  • the communication unit 12 is configured to perform signal interaction with the peer device, which may include a baseband processor for performing communication protocol and algorithm processing and a transceiver for transceiving signals, and may further include an antenna and a radio frequency front end device such as filtering , impedance matching and power amplification components.
  • the PMU 13 can be a highly integrated power management unit for portable applications for use with chips (such as the first semiconductor chip 11 and communication unit 12 described above) or components of the chip (such as the processor described above) 11a, power-on components 11b and SE 11c) provide a stable power supply. It will be appreciated that the PMU 13 may be integrated in the first semiconductor chip 11 or as a separate chip.
  • the mobile terminal 10 further includes: a battery 14.
  • Battery 14 is coupled to PMU 13 and communication unit 12, respectively.
  • Battery 14 is used to provide power to mobile terminal 10.
  • the PMU 13 can further generate power to the first semiconductor chip 11 based on the power provided by the battery 14.
  • the mobile terminal 10 further includes an external memory, which refers to a memory external to the first semiconductor chip 11.
  • the memory external to the first semiconductor chip 11 may be an embedded multimedia media card (eMMc) or a universal flash memory (UFS).
  • the memory outside the first semiconductor chip 11 includes a Replay Protected Memory Block (RPMB) for storing the execution program of the SE 11c.
  • RPMB Replay Protected Memory Block
  • the first semiconductor chip 11 includes a processor 11a, a power-on component 11b, an SE 11c, a RAM 11d, and a memory controller 11e.
  • the RAM 11d of the first semiconductor chip 11 is a memory of the first semiconductor chip 11 capable of directly interacting with the processor 11a, and is generally a storage medium for temporary data generated by a program that the processor 11a is running.
  • the memory controller 11e controls data interaction of the first semiconductor chip 11 with an external memory.
  • the first semiconductor chip 11 of FIGS. 2 and 3 does not include the communication unit 12 and the PMU 13, but this is an example.
  • the PMU 13 may be integrated in the first semiconductor chip 11 or may not be integrated in the first semiconductor chip 11;
  • the communication unit 12 may be integrated in the first semiconductor chip 11 or may not be integrated in the first semiconductor chip 11.
  • the PMU 13 and the communication unit 12 may be located on the same or different chips outside the first semiconductor chip 11.
  • a technical solution capable of triggering the SE to be powered on after the processor is powered off is provided, which can not affect the security function under the premise of saving power as much as possible.
  • the technical solution provided by the embodiment of the present application has strong practical value, for example, to meet the practical application requirements of the user to implement the operation of the card, such as the card payment, the bus card, the access card, and the like.
  • the communication unit 12 is configured to receive a communication signal that meets a preset condition, and output a first power-on signal to the power-on component 11b according to the communication signal.
  • the communication signal can be various types of communication signals as previously described, including but not limited to short range signals and cellular communication signals.
  • the communication unit 12 in the mobile terminal 10 is capable of receiving different communication signals.
  • the first shutdown state refers to a situation in which at least one component of the mobile terminal 10 except the power-on component 11b, the communication unit 12, and the PMU 13 on the first semiconductor chip 11 is in a power-off state, for example, at the first In the off state, the processors 11a and SE 11c of the first semiconductor chip 11 are both in a power-down state.
  • the power-off state includes a fully powered-off state and a low-power state
  • the fully powered-off state refers to a state in which components of the chip or chip are not powered, and is also referred to as a power-off state.
  • the low-power state refers to the fact that the components of the chip or chip consume lower power consumption to maintain the running state than the normal working state, and enter the normal working state from the power-off state, and enter the normal working from the low-power state.
  • the chip or chip components start up faster.
  • the components of the chip cannot implement the function or complete function of the component.
  • the components of the chip only accept the lowest voltage, but the voltage is not sufficient to maintain its full processing function.
  • each unit in FIG. 2 and FIG. 3 may be a component in a chip, and other components may be included in the chip.
  • the first semiconductor chip 11 may further include a graphics processing unit (Graphics Processing Unit, GPU).
  • GPU Graphics Processing Unit
  • At least one of these components can be powered down while the power up component 11b is always powered up to save power.
  • the card reading device 20 capable of cooperating with the mobile terminal 10 to implement the card swiping function transmits a communication signal conforming to a preset condition, and the communication signal is used to enable the mobile terminal 10 around the card reading device 20 to perceive the card reading device 20 presence. For example, the card reading device 20 continuously transmits a communication signal outward, or transmits the communication signal once every predetermined time interval. After receiving the communication signal, the communication unit 12 in the mobile terminal 10 detects whether the communication signal meets the preset condition. If the communication signal meets the preset condition, the first power-on signal is output to the power-up component 11b.
  • the communication unit 12 is an NFC chip
  • the NFC chip receives a communication signal that meets a preset condition
  • the first power-on is output to the upper electrical component 11b through a General Purpose Input Output (GPIO) interface. signal.
  • the power-on component 11b is provided with a GPIO interface for acquiring a first power-on signal.
  • the first power-on signal is used to trigger the power-on component 11b to control the processor 11a to power up.
  • the preset condition is that the communication signal includes a preset identifier.
  • the preset identifier is used by the communication unit 12 in the mobile terminal 10 to recognize whether the communication signal it receives is a communication signal related to the card swipe function provided by itself.
  • the communication signal detected by the communication unit 12 in the mobile terminal 10 includes a preset identifier related to the bus card function, and after the communication unit 12 recognizes the preset identifier, it determines that the bus card operation is subsequently performed.
  • the preset condition is that the frequency of the communication signal is within the preset frequency band.
  • the preset frequency band may be preset according to actual needs.
  • the preset frequency band may be a frequency band used by the NFC, or may be one of the frequency bands used by the NFC.
  • the preset condition may be that the interval of the communication signal is a preset duration, and the preset duration may be a value or a range of values.
  • the preset condition may be preset according to actual needs to ensure that the communication unit 12 can accurately recognize the communication signal and other unrelated communication signals related to the card-swapping function provided by itself.
  • the communication unit 12 is a short-range communication chip, such as an NFC chip
  • the communication signal may be a radio frequency signal.
  • the power-on component 11b is configured to acquire a first power-on signal from the communication unit 12 and trigger the processor 11a to be powered on.
  • the power-on component 11b triggers the processor 11a to power up: the power-on component 11b outputs a second power-on signal to the PMU 13, and the second power-on signal is used to trigger the PMU 13 to supply power to the processor 11a.
  • the PMU 13 acquires a second power up signal from the power up component 11b and supplies power to the processor 11a based on the second power up signal.
  • the power up component 11b includes a first register.
  • the power-on component 11b is further configured to write SE power-on indication information for indicating that the control SE 11c is powered on in the first register after the first power-on signal is acquired.
  • the SE power-on indication information written by the power-on component 11b in the first register is "01" for instructing the processor 11a to control the SE 11c to be powered on.
  • the processor 11a is configured to switch from the first power-off state to the first power-on state triggered by the power-on component 11b, obtain the SE power-on indication information from the power-on component 11b, and control the SE 11c according to the SE power-on indication information. Electricity.
  • the first power-off state may be a fully powered down state, or may be a low power consumption state, and the first powered-on state is an energized state.
  • the processor 11a obtains SE power-on indication information from the first register of the power-on component 11b.
  • the processor 11a controls the SE 11c to be powered up by the processor 11a transmitting a third power-on signal to the PMU 13, and the third power-on signal for instructing the PMU 13 to supply power to the SE 11c.
  • the PMU 13 receives the third power up signal from the processor 11a and supplies power to the SE 11c based on the third power up signal.
  • the SE 11c is configured to switch from the second power-off state to the second power-on state under the control of the processor 11a, interact with the communication unit 12 to securely communicate data, and perform secure processing on the secure communication data.
  • the second power-down state may be a fully powered down state, or may be a low power consumption state, and the second power-on state is an energized state.
  • the card reading device 20 is a POS machine
  • the SE 11c when the SE 11c is powered on, it communicates with the communication unit 12 and exchanges payment information, and simultaneously performs security processing on the payment information, and the communication unit 12 communicates with the POS machine to complete the card swiping.
  • the card reading device 20 when the card reading device 20 is a bus card reader, after the SE 11c is powered on, it communicates with the communication unit 12 and exchanges the bus card information, and simultaneously performs security processing on the bus card information, and the communication unit 12 and the bus card
  • the card reader communicates to complete the bus card swiping operation; when the card reading device 20 is the access card reader, after the SE 11c is powered on, it communicates with the communication unit 12 and interacts with the access control information, and simultaneously performs security processing on the access control information, and the communication
  • the unit 12 communicates with the access card reader to complete the access card swipe operation.
  • the communication unit 12 outputs the first power-on signal to the upper power component 11b when receiving the communication signal that meets the preset condition, thereby triggering the processor 11a to power on,
  • the SE 11c integrated with the processor 11a on the same chip is powered on, and then the communication unit 12 interacts with the secure communication data and performs security processing thereof.
  • the SE 11c is still powered on for security processing. Under the premise of saving power as much as possible, it does not affect the use of security functions.
  • FIG. 4 shows a flowchart of a method for controlling an SE provided by an embodiment of the present application.
  • the method is applicable to the mobile terminal 10 shown in FIG. 2.
  • the method can include the following steps:
  • step 401 the communication unit 12 receives the communication signal that meets the preset condition, and outputs the first power-on signal to the power-on component 11b according to the communication signal.
  • the communication unit 12 When the mobile terminal 10 is in the first power-off state, the communication unit 12 is in an energized state, and can receive the communication signal sent by the card reading device 20. When the communication unit 12 receives the communication signal that meets the preset condition, the up-up component 11b outputs a first power-on signal, which is used to instruct the power-on component 11b to trigger the processor 11a to power up.
  • Step 402 the power-on component 11b acquires the first power-on signal from the communication unit 12, and triggers the processor 11a to power up.
  • the processor 11a After the power-on component 11b acquires the first power-on signal, the processor 11a is automatically triggered to be powered on.
  • the power up component 11b includes a first register. After the power-on component 11b acquires the first power-on signal, the SE power-on indication information for instructing the control SE 11c to power up is written in the first register.
  • Step 403 The processor 11a switches from the first power-off state to the first power-on state triggered by the power-on component 11b, acquires the SE power-on indication information from the power-on component 11b, and controls the SE 11c according to the SE power-on indication information. Electricity.
  • the processor 11a After switching from the first power-off state to the first power-on state, the processor 11a acquires the indication information from the power-on component 11b, and performs a subsequent operation according to the indication information. Optionally, the processor 11a obtains indication information from the first register of the power-on component 11b. If the indication information acquired by the processor 11a is the SE power-on indication information, it indicates that the processor 11a is triggered to be powered on when the mobile terminal 10 is in the first power-off state, and the processor 11a controls the SE 11c to be powered on.
  • the indication information acquired by the processor 11a is the normal power-on indication information, it indicates that the processor 11a is triggered to be powered on when the button is powered on, the timer is turned on, or the battery is turned on, and the processor 11a performs a normal power-on operation.
  • the normal boot operation includes starting the operating system and displaying a user interface (UI).
  • Step 404 the SE 11c switches from the second power-off state to the second power-on state under the control of the processor 11a, interacts with the communication unit 12 to securely communicate data, and performs secure processing on the secure communication data.
  • the SE 11c After switching from the second power-down state to the second power-on state, the SE 11c communicates with the communication unit 12 and interacts with the secure communication data to complete the card swipe operation. Among them, the SE 11c performs security processing on the secure communication data, and the purpose thereof is to ensure the security of data exchanged with the communication unit 12. For example, secure communication processing such as encryption and decryption of a secure communication data, a message authentication code (MAC) operation, or a decoding MAC operation.
  • MAC message authentication code
  • the SE 11c can communicate with the communication unit 12 through a Single Wire Protocol (SWP), thereby receiving and responding to an application protocol data unit required for the card-swapping operation sent by the communication unit 12 (Application Protocol Data Unit (APDU) command.
  • SWP Single Wire Protocol
  • APDU Application Protocol Data Unit
  • the communication unit 12 is an NFC chip.
  • the SE 11c communicates with the NFC chip.
  • the NFC chip can perform the card analog operation.
  • the card analog operation refers to the NFC chip simulating the card signal to be swiped, thereby performing the card swiping.
  • the communication unit 12 outputs the first power-on signal to the upper power component 11b when receiving the communication signal that meets the preset condition, thereby triggering the processor 11a to power on,
  • the SE 11c integrated with the processor 11a on the same chip is powered on, and then the communication unit 12 interacts with the secure communication data and performs security processing thereof.
  • the SE 11c is still powered on for security processing. Under the premise of saving power as much as possible, it does not affect the use of security functions.
  • FIG. 5 is a flowchart of a method for controlling an SE provided by another embodiment of the present application.
  • the method is applicable to the mobile terminal 10 shown in FIG. 2.
  • the method can include the following steps:
  • Step 501 The communication unit 12 receives the communication signal that meets the preset condition, and outputs the first power-on signal to the power-on component 11b according to the communication signal.
  • Step 502 the power-on component 11b acquires the first power-on signal from the communication unit 12, and triggers the processor 11a to power up.
  • steps 501 and 502 are the same as the steps 401 and 402 in the embodiment of FIG. 4, and the descriptions in the embodiment of FIG. 4 are omitted.
  • step 503 the processor 11a runs a processor ROM program and runs a boot program through the processor ROM program.
  • the processor 11a runs a processor ROM program, and the processor ROM program is stored in a read-only memory (ROM) corresponding to the processor 11a, and the ROM can be in the first semiconductor chip 11. .
  • the processor ROM program is used to determine whether the processor 11a needs to run a boot program.
  • the processor 11a determines, by the processor ROM program, whether the mobile terminal 10 is in the first shutdown state when it is triggered to power up; if so, the boot program is run; if not, the normal boot operation is performed.
  • the boot program is used to control the processor 11a to perform operations related to the first shutdown state, such as controlling the SE 11c to power up in the first shutdown state.
  • the processor 11a determines that the mobile terminal 10 is not in the first power-off state when it is triggered by the processor ROM, it indicates that the mobile terminal 10 is triggered to be powered on in the normal shutdown state, so the processor 11a performs normal booting. operating.
  • the normal shutdown state refers to a situation in which all components in the mobile terminal 10 are in a power-off state.
  • the power-on component 11b further includes a second register.
  • the processor 11a controls the mobile terminal 10 to enter the first power-off state
  • the first state data is written in the second register of the power-on component 11b, and the first state data is used to indicate that the processor 11a is triggered to be powered on. 10 is in the first shutdown state.
  • the processor 11a runs the processor ROM program, acquires the first state data from the second register by using the processor ROM program, and determines that the mobile terminal 10 is in the time when it is triggered to be powered on according to the first state data.
  • the first shutdown state is the processor ROM program
  • the processor 11a controls the mobile terminal 10 to enter the normal shutdown state
  • the second state data is written in the second register in the power-on component 11b
  • the second state data is used to indicate that the processor 11a is triggered to be powered on.
  • the mobile terminal 10 is not in the first shutdown state.
  • the processor 11a runs the processor ROM program, acquires the second state data from the second register through the processor ROM program, and determines, according to the second state data, that the mobile terminal 10 is not triggered when the power is turned on. In the first shutdown state
  • the boot controller is obtained from the memory outside the first semiconductor chip 11 by the storage controller, and is checked. Verify the legitimacy of the bootloader to ensure data security.
  • the processor 11a controls the mobile terminal 10 to enter the first shutdown state
  • the boot program stored in the memory external to the first semiconductor chip 11 is acquired by the storage controller, and the boot is verified. The legitimacy of the program to ensure data security, and then store the boot program in the RAM of the power-on component 11b.
  • the processor 11a determines that the mobile terminal 10 is in the first power-off state when it is triggered to power up, and acquires the boot program from the RAM of the power-on component 11b.
  • step 504 the processor 11a obtains the SE power-on indication information from the power-on component 11b through the booting procedure, and controls the SE 11c to be powered on.
  • the processor 11a obtains the SE power-on indication information from the first register of the power-on component 11b through the booting procedure, and controls the SE 11c to be powered on according to the SE power-on indication information.
  • the processor 11a loads the execution program of the SE 11c from the memory outside the first semiconductor chip 11 into the memory inside the first semiconductor chip 11 through the booting program, and the processor 11a can The memory outside the first semiconductor chip 11 is accessed by a memory controller in the first semiconductor chip 11.
  • the execution program of SE 11c can be COS.
  • the execution program of the SE 11c is stored in a memory external to the first semiconductor chip 11, and by acquiring the execution program of the SE 11c from the memory external to the first semiconductor chip 11, the storage space of the SE 11c can be saved, so that the SE 11c Can be designed to be lighter and thinner.
  • the execution program of the SE 11c may also be stored in a memory inside the SE 11c or in a memory inside the first semiconductor chip 11.
  • step 505 the SE 11c runs the ROM program of the SE 11c, and loads the execution program of the SE 11c through the ROM program of the SE 11c.
  • the ROM program of SE 11c is run, and the ROM program of SE 11c is used to load the execution program of SE 11c.
  • the SE program of the SE 11c is stored in the ROM inside the SE 11c.
  • the SE 11c loads its execution program from the memory inside the first semiconductor chip 11 into the memory inside the SE 11c.
  • the SE 11c cannot directly load the execution program of the SE 11c from the memory outside the first semiconductor chip 11, and thus the processor 11a loads the execution program of the SE 11c from the memory outside the first semiconductor chip 11 to the inside of the first semiconductor chip 11.
  • the SE 11c loads its execution program from the internal memory of the first semiconductor chip 11 into the memory inside the SE 11c through the ROM program of the SE 11c, and runs the execution program.
  • the execution program of the SE 11c may be an image file, and the image file is a specific file in a certain format to facilitate loading and running.
  • the ROM program of SE 11c is run by the processor in SE 11c, and SE 11c loads its execution program into the RAM of SE 11c and is run by the processor of SE 11c.
  • the SE 11c verifies the legitimacy of the program to be run before running the ROM program of the SE 11c or its execution program to ensure data security.
  • the execution program of SE 11c takes the execution program of SE 11c as an example, if the verification result is that the execution program of SE 11c is legal, SE 11c runs the execution program; if the verification result is that the execution program of SE 11c is illegal, SE 11c does not Run the executor.
  • step 506 the SE 11c interacts with the communication unit 12 through its execution program to securely communicate data and securely process the secure communication data.
  • the SE 11c communicates with the communication unit 12, and during the communication, the SE 11c can read from the memory external to the first semiconductor chip 11 through the interaction with the processor 11a to be transmitted to the communication unit 12. The data, while the SE 11c can write data received from the communication unit 12 into the memory outside the first semiconductor chip 11 by interaction with the processor 11a.
  • the SE 11c interacts with the processor 11a through Inter-Process Communication (IPC) and a mailbox (Mailbox) to access the memory stored outside the first semiconductor chip 11.
  • IPC Inter-Process Communication
  • Mailbox a mailbox
  • the mailbox memory can also be replaced by a bus bridge, regardless of whether the mailbox memory or the bus bridge is a dedicated interaction channel between the processor 11a and the SE 11c.
  • the SE 11c is hardware independent of the processor 11a, and can implement various types of security services. Unlike the traditional Trust Zone or Trusted Execution Environment (TEE), the various types of calculations that the SE 11c performs for security processing may not depend on the processor 11a.
  • SE 11c includes a processor dedicated to secure processing for running COS or a secure application for COS.
  • the SE 11c may also include a dedicated memory dedicated to security processing, such as RAM or ROM, and various types of hardware accelerators dedicated to secure processing, such as a key generator, an encryption and decryption device, a hash operation device, or One Time Programable (OTP) memory.
  • TEP One Time Programable
  • the SE 11c there is a safety isolation between the SE 11c and the other one or more devices in the first semiconductor chip 11 such that other one or more devices are not free to access data stored or running in the SE 11c.
  • the dedicated interactive channels described above include, but are not limited to, the mailbox memory and bus bridges previously described.
  • the SE 11c and communication unit 12 interactive secure communication data can be used for card swipe operations.
  • the mobile terminal 10 can be restored to the first shutdown state, so the processor 11a can perform the third shutdown operation after completing the card swipe operation, and the third shutdown operation includes the control processor 11a and the SE 11c being powered off, maintaining the upper The electrical component 11b is in an energized state.
  • the processor completes the third shutdown operation, only the power-on component 11b is in the power-on state in the first semiconductor chip.
  • the processor 11a performs a third shutdown operation after a preset period of time.
  • the processor 11a is capable of performing a third shutdown operation after the preset duration by the boot program. Illustratively, assuming that the preset duration is 10 seconds, the processor 11a performs a third shutdown operation by the boot program after the SE 11c is powered on for 10 seconds.
  • the processor 11a After the SE 11c is powered on, the processor 11a starts a timing clock. When receiving the reset command sent by the SE 11c, the processor 11a resets the timing clock when the timing clock expires. The processor 11a performs a third shutdown operation. When the SE 11c communicates with the communication unit 12, each time a signal from the communication unit 12 is received, a reset command is transmitted to the processor 11a, and when the processor 11a receives the reset command, the timing clock is reset by the boot program.
  • the first shutdown state is automatically entered after the card swiping operation is completed, and the waste of the mobile terminal 10 is avoided.
  • the processor 11a receives the trigger signal of the normal power-on, the shutdown operation is no longer performed, and the normal power-on operation is directly performed.
  • the processor 11a in the first semiconductor chip 11 is a control device of the chip, which may be a CPU or an MCU. Since the MCU consumes less power, using the MCU as the processor 11a helps to reduce the first semiconductor when the card is turned off.
  • the processor 11a is an MCU, there are other CPUs in the system, that is, the first semiconductor chip 11, and at this time, the other CPU is the main core of the first semiconductor chip 11, and the power consumption of the processor 11a is lower than that of the above main The core, which is equivalent to a low-power core.
  • the main core is an application processor for running an operating system such as Android and application software based on the operating system.
  • the processor 11a is only used to implement the necessary control functions, such as power consumption control for the entire first semiconductor chip 11 or portions thereof, and is not used to run complex operating systems and applications.
  • the power consumption control includes, but is not limited to, adjustment of a clock frequency, an operating voltage, or an operating current.
  • the power consumption of the SE 11c may be lower than that of the processor 11a.
  • the solution for the built-in SE outputs the first power-on signal to the upper power component 11b when the communication unit 12 detects the communication signal that meets the preset condition, thereby triggering the processor 11a to power on.
  • the SE integrated on the same chip as the processor 11a is powered on, and then the communication unit 12 exchanges secure communication data and performs security processing thereof. After the processor 11a is powered off, the SE can be powered on for security processing.
  • the use of safety functions is not affected under the premise of saving power as much as possible.
  • the above embodiment describes a method of controlling the SE 11c in the first power-off state.
  • the following FIG. 6 embodiment will describe a process of controlling the mobile terminal 10 to enter the first power-off state and enter the normal power-off state from the first power-off state. Referring to FIG. 6, the process may include the following steps:
  • step 601 the processor 11a performs a first shutdown operation.
  • the user can select whether to enable the function of entering the first shutdown state by using the configuration item in the mobile terminal 10. If the mobile terminal 10 is turned off, the processor 11a performs a first shutdown operation, so that the mobile terminal 10 enters the first shutdown state, thereby enabling the shutdown card swipe function.
  • the first shutdown operation includes: the control processor 11a and the SE 11c are powered off.
  • the first shutdown operation requires control of the other components of the mobile terminal 10 except the communication unit 12 and the PMU 13 to be powered off, in addition to the need to power down the control processor 11a and the SE 11c.
  • the processor 11a when receiving the first shutdown signal sent by the PMU 13, the processor 11a performs a first shutdown operation, where the first shutdown signal is detected by the PMU 13 when the battery power is less than the first preset threshold. It is transmitted to the processor 11a.
  • the first preset threshold may be set according to actual experience. Exemplarily, the battery power is 3000 mAh, the first preset threshold is 150 mAh, and when the battery power is less than 150 mAh, the processor 11a performs a first shutdown operation, so that the mobile terminal 10 enters the first shutdown state, while ensuring that the mobile terminal 10 remains There is 150mAh of power for the shutdown card.
  • the processor 11a when detecting the second shutdown signal triggered by the user, the processor 11a performs a first shutdown operation, and the second shutdown signal is a signal triggered by the user manual shutdown operation, for example, the user presses the power button.
  • the second shutdown signal is triggered, and when the second shutdown signal is detected, the processor 11a performs the first shutdown operation.
  • Step 602 The PMU 13 outputs a fourth power-on signal to the power-on component 11b when detecting that the battery power is less than the second preset threshold.
  • the mobile terminal 10 After the mobile terminal 10 enters the first power-off state, since the power-on component 11b, the PMU 13, and the communication unit 12 are still in the power-on state, the mobile terminal 10 is still consuming the power of the battery.
  • the PMU 13 When the battery power is lower than the second predetermined threshold, the PMU 13 outputs a fourth power-on signal to the upper electrical component 11b.
  • the second preset threshold may be set according to actual experience, or may be set according to user requirements, and the second preset threshold is smaller than the first preset threshold.
  • Step 603 the power-on component 11b acquires the fourth power-on signal from the PMU 13, and triggers the processor 11a to power up.
  • the power up component 11b includes a first register.
  • the power-up component 11b writes shutdown instruction information for instructing execution of the second shutdown operation in the first register after acquiring the fourth power-on signal.
  • the shutdown indication information written by the power-on component 11b in the first register is "11" for instructing the processor 11a to perform the second shutdown operation.
  • Step 604 the processor 11a switches from the first power-off state to the first power-on state triggered by the power-on component 11b, acquires the shutdown indication information from the power-on component 11b, and performs a second shutdown operation according to the shutdown indication information.
  • the processor 11a performs a second shutdown operation to cause the mobile terminal 10 to enter a normal shutdown state.
  • the second shutdown operation includes: controlling the processor 11a, the SE 11c, and the power-on component 11b to be powered down.
  • the second shutdown operation further includes: controlling the PMU 13 and the communication unit 12 to be powered off.
  • the PMU 13 detects the battery power.
  • the PMU 13 outputs the fourth power-on to the upper component 11b.
  • the signal causes the power-on component 11b to trigger the processor 11a to be powered on, and the second shutdown operation is performed by the processor 11a to put the mobile terminal into a normal shutdown state.
  • the mobile terminal is prevented from consuming the power in the first shutdown state, so that a part of the power is reserved for subsequent use (such as making an emergency call, starting a shutdown alarm, etc.).
  • FIG. 6 describes a possible scenario for controlling the mobile terminal 10 to enter a normal shutdown state from the first off state.
  • FIG. 7 embodiment will introduce another situation in which the mobile terminal 10 is controlled to enter a normal shutdown state from the first off state. Please refer to FIG. 7, which may include the following steps:
  • step 701 the processor 11a performs a first shutdown operation.
  • step 701 is the same as the step 601 in the embodiment of FIG. 6. Referring to the description in the embodiment of FIG. 6, this embodiment will not be described again.
  • Step 702 the power-on component 11b starts the timer after the processor 11a performs the first shutdown operation.
  • the power-on component 11b starts a timer after the processor 11a performs the first shutdown operation, that is, after the mobile terminal 10 enters the first shutdown state, the power-on component 11b starts a timer and starts timing.
  • Step 703 when the timer expires, the power-on component 11b triggers the processor 11a to power up.
  • the power-on component 11b triggers the processor 11a to be powered on.
  • the power up component 11b includes a first register.
  • the power-on component 11b writes shutdown instruction information for instructing execution of the second shutdown operation in the first register when the timer expires.
  • Step 704 the processor 11a switches from the first power-off state to the first power-on state triggered by the power-on component 11b, acquires the shutdown indication information from the power-on component 11b, and performs a second shutdown operation according to the shutdown indication information.
  • step 704 is the same as the step 604 in the embodiment of FIG. 6.
  • step 704 is the same as the step 604 in the embodiment of FIG. 6.
  • the timer is timed by the timer, and after the timer is set, the power-on component 11b controls the processor 11a to be powered on, and is executed by the processor 11a.
  • the second shutdown operation causes the mobile terminal to enter a normal shutdown state.
  • the length of time that the mobile terminal enters the first power-off state can be set according to the user's requirement, and the mobile terminal is prevented from remaining in the first power-off state for a long time, so that the mobile terminal consumes power in the first power-off state, so as to leave a part of power for subsequent use. (such as making an emergency call, starting a shutdown alarm, etc.).
  • An exemplary embodiment of the present application also provides a chip, that is, the first semiconductor chip 11 described above, which includes the SE 11c, the processor 11a, and the power-on component 11b as mentioned in the previous embodiment.
  • An exemplary embodiment of the present application further provides a method for controlling an SE, which is applied to the first semiconductor chip 11, as shown in FIG. 8, the method includes the following steps:
  • Step 801 the power-on component 11b receives the power supply of the PMU 13, receives the first power-on signal from the communication unit 12, and triggers the processor 11a to power up.
  • step 802 the processor 11a receives the power supply of the PMU 13 and switches from the first power-off state to the first power-on state, and the SE power-on indication information is obtained from the power-on component 11b, and is powered on according to the SE.
  • the indication information controls the SE 11c to be powered on.
  • Step 803 the SE 11c receives the power supply of the PMU 13 under the control of the processor 11a and switches from the second power-off state to the second power-on state, interacts with the communication unit 12 to securely communicate data, and performs secure processing on the secure communication data.
  • An exemplary embodiment of the present application also provides a computer program product, which can be stored in a RAM, a flash memory, a ROM, an Erasable Programmable ROM (EPROM), and an electrically erasable Programmable EPROM (EEPROM), a register, or any other form of storage medium known in the art for implementing the processor 11a side of the above-described embodiment when the computer program product is executed by the processor 11a.
  • a computer program product which can be stored in a RAM, a flash memory, a ROM, an Erasable Programmable ROM (EPROM), and an electrically erasable Programmable EPROM (EEPROM), a register, or any other form of storage medium known in the art for implementing the processor 11a side of the above-described embodiment when the computer program product is executed by the processor 11a.
  • An exemplary embodiment of the present application also provides a computer program product that can be stored in RAM, flash memory, ROM, EPROM, EEPROM, registers, or any other form of storage medium known in the art.
  • the computer program product is executed by the SE 11c, it is used to implement the method steps of the SE 11c side in the above embodiment.

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Abstract

一种控制SE（11c）的系统、方法及芯片。所述系统包括SE（11c）、处理器（11a）、上电组件（11b）、PMU（13）和通信单元（12）；SE（11c）、处理器（11a）、上电组件（11b）位于第一半导体芯片（11）内；通信单元（12），用于接收符合预设条件的通信信号，并根据通信信号输出第一上电信号至上电组件（11b）；上电组件（11b），用于触发处理器（11a）上电；处理器（11a），用于从上电组件获取SE（11c）上电指示信息，并根据SE（11c）上电指示信息控制SE（11c）上电；SE（11c），用于与通信单元（12）交互安全通信数据，并对安全通信数据进行安全处理；PMU（13），用于为处理器（11a）、SE（11c）、上电组件（11b）和通信单元（12）供电。该系统针对内置SE（11c）的方案，能够在处理器（11a）下电之后依然触发SE（11c）上电进行安全处理，在尽量节省功耗的前提下不影响安全功能的使用。

Description

控制SE的系统、方法及芯片
本申请要求于2017年11月21日提交中国国家知识产权局、申请号为201711164962.0、申请名称为“控制SE的系统、方法及芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及芯片技术领域，特别涉及一种控制安全元件(Secure Element，SE)的系统、方法及芯片。
背景技术
随着移动终端的不断发展，移动终端具备越来越多的功能，同时人们对于移动终端中的数据安全也越来越重视。通常，通过SE来保护移动终端中的数据安全。SE是独立于系统中主处理器的具有加密和解密逻辑电路，其内部包括专用于安全处理的处理器和各类硬件电路，用于对数据交互过程中设备之间交互的数据进行加解密，以提高数据的安全性。通常来说，SE可用于实现包括移动支付、公交卡刷卡或门禁刷卡等各类安全处理。
目前，在移动终端中，采用在应用处理器(Application Processor，AP)芯片中内置SE的方案。内置SE的方案是指将SE集成于移动终端的AP芯片上，也即SE是AP芯片的一部分。对于内置SE方案，SE是否启动依赖于移动终端的电源管理单元(Power Management Unit，PMU)是否向AP芯片供电。当移动终端处于开机状态时，PMU向AP芯片供电，AP芯片处于通电状态，SE也处于通电状态；当移动终端处于关机状态时，PMU停止向AP芯片供电，AP芯片处于断电状态，SE也处于断电状态。
针对内置SE的方案，当移动终端处于关机状态时，由于集成在AP芯片上的SE处于断电状态，因此无法对交互数据进行安全处理。
发明内容
本申请实施例提供了一种控制SE的系统、方法及芯片，针对内置SE的方案，当系统中处理器处于下电状态时，实现利用SE做安全处理。
第一方面，本申请实施例提供一种控制SE的系统，包括SE、处理器、上电组件、电源管理单元PMU和通信单元。SE、处理器、上电组件位于第一半导体芯片内。可选地，所述PMU和通信单元中的至少一项位于该第一半导体芯片内。可选地，所述PMU和通信单元位于第一半导体芯片之外的其他同一或不同的半导体芯片中。
通信单元，用于接收符合预设条件的通信信号，并根据通信信号输出第一上电信号至上电组件。上电组件，用于获取来自通信单元的第一上电信号，并触发处理器上电。处理器，用于在上电组件触发下从第一下电状态切换至第一上电状态，以及从上电组件获取SE上电指示信息，并根据SE上电指示信息控制SE上电。SE，用于在处理器的控制下从第二下电状态切换至第二上电状态，与通信单元交互安全通信数据， 并对安全通信数据进行安全处理。PMU，用于为处理器、SE、上电组件和通信单元供电。
本申请实施例提供的方案中，针对内置SE的方案，通过通信单元在检测到符合预设条件的通信信号时向上电模块输出第一上电信号，从而触发处理器上电，以使得与处理器集成于同一芯片上的SE上电启动，进而与通信单元交互安全通信数据并对其进行安全处理，能够在处理器下电之后依然触发SE上电进行安全处理，在尽量节省功耗的前提下不影响安全功能的使用。
在一种可能的实施方式中，在上电组件用于触发处理器上电的方面，上电组件具体用于输出第二上电信号至PMU。PMU，用于获取来自上电组件的第二上电信号，并根据第二上电信号向处理器供电。
通过上述方式，使得上电组件能够通过PMU触发处理器上电。
在又一个可能的设计中，在处理器用于控制SE上电的方面，处理器具体用于向PMU发送第三上电信号。PMU，用于接收来自处理器的第三上电信号，并根据第三上电信号向SE供电。
通过上述方式，使得处理器能够控制SE上电。
在又一个可能的设计中，PMU，还用于当检测到电池电量小于第一预设阈值时，向处理器发送第一关机信号。处理器，还用于接收来自PMU的第一关机信号，并根据第一关机信号执行第一关机操作，其中，第一关机操作包括：控制处理器和SE下电。
在本发明实施例中，通过第一关机操作，控制处理器和SE下电，使得移动终端通过不下电的上电组件触发SE上电进行安全处理。
在又一个可能的设计中，PMU，还用于当检测到电池电量小于第二预设阈值时，输出第四上电信号至上电组件，第二预设阈值小于第一预设阈值。上电组件，还用于获取来自PMU的第四上电信号，并触发处理器上电。处理器，还用于在上电组件触发下从第一下电状态切换至第一上电状态，以及从上电组件获取关机指示信息，并根据关机指示信息执行第二关机操作，第二关机操作包括：控制处理器、SE和上电组件下电。
在本申请实施例中，通过PMU检测电池电量，当电池电量低于第二预设阈值时，PMU向上电组件输出第四上电信号，使得上电组件触发处理器上电，通过处理器执行第二关机操作，让移动终端进入正常关机状态。通过上述方式，避免移动终端在第一关机状态消耗完电量，以便留有一部分电量供后续(如拨打紧急电话、启动关机闹钟等)使用。
在又一个可能的设计中，上电组件，还用于：在处理器执行第一关机操作之后启动定时器；当定时器超时时，触发处理器上电。处理器，还用于在上电组件触发下从第一下电状态切换至第一上电状态，以及从上电组件获取关机指示信息，并根据关机指示信息执行第二关机操作，第二关机操作包括：控制处理器、SE和上电组件下电。
在本申请实施例中，通过定时器计时，经过定时器设置的时长后，上电组件控制处理器上电，通过处理器执行第二关机操作，让移动终端进入正常关机状态。通过上述方式，能够根据用户需求设置移动终端进入第一关机状态的时长，避免移动终端保 持第一关机状态过长时间而导致移动终端在第一关机状态消耗完电量，以便留有一部分电量供后续(如拨打紧急电话、启动关机闹钟等)使用。
在又一个可能的设计中，预设条件为通信信号中包括预设标识，或者，预设条件为通信信号的频段在预设频段内。
通过上述方式，使得通信单元能够准确地辨识出与自身提供的刷卡功能相关的通信信号。
在又一个可能的设计中，处理器，还用于在从上电组件获取SE上电指示信息之后，将SE的执行程序从第一半导体芯片外部的存储器加载至第一半导体芯片内部的存储器中。SE，还用于在处理器的控制下从第二下电状态切换至第二上电状态之后，将执行程序从第一半导体芯片内部的存储器加载至SE内部的存储器中，并运行执行程序以实现与通信单元交互安全通信数据，并对安全通信数据进行安全处理的功能。
通过上述方式，将SE的执行程序存储在第一半导体芯片外部的存储器中，可以节省SE的存储空间，使得SE能够设计地更加轻薄化。
在又一个可能的设计中，处理器，还用于在SE上电之后经过预设时长执行第三关机操作；或者，在SE上电之后启动定时时钟，在接收到SE发送的重置命令时，重置定时时钟，其中，SE每接收到来自通信单元的信号时，向处理器发送重置命令，当定时时钟超时时，执行第三关机操作；其中，第三关机操作包括控制处理器和SE下电，维持所述上电组件处于通电状态。
通过上述两种方式，实现了在SE对安全通信数据进行安全处理之后执行自动关机，避免浪费移动终端的电量。
另一方面，本申请实施例提供一种控制SE的方法，该方法包括：通信单元接收符合预设条件的通信信号，并根据通信信号输出第一上电信号至第一半导体芯片内的上电组件；上电组件获取来自通信单元的第一上电信号，并触发第一半导体芯片内的处理器上电；处理器在上电组件触发下从第一下电状态切换至第一上电状态，从上电组件获取SE上电指示信息，并根据SE上电指示信息控制第一半导体芯片内的SE上电；SE在处理器的控制下从第二下电状态切换至第二上电状态，与通信单元交互安全通信数据，并对安全通信数据进行安全处理；通过PMU为上述处理器、SE、上电组件和通信单元供电。
又一方面，本申请实施例提供一种芯片，包括SE、处理器和上电组件。上电组件，耦合于通信单元和PMU，用于接收PMU的供电，接收来自通信单元的第一上电信号，并触发处理器上电；处理器，耦合于上电组件、SE和PMU，用于在上电组件触发下接收PMU的供电并从第一下电状态切换至第一上电状态，以及从上电组件获取SE上电指示信息，并根据SE上电指示信息控制SE上电；SE，耦合于通信单元、处理器和PMU，用于在处理器的控制下接收PMU的供电并从第二下电状态切换至第二上电状态，与通信单元交互安全通信数据，并对安全通信数据进行安全处理。可选地，该芯片还可通过第一方面中各种可能的实施方式或设计来实现。
又一方面，本申请实施例提供一种移动终端，该移动终端包括如上述方面所述的控制SE的系统。
又一方面，本申请实施例提供一种计算机程序产品，当该计算机程序产品被第一 半导体芯片内的处理器执行时，用于实现上述方面所述的处理器侧的方法步骤。
又一方面，本申请实施例提供一种计算机程序产品，当该计算机程序产品被第一半导体芯片内的SE执行时，用于实现上述方面所述的SE侧的方法步骤。
相较于现有技术，本申请实施例提供的方案中，针对内置SE的方案，通过通信单元在检测到符合预设条件的通信信号时向上电模块输出第一上电信号，从而触发处理器上电，以使得与处理器集成于同一芯片上的SE上电启动，进而与通信单元交互安全通信数据并对其进行安全处理，能够在处理器下电之后依然触发SE上电进行安全处理，在尽量节省功耗的前提下不影响安全功能的使用。
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图1是本申请一个实施例提供的实施环境的示意图；
图2是本申请一个实施例提供的移动终端的结构示意图；
图3是本申请一个实施例提供的第一半导体芯片的结构示意图；
图4是本申请一个实施例提供的控制SE的方法的流程图；
图5是本申请另一个实施例提供的控制SE的方法的流程图；
图6是本申请一个实施例提供的从第一关机状态进入正常关机状态的流程图；
图7是本申请另一个实施例提供的从第一关机状态进入正常关机状态的流程图；
图8是本申请另一个实施例提供的控制SE的方法的流程图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。本申请实施例描述的系统架构以及业务场景是为了更加清楚地说明本申请实施例的技术方案，并不构成对本申请实施例提供的技术方案的限定，本领域普通技术人员可知，随着系统架构的演变和新业务场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
请参考图1，其示出了本申请一个实施例提供的实施环境的示意图。该实施环境包括：移动终端10和读卡设备20。移动终端10可以是诸如手机、平板电脑、可穿戴设备等便携式电子设备。读卡设备20可以是任意具有读卡功能的电子设备，如销售点(Point Of Sales，POS)机、公交卡读卡器、门禁卡读卡器等。
示例性地，当读卡设备20为POS机时，移动终端10可以代替银行卡与读卡设备20进行通信，以完成刷卡支付操作；当读卡设备20为公交卡读卡器时，移动终端10可以代替公交卡与读卡设备20进行通信，以完成公交刷卡操作；当读卡设备20为门禁卡读卡器时，移动终端10可以代替门禁卡与读卡设备20进行通信，以完成门禁刷卡操作。
移动终端10和读卡设备20中配备有相适配的通信单元，通过上述通信单元进行通信，完成刷卡操作。其中，移动终端10与读卡设备20之间可以通过短距离无线通信技术来完成刷卡操作。示例性地，当移动终端10与读卡设备20之间通过短距离无线通信协议进行通信，来完成刷卡操作时，上述通信单元可以是短距离通信芯片，如 近场通信(Near Field Communication，NFC)芯片。
以上应用场景是以短距离通信为基础的刷卡应用，但实际上本方案可以扩展到其他应用场景。例如，通信单元可以支持各类蜂窝式通信，例如，全球移动通讯(Global System of Mobile communication，GSM)系统、码分多址(Code Division Multiple Access，CDMA)系统、宽带码分多址(Wideband Code Division Multiple Access，WCDMA)系统、通用分组无线业务(General Packet Radio Service，GPRS)、长期演进(Long Term Evolution，LTE)系统、LTE频分双工(Frequency Division Duplex，FDD)系统、LTE时分双工(Time Division Duplex，TDD)、通用移动通信系统(Universal Mobile Telecommunication System，UMTS)等。当通信单元支持任一类型的蜂窝式通信，则移动终端10可以与对端设备(例如服务器、基站等)实现基于通信的安全操作，例如用户识别模块(Subscriber Identification Module，SIM)的安全操作。
在本申请实施例中，如图2所示，移动终端10采用内置SE的方案。该移动终端10包括控制SE的系统，该系统可以包括：第一半导体芯片11、通信单元12和PMU 13。第一半导体芯片11上集成有处理器11a、上电组件11b和SE 11c。其中，处理器11a分别与SE 11c和PMU 13耦合，SE 11c分别与PMU 13和通信单元12耦合，上电组件11b分别与PMU 13和通信单元12耦合。当通信单元12支持短距离通信，则SE 11c对应执行与刷卡有关的安全处理。当通信单元12支持蜂窝式通信，则SE 11c对应执行与蜂窝式通信的SIM有关的安全处理，例如，虚拟SIM功能或SIM卡安全加解密或认证功能。本申请后续实施例以安全刷卡为应用场景为例作介绍，但这种应用场景不用于限定技术方案的适用范围。
第一半导体芯片11负责处理移动终端10的各项操作，包括开机和关机操作。可选地，第一半导体芯片11是移动终端10的AP芯片。该AP芯片包括应用处理器，以及除应用处理器外的其他一个或多个器件，以形成一个系统芯片(System on Chip，SoC)。第一半导体芯片11除包括处理器11a、上电组件11b和SE 11c之外，还包括至少一个存储器，存储器用于存储第一半导体芯片11临时加载的程序以及处理器11a运行程序产生的临时数据。例如，该至少一个存储器为随机存取存储器(Random Access Memory，RAM)。
可选地，处理器11a可以是应用处理器，用于运行移动终端10的通用操作系统，如安卓(Android)操作系统、iOS操作系统、Windows操作系统等。示例性地，处理器11a为包括ARM(Advanced RISC Machine)处理器在内的中央处理单元(Central Processing Unit，CPU)或微控制单元(Micro Control Unit，MCU)。进一步地，处理器11a可用于运行基于上述操作系统的各类应用场景或者其他程序。
上电组件11b用于在进行关机刷卡时，触发处理器11a上电。其中，当PMU 13处于通电状态时，上电组件11b也处于通电状态。上电组件11b包括定时器(Timer)和置于上电组件11b内的RAM。定时器用于计时，当计时超时后，使得上电组件11b触发处理器11a上电。上电组件11b内的RAM用于在第一半导体芯片11处于断电状态时临时存储数据。上电组件11b用于在第一半导体芯片11内其他至少一个部分，如处理器11a下电的时候，处于始终通电状态。
SE 11c用于与通信单元12通信，还用于对移动终端10与对端设备(如刷卡场景 中的读卡设备20)之间交互的安全通信数据进行安全处理，以提高数据的安全性。安全处理可以包括如下至少一项：数据加密、数据完整性保护。安全处理还可包括各类安全驱动程序或安全应用程序处理。例如，SE 11c可支持安全操作系统软件处理，该操作系统软件可以是各类平台软件，如片内操作系统(Chip Operating System，COS)。一种典型的COS就是支持刷卡操作的操作系统。进一步地，SE 11c可支持安全应用软件处理。典型的安全应用软件可以使基于上述COS的刷卡软件。
通信单元12用于与读卡设备20进行通信，以实现刷卡操作。例如，当通信单元12为NFC芯片时，移动终端10的NFC芯片与读卡设备20的NFC芯片之间可以基于无线射频识别(Radio Frequency Identification，RFID)协议进行通信，以交互刷卡应用中的信号。如之前所述，在其他应用场景下，通信单元12可支持其他类型的通信，如蜂窝通信。通信单元12被用于与对端设备执行信号交互，其可以包括用于执行通信协议和算法处理的基带处理器和用于收发信号的收发机，还可以进一步包括天线和射频前端器件，如滤波、阻抗匹配和功率放大等部件。
PMU 13可以是一种高度集成的针对便携式应用的电源管理单元，用于向芯片(如上文介绍的第一半导体芯片11和通信单元12)或者向芯片的组成元器件(如上文介绍的处理器11a、上电组件11b和SE 11c)提供稳定电源。可以理解，PMU 13可以集成在第一半导体芯片11中，或者作为一个独立芯片而存在。
可选地，如图2所示，移动终端10还包括：电池14。电池14分别与PMU 13和通信单元12耦合。电池14用于为移动终端10提供电能。PMU 13可以基于电池14提供的电能进一步产生第一半导体芯片11的电源。
可选地，移动终端10还包括外部存储器，该外部存储器是指第一半导体芯片11外部的存储器。第一半导体芯片11外部的存储器可以是嵌入式的多媒体存储卡(Embedded Multi Media Card，eMMc)或通用闪存存储(Universal Flash Storage，UFS)。第一半导体芯片11外部的存储器包括回放保护存储分区(Replay Protected Memory Block，RPMB)，RPMB用于存储SE 11c的执行程序。
示例性地，如图3所示，其示出了一种第一半导体芯片11的结构示意图。第一半导体芯片11包括：处理器11a、上电组件11b、SE 11c、RAM 11d、存储控制器11e。
第一半导体芯片11的RAM 11d是第一半导体芯片11中的一种能够与处理器11a直接交互数据的存储器，通常作为处理器11a正在运行中的程序产生的临时数据的存储媒介。存储控制器11e控制第一半导体芯片11与外部存储器的数据交互。
需要说明的是，图2和图3中第一半导体芯片11的不包括通信单元12和PMU13，但这是一种举例。实际上，PMU 13可以集成于第一半导体芯片11，也可以不集成于第一半导体芯片11；通信单元12可以集成于第一半导体芯片11，也可以不集成于第一半导体芯片11。在本申请实施中，仅以PMU 13和通信单元12不位于第一半导体芯片11上的情况进行介绍。PMU 13和通信单元12可以位于第一半导体芯片11之外的相同或不同的芯片上。
在本申请实施例中，针对内置SE的方案，提供了一种能够在处理器下电之后依然触发SE上电进行安全处理的技术方案，能够在尽量节省功耗的前提下不影响安全 功能的使用，例如满足用户对移动终端处于低电关机状态下实现刷卡支付、公交刷卡、门禁刷卡等操作的实际应用需求，本申请实施例提供的技术方案具有较强的实用价值。
下面将基于上面所述的本申请实施例涉及的共性方面，对本申请实施例进一步详细说明。结合参考图2所示的移动终端10，在通过上述控制SE的系统实现关机刷卡功能时，其各部分组成部件的功能如下：
通信单元12，用于接收符合预设条件的通信信号，并根据该通信信号输出第一上电信号至上电组件11b。该通信信号可以是如前所述的各种类型的通信信号，包括但不限于短距离信号和蜂窝通信信号。
在移动终端10处于第一关机状态的情况下，移动终端10中的通信单元12能够接收不同的通信信号。其中，第一关机状态是指移动终端10中除第一半导体芯片11上的上电组件11b、通信单元12和PMU 13之外的至少一个元器件处于下电状态的情况，例如，在第一关机状态下，第一半导体芯片11的处理器11a和SE 11c均处于下电状态。在本申请实施例中，下电状态包括完全下电状态和低功耗状态，完全下电状态是指芯片或者芯片的元器件未接通电源的状态，也称为断电状态。低功耗状态是指芯片或者芯片的元器件以相较于正常工作状态消耗更低功耗以维持运行的状态，相较于由断电状态进入正常工作状态，由低功耗状态进入正常工作状态时，芯片或者芯片的元器件启动速度更快。例如，在低功耗状态下，芯片的元器件不能实现该元器件的功能或完整的功能。又例如，在低功耗状态下，芯片的元器件仅接受最低电压，但该电压不足以维持其实现完整的处理功能。如前所述，图2和图3中的各个单元可以是芯片中的元器件，此外芯片中可包括其他元器件，例如第一半导体芯片11中还可以包括图形处理单元(Graphics Processing Unit，GPU)、编解码器、接口电路、三维(Three Dimensional，3D)处理电路、图像信号处理器(Image Signal Processing，ISP)、人工智能(Artificial Intelligence，AI)处理器、音频处理器、或传感器集线器中至少一项。这些元器件的至少一个可以与处理器11a一样，可以在上电组件11b维持始终上电状态的时候处于下电状态，以节省功耗。
能够与移动终端10配合实现刷卡功能的读卡设备20会向外发射符合预设条件的通信信号，该通信信号用于使得读卡设备20周围的移动终端10能够感知到该读卡设备20的存在。例如，读卡设备20持续向外发射通信信号，或者每隔预设时间间隔向外发射一次通信信号。移动终端10中的通信单元12在接收到通信信号之后，检测该通信信号是否符合预设条件，若该通信信号符合预设条件，则向上电组件11b输出第一上电信号。示例性地，假设通信单元12是NFC芯片，则当NFC芯片接收到符合预设条件的通信信号时，通过通用输入/输出(General Purpose Input Output，GPIO)接口向上电组件11b输出第一上电信号。其中，上电组件11b上设置有用于获取第一上电信号的GPIO接口。第一上电信号用于触发上电组件11b控制处理器11a上电。
可选地，预设条件为通信信号中包括预设标识。预设标识用于供移动终端10中的通信单元12辨识其接收到的通信信号是否为与自身提供的刷卡功能相关的通信信号。例如，移动终端10中的通信单元12检测到的通信信号中包括与公交刷卡功能相关的预设标识，则通信单元12辨识出该预设标识之后，确定后续执行公交刷卡操作。或者， 预设条件为通信信号的频率在预设频段内。上述预设频段可以根据实际需求预先设定，例如该预设频段可以是NFC所使用的频段，也可以是NFC所使用的频段中的一个子频段。当然，在其它可能的实施方式中，预设条件还可以是通信信号的间隔为预设时长，该预设时长可以是一个数值，也可以是一个取值范围。在实际应用中，预设条件可根据实际需求预先设定，以确保通信单元12能够准确地辨识出与自身提供的刷卡功能相关的通信信号和其它无关的通信信号即可。当通信单元12为短距离通信芯片时，例如NFC芯片，通信信号可以是射频信号。
上电组件11b，用于获取来自通信单元12的第一上电信号，并触发处理器11a上电。
可选地，上电组件11b通过如下方式触发处理器11a上电：上电组件11b输出第二上电信号至PMU 13，该第二上电信号用于触发PMU 13向处理器11a供电。PMU 13获取来自上电组件11b的第二上电信号，并根据该第二上电信号向处理器11a供电。
可选地，上电组件11b包括第一寄存器。上电组件11b还用于在获取到第一上电信号之后，在第一寄存器中写入用于指示控制SE 11c上电的SE上电指示信息。例如，上电组件11b在第一寄存器中写入的SE上电指示信息为“01”，用于指示处理器11a控制SE 11c上电。
处理器11a，用于在上电组件11b触发下从第一下电状态切换至第一上电状态，从上电组件11b获取SE上电指示信息，并根据SE上电指示信息控制SE 11c上电。
第一下电状态可以是完全下电状态，也可以是低功耗状态，而第一上电状态为通电状态。可选地，处理器11a从上电组件11b的第一寄存器中获取SE上电指示信息。
可选地，处理器11a通过如下方式控制SE 11c上电：处理器11a向PMU 13发送第三上电信号，第三上电信号用于指示PMU 13向SE 11c供电。PMU 13接收来自处理器11a的第三上电信号，并根据该第三上电信号向SE 11c供电。
SE 11c，用于在处理器11a的控制下从第二下电状态切换至第二上电状态，与通信单元12交互安全通信数据，并对安全通信数据进行安全处理。
第二下电状态可以是完全下电状态，也可以是低功耗状态，而第二上电状态为通电状态。示例性地，当读卡设备20为POS机时，SE 11c上电后，与通信单元12进行通信并交互支付信息，同时对支付信息进行安全处理，而通信单元12与POS机通信，完成刷卡支付操作；当读卡设备20为公交卡读卡器时，SE 11c上电后，与通信单元12进行通信并交互公交卡信息，同时对公交卡信息进行安全处理，而通信单元12与公交卡读卡器通信，完成公交刷卡操作；当读卡设备20为门禁卡读卡器时，SE 11c上电后，与通信单元12进行通信并交互门禁信息，同时对门禁信息进行安全处理，而通信单元12与门禁卡读卡器通信，完成门禁刷卡操作。
本申请实施例提供的方案中，针对内置SE的方案，通过通信单元12在接收到符合预设条件的通信信号时向上电组件11b输出第一上电信号，从而触发处理器11a上电，以使得与处理器11a集成于同一芯片上的SE 11c上电启动，进而与通信单元12交互安全通信数据并对其进行安全处理，能够在处理器11a下电之后依然触发SE 11c上电进行安全处理，在尽量节省功耗的前提下不影响安全功能的使用。
下述为本申请方法实施例，方法实施例与上文产品实施例相对应。对于本申请产品实施例中未描述的内容，可参见本申请方法实施例；同样地，对于本申请方法实施例中未描述的内容，可参见本申请产品实施例。
请参考图4，其示出了本申请一个实施例提供的控制SE的方法的流程图。该方法可应用于图2所示的移动终端10中。该方法可以包括如下几个步骤：
步骤401，通信单元12接收符合预设条件的通信信号，并根据通信信号输出第一上电信号至上电组件11b。
在移动终端10处于第一关机状态下，通信单元12处于通电状态，能够接收读卡设备20发出的通信信号。当通信单元12接收到符合预设条件的通信信号时，向上电组件11b输出第一上电信号，该第一上电信号用于指示上电组件11b触发处理器11a上电。
步骤402，上电组件11b获取来自通信单元12的第一上电信号，并触发处理器11a上电。
上电组件11b获取到第一上电信号之后，自动触发处理器11a上电。可选地，上电组件11b包括第一寄存器。上电组件11b在获取到第一上电信号之后，在第一寄存器中写入用于指示控制SE 11c上电的SE上电指示信息。
步骤403，处理器11a在上电组件11b触发下从第一下电状态切换至第一上电状态，从上电组件11b获取SE上电指示信息，并根据SE上电指示信息控制SE 11c上电。
处理器11a在从第一下电状态切换至第一上电状态之后，从上电组件11b获取指示信息，根据该指示信息执行后续操作。可选地，处理器11a从上电组件11b的第一寄存器中获取指示信息。若处理器11a获取到的指示信息为SE上电指示信息，则表示处理器11a是在移动终端10处于第一关机状态的情况下被触发上电的，处理器11a控制SE 11c上电启动。
另外，若处理器11a获取到的指示信息为正常开机指示信息，则表示处理器11a是在按键开机、定时开机或者充电开机等情况下被触发上电的，则处理器11a执行正常开机操作。其中，正常开机操作包括启动操作系统和显示用户界面(User Interface，UI)。
步骤404，SE 11c在处理器11a的控制下从第二下电状态切换至第二上电状态，与通信单元12交互安全通信数据，并对安全通信数据进行安全处理。
SE 11c在从第二下电状态切换至第二上电状态之后，与通信单元12通信并交互安全通信数据，完成刷卡操作。其中，SE 11c对安全通信数据进行安全处理，其目的是为了确保与通信单元12之间交互的数据的安全性。例如，对安全通信数据进行加解密、消息认证码(Message Authentication Code，MAC)运算或解MAC运算等安全运算处理。
可选地，SE 11c在上电启动之后，能够通过单线协议(Single Wire Protocol，SWP)与通信单元12进行通信，从而接收并响应通信单元12发送的刷卡操作所需的应用协议数据单元(Application Protocol Data Unit，APDU)命令。
可选地，通信单元12为NFC芯片。SE 11c在与NFC芯片通信，完成刷卡操作时， NFC芯片能够执行卡模拟操作，卡模拟操作是指NFC芯片模拟所要进行刷卡操作的卡信号，从而进行刷卡。
本申请实施例提供的方案中，针对内置SE的方案，通过通信单元12在接收到符合预设条件的通信信号时向上电组件11b输出第一上电信号，从而触发处理器11a上电，以使得与处理器11a集成于同一芯片上的SE 11c上电启动，进而与通信单元12交互安全通信数据并对其进行安全处理，能够在处理器11a下电之后依然触发SE 11c上电进行安全处理，在尽量节省功耗的前提下不影响安全功能的使用。
请参考图5，其示出了本申请另一个实施例提供的控制SE的方法的流程图。该方法可应用于图2所示的移动终端10中。该方法可以包括如下几个步骤：
步骤501，通信单元12接收符合预设条件的通信信号，并根据通信信号输出第一上电信号至上电组件11b。
步骤502，上电组件11b获取来自通信单元12的第一上电信号，并触发处理器11a上电。
上述步骤501和步骤502与图4实施例中的步骤401和步骤402相同，参见图4实施例中的介绍说明，本实施例对此不再赘述。
步骤503，处理器11a运行处理器ROM程序，通过处理器ROM程序运行引导程序。
处理器11a在上电启动之后，运行处理器ROM程序，处理器ROM程序存储在对应于处理器11a的只读存储器(Read-Only Memory，ROM)中，该ROM可在第一半导体芯片11中。处理器ROM程序是指用于判断处理器11a是否需要运行引导程序。处理器11a通过处理器ROM程序判断其被触发上电时移动终端10是否处于第一关机状态；若是，则运行引导程序；若否，则执行正常开机操作。引导程序用于控制处理器11a执行与第一关机状态相关的操作，例如在第一关机状态下控制SE 11c上电。若处理器11a通过处理器ROM程序判断出其被触发上电时移动终端10不处于第一关机状态，则表明移动终端10在处于正常关机状态下被触发上电，所以处理器11a执行正常开机操作。可选地，正常关机状态是指移动终端10中的所有元器件都处于断电状态的情况。
可选地，上电组件11b中还包括第二寄存器。当处理器11a控制移动终端10进入第一关机状态时，在上电组件11b的第二寄存器中写入第一状态数据，该第一状态数据用于指示处理器11a被触发上电时移动终端10处于第一关机状态。处理器11a在上电启动之后，运行处理器ROM程序，通过处理器ROM程序从上述第二寄存器中获取第一状态数据，并根据第一状态数据确定其被触发上电时移动终端10正处于第一关机状态。另外，当处理器11a控制移动终端10进入正常关机状态时，在上电组件11b中的第二寄存器中写入第二状态数据，该第二状态数据用于指示处理器11a被触发上电时移动终端10不处于第一关机状态。处理器11a在上电启动之后，运行处理器ROM程序，通过处理器ROM程序从上述第二寄存器中获取第二状态数据，并根据该第二状态数据确定其被触发上电时移动终端10不处于第一关机状态
在一种可能的实施方式中，处理器11a确定其被触发上电时移动终端10正处于第 一关机状态之后，通过存储控制器从第一半导体芯片11外部的存储器中获取引导程序，并校验该引导程序的合法性，以确保数据安全。
在另一种可能的实施方式中，当处理器11a控制移动终端10进入第一关机状态时，通过存储控制器获取存储在第一半导体芯片11外部的存储器中的引导程序，并校验该引导程序的合法性，以确保数据安全，再将该引导程序存储到上电组件11b的RAM中。处理器11a确定其被触发上电时移动终端10处于第一关机状态后，从上电组件11b的RAM中获取引导程序。
步骤504，处理器11a通过引导程序从上电组件11b获取SE上电指示信息，并控制SE 11c上电。
处理器11a通过引导程序从上电组件11b的第一寄存器中获取SE上电指示信息，并根据SE上电指示信息控制SE 11c上电启动。
可选地，处理器11a在获取SE上电指示信息后，通过引导程序将SE 11c的执行程序从第一半导体芯片11外部的存储器加载至第一半导体芯片11内部的存储器中，处理器11a能够通过第一半导体芯片11中的存储控制器访问第一半导体芯片11外部的存储器。SE 11c的执行程序可以是COS。在本实施例中，SE 11c的执行程序存储在第一半导体芯片11外部的存储器中，通过从第一半导体芯片11外部的存储器获取SE11c的执行程序，可以节省SE 11c的存储空间，使得SE 11c能够设计地更加轻薄化。在其它可能的实施例中，SE 11c的执行程序也可以存储在SE 11c内部的存储器中，或者存储在第一半导体芯片11内部的存储器中。
步骤505，SE 11c运行SE 11c的ROM程序，通过SE 11c的ROM程序加载SE 11c的执行程序。
SE 11c在上电启动之后，运行SE 11c的ROM程序，SE 11c的ROM程序用于加载SE 11c的执行程序。SE 11c的ROM程序存储在SE 11c内部的ROM中。
SE 11c将其执行程序从第一半导体芯片11内部的存储器加载至SE 11c内部的存储器中。SE 11c无法直接从第一半导体芯片11外部的存储器中加载SE 11c的执行程序，因此由处理器11a从第一半导体芯片11外部的存储器中加载SE 11c的执行程序至第一半导体芯片11内部的存储器中，SE 11c再通过SE 11c的ROM程序从第一半导体芯片11内部的存储器中加载其执行程序至SE 11c内部的存储器中，并运行该执行程序。
可选地，SE 11c的执行程序可以是镜像文件，镜像文件将特定的一系列文件按照一定的格式制作成单一的文件，以方便加载和运行。
可选地，由SE 11c中的处理器运行SE 11c的ROM程序，SE 11c将其执行程序加载到SE 11c的RAM中，并由SE 11c的处理器运行。
可选地，SE 11c运行SE 11c的ROM程序或其执行程序前，校验所要运行的程序的合法性，以确保数据安全。示例性地，以SE 11c的执行程序为例，若校验结果为SE 11c的执行程序合法，则SE 11c运行该执行程序；若校验结果为SE 11c的执行程序不合法，则SE 11c不运行该执行程序。
步骤506，SE 11c通过其执行程序与通信单元12交互安全通信数据，并对安全通信数据进行安全处理。
SE 11c运行其执行程序后，与通信单元12进行通信，在通信的过程中，SE 11c能够通过与处理器11a的交互从第一半导体芯片11外部的存储器中读取需要发送给通信单元12的数据，同时SE 11c能够通过与处理器11a的交互将从通信单元12接收的数据写入第一半导体芯片11外部的存储器中。
可选地，SE 11c在运行其执行程序后，通过进程间通信(Inter-Process Communication，IPC)、邮箱内存(Mailbox)与处理器11a进行交互，以访问存储在第一半导体芯片11外部的存储器中的数据。邮箱内存也可以被一个总线桥代替，无论邮箱内存还是总线桥都是处理器11a与SE 11c之间的专用交互通道。
在本实施例中，SE 11c是一个独立于处理器11a之外的硬件，可实现各类安全业务的处理。与传统的安全区域(Trustzone)或可信执行环境(Trusted Execution Environment，TEE)不同，SE 11c进行安全处理的各类计算可不依赖于处理器11a。例如，SE 11c中包括专用于安全处理的处理器，用于运行COS或给予COS的安全应用程序。再例如，SE 11c中还可包括安全处理专用的存储器，如RAM或ROM等，以及专用于安全处理的各类硬件加速器，如密钥生成器、加解密器件、哈希(Hash)运算器件或一次性可编程(One Time Programable，OTP)存储器。再例如，SE 11c与第一半导体芯片11中的其他一个或多个器件之间存在安全隔离以使得其他一个或多个器件无法随意访问SE 11c中存储或运行的数据。在一种典型的方案中，SE 11c与处理器11a之间存在安全隔离。在上述安全隔离下，处理器11a无法随意访问SE 11c中存储或运行的数据。在上述安全隔离下，SE 11c和处理器11a或其他器件之间的数据交互均需通过之前提到的专用交互通道。上述专用交互通道包括但不限于之前所述的邮箱内存和总线桥。
SE 11c和通信单元12交互安全通信数据可以用于刷卡操作。在完成刷卡操作之后，移动终端10可以恢复至第一关机状态，所以处理器11a可以在完成刷卡操作之后执行第三关机操作，第三关机操作包括控制处理器11a和SE 11c下电，维持上电组件11b处于通电状态。当处理器完成第三关机操作后，在第一半导体芯片中仅存在上电组件11b处于通电状态。
在一种可能的实施方式中，在SE 11c上电启动后，处理器11a经过预设时长后执行第三关机操作。处理器11a能够通过引导程序在预设时长之后执行第三关机操作。示例性地，假设预设时长为10秒，则处理器11a在SE 11c上电启动10秒后通过引导程序执行第三关机操作。
在另一种可能的实施方式中，在SE 11c上电启动后，处理器11a启动定时时钟，在接收到SE 11c发送的重置命令时，处理器11a重置定时时钟，当定时时钟超时时，处理器11a执行第三关机操作。SE 11c与通信单元12通信时，每接收到来自通信单元12的信号，则向处理器11a发送重置命令，处理器11a接收到重置命令，则通过引导程序重置定时时钟。
通过上述两种方式，实现了在完成刷卡操作之后自动进入第一关机状态，避免浪费移动终端10的电量。此外，在上述自动关机的过程中，若处理器11a接收到正常开机的触发信号，则不再执行关机操作，直接执行正常开机操作。
可选地，第一半导体芯片11中的处理器11a是芯片的控制器件，可以是CPU或 MCU，因为MCU耗电较小，所以使用MCU作为处理器11a有助于降低关机刷卡时第一半导体芯片11的功耗。当处理器11a是MCU时，系统中，即第一半导体芯片11中还存在其他CPU，此时，该其他CPU是第一半导体芯片11的主核，而处理器11a的功耗低于上述主核，其相当于是一个低功耗核。此时，主核是应用处理器，用于运行例如安卓一类的操作系统和基于该操作系统的应用程序软件。示例性地，处理器11a仅用于实现必要控制功能，例如对于整个第一半导体芯片11或其中部分器件的功耗控制，不用于运行复杂的操作系统和应用程序。所述功耗控制包括但不限于时钟频率、工作电压或工作电流的调整。进一步地，SE 11c的功耗可以低于处理器11a。
本申请实施例提供的方案中，针对内置SE的方案，通过通信单元12在检测到符合预设条件的通信信号时向上电组件11b输出第一上电信号，从而触发处理器11a上电，以使得与处理器11a集成于同一芯片上的SE上电启动，进而与通信单元12交互安全通信数据并对其进行安全处理，能够在处理器11a下电之后依然触发SE上电进行安全处理，在尽量节省功耗的前提下不影响安全功能的使用。
上文实施例介绍了在第一关机状态下控制SE 11c的方法，下述图6实施例将介绍控制移动终端10进入第一关机状态以及从第一关机状态进入正常关机状态的过程。请参考图6，该过程可以包括如下几个步骤：
步骤601，处理器11a执行第一关机操作。
在本申请实施例中，用户可以通过移动终端10中的配置项，选择是否开启进入第一关机状态的功能。若开启，则移动终端10进行关机时，处理器11a执行第一关机操作，使得移动终端10进入第一关机状态，从而能够实现关机刷卡功能。其中，第一关机操作包括：控制处理器11a和SE 11c下电。可选地，第一关机操作除了需要控制处理器11a和SE 11c下电，还需要控制移动终端10中除通信单元12和PMU 13外的其它元器件下电。
在一种可能的实施方式中，处理器11a在接收到PMU 13发送的第一关机信号时，执行第一关机操作，第一关机信号由PMU 13在检测到电池电量小于第一预设阈值时向处理器11a发送。其中第一预设阈值可以根据实际经验设定。示例性地，电池电量为3000mAh，第一预设阈值为150mAh，当电池电量小于150mAh时，处理器11a执行第一关机操作，使得移动终端10进入第一关机状态，同时确保了移动终端10仍有150mAh的电量用于关机刷卡。
在另一种可能的实施方式中，处理器11a在检测到用户触发的第二关机信号时，执行第一关机操作，第二关机信号是用户手动关机操作触发的信号，例如，用户长按电源键进行关机时会触发第二关机信号，则处理器11a在检测到第二关机信号时，执行第一关机操作。
步骤602，PMU 13在检测到电池电量小于第二预设阈值时，输出第四上电信号至上电组件11b。
在移动终端10进入第一关机状态之后，由于上电组件11b、PMU 13和通信单元12仍处于通电状态，所以移动终端10仍然在消耗电池的电量。当电池电量低于第二预设阈值时，PMU 13向上电组件11b输出第四上电信号。其中，第二预设阈值可以 根据实际经验设定，也可以根据用户需求设定，并且第二预设阈值小于第一预设阈值。
步骤603，上电组件11b获取来自PMU13的第四上电信号，并触发处理器11a上电。
可选地，上电组件11b包括第一寄存器。上电组件11b在获取到第四上电信号之后，在第一寄存器中写入用于指示执行第二关机操作的关机指示信息。例如，上电组件11b在第一寄存器中写入的关机指示信息为“11”，用于指示处理器11a执行第二关机操作。
步骤604，处理器11a在上电组件11b触发下从第一下电状态切换至第一上电状态，从上电组件11b获取关机指示信息，并根据关机指示信息执行第二关机操作。
处理器11a执行第二关机操作，使得移动终端10进入正常关机状态。第二关机操作包括：控制处理器11a、SE 11c和上电组件11b下电。可选地，第二关机操作还包括：控制PMU 13和通信单元12下电。
在本申请实施例中，在移动终端进入能够关机刷卡的第一关机状态后，通过PMU13检测电池电量，当电池电量低于第二预设阈值时，PMU 13向上电组件11b输出第四上电信号，使得上电组件11b触发处理器11a上电，通过处理器11a执行第二关机操作，让移动终端进入正常关机状态。通过上述方式，避免移动终端在第一关机状态消耗完电量，以便留有一部分电量供后续(如拨打紧急电话、启动关机闹钟等)使用。
上述图6实施例介绍了控制移动终端10从第一关机状态进入正常关机状态的一种可能情形。下述图7实施例将介绍另一种控制移动终端10从第一关机状态进入正常关机状态的情形。请参考图7，其可以包括如下几个步骤：
步骤701，处理器11a执行第一关机操作。
上述步骤701与图6实施例中的步骤601相同，参见图6实施例中的介绍说明，本实施例对此不再赘述。
步骤702，上电组件11b在处理器11a执行第一关机操作之后启动定时器。
上电组件11b在处理器11a执行第一关机操作之后启动定时器，即当移动终端10进入第一关机状态后，上电组件11b启动定时器，开始计时。
步骤703，当定时器超时时，上电组件11b触发处理器11a上电。
当移动终端10进入第一关机状态后经过定时器设置的时长后，上电组件11b触发处理器11a上电。可选地，上电组件11b包括第一寄存器。上电组件11b在定时器超时时在第一寄存器中写入用于指示执行第二关机操作的关机指示信息。
步骤704，处理器11a在上电组件11b触发下从第一下电状态切换至第一上电状态，从上电组件11b获取关机指示信息，并根据关机指示信息执行第二关机操作。
上述步骤704与图6实施例中的步骤604相同，详情请参见图6实施例中的介绍说明，本实施例对此不再赘述。
在本申请实施例中，在移动终端进入能够关机刷卡的第一关机状态后，通过定时器计时，经过定时器设置的时长后，上电组件11b控制处理器11a上电，通过处理器11a执行第二关机操作，让移动终端进入正常关机状态。通过上述方式，能够根据用户需求设置移动终端进入第一关机状态的时长，避免移动终端保持第一关机状态过长 时间而导致移动终端在第一关机状态消耗完电量，以便留有一部分电量供后续(如拨打紧急电话、启动关机闹钟等)使用。
本申请一示例性实施例还提供了一种芯片，也即上文介绍的第一半导体芯片11，该芯片包括如之前实施例提到的SE 11c、处理器11a和上电组件11b。
本申请一示例性实施例还提供了一种控制SE的方法，该方法应用于第一半导体芯片11中，如图8所示，该方法包括如下几个步骤：
步骤801，上电组件11b接收PMU 13的供电，接收来自通信单元12的第一上电信号，并触发处理器11a上电。
步骤802，处理器11a在上电组件11b触发下接收PMU 13的供电并从第一下电状态切换至第一上电状态，从上电组件11b获取SE上电指示信息，并根据SE上电指示信息控制SE 11c上电。
步骤803，SE 11c在处理器11a的控制下接收PMU 13的供电并从第二下电状态切换至第二上电状态，与通信单元12交互安全通信数据，并对安全通信数据进行安全处理。
有关上述两个实施例的介绍说明，参见上文相应内容的介绍说明，此处不再赘述。
本申请一示例性实施例还提供了一种计算机程序产品，该计算机程序产品可以被存放于RAM、闪存、ROM、可擦除可编程只读存储器(Erasable Programmable ROM，EPROM)、电可擦可编程只读存储器(Electrically EPROM，EEPROM)、寄存器、或者本领域熟知的任何其它形式的存储介质中，当该计算机程序产品被处理器11a执行时，用于实现上述实施例中处理器11a侧的方法步骤。
本申请一示例性实施例还提供了一种计算机程序产品，该计算机程序产品可以被存放于RAM、闪存、ROM、EPROM、EEPROM、寄存器、或者本领域熟知的任何其它形式的存储介质中，当该计算机程序产品被SE 11c执行时，用于实现上述实施例中SE 11c侧的方法步骤。
以上所述的具体实施方式，对本申请实施例的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请实施例的具体实施方式而已，并不用于限定本申请实施例的保护范围，凡在本申请实施例的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请实施例的保护范围之内。

Claims (21)

  1. 一种控制安全元件SE的系统，其特征在于，包括SE、处理器、上电组件、电源管理单元PMU和通信单元；所述SE、处理器、上电组件位于第一半导体芯片内；
    所述通信单元，用于接收符合预设条件的通信信号，并根据所述通信信号输出第一上电信号至所述上电组件；
    所述上电组件，用于获取来自所述通信单元的所述第一上电信号，并触发所述处理器上电；
    所述处理器，用于在所述上电组件触发下从第一下电状态切换至第一上电状态，以及从所述上电组件获取SE上电指示信息，并根据所述SE上电指示信息控制所述SE上电；
    所述SE，用于在所述处理器的控制下从第二下电状态切换至第二上电状态，与所述通信单元交互安全通信数据，并对所述安全通信数据进行安全处理；
    所述PMU，用于为所述处理器、所述SE、所述上电组件和所述通信单元供电。
  2. 根据权利要求1所述的系统，其特征在于，
    在所述上电组件用于触发所述处理器上电的方面，所述上电组件具体用于输出第二上电信号至所述PMU；
    所述PMU，用于获取来自所述上电组件的所述第二上电信号，并根据所述第二上电信号向所述处理器供电。
  3. 根据权利要求1或2所述的系统，其特征在于，
    在所述处理器用于控制所述SE上电的方面，所述处理器具体用于向所述PMU发送第三上电信号；
    所述PMU，用于接收来自所述处理器的所述第三上电信号，并根据所述第三上电信号向所述SE供电。
  4. 根据权利要求1至3中任一项所述的系统，其特征在于，
    所述PMU，还用于当检测到电池电量小于第一预设阈值时，向所述处理器发送第一关机信号；
    所述处理器，还用于接收来自所述PMU的所述第一关机信号，并根据所述第一关机信号执行第一关机操作，其中，所述第一关机操作包括：控制所述处理器和所述SE下电。
  5. 根据权利要求4所述的系统，其特征在于，
    所述PMU，还用于当检测到所述电池电量小于第二预设阈值时，输出第四上电信号至所述上电组件，所述第二预设阈值小于所述第一预设阈值；
    所述上电组件，还用于获取来自所述PMU的所述第四上电信号，并触发所述处理器上电；
    所述处理器，还用于在所述上电组件触发下从所述第一下电状态切换至所述第一 上电状态，从所述上电组件获取关机指示信息，并根据所述关机指示信息执行第二关机操作，所述第二关机操作包括：控制所述处理器、所述SE和所述上电组件下电。
  6. 根据权利要求4或5所述的系统，其特征在于，
    所述上电组件，还用于在所述处理器执行所述第一关机操作之后启动定时器；当所述定时器超时时，触发所述处理器上电；
    所述处理器，还用于在所述上电组件触发下从所述第一下电状态切换至所述第一上电状态，以及从所述上电组件获取关机指示信息，并根据所述关机指示信息执行第二关机操作，所述第二关机操作包括：控制所述处理器、所述SE和所述上电组件下电。
  7. 根据权利要求1至6中任一项所述的系统，其特征在于，所述预设条件为所述通信信号中包括预设标识，或者，所述预设条件为所述通信信号的频率在预设频段内。
  8. 根据权利要求1至7中任一项所述的系统，其特征在于，
    所述处理器，还用于在从所述上电组件获取所述SE上电指示信息之后，将所述SE的执行程序从所述第一半导体芯片外部的存储器加载至所述第一半导体芯片内部的存储器中；
    所述SE，还用于在所述处理器的控制下从所述第二下电状态切换至所述第二上电状态之后，将所述执行程序从所述第一半导体芯片内部的存储器加载至所述SE内部的存储器中，并运行所述执行程序以实现与所述通信单元交互安全通信数据，并对所述安全通信数据进行安全处理的功能。
  9. 根据权利要求1至8中任一项所述的系统，其特征在于，所述处理器，还用于：
    在所述SE上电之后经过预设时长执行第三关机操作；
    或者，
    在所述SE上电之后启动定时时钟，在接收到所述SE发送的重置命令时，重置所述定时时钟，其中，所述SE每接收到来自所述通信单元的信号时，向所述处理器发送所述重置命令，当所述定时时钟超时时，执行所述第三关机操作；
    其中，所述第三关机操作包括控制所述处理器和所述SE下电，维持所述上电组件处于通电状态。
  10. 一种控制安全元件SE的方法，其特征在于，所述方法包括：
    通信单元接收符合预设条件的通信信号，并根据所述通信信号输出第一上电信号至第一半导体芯片内的上电组件；
    所述上电组件获取来自所述通信单元的所述第一上电信号，并触发所述第一半导体芯片内的处理器上电；
    所述处理器在所述上电组件触发下从第一下电状态切换至第一上电状态，从所述上电组件获取SE上电指示信息，并根据所述SE上电指示信息控制所述第一半导体芯 片内的SE上电；
    所述SE在所述处理器的控制下从第二下电状态切换至第二上电状态，与所述通信单元交互安全通信数据，并对所述安全通信数据进行安全处理；
    通过PMU为所述处理器、所述SE、所述上电组件和所述通信单元供电。
  11. 根据权利要求10所述的方法，其特征在于，所述方法还包括：
    当所述PMU检测到电池电量小于第一预设阈值时，所述PMU向所述处理器发送第一关机信号；
    所述处理器接收来自所述PMU的所述第一关机信号，并根据所述第一关机信号执行第一关机操作，所述第一关机操作包括：控制所述处理器和所述SE下电。
  12. 根据权利要求11所述的方法，其特征在于，所述方法还包括：
    当所述PMU检测到所述电池电量小于第二预设阈值时，所述PMU输出第四上电信号至所述上电组件；
    所述上电组件获取来自所述PMU的所述第四上电信号，并触发所述处理器上电；
    所述处理器在所述上电组件触发下从所述第一下电状态切换至所述第一上电状态，从所述上电组件获取关机指示信息，并根据所述关机指示信息执行第二关机操作，所述第二关机操作包括：控制所述处理器、所述SE和所述上电组件下电。
  13. 根据权利要求11或12所述的方法，其特征在于，所述方法还包括：
    所述上电组件在所述处理器执行所述第一关机操作之后启动定时器；
    当所述定时器超时时，所述上电组件触发所述处理器上电；
    所述处理器在所述上电组件触发下从所述第一下电状态切换至所述第一上电状态，从所述上电组件获取关机指示信息，并根据所述关机指示信息执行第二关机操作，所述第二关机操作包括：控制所述处理器、所述SE和所述上电组件下电。
  14. 一种芯片，其特征在于，包括安全元件SE、处理器和上电组件；
    所述上电组件，耦合于通信单元和电源管理单元PMU，用于接收所述PMU的供电，接收来自所述通信单元的第一上电信号，并触发所述处理器上电；
    所述处理器，耦合于所述上电组件、所述SE和所述PMU，用于在所述上电组件触发下接收所述PMU的供电并从第一下电状态切换至第一上电状态，以及从所述上电组件获取SE上电指示信息，并根据所述SE上电指示信息控制所述SE上电；
    所述SE，耦合于所述通信单元、所述处理器和所述PMU，用于在所述处理器的控制下接收所述PMU的供电并从第二下电状态切换至第二上电状态，与所述通信单元交互安全通信数据，并对所述安全通信数据进行安全处理。
  15. 根据权利要求14所述的芯片，其特征在于，
    在所述上电组件用于触发所述处理器上电的方面，所述上电组件具体用于输出第二上电信号至所述PMU，以指示所述PMU向所述处理器供电。
  16. 根据权利要求14或15所述的芯片，其特征在于，
    在所述处理器用于控制所述SE上电的方面，所述处理器具体用于向所述PMU发送第三上电信号，以指示所述PMU向所述SE供电。
  17. 根据权利要求14至16中任一项所述的芯片，其特征在于，
    所述处理器，还用于接收来自所述PMU的第一关机信号，并根据所述第一关机信号执行第一关机操作，所述第一关机操作包括：控制所述处理器和所述SE下电。
  18. 根据权利要求17所述的芯片，其特征在于，
    所述上电组件，还用于获取来自所述PMU的第四上电信号，并触发所述处理器上电；
    所述处理器，还用于在所述上电组件触发下从所述第一下电状态切换至所述第一上电状态，从所述上电组件获取关机指示信息，并根据所述关机指示信息执行第二关机操作，所述第二关机操作包括：控制所述处理器、所述SE和所述上电组件下电。
  19. 根据权利要求17或18所述的芯片，其特征在于，
    所述上电组件，还用于在所述处理器执行所述第一关机操作之后启动定时器；当所述定时器超时时，触发所述处理器上电；
    所述处理器，还用于在所述上电组件触发下从所述第一下电状态切换至所述第一上电状态，以及从所述上电组件获取关机指示信息，并根据所述关机指示信息执行第二关机操作，所述第二关机操作包括：控制所述处理器、所述SE和所述上电组件下电。
  20. 根据权利要求14至19中任一项所述的芯片，其特征在于，
    所述处理器，还用于在从所述上电组件获取所述SE上电指示信息之后，将所述SE的执行程序从所述第一半导体芯片外部的存储器加载至所述第一半导体芯片内部的存储器中；
    所述SE，还用于在所述处理器的控制下从所述第二下电状态切换至所述第二上电状态之后，将所述执行程序从所述第一半导体芯片内部的存储器加载至所述SE内部的存储器中，并运行所述执行程序以实现与所述通信单元交互安全通信数据，并对所述安全通信数据进行安全处理的功能。
  21. 根据权利要求14至20中任一项所述的芯片，其特征在于，所述处理器，还用于：
    在所述SE上电之后经过预设时长执行第三关机操作；
    或者，
    在所述SE上电之后启动定时时钟，在接收到所述SE发送的重置命令时，重置所述定时时钟，其中，所述SE每接收到来自所述通信单元的信号时，向所述处理器发 送所述重置命令，当所述定时时钟超时时，执行所述第三关机操作；
    其中，所述第三关机操作包括控制所述处理器和所述SE下电，维持所述上电组件处于通电状态。
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