WO2019094052A1

WO2019094052A1 - Socs with group iv and group iii-nitride devices on soi substrates

Info

Publication number: WO2019094052A1
Application number: PCT/US2017/061360
Authority: WO
Inventors: Reinhard Mahnkopf; Andreas Wolter; Han Wui Then
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2017-11-13
Filing date: 2017-11-13
Publication date: 2019-05-16
Anticipated expiration: 2020-05-13

Abstract

A semiconductor-on-insulator (SOI) substrate includes a (111) crystalline substrate layer advantageous for seeding an epitaxial III-N material upon which III-N devices may be formed. The SOI substrate may further include another crystalline substrate layer that may have one or more of lower electrical resistivity or a different crystal orientation relative to the other crystalline substrate layer. A SOI substrate may include a (100) or (110) crystal advantageous for integrating Group IV devices, such as Si MOSFETs, for example. Regions of the SOI substrate may be patterned to remove the (100) or (110) crystal and expose the underlying (111) crystal for subsequent III-N heteroepitaxy. An amorphous material may be deposited over a sidewall of the (100) or (110) crystal exposed at a perimeter of the patterned region. III-N heteroepitaxy may proceed from the (111) crystal within an opening of the amorphous material.

Description

SOCs with Group IV and Group Ill-Nitride Devices On SOI Substrates

Demand for integrated circuits (ICs) in portable electronic applications has motivated greater levels of semiconductor device integration. Many advanced semiconductor devices in development leverage non-silicon semiconductor materials, a subset of which have wurtzite crystallinity. Exemplary wurtzite materials include the Group Ill-Nitride ("III-N" or IUPAC "13-N") materials. The III-N material system shows particular promise for high voltage and high frequency applications like power management ICs (PMJCs) and radio frequency (RF) power amplifiers (PAs) found in RFICs. III-N heterostructure field effect transistors (HFETs), such as high electron mobility transistors (HEMTs) and metal oxide semiconductor (MOS) HEMTs, employ a semiconductor heterostructure with one or more heterojunction. One heterojunction is often at an interface of a GaN semiconductor crystal and another IINN semiconductor alloy, such as AlGaN or AlInN. III-N HFET devices benefit from a relatively wide bandgap (~3.4eV), enabling higher breakdown voltages than Si-based MOSFETs, as well as high carrier mobility. The III-N material system is also useful for photonics (e.g., LEDs) and piezoelectric sensors, one or more of which may be useful to integrate with Si-based FETs into an electronic device platform.

Forming devices utilizing the wurtzite material system on large format silicon substrates is a challenge due to a large lattice mismatch (e.g., -41% between GaN and Si) and a large thermal expansion coefficient mismatch (e.g., ~116% between Si and GaN). However, from a commercial standpoint it is advantageous to integrate III-N transistors into the silicon device fabrication infrastructure to take advantage of the economies of scale brought by 300mm/450mm wafer processing as well as achieve the higher device performance possible with integrated system-on-chip (SOC) architectures.

BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in simplified "ideal" forms and geometries for clarity of discussion, but it is nevertheless to be understood that practical implementations may only approximate the illustrations. For example, smooth surfaces and square intersections may be drawn in disregard of finite roughness, corner-rounding, sloping sidewalls, and imperfect angular intersections characteristic of structures formed by nanofabrication techniques. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:

FIG. 1 is a flow diagram illustrating methods of integrating III-N HFET circuitry and Si-based FET circuitry, in accordance with some embodiments;

FIG. 2A is a plan view of illustrating regions on a semiconductor-on-insulator (SOI) substrate suitable for III-N HFET circuitry and surround regions suitable for Group IV-based FET circuitry, in accordance with some embodiments;

FIG. 2B is a cross-sectional view illustrating the semiconductor-on-insulator (SOI) substrate shown in FIG. 2A, in accordance with some embodiments;

FIG. 3 is a cross-sectional view illustrating a definition of first and second regions of a SOI substrate, in accordance with some embodiments;

FIG. 4 and 5 are cross-sectional views illustrating delineation of an amorphous growth mask, in accordance with some embodiments;

FIG. 6 is a cross-sectional view illustrating epitaxial growth of III-N material within a region of a SOI substrate, in accordance with some embodiments;

FIG. 7 and FIG. 8 are cross-sectional views illustrating deposition of an interlayer dielectric (ILD) material and formation of a III-N polarization layer, in accordance with some embodiments;

FIG. 9 is a cross-sectional view illustrating formation of a plurality of HFET terminals coupled to III-N material in one region of a SOI substrate, in accordance with some embodiments;

FIG. 10 is a cross-sectional view illustrating formation of a plurality of MOSFET terminals coupled to substrate material in another region of a SOI substrate, in accordance with some embodiments; FIG. 11 is a cross-section view illustrating a plurality of metallization levels interconnecting MOSFETs into CMOS circuitry, and III-N-based HFETs into HFET circuitry, in accordance with some embodiments;

FIG. 12 is a schematic illustrating a mobile computing platform and a data server machine employing an SoC including both III-N HFET circuitry and Si-based CMOS circuitry, in accordance with some embodiments; and

FIG. 13 is a functional block diagram illustrating an electronic computing device, in accordance with some embodiments.

DETAILED DESCRIPTION

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that the present invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms "over," "above," "under," "below," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material over or under another may be directly in contact or may have one or more intervening materials. One material "over" a second material has a footprint that overlaps at least a portion of the second material's footprint. One material "above" a second material is higher within a stack of materials, but footprints of the materials need not overlap. Moreover, one material between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of or "one or more of can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

Described herein are SOC structures including a semiconductor-on-insulator (SOI) substrate that has a (111) crystalline substrate layer advantageous for seeding an epitaxial III- N material with which III-N devices may be integrated into the SOC structures. The SOI substrate may further include another crystalline substrate layer that has a different crystal orientation than the other crystalline substrate layer. For example, the SOI substrate may include a (100) or (110) crystal that is advantageous for integrating Group IV devices, such as Si MOSFETs, into the SOC structures. Regions of the SOI substrate may be patterned to remove the (100) or (110) crystal and expose the underlying (111) crystal. An amorphous material may be deposited over a sidewall of the (100) or (110) crystal layer that is exposed at a perimeter of the patterned region. III-N heteroepitaxy may proceed from the (111) crystal within an opening of the amorphous material with the amorphous material serving as a growth mask preventing competitive III-N heteroepitaxial fronts from forming on the sidewall of the (100) or (110) crystal. In accordance with some embodiments, an SOI substrate layer employed as an epitaxial platform includes a (111) silicon layer. In some further embodiments, the (111) silicon layer may be recessed as needed to accommodate 1-5 microns of III-N buffer thickness while maintaining planarity between the HFET and MOSFET regions of an SOC. In some further embodiments, the (111) crystal layer may have high electrical resistivity, for example to reduce parasitic losses between MOSFET circuitry formed on the (100) or (110) crystal layer and other regions of the SOC. The (100) or (110) crystal layer may also include silicon (e.g., a silicon or silicon alloy layer) advantageous for forming Group IV logic devices (e.g., Si FETs). The (100) or (110) crystal layer may have higher conductivity than the (111) crystal layer, which may for example, mitigate fabrication issues associated with highly resistive substrates and/or facilitate CMOS multi-well architectures. FIG. 1 is a flow diagram illustrating methods 101 for fabricating an SOC that includes both Group IV MOSFET circuitry and III-N HFET circuitry, in accordance with some embodiments. Although methods 101 are described in the context of exemplary HFET embodiments, it will be appreciated that similar integration may be applied to other III-N based transistor architectures (e.g., any HEMT architecture), as well as other III-N based devices, such as, but not limited to, bipolar transistors and (light emitting) diodes. Likewise, although methods 101 are described in the context of exemplary finFET embodiments, it will be appreciated that similar integration may be applied to other Group IV-based transistor architectures (e.g., any planar MOSFET), as well as other Group IV-based devices, such as, but not limited to, bipolar transistors and diodes.

Methods 101 begin with receiving a SOI substrate at operation 105. The SOI substrate includes at least two crystalline material layers. At least the top crystal layer is patterned to expose the underlying crystal layer within predetermined regions of the substrate. Within these regions, III-N material is to be heteroepitaxially grown from the lower crystal layer. This III-N material is to host one or more III-N devices. Regions where the top crystal layer is retained are to host one or more Group IV devices. Interconnect metallization formed during back-end-of-line (BEOL) processing then couples the III-N devices and Group IV devices into a function integrated circuit (e.g., an SOC that includes both Group IV and III-N devices). Notably, methods 101 may be practiced over a range of substrate areas. In addition to an SOI substrate size varying (e.g., 300 mm or 450 mm diameter), the area of a SOI substrate of a given size (e.g., 300 mm diameter) that is apportioned to a III-N device region or to a Group IV device region may also vary with implementation.

FIG. 2A is a plan view illustrating a semiconductor-on-insulator (SOI) substrate portion 201 suitable for III-N devices within substrate regions 207 and Group IV-based devices within the surrounding regions 206, in accordance with some embodiments. Substrate portion 201 may correspond to a single SOC, a portion thereof, or multiple SOCs may be singulated from substrate portion 201. One or more island of III-N material is to be heteroepitaxially grown within each substrate region 207. In some embodiments, a continuous III-N material layer is formed within each substrate region 207. In other embodiments, III-N material growth may be confined to one or more smaller regions (e.g., through pinholes in a growth mask) within each substrate region 207 so that many discrete islands or mesas of III-N material may span the area of one substrate region 207. Each substrate region 207 may have lateral dimensions (e.g., x-y axes) ranging from a few microns on a side to many hundreds of microns. Although shown as substantially square, substrate regions 207 may be any arbitrary polygon. Substrate regions 207 are surrounded by substrate region 206 that is to be substantially free of III -N material. Portions of a crystal layer present within substrate 206 may be employed as channel material in a MOSFET, for example.

An SOC that includes the substrate regions 206 and 207 may implement any integrated circuitry. In some exemplary embodiments, MOSFETs in substrate region 206 implement a plurality of LED driver circuits, individual ones of which are coupled to one or more light emitters (e.g., LEDs) arrayed over one or more of the substrate regions 207. In some other embodiments, a FET in substrate region 206 implements CMOS logic circuitry coupled to a RF power amplifier (PA) implemented in one or more of the substrate regions 207. In some other embodiments, FETs in substrate regions 206 implement CMOS logic circuitry coupled to one or more high voltage (e.g., > 100V) switches implemented in one or more of the substrate regions 207.

In exemplary embodiments, the substrate received at operation 105 (FIG. 1) includes a top crystal layer that has a crystal orientation other than that of an underlying crystal layer. FIG. 2B is a cross-sectional view further illustrating the semiconductor-on-insulator (SOI) substrate shown in FIG. 2A along the A-A' line, in accordance with some embodiments. As shown in FIG. 2B, SOI substrate portion 201 includes a top substrate layer 215 over bottom substrate layer 205 with an intervening dielectric material 210 between crystalline substrate layers 205 and 215.

In some Group IV substrate embodiments, substrate layer 215 has (100) or (110) cubic crystal orientation. A top surface of substrate layer 215 may therefore be a (100) or (110) crystal plane of a group IV material having cubic crystallinity (e.g., Si, Ge, or SiGe alloy), which is well suited to the fabrication of silicon CMOS circuitry. In the illustrated example, substrate layer 215 is monocrystalline (100) silicon. Substrate layer 215 may have a wide range of thicknesses. In some embodiments, substrate layer 215 may have a thickness that is on the order of a predetermined height of a fin that is to be formed into substrate layer 215 (e.g., substrate layer 215 may be 100 nm, or less). In other embodiments, substrate layer 215 may have a thickness that is much greater than a predetermined height of a fin that is to be formed into substrate layer 215 (e.g., substrate layer 215 may be 1-2 μιτι, or more). As described further below, greater thicknesses may be leveraged to maintain planarity between substrate regions 206 and 207 following subsequent processing.

Substrate layer 215 may have any impurity doping that is suitable for hosting complementary MOS (CMOS) transistors. For example, substrate layer 215 may include donor or acceptor impurities that impart n-type or p-type conductivity. Exemplary impurities include phosphorus, arsenic (n-type dopants of silicon) and boron (p-type dopant of silicon). However, any known dopant species may be selected depending on the semiconductor material system. In some embodiments where substrate layer 215 is Si, substrate layer 215 includes a background level of acceptor impurities such that substrate layer 215 is p-type with a resistivity that is less than 500 ohm-cm, and may be less than 100 ohm-cm. In addition to facilitating CMOS multi-well fabrication, these lower resistivities may be beneficial because high-resistivity substrates can cause complications during the IC fabrication process. For example, plasma etching and plasma enhanced chemical vapor deposition (PECVD), for example, may induce a local build-up of electrical charges. A lower resistivity (higher conductivity) of substrate layer 205 may be leveraged to mitigate such issues. In some embodiments substrate layer 205 has a resistivity below 500 ohm-cm, and advantageously less than 100 ohm-cm.

Substrate layer 215 may further comprise regions (e.g., wells) having a conductivity type that is complementary to the background (e.g., n-type wells). Substrate layer 215 may have any of the attributes described above and may have all of the attributes described above. For example, in some embodiments substrate layer 215 is (100) silicon, with a thickness of at least 100 nm, and a resistivity less than 500 ohm-cm.

For the substrate portion 201 illustrated in FIG. 2B, substrate layer 205 is a portion of a "handle" wafer. In some of the exemplary Group IV substrate embodiments, substrate layer 205 has (111) crystal orientation. A top surface of the layer may therefore be a (111) crystal plane of a group IV material (e.g., Si, Ge, or SiGe alloy) having cubic crystallinity. A (111) surface of a group IV material (e.g., Silicon or SiGe) having cubic crystallinity offers a larger lattice spacing than other first order cubic crystal planes, such as (100) and (110). This larger lattice spacing is a better match with many materials with hexagonal/wurtzite crystallinity, including III-N semiconductor materials, and is therefore advantageous for seeding heteroepitaxial growths of such materials. Substrate layer 205 may however also have other crystallographic orientations. For example, a (111) silicon crystal surface may be miscut or offcut, for example 2-10° toward [110] or [100], exposing higher order planes. In the illustrated example, substrate layer 215 is monocrystalline silicon.

In some embodiments, substrate layer 205 has a higher electrical resistivity than substrate layer 215. For high frequency (e.g., GHz band) devices (e.g., RFICs), electrical resistance of the substrate material upon which an IC is fabricated is often important. As an IC's operating frequency increases, parasitic losses associated with the substrate become more substantial unless the resistivity of the substrate material is increased. In some embodiments where substrate layer 205 is silicon, the silicon is substantially undoped and has a resistivity over 500 ohm-cm, advantageously at least 1000 ohm-cm, and potentially 5000 ohm-cm, or higher. Substrate layer 205 is generally thicker than substrate layer 215.

Although there may be any number of substrate layers, in an embodiment where substrate layer 205 is a bulk crystalline handle wafer of a bi-layer SOI wafer. For such embodiments, substrate layer 205 may have any thickness ranging from tens to many hundreds of micrometers (e.g., 800 μηι). Substrate layer 205 may have any and all of the attributes described above. For example, in some embodiments substrate layer 205 is (111) silicon, with a thickness over 100 μιτι, and a resistivity over 500 ohm-cm.

Substrate dielectric material 210 may be any suitable dielectric material, such as a buried silicon dioxide (BOX) layer. Substrate dielectric material 210 may have any ratio of oxygen and silicon constituents, for example. Other dielectric material compositions are also possible, such as, but not limited to materials having a relative permittivity below 3.5, and even below 3.0. The thickness (z-dimension in FIG. 2B) of the layer of substrate dielectric material 210 may vary with implementation. The thickness may be targeted, for example, based on device performance parameters, such as a level electrical isolation between circuitry formed over substrate layer 215 and substrate layer 205. For example, where an SOC fabricated from SOI substrate portion 201 is to include nominally clocked CMOS circuitry over substrate layer 205, the layer of substrate dielectric material 210 may be thin (50-200 nm). Where an SOC fabricated from SOI substrate portion 201 is to include a high frequency RF circuit, the layer of substrate dielectric material 210 may be thick (e.g., 1-2 μιτι, or more) to provide better noise isolation at higher frequencies (e.g., > 2GHZ). As described further below, the thickness of the layer of substrate dielectric material 210 may also be designed to minimize non-planarity between substrate regions 206 and 207. Hence, even where not necessary for electrical isolation, the thickness of substrate dielectric material 210 may be multiple microns.

Returning to FIG. 1, methods 101 continue at operation 110 where portions of the SOI in which III-N devices are to be fabricated are defined. At operation 110, at least the top crystalline substrate layer is removed from within a first substrate region where the III-N material is to be subsequently grown. Operation 110 may be staged anywhere within a frontend MOS transistor fabrication process. For example, operation 110 may be performed before or after, or integrated into, any known shallow trench isolation (STI) process. The top crystalline substrate layer may be removed with any suitable masked etch. The underlying substrate dielectric may be similarly removed to expose the underlying crystalline substrate layer. At operation 120, an amorphous material is formed over at least the sidewall of the substrate layer(s) etched at operation 110. The amorphous material is to block, mask, or otherwise preclude growth of III-N material on the crystalline substrate layer sidewall during an III-N epitaxial growth operation 125. FIG. 3 is a cross-sectional view of a structure 301 illustrating first and second regions of a SOI substrate along the A-A' line following a selective removal of substrate layer 215, in accordance with some embodiments. In the example shown in FIG. 3, device structures have been fabricated within substrate region 206. STI processing has been performed to define fins 318 surrounded by STI material 316. STI material 316 may include one or more layers of any suitable dielectric material, such as, but not limited to, S1O2 or S13N4. Where substrate layer 215 has a thickness on the order of a desired total fin height, STI material 316 may extend through the entire thickness of substrate layer 215, as denoted by dashed lines 317.

Alternatively, where substrate layer 215 has a thickness greater than a desired total fin height, STI material 316 may only extend into a portion of substrate layer 215 such that fin 318 resides in an upper portion of substrate layer 215. In the illustrated example, structure 301 further includes a sacrificial gate mandrel 321 extending over a channel portion of fin 318. A hard mask 322 is over substrate layer 215 and may also be over gate mandrel 321. Hard mask 322 may be a dielectric material, such as, but not limited to, a compound of silicon and oxygen, such as S1O2. In other examples, hard mask 322 is SiON, SiOC(H). Within substrate region 207, substrate layer 215 and substrate dielectric material 210 have been removed, forming recess 330. Any etch process known to be suitable for the compositions of substrate layer 215 and substrate dielectric material 210 may be enlisted to form recess 330. Substrate layer 215 and substrate dielectric material 210 remain only within substrate region 206. In the illustrated embodiment, a (111) surface of substrate layer 205 is exposed within recess 330. Substrate layer sidewall 320 is also exposed along a perimeter of recess 330. The etch process employed to remove substrate layer 215 and dielectric material 210 may stop at any depth within substrate layer 205, as denoted in FIG. 3 by dashed line 350. Recess 330 may therefore have any depth (e.g., z-axis) relative to a top surface of substrate layer 215. In some embodiments, recess 330 extends into substrate layer 250 by a micron, or more. The depth of recess 330 may be predetermined, for example, to accommodate a predetermined thickness of III-N material within recess 330 in a manner that improves planarity between a substrate regions 206 and 207.

A top surface of substrate layer 215 is covered with a hard mask 322, which may be any dielectric material, such as, but not limited to, SiOx, SiN_x, SiON, or SiOC(H). A layer of amorphous material 324 is deposited over both substrate regions 206 and 207, for example covering hard mask 322 and covering the (111) surface of substrate layer 205 that would otherwise be exposed within recess 330. Amorphous material 324 also covers substrate layer sidewall 320. In some advantageous embodiments, amorphous material 324 is a substantially conformal layer having a thickness over substrate layer sidewall 320 that is at least 80% of its average thickness over substrate layer 205. Amorphous material 324 is to be retained over at least substrate layer sidewall 320 and may be of any material known to be suitable for blocking, masking or otherwise precluding growth of III-N material. In some embodiments, amorphous material 324 is a nitride. In some such embodiments, amorphous material 324 includes one or more layers of a compound including predominantly silicon and nitrogen, such as S13N4. In some other embodiments, amorphous material 324 includes one or more layers of a compound including silicon, oxygen, and nitrogen, such as silicon oxynitride (SiON). In other embodiments, amorphous material 324 includes one or more layers of a compound of predominantly silicon and oxygen (e.g., S1O2). In still other embodiments, amorphous material 324 may be a metallic compound or metal oxide. Amorphous material 324 may be deposited with any conformal deposition technique known to be suitable for the desired material composition, such as, but not limited to chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or atomic layer deposition (ALD). Amorphous material 324 may have any thickness sufficient to preclude subsequent material growth over substrate layer sidewall 320. Amorphous material 324 may then be patterned with either a self-aligned technique (e.g., with an anisotropic spacer etch) or with a masked patterning technique. In some exemplary self-aligned patterning embodiments, spacers of amorphous material 324 are retained only along the perimeter of substrate region 207. The resulting spacers may then protect a sidewall of substrate layer 215. Where a significant portion of substrate layer 205 is also recessed, the spacers of amorphous material may also protect a sidewall of substrate layer 205, which may also otherwise present an undesirable seeding surface during subsequent III-N material growth. In alternative non-self-aligned patterning embodiments, amorphous material 324 is masked, and openings or windows are defined through amorphous material 324.

In the exemplary structure 401 illustrated in FIG. 4, recess 330 is backfilled with a sacrificial masking material 410. A top surface of masking material 410 is then planarized (e.g., within a few tens of nanometers) with a top surface of substrate region 206. In the example shown in FIG. 4, masking material 410 has been planarized with hard mask 322, for example with a polish that removed amorphous material 324 from substrate region 206. Alternatively, masking material 410 may be planarized with top surface of amorphous material 324. An opening 415 is then defined in a masking material 410, which may be a photodefinable material, or may be any suitable hardmask. Opening 415 is then translated with one or more process (e.g., dry develop and/or anisotropic etch) through masking material 410, and through amorphous material 324.

Masking material 410 is then subsequently removed as further illustrated in FIG. 5. Exemplary structure 501 shown in FIG. 5 includes a patterned amorphous growth mask 524 within substrate region 207 that is suitable for templating a III-N epitaxial growth from the (11 1) surface of substrate 205 exposed within opening 515 without competitive growths on a substrate layer sidewall 320. III-N material growth over the top surface of substrate layer 215 within substrate region 206 may also be prevented by growth mask 524 if retained over substrate region 206, or prevented by an underlying amorphous material (e.g., hard mask 322) that is retained within substrate region 206.

Returning to FIG. 1 , methods 101 continue at operation 125 where one or more layers of III-N material are heteroepitaxially grown over the substrate layer having (1 1 1) orientation. The heteroepitaxial growth process may form III-N material over an entire SOI substrate wherever the (11 1) substrate layer is exposed. The growth mask covering at least the sidewalls at the perimeter of the III-N device region may further limit the formation of III-N material to only the (111) surface. Any number of layers of III-N material may be grown to any suitable thickness during operation 125. Any III-N material composition including binary alloys (e.g., GaN, InN), ternary alloys (e.g., Al_xIni-_xN, In_xGai-_xN, or ALGai- xN), and quaternary alloys (e.g., In_xGa_yAli-_x-_yN) may be grown at operation 125. In some embodiments, the III-N semiconductor material grown at operation 125 is a III-N

semiconductor stack that includes at least a buffer proximal to the seeding surface. Any known III-N heteroepitaxial growth process may be employed at operation 125, such as, but not limited to, molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), or any other technique known to be suitable for III-N material growth. In some embodiments, elevated temperatures of 900 °C, or more, are employed to epitaxially grow a GaN crystalline structure over the buffer. In some advantageous embodiments, the growth process includes growth of intrinsic GaN material (having no intentional donor or acceptor impurity doping). For example, oxygen impurity concentration may be less than lel7/cm³ (e.g., Iel5-lel6/cm³).

For the exemplary structure 601 shown in FIG. 6, III-N material 620 is grown within substrate region 207, wherever growth mask 524 is absent. In some exemplary embodiments, III-N material 330 is monocrystalline with the hexagonal/wurzite oaxis substantially orthogonal to the (111) plane of silicon substrate layer 205. Advantageously, the c-plane of the III-N material is no more than 10° from parallel to the (111) plane of silicon substrate layer 205. In some exemplary embodiments, III-N material 620 includes a buffer layer grown directly on exposed regions of substrate layer 205. While any known buffer structure may be employed, examples include an A1N and/or AlGaN nucleation layer directly on the (111) silicon surface, with one or more AlGaN and/or GaN layers on the nucleation layer. For such embodiments, after growth of a nucleation layer, a buffer of III-N material (e.g., GaN) is grown with first epitaxial growth conditions (e.g., a first growth pressure, a first growth temperature, and a first V/III growth precursor ratio). Following an initial growth period, growth conditions may be changed to a second growth temperature, and/or second growth pressure, and/or a second V/III growth precursor ratio favoring lateral epitaxial overgrowth (LEO) of III-N material (e.g., GaN) to extend III-N material 620 over growth mask portion 622. In some embodiments, the LEO process employed favors formation of inclined sidewall facets. Overgrowth at rates that favor wurtzite crystal facets non-parallel and non-normal (e.g., -60°) to the c-plane have been found to bend defects away from the c-plane and toward the sidewalls such that the quality of a top surface of the III-N crystalline structure can improve with overgrowth time. Upon termination of the growth operation, III-N material 330 has a trapezoidal profile, the dimensions of which depend on growth time. In some embodiments, III-N material 620 is grown to a z-thickness of 1-3 μιτι, or more, over the interface with substrate layer 205. This thickness may be selected to arrive at a desirable crystal quality (e.g., defect density below le9/cm²). As shown in FIG. 6, thicknesses of substrate layer 215 and dielectric material layer 210, along with a depth of a recess into substrate layer 205 may be predetermined so that a desired thickness of III-N material 620 results in planarity of III-N material top surface 621 and a top surface 615 of substrate layer 215. Optionally, a polish may be performed following III-N material growth to planarize III- N material top surface 621 with top surface 615.

Returning to FIG. 1 , methods 101 continue at operation 130 where another amorphous material is formed over sidewalls of the III-N material grown at operation 125. This amorphous material may serve as another growth mask confining further epitaxial growth to portions of the III-N material. For example, the amorphous material may be deposited over non-polar and/or semi-polar surfaces of the III-N material grown at operation 125. Any amorphous material known to be suitable for such purposes may be deposited by any technique known to be suitable for the material. In some embodiments, the amorphous material deposited at operation 130 has the same composition as the amorphous material deposited at operation 120. Amorphous material formed at operation 125 may be deposited with any deposition technique known to be suitable for the desired material composition, such as, but not limited to, CVD, PECVD, or ALD.

For the exemplary structure 701 illustrated in FIG. 7, an amorphous material 725 is deposited over III-N material 620 and over amorphous growth mask 524. Amorphous material 725 backfills the recess within substrate region 207. Amorphous material 725 may include multiple material layers, for example including a substantially conformal layer having a thickness over a sidewall of III-N material 620 that is at least 80% of its average thickness over adjacent portions of growth mask 524. Amorphous material 725 may further include one or more gap-filling material layers over any conformal layer(s). Amorphous material 725 is to be retained over at least a sidewall of III-N material 620. In some exemplary embodiments, amorphous material 725 includes a nitride layer in contact with III- N material 620. In some such embodiments, the nitride layer is a compound including predominantly silicon and nitrogen, such as S13N4. In some other embodiments, amorphous material 725 includes a layer of a compound including silicon, oxygen, and nitrogen, such as silicon oxynitride (SiON), in contact with III-N material 620. In other embodiments, amorphous material 725 includes a layer of a compound of predominantly silicon and oxygen (e.g., S1O2) in contact with III-N material 620. In still other embodiments, amorphous material 725 includes a layer of metal oxide in contact with III-N material 620. In the illustrated embodiment, amorphous material 725 further includes a gap filling material, such as any flowable oxide known to be suitable for such applications. Following deposition of amorphous material 725, growth mask 524 and amorphous material 725 (e.g. in the x- dimension) occupy space between III-N material 620 and a sidewall of substrate layer 215.

A portion of III-N material 620 that is to host a III-N device is then further processed. For example, returning to FIG. 1 , methods 101 continue at operation 135 where a III-N FET is fabricated in one substrate region. Any III-N FET may be fabricated at operation 135 according to any suitable techniques. In some embodiments, a III-N HFET including a gate electrode, a source, and a drain is fabricated at operation 135. For the exemplary structure

801 illustrated in FIG. 8, HFET fabrication begins with forming a polarization layer 850 over a polar plane (e.g., oplane) of III-N material 620. Polarization layer 850 may be epitaxially grown on exposed surface of III-N material 620 using any suitable growth technique, such as any of those employed to form III-N material 620. During epitaxial growth of polarization layer 850, portions of III-N material 620 are protected from III-N material overgrowth by amorphous material 725.

Polarization layer 850 may include any binary, ternary, or quaternary III-N alloy that has a spontaneous polarization and/or piezoelectric polarization suitable for inducing a charge carrier sheet (e.g., electron gas or hole gas) within a channel portion of the underlying III-N material 620. In an embodiment, polarization charge layer 850 includes a material such as, but not limited to, Al_zGai-_zN (e.g., where Z ranges from 0.2-0.3), or Al_wIni-_wN (e.g., where W ranges from 0.7-0.85), or A1N. In some embodiments where polarization layer 850 is on binary GaN, polarization layer 850 includes a layer of Al_zGai-_zN. The thickness of the polarization layer 850 may vary with material composition. A layer of Al_zGai-_zN can have a thickness between 5nm-30nm with the thickness varying inversely with the Al concentration. For example, for Z between 20 and 50 atomic percent, the thickness may vary between 30nm and 5nm, respectively. In an exemplary embodiment where polarization layer 850 includes AlzGai-zN with Z being 30 atomic percent, the thickness of polarization layer 850 is approximately 25nm (e.g., +/- 20%). In another example where polarization layer 850 includes is Al_wIni-_wN, the thickness is between 10nm-20nm depending on the Al concentration. The thickness may again vary inversely with the Al concentration. For example, for W between 60 and 80 atomic percent, the Al_wIni-_wN layer thickness may vary between 20nm and l Onm, respectively. In some further embodiments, there may be an intermediate layer (not depicted) between polarization layer 850 and III-N material 620. Such an intermediate layer may help to improve mobility of the charge carriers induced by polarization layer 850. A mobility enhancement layer may have a thickness of lnm, or less, for example. A mobility enhancement layer may be a binary alloy. In one such embodiment where III-N material 620 includes binary GaN nearest to polarization layer 850, a layer of A1N may function as a mobility enhancement layer.

Returning to FIG. 1 , methods 101 continue at operation 135 where a III-N device is fabricated over, on, or in the III-N material that was formed at operation 1 15. Exemplary III- N devices that may be fabricated at operation 135 include, but are not limited to, diodes, light emitting diodes (LEDs), transistors, lasers, and piezoelectric sensors. In the illustrated embodiment, the III-N devices fabricated include transistors, and more specifically heteroj unction field effect transistors. The transistors fabricated at operation 135 may have any architecture known to be suitable for an RFIC, power (high-voltage) IC, or a logic IC. In the example shown in FIG. 9, an ILD material 965 is deposited over substrate regions 206 and 207. ILD material 965 may be any dielectric material composition known to be suitable for ICs. Optionally, ILD material 965 may be planarized with any suitable planarization process (e.g., polish). ILD material 965 may be patterned and III-N epitaxial growth or deposition processes may be practiced as needed to fabricate a given device structure. For example, impurity (e.g., donor) doped III-N material may be selectively grown as source and drain terminals according to any suitable technique. In the exemplary structure 901 shown in FIG. 9, source and drain terminals 971 are coupled to a device layer (e.g., 2DEG within a top portion of III-N material 360) on opposite sides of a gate electrode stack that includes a gate electrode 981 separated from the device layer by a gate dielectric 975. Gate electrode 981, along with source and drain terminals 971 on opposite sides of gate electrode 981, are operable as a first transistor based on electric field modulation of the 2DEG. Returning to FIG. 1, methods 101 continue at operation 140, where Group IV -based devices are fabricated within another substrate region. Exemplary devices that may be fabricated at operation 140 include, but are not limited to, diodes, light emitting diodes (LEDs), photovoltaics, transistors, and optical sensors. In the illustrated embodiment, the devices include silicon-based transistors, and more specifically n-type and p-type MOSFETs that may form any desired CMOS circuitry. The transistors fabricated at operation 140 may have any architecture known to be suitable for a logic IC, for example. Notably, the sequence of operations 135 and 140 may be reversed from that illustrated. However, where fabrication of the III-N device includes an epitaxial growth of III-N material, for example to form semiconductor device terminals, it may be advantageous to perform such III-N growths prior to fabrication of Group IV transistors (e.g., for the sake of accommodating the thermal budget of a MOSFET).

For the exemplary structure 1001 illustrated in FIG. 10, a gate stack including a gate electrode 1082 and a gate dielectric 1083 is over one or more fin 318. Such a gate stack may be formed according to any known finFET fabrication technique. For example the gate mandrel 321 may be replaced with a permanent gate stack according to any "gate-last" technique. FinFET transistors include double-gate transistors and tri-gate transistors, and wrap-around or "gate all-around" transistors, such as nanoribbon and nanowire transistors. MOSFETs fabricated within region 206 may also be planar transistors, or a combination of both planar and non-planar transistors. A source and drain terminals 1071 are formed on opposite sides of gate electrode 1082. Gate electrode 1082 and source and drain terminals 1081 are operable as a transistor based on electric field modulation of conductivity with a channel portion of fin 318. With substrate regions 206 and 207 substantially planar, transistor fabrication processes within each substrate region 206, 207 may be performed concurrently in some advantageous embodiments.

In structure 1001 shown in FIG. 10, the gate dielectric layers 1075 and 1083 may each include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high- k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

The gate electrodes 981 and 1082 may include at least one P-type work function metal or N-type work function metal, depending on conductivity type of the transistor channel. In some embodiments, substrate region 206 includes NMOS transistors with N-type work function metal and PMOS transistors with P-type work function metal. In some implementations, the gate electrodes 981 and 1082 include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. For PMOS transistors fabricated in substrate region 206, metals that may be used for the gate electrode 1082 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For NMOS transistors fabricated in substrate region 206, metals that may be used for the gate electrode layer 1082 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. These same gate metals may be employed for gate electrodes 981. Alternatively, different gate metals (e.g., titanium nitride, etc.) may be employed for gate electrodes 981.

In some implementations, a pair of sidewall spacers may be formed on opposing sides of the gate stacks. The sidewall spacers may separate the gate stack from the source and drain terminals. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. Source and drain terminals 1071 may be formed using either an

implantation/diffusion process or an etching/deposition process. For example, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the (100) or (110) silicon to form the source and drain terminals 1071 1. Alternatively, the (100) or (110) silicon may be first etched to form recesses and an epitaxial growth process may fill the recesses with source and drain terminals 1071. In some implementations, the source and drain terminals 1071 are a silicon alloy such as silicon germanium or silicon carbide. Returning to FIG. 1, methods 101 continue at operation 145 where the optional Group IV device (low voltage/frequency CMOS) circuitry is interconnected to III-N device (e.g., high voltage/frequency HFET) circuitry. In some embodiments, metallization levels and intervening ILD is fabricated over both device regions 206, 207, interconnecting all devices on the SOC concurrently. In some advantageous embodiments however, the number of metallization levels disposed over substrate region 206 differs from the number of metallization levels disposed over substrate region 207. For example, within substrate region 207 there may less than half the metallization layers than are present in substrate region 206. In exemplary embodiments where 9-10 metallization levels may be disposed over substrate region 206, only 1-5 metallization levels may be disposed over substrate region 207. A reduced metallization level count within the III-N device region may be associated with metallization levels that have significantly greater z-thicknesses than the levels employed in the Group IV device region. In some exemplary applications, HFET device density is much lower than that of the Si FETs. While a larger and/or lower transistor count within the HFET region of the substrate can be interconnected by fewer metallization levels, a higher interconnect power rating, and/or inductance may be beneficial to high-voltage (HV) circuitry of an integrated SOC. In one specific embodiment, where the III-N HFET circuitry within substrate region 207 comprises one or more RF power amplifier transistors, at least one thick metallization (e.g., >1.5 μιτι) level and/or thick ILD is routed within substrate region 207. In some embodiments, HFET circuitry disposed over the HFET region of the substrate includes an inductor. The inductor may be fabricated in at least one thick metallization level with any known technique. Use of the thick metallization may enable an inductor of advantageous quality factor (Q) to be fabricated over the HFET region within the same z-thickness occupied by the more numerous, but thinner metallization levels disposed over the Si FET region. This high-Q inductor may further benefit from high resistance of substrate layer 205.

In the exemplary structure 1101 illustrated in FIG. 11, a plurality of interconnect metallization levels 1172 interconnect MOS transistor terminals into CMOS circuitry, formed in accordance with some embodiments. A plurality of metallization levels 1165 and intervening ILD 1166 is formed over substrate region 206. Within substrate region 207 however, thick metallization levels 1167 are formed. In the exemplary embodiment, the ILD levels 1166 are present in both substrate regions 206, 207. In some embodiments, formation of thick metallization levels 1167 within III-N HFET regions of the substrate involves etching a pattern through multiple ILD levels and backfilling the etched pattern in one plating operation. In other embodiments, formation of a thick metallization level within the III-N HFET regions of the substrate entails an iterative stacking of the same metallization levels employed for the CMOS circuitry in region 206. In FIG. 11, thick metallization level 367 may implement an inductor having a z- thickness of at least 1.5 μιτι and disposed only over substrate region 207. Multiple ILD levels 1166 corresponding to a least two metallization levels within substrate region 206 are patterned and backfilled to form thick metallization level 367. As further illustrated, thick metallization level 367 lands on an underlying metallization level 365, further increasing the effective III-N HFET metallization level thickness by forming a metallization stack including at least one Si FET metallization level.

Returning to FIG. 1, methods 101 complete with output of an integrated III-N and Si device (e.g., SOC), for example substantially as illustrated in FIG. 11. Hence, structure 1101 may be portion of a monolithic SOC that includes any and/or all of the device structures and properties described above. In some embodiments, the SOC includes III-N (GaN) HFETs within high voltage circuitry of a power management integrated circuit, while Si FETs implement logic and/or controller functions in low voltage circuitry of the PMIC. In some other embodiments, the SOC includes III-N (GaN) HFETs within high voltage power amplifier circuitry of an RF transceiver, while Si FETs implement logic and/or controller functions in low voltage circuitry of the RF transceiver.

FIG. 12 illustrates a system 1200 in which a mobile computing platform 1205 and/or a data server machine 1206 employs a monolithically integrated SOC including both III-N HFET circuitry and Si CMOS circuitry, for example in accordance with one or more embodiments described above. The server machine 1206 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a packaged device 1250.

The mobile computing platform 1205 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 1205 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 1210, and a battery 1215.

Whether disposed within the integrated system 1210 illustrated in the expanded view 1220, or as a stand-alone packaged device within the server machine 1206, SOC 1260 includes at least III-N HFET circuitry and Si-based CMOS(FET) circuitry. SOC 1260 may further include a memory circuitry and/or a processor circuitry 1240 (e.g., RAM, a microprocessor, a multi-core microprocessor, graphics processor, etc.). III-N HFET and Si- FET circuitry may implement high and low voltage portions, respectively, of one or more of PMIC 1230, or RF (radio frequency) integrated circuitry (RFIC) 1225 including a wideband RF transmitter and/or receiver (TX/RX). In some embodiments for example, SoC 1260 includes a digital baseband and an analog front end module further comprising a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controller 1235.

Functionally, PMIC 1230 may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery 1215, and an output providing a current supply to other functional modules. As further illustrated, in the exemplary embodiment, RFIC 1225 has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT,

Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. In alternative implementations, each of these SoC modules may be integrated onto separate ICs coupled to a package substrate, interposer, or board.

FIG. 13 is a functional block diagram of a computing device 1300, arranged in accordance with at least some implementations of the present disclosure. Computing device 1300 may be found inside platform 1205 or server machine 1206, for example. Device 1300 further includes a motherboard 1302 hosting a number of components, such as, but not limited to, a processor 1304 (e.g., an applications processor), which may further incorporate III-N HFET circuitry interconnected with Si FET circuitry, in accordance with embodiments of the present invention. Processor 1304 may for example include power management integrated circuitry (PMIC) that includes III-N HFET circuitry interconnected with Si FET circuitry. Processor 1304 may be physically and/or electrically coupled to motherboard 1302. In some examples, processor 1304 includes an integrated circuit die packaged within the processor 1304. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.

In various examples, one or more communication chips 1306 may also be physically and/or electrically coupled to the motherboard 1302. In further implementations,

communication chips 1306 may be part of processor 1304. Depending on its applications, computing device 1300 may include other components that may or may not be physically and electrically coupled to motherboard 1302. These other components include, but are not limited to, volatile memory (e.g., MRAM 1330, DRAM 1332), non-volatile memory (e.g., ROM 1335), flash memory, a graphics processor 1322, a digital signal processor, a crypto processor, a chipset, an antenna 1325, touchscreen display 1315, touchscreen controller 1375, battery 1310, audio codec, video codec, power amplifier 1321, global positioning system (GPS) device 1340, compass 1345, accelerometer, gyroscope, audio speaker 1320, camera 1341, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.

Communication chips 1306 may enable wireless communications for the transfer of data to and from the computing device 1300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips 1306 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 1300 may include a plurality of communication chips 1306. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless

communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.

It will be recognized that the invention is not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below:

In first examples, an integrated circuit (IC) structure includes a first device region comprising a first substrate layer over a second substrate layer with a layer of intervening dielectric material therebetween, wherein the first substrate layer comprises silicon and has (100) or (110) crystallinity, and wherein the second substrate layer comprises silicon and has (111) crystallinity. The IC structure includes a second device region lacking the first substrate layer, and comprising a Group Ill-Nitride (III-N) material and an amorphous material, wherein the amorphous material is over a sidewall of the first substrate layer, and wherein the III-N material is over the second substrate layer with a portion of the III-N material within an opening in the amorphous material.

In second examples for any of the first examples the amorphous material defines a perimeter enclosing the second device region.

In third examples, for any of the second examples the amorphous material comprises one or more layer of dielectric material. In fourth examples, for any of the third examples, the intervening dielectric material comprises silicon and oxygen, the amorphous material comprises silicon and nitrogen.

In fifth examples, for any of the first through fourth examples the III-N material comprises a buffer with one or more III-N alloy layers, the buffer contacting the second substrate layer. The III-N material comprises a polarization layer over the buffer, wherein the polarization layer comprises a first III-N alloy that induces a two-dimensional charge sheet within a second III-N alloy that is below the polarization layer.

In sixth examples, for any of the fifth examples the polarization layer is on a oplane of the buffer, the buffer has a thickness of at least 1 μιτι, and a top surface of the buffer is planar with a top surface of the first substrate layer. In seventh examples, for any of the first through sixth examples the IC structure further includes a first transistor within the first device region, wherein the first transistor includes a first source coupled to a first drain through at least a portion of the first substrate layer. The IC structure further includes a second transistor within the second device region, wherein the second transistor includes a second source coupled to a second drain through at least a portion of the III-N material. The IC structure further includes one or more metallization levels electrically interconnecting the first transistor to the second transistor.

In eighth examples, for any of the seventh examples the IC structure includes an interlay er dielectric (ILD) over the amorphous material and over a sidewall of the III-N material, wherein a portion of the second source and the second drain is within an opening in the ILD.

In ninth examples, for any of the eighth examples the amorphous material is in direct contact with the sidewall of the first substrate layer, and in direct contact with the second substrate layer. A portion of the III-N material extends laterally over the amorphous material. The ILD is in direct contact with the amorphous material and the portion of the III-N material that extends laterally over the amorphous material.

In tenth examples, for any of the seventh through eighth examples the first transistor comprises a metal-oxide-semiconductor (MOS)FET that further includes a first gate electrode separated from the first substrate layer by a first gate dielectric. The second transistor comprises a III-N heterostructure field effect transistor (HFET) that further includes a gate electrode separated from the III-N material by a second gate dielectric.

In eleventh examples, for any of the first through first through sixth examples the first substrate layer has a thickness greater than 100 nm, the second substrate layer has a lower electrical resistivity than the first substrate layer, and the layer of substrate dielectric material has a thickness greater than that of the first layer.

In twelfth examples, a system-on-chip (SOC) comprises processor circuitry coupled to the RF transceiver circuitry, wherein the processor circuitry comprises a first transistor within the first device region of any of the first through sixth examples. RF circuitry comprising a second transistor is within the second device region of any of the first through sixth examples. In thirteenth examples, a system-on-chip (SOC) includes processor circuitry. The processor circuitry comprises metal-oxide-semiconductor field effect transistors (MOSFETs) including a portion of a (100) or (110) crystalline substrate layer within a first region of the SOC, the (100) or (110) crystalline substrate layer separated from a (111) crystalline substrate layer by an intervening dielectric material. The SOC includes RF circuitry coupled to the processor circuitry. The RF circuitry comprises one or more heterostructure field effect transistors (HFETs) including a Group Ill-Nitride (III-N) material within a second region of the SOC that lacks the (100) or (110) crystalline substrate layer. A portion of the III-N material that is within an opening in an amorphous material is in contact with the (111) crystalline substrate layer. The amorphous material extends over a sidewall of the (100) or (110) crystalline substrate layer along a perimeter of the second region.

In fourteenth examples, for any of the thirteenth examples the HFETs further comprise a gate electrode disposed over a (0001) surface of the III-N material. The (111) crystalline substrate layer has a higher electrical resistivity than the (100) or (110) crystalline substrate layer. The amorphous material comprises silicon and nitrogen and has a thickness less than 1 μιτι.

In fifteenth examples, for any of the thirteenth through fourteenth examples the HFETs further comprise a source and a drain disposed over a (0001) surface of the III-N material. The SOC further comprises an interlay er dielectric (ILD) over the amorphous material and over a sidewall of the III-N material, wherein a portion of the second source and the second drain is within an opening in the ILD.

In sixteenth examples, a method of fabricating a system-on-chip (SOC) includes receiving a substrate comprising a first substrate layer over a second substrate layer with a layer of intervening dielectric material therebetween, wherein the first substrate layer comprises silicon and has (100) or (110) crystallinity, and wherein the second substrate layer comprises silicon and has (111) crystallinity. The method includes exposing the second substrate layer within a first region of the substrate by removing the first substrate layer and the intervening dielectric material from the first region selectively to a second region where the first substrate layer is retained. The method includes depositing an amorphous material over a sidewall of the first substrate layer along a perimeter of the first region. The method includes epitaxially growing a Group Ill-Nitride (III-N) material over the second substrate layer within the first region, forming one or more heterostructure field effect transistors (HFETs) comprising the III-N material, and forming one or more metal-oxide-semiconductor FETs (MOSFETs) comprising the first substrate layer.

In seventeenth examples, for any of the sixteenth examples depositing the amorphous material further comprises depositing a dielectric material over the sidewall of the first substrate layer and over an exposed surface of the second substrate layer, the method further includes forming an opening in the dielectric material that exposes the second substrate layer, and epitaxially growing the III-N material further comprises growing the III-N material within the opening in the dielectric material.

In eighteenth examples for any of the seventeenth examples, epitaxially growing the III-N material further comprises laterally over-growing the III-N material layer over a surface of the dielectric material.

In nineteenth examples, for any of the sixteenth through eighteenth examples, the method includes planarizing a top surface of the III-N material with a top surface of the second substrate layer.

In twentieth examples, for any of the sixteenth through nineteenth examples, the method includes depositing an interlay er dielectric (ILD) material over a sidewall of the III-N material and over the amorphous material, forming an opening in the ILD material that exposes a portion of the III-N material, and epitaxially growing source and drain material on the exposed portion of the III-N material.

In twenty -first examples, for any of the sixteenth through twentieth examples, the MOSFETs comprise (100) silicon, the method further comprises interconnecting the HFETs with the MOSFETs.

In twenty-second examples, for any of the sixteenth through twenty-first examples exposing the second substrate layer within a first region further comprises recess etching the second substrate layer by a predetermined amount.

In twenty -third examples, for any of the sixteenth through twenty-second examples growing the III-N material further comprises growing a polarization layer from at least a (0001) surface of an underlying III-N layer, the polarization layer having a composition that induces a 2D electron gas (2DEG) in the underlying III-N layer. Forming the one or more HFETs further comprises forming first gate electrodes and first source and drain terminals that are coupled to the 2DEG. Forming the one or more MOSFETs further comprises forming second gate electrodes and second source and drain terminals that are coupled to a portion of the first substrate layer. In twenty -fourth examples, for any of the sixteenth through twenty-first examples, the second substrate layer and has an electrical resistivity that is higher than that of the first substrate layer.

In twenty -fifth examples, for any of the sixteenth through twenty-first examples, the method further comprises forming one or more metallization levels, wherein forming the one or more metallization levels further comprises forming first metallization over first gate electrodes and first source and drain terminals within the first region of the SOC, forming second metallization over second gate electrodes and second source and drain terminals within the second region of the SOC, and forming a third metallization over both the first metallization and the second metallization, the third metallization level interconnecting the first metallization with the second metallization.

However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

CLAIMS What is claimed is:

1. An integrated circuit (IC) structure, comprising:

a first device region comprising a first substrate layer over a second substrate layer with a layer of intervening dielectric material therebetween, wherein the first substrate layer comprises silicon and has (100) or (110) crystallinity, and wherein the second substrate layer comprises silicon and has (1 11) crystallinity; and

a second device region lacking the first substrate layer, and comprising:

the second substrate layer;

a Group Ill-Nitride (III-N) material; and

an amorphous material, wherein:

the amorphous material is adjacent to a sidewall of the first substrate layer within the first device region; and

the III-N material is over the second substrate layer with a portion of the III-N material within an opening in the amorphous material.

2. The IC structure of claim 1 , wherein the amorphous material defines a perimeter enclosing the second device region.

3. The IC structure of claim 2, wherein the amorphous material comprises one or more layer of dielectric material.

4. The IC structure of claim 3, wherein:

the intervening dielectric material comprises silicon and oxygen; and

the amorphous material comprises silicon and nitrogen.

5. The IC structure of claim 1, wherein the III-N material comprises:

a buffer with one or more III-N alloy layers, the buffer contacting the second substrate layer; and

a polarization layer over the buffer, wherein the polarization layer comprises a first III-N alloy that induces a two-dimensional charge sheet within a second III-N alloy that is below the polarization layer.

6. The IC structure of claim 5, wherein:

the polarization layer is on a oplane of the buffer;

the buffer has a thickness of at least 1 μιη; and

a top surface of the buffer is planar with a top surface of the first substrate layer.

7. The IC structure of any one of claims 1 -6, further comprising:

a first transistor within the first device region, wherein the first transistor includes a first source coupled to a first drain through at least a portion of the first substrate layer; a second transistor within the second device region, wherein the second transistor includes a second source coupled to a second drain through at least a portion of the III-N material; and

one or more metallization levels electrically interconnecting the first transistor to the second transistor.

8. The IC structure of claim 7, further comprising:

an interlay er dielectric (ILD) over the amorphous material and over a sidewall of the III-N material, wherein a portion of the second source and the second drain is within an opening in the ILD.

9. The IC structure of claim 8, wherein:

the amorphous material is in direct contact with the sidewall of the first substrate layer, and in direct contact with the second substrate layer;

a portion of the III-N material extends laterally over the amorphous material; and the ILD is in direct contact with the amorphous material and the portion of the III-N material that extends laterally over the amorphous material.

10. The IC structure of claim 7, wherein:

the first transistor comprises a metal-oxide-semiconductor (MOS)FET that further includes a first gate electrode separated from the first substrate layer by a first gate dielectric; and

the second transistor comprises a III-N heterostructure field effect transistor (HFET) that further includes a gate electrode separated from the III-N material by a second gate dielectric.

11. The IC structure of any one of claims 1-6, wherein:

the first substrate layer has a thickness greater than 100 nm;

the second substrate layer has a lower electrical resistivity than the first substrate layer; and the layer of substrate dielectric material has a thickness greater than that of the first layer.

12. A system-on-chip (SOC), comprising:

processor circuitry coupled to the RF transceiver circuitry, wherein the processor circuitry comprises a first transistor within the first device region of any one of claims 1-6; and

RF circuitry comprising a second transistor within the second device region of any one of claims 1-6; and

13. A system-on-chip (SOC), comprising:

processor circuitry, wherein the processor circuitry comprises metal-oxide-semiconductor field effect transistors (MOSFETs) including a portion of a (100) or (110) crystalline substrate layer within a first region of the SOC, the (100) or (110) crystalline substrate layer separated from a (111) crystalline substrate layer by a layer of intervening dielectric material; and

RF circuitry coupled to the processor circuitry, wherein the RF circuitry comprises one or more heterostructure field effect transistors (HFETs) including a Group Ill-Nitride (III-N) material within a second region of the SOC that lacks the (100) or (110) crystalline substrate layer, wherein a portion of the III-N material that is within an opening in an amorphous material is in contact with the (111) crystalline substrate layer, and wherein the amorphous material extends over a sidewall of the (100) or (110) crystalline substrate layer along a perimeter of the second region.

14. The SOC of claim 13, wherein:

the HFETs further comprise a gate electrode disposed over a (0001) surface of the III-N material;

the (111) crystalline substrate layer has a higher electrical resistivity than the (100) or (110) crystalline substrate layer; and

the amorphous material comprises silicon and nitrogen and has a thickness less than 1 μιτι.

15. The SOC of claim 13, wherein the HFETs further comprise a source and a drain disposed over a (0001) surface of the III-N material; and

further comprising an interlay er dielectric (ILD) over the amorphous material and over a sidewall of the III-N material, wherein a portion of the second source and the second drain is within an opening in the ILD.

16. A method of fabricating a system-on-chip (SOC), the method comprising:

receiving a substrate comprising a first substrate layer over a second substrate layer with a layer of intervening dielectric material therebetween, wherein the first substrate layer comprises silicon and has (100) or (110) crystallinity, and wherein the second substrate layer comprises silicon and has (1 11) crystallinity;

exposing the second substrate layer within a first region of the substrate by removing the first substrate layer and the intervening dielectric material from the first region selectively to a second region where the first substrate layer is retained;

depositing an amorphous material over a sidewall of the first substrate layer along a

perimeter of the first region;

epitaxially growing a Group Ill-Nitride (III-N) material over the second substrate layer

within the first region;

forming one or more heterostructure field effect transistors (HFETs) comprising the III-N material; and

forming one or more metal-oxide-semiconductor FETs (MOSFETs) comprising the first substrate layer.

17. The method of claim 16, wherein:

depositing the amorphous material further comprises depositing a dielectric material over the sidewall of the first substrate layer and over an exposed surface of the second substrate layer;

the method further comprises forming an opening in the dielectric material that exposes the second substrate layer; and

epitaxially growing the III-N material further comprises growing the III-N material within the opening in the dielectric material.

18. The method of claim 17, wherein epitaxially growing the III-N material further comprises laterally over growing the III-N material layer over a surface of the dielectric material.

19. The method of claim 16, further comprising planarizing a top surface of the III-N material with a top surface of the second substrate layer.

20. The method of claim 16, further comprising:

depositing an interlay er dielectric (ILD) material over a sidewall of the III-N material and over the amorphous material;

forming an opening in the ILD material that exposes a portion of the III-N material; and epitaxially growing source and drain material on the exposed portion of the III-N material.

21. The method of claim 16, wherein the MOSFETs comprise (100) silicon; and

the method further comprises interconnecting the HFETs with the MOSFETs.

22. The method of claim 16, wherein exposing the second substrate layer within a first region further comprises recess etching the second substrate layer by a predetermined amount.

23. The method of claim 16, wherein:

growing the III-N material further comprises growing a polarization layer from at least a (0001) surface of an underlying III-N layer, the polarization layer having a composition that induces a 2D electron gas (2DEG) in the underlying III-N layer; forming the one or more HFETs further comprises forming first gate electrodes and first source and drain terminals that are coupled to the 2DEG;

forming the one or more MOSFETs further comprises forming second gate electrodes and second source and drain terminals that are coupled to a portion of the first substrate layer.

24. The method of any one of claims 16-21, wherein the second substrate layer and has an electrical resistivity that is higher than that of the first substrate layer.

25. The method of any one of claims 16-21, further comprising forming one or more

metallization levels, wherein forming the one or more metallization levels further comprises:

forming first metallization over first gate electrodes and first source and drain terminals

within the first region of the SOC; forming second metallization over second gate electrodes and second source and drain terminals within the second region of the SOC; and

forming a third metallization over both the first metallization and the second metallization, the third metallization level interconnecting the first metallization with the second metallization.