WO2019091541A1

WO2019091541A1 - Power amplifier and method

Info

Publication number: WO2019091541A1
Application number: PCT/EP2017/078439
Authority: WO
Inventors: Francesc Purroy MARTIN; Suo HAILEI
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2017-11-07
Filing date: 2017-11-07
Publication date: 2019-05-16

Abstract

A power amplifier (300), comprising a main amplifier (320); a balanced amplifier (310) connected using a hybrid combiner (330), wherein an isolated port of the hybrid combiner (330) is connected to the main amplifier (320), wherein power is delivered at an output port of the hybrid combiner (330); which power amplifier (300) is configured to, when ramping up output power from zero to maximum power level: firstly, switch on the main amplifier (320) and increase the output power up to a maximum while keeping the balanced amplifier (310) switched off; secondly, switch on power of the balanced amplifier (310) and increase the output power, while decreasing the output power of the main amplifier (320) down to a defined minimum value; and thirdly, increase the main amplifier output power up to maximum while continuing increasing the output power of the balanced amplifier (310) up to its maximum power level.

Description

POWER AMPLIFIER AND METHOD

TECHNICAL FIELD

Implementations described herein generally relate to a power amplifier architecture intended to be used in mobile communications base stations. In particular, is herein described a power amplifier, a method in a power amplifier, a computer program, a power amplifier arrangement, and a driving circuitry.

BACKGROUND

In August 1940 W.H. Doherty introduces Power Amplifier (PA) Doherty architecture. Some years later in 1987, F.H. Raab generalise the Doherty theory and for introduce the multistage Doherty, 3-way Doherty, as illustrated in Figure 1A. An advantage of F.H. Raab 3-way Doherty architecture compared with prior art 2-way Doherty is that it allows to extend the efficiency Back-Off (BO) range compromising less the average efficiency comparing with the 2-way Doherty. Later in 2007 R. Hellberg introduced the concept Chireix-Doherty, which replace in a Doherty structure the main power amplifier with a Chireix power amplifier in this way a theoretical flatter efficiency can be achieved compared with 3-way Doherty. Chireix- Doherty is illustrated in Figure 1 B.

In 2014 Haynes Mervin introduce the Load Modulated Balanced Amplifier (LMBA) concept consisting of two amplifiers connected to a quadrature hybrid coupler as a balanced amplifier and a third amplifier (control) connected to the isolated port of the quadrature hybrid. The advantage of this configuration is that the control amplifier can equally modulated the load of the two constituent amplifiers of the balanced amplifier. By selecting the right signal at the control amplifier it is possible to present the optimum loads to the balanced amplifier in a wide range of frequencies and for different output powers or Back-Offs. LMBA is illustrated in Figure 1 C.

One aspect not considered in the prior art implementations is the practical device limitations. Practical Radio Frequency (RF) devices have a limited output power range where the drain efficiency can be kept elevated, see example of a typical prior art device in Figure 2. Because this type of PA uses the load modulation technique this change in power will be achieved by actively load pulling the load. Because the available Load Pull Range LPR is limited, the best PA architecture will be the one that achieves higher efficiency BO with a small Load Pull Ratio (LPR).

Smaller LPR has another benefit which is the RF Bandwidth (BW). Smaller LPR will make possible to implement broadband matching networks, capable of tracking the required loads for the different status of the amplifiers which constitute the whole PA architecture.

Another important aspect is the possibility to switch on/ off different power amplifiers. This is typically done in Doherty type structures where peak PAs are off until a certain threshold. This extend the BO of the efficiency without incrementing the LPR. This is the reason why Chireix amplifiers have higher LPR than Doherty amplifiers. Prior art 1 and 2 in Figure 1A and Figure 1 B implement switching but prior art 3, illustrated in Figure 1 C does not.

One problem in prior art 1 and prior art 2 is that when the peak amplifier starts, the efficiency degrades because the peak amplifier is not operating at maximum voltage swing. Only at maximum power the peak amplifier will achieve its maximum efficiency.

Prior art 3 has two main problems which limits its applicability: The first is the fact that there is no switching on/ off of any PA, all the PAs are on always; and the second is that the control amplifier power consumption will degrade the whole PA efficiency.

It would be desired to provide an improved PA architecture intended to be used in mobile communications base stations, not suffering from the disadvantages of the prior art solutions. SUMMARY

It is therefore an object to obviate at least some of the above mentioned disadvantages and to improve the performance of a power amplifier.

This and other objects are achieved by the features of the appended independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

According to a first aspect, a power amplifier is provided. The power amplifier comprises a main amplifier and a balanced amplifier. The balanced amplifier is connected using a hybrid combiner wherein an isolated port of the hybrid combiner is connected to the main amplifier. Further the power is delivered at an output port of the hybrid combiner. The power amplifier is configured to, when ramping up output power from zero to maximum power level of the power amplifier: firstly, to switch on the main amplifier and increase the main amplifier output power up to a maximum power level of the main amplifier, while keeping the balanced amplifier switched off. Then, secondly, to switch on power of the balanced amplifier and increase the balanced amplifier output power, while decreasing the output power of the main amplifier down to a defined minimum value. Further, thirdly, the power amplifier is configured to increase the output power of the main amplifier up to the maximum main amplifier power level while continuing increasing the output power of the balanced amplifier up to the maximum balanced amplifier power level.

Due to the provided solution, a new power amplifier architecture family is provided solving various known problems of the previously known solutions. By implementing ability to switch on/ off not only the balanced amplifier but also the main amplifier, an improved trade-off between back-off and load pull ratio is achieved. Due to the driving, the balanced amplifier will operate at maximum efficiency from the lowest power level until the maximum power level, thereby increasing efficiency of the amplifier. By enabling switch off of the main amplifier and the balanced amplified alternatively at back-off, power consumption of the power amplifier is decreased leading to enhanced power amplifier efficiency.

In a first possible implementation of the power amplifier according to the first aspect, the balanced amplifier comprises at least a first amplifier and a second amplifier. Further, the main amplifier may comprise at least one third amplifier; and wherein the first amplifier of the balanced amplifier may be connected to a first connection port of the hybrid combiner. In addition, the second amplifier of the balanced amplifier may be connected to a second connection port of the hybrid combiner. Also, a third connection port of the hybrid combiner may be configured for output. Additionally, the third amplifier of the main amplifier may be connected to a fourth connection port of the hybrid combiner connected via an impedance modifying structure.

Thereby a convenient embodiment of the power amplifier is implemented. In a second possible implementation of the power amplifier according to the first aspect, or the first possible implementation of the power amplifier according to the first aspect, the main amplifier may have further back-off efficiency of the power amplifier, increasing the back-off efficiency of the power amplifier. Thereby back-off efficiency of the power amplifier is increased.

In a third possible implementation of the power amplifier according to the first aspect, or any previous possible implementation of the power amplifier according to the first aspect, the total back-off of the power amplifier may be equal the sum of the back-off of the main amplifier and a threshold value defined by the output power of the power amplifier, where the balanced amplifier is switched on.

Thereby, the functionality of the power amplifier is further defined. In a fourth possible implementation of the power amplifier according to the first aspect, or any previous possible implementation of the power amplifier according to the first aspect, the main amplifier may be single ended. In a fifth possible implementation of the power amplifier according to the first aspect, or any previous possible implementation of the power amplifier according to the first aspect, the main amplifier may comprise a Doherty amplifier.

In a sixth possible implementation of the power amplifier according to the first aspect, or any previous possible implementation of the power amplifier according to the first aspect, the main amplifier may comprise a Chireix amplifier.

In a seventh possible implementation of the power amplifier according to the first aspect, or any previous possible implementation of the power amplifier according to the first aspect, the impedance modifying structure may comprise a matching network and a combiner.

In an eighth possible implementation of the power amplifier according to the first aspect, or any previous possible implementation of the power amplifier according to the first aspect, the impedance modifying structure may be implemented by a transformer.

According to a second aspect, a method is provided for ramping up output power of a power amplifier, from zero to maximum power level of the power amplifier. The power amplifier comprises a balanced amplifier and a main amplifier, which are connected via a hybrid combiner. The method comprises: switching on the main amplifier; further, the method also comprises increasing output power of the main amplifier up to a maximum power level of the main amplifier, while keeping the balanced amplifier switched off. The method in addition comprises switching on the balanced amplifier. Additionally, the method also comprises increasing output power of the balanced amplifier, while decreasing the output power of the main amplifier down to a defined minimum value. The method furthermore comprises increasing output power of the main amplifier up to its maximum main amplifier power level while continuing increasing the output power of the balanced amplifier up to the maximum balanced amplifier power level.

Due to the provided solution, a new power amplifier architecture family is provided solving various known problems of the previously known solutions. By implementing ability to switch on/ off not only the balanced amplifier but also the main amplifier, an improved trade-off between back-off and load pull ratio is achieved. Thanks to the driving, the balanced amplifier will operate at maximum efficiency from the lowest power level until the maximum power level, thereby increasing efficiency of the amplifier.

The advantages of the method according to the second aspect, and the implementations thereof, are the same as has been described for the wearable device of the first aspect, and the corresponding implementations thereof.

In a first possible implementation of the power amplifier method according to the second aspect, the balanced amplifier comprises at least a first amplifier and a second amplifier. Further, the main amplifier may comprise at least one third amplifier; and wherein the first amplifier of the balanced amplifier may be connected to a first connection port of the hybrid combiner. In addition, the second amplifier of the balanced amplifier may be connected to a second connection port of the hybrid combiner. Also, a third connection port of the hybrid combiner may be configured for output. Additionally, the third amplifier of the main amplifier may be connected to a fourth connection port of the hybrid combiner connected via an impedance modifying structure.

In a second possible implementation of the power amplifier method according to the second aspect, or the first possible implementation of the method according to the second aspect, the main amplifier may have further back off efficiency of the power amplifier, increasing the back off efficiency of the power amplifier.

In a third possible implementation of the power amplifier method according to the second aspect, or any previous possible implementation of the method according to the second aspect, the total back of the power amplifier may be equal the sum of the back off of the main amplifier and a threshold value of 1/ 9 of the output power of the power amplifier, where the balanced amplifier is switched on.

In a fourth possible implementation of the power amplifier method according to the second aspect, or any previous possible implementation of the method according to the second aspect, the main amplifier may be single ended.

In a fifth possible implementation of the power amplifier method according to the second aspect, or any previous possible implementation of the method according to the second aspect, the main amplifier may comprise a Doherty amplifier.

In a sixth possible implementation of the power amplifier method according to the second aspect, or any previous possible implementation of the method according to the second aspect, the main amplifier may comprise a Chireix amplifier. In a seventh possible implementation of the power amplifier method according to the second aspect, or any previous possible implementation of the method according to the second aspect, the impedance modifying structure comprises a matching network and a combiner.

In an eighth possible implementation of the power amplifier method according to the second aspect, or any previous possible implementation of the method according to the second aspect, the impedance modifying structure may be implemented by a transformer. According to a third aspect, a computer program is provided, comprising program code for performing a method according to the second aspect, when the computer program runs on a computer.

According to a fourth aspect, a power amplifier arrangement is provided. The power amplifier arrangement comprises the power amplifier according to the first aspect, or any possible implementation thereof. Further, the power amplifier arrangement also comprises a driving circuitry, having two input ports and four output ports being connected to drive each of a balanced amplifier and a main amplifier, respectively; and an analogue SD signal decomposition.

Due to the provided solution, a new power amplifier architecture family is provided solving various known problems of the previously known solutions. By implementing ability to switch on/ off not only the balanced amplifier but also the main amplifier, an improved trade-off between back-off and load pull ratio is achieved. Thanks to the driving, the balanced amplifier will operate at maximum efficiency from the lowest power level until the maximum power level, thereby increasing efficiency of the amplifier. According to a fifth aspect, a power amplifier arrangement is provided. The power amplifier arrangement comprises the power amplifier according to the first aspect, or any possible implementation thereof. Further, the power amplifier arrangement also comprises a driving circuitry. The driving circuitry comprises three input ports and four output ports being connected to drive each of the balanced amplifier and the main amplifier, respectively; which driving circuitry is configured for digital SD signal decomposition.

According to a sixth aspect, a driving circuitry is provided. The driving circuitry aims at driving a power amplifier. The driving circuitry is configured to provide a driving signal to switch on the main amplifier. Further, the driving circuitry is configured to increase output power of the main amplifier up to a maximum main amplifier power level, while keeping the balanced amplifier switched off. The driving circuitry is in addition also configured to switch on the balanced amplifier. The driving circuitry is also configured to increase output power of the balanced amplifier, while decreasing the output power of the main amplifier down to a defined minimum value. In addition, the driving circuitry is furthermore configured to increase output power of the main amplifier up to the maximum main amplifier power level while continuing increasing the output power of the balanced amplifier up to the maximum balanced amplifier power level.

The especial driving together with right dimensioning of the size of the different power amplifiers allows to maximise the voltage swing of the balanced amplifier. Thereby, the balanced amplifier will operate at maximum efficiency from the lowest power level until the maximum power level, unlike the situation of previously known solutions.

In some embodiments, the main amplifier may have further back off efficiency of the power amplifier, thereby increasing the back off efficiency of the power amplifier.

Thereby advantages are achieved, corresponding with the previously described advantages of the first and second aspects. Thus an improved performance within a wireless communication system is provided. Other objects, advantages and novel features of the aspects of the invention will become apparent from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments are described in more detail with reference to attached drawings in which:

Figure 1 A illustrates a 3-Way Doherty Power Amplifier according to Prior Art.

Figure 1 B illustrates a Chireix Doherty Power Amplifier according to Prior Art.

Figure 1 C illustrates a Load Modulated Balanced Amplifier according to Prior Art.

Figure 2 is a diagram illustrating a trade-off between efficiency and output power for a typical Prior Art device.

Figure 3 illustrates a Balanced Single Ended Single Ended Amplifier (BSS) according to an embodiment of the invention.

Figure 4A is a diagram illustrating amplitude driving currents/ output voltage for a

Balanced Single Ended Single Ended Amplifier (BSS) according to an embodiment of the invention.

Figure 4B is a diagram illustrating phase driving currents/ output voltage for a Balanced

Single Ended Single Ended Amplifier (BSS) according to an embodiment of the invention.

Figure 5 illustrates a Balanced Single ended Doherty amplifier (BSD) according to an embodiment of the invention.

Figure 6A is a diagram illustrating amplitude driving currents/ output voltage for a

Balanced Single ended Doherty amplifier (BSD) according to an embodiment of the invention.

Figure 6B is a diagram illustrating phase driving currents/ output voltage for a Balanced

Single ended Doherty amplifier (BSD) according to an embodiment of the invention.

Figure 7 illustrates a Balanced Single ended Chireix amplifier (BSC) according to an embodiment of the invention.

Figure 8A is a diagram illustrating amplitude driving currents/ output voltage for a

Balanced Single ended Chireix amplifier (BSC) according to an embodiment of the invention.

Figure 8B is a diagram illustrating phase driving currents/ output voltage for a Balanced

Single ended Chireix amplifier (BSC) according to an embodiment of the invention.

Figure 9 illustrates a Quadrature Hybrid combiner and Z matrix according to an embodiment of the invention.

Figure 10 illustrates a Balanced Single Ended Single Ended Amplifier (BSS) according to an embodiment of the invention.

Figure 11 is a diagram illustrating power distribution for the proposed driving with a

Figure 12 illustrates a transformer according to an embodiment of the invention.

Figure 13A is a diagram illustrating driving currents amplitude/ normalised output voltage for a Balanced Single Ended Single Ended Amplifier (BSS) according to an embodiment of the invention.

Figure 13B is a diagram illustrating driving currents phase/ normalised output voltage for a Balanced Single Ended Single Ended Amplifier (BSS) according to an embodiment of the invention.

Figure 14A is a diagram illustrating output voltage swing/ normalised output voltage for a

Figure 14B is a diagram illustrating efficiency versus back off for a Balanced Single Ended

Single Ended Amplifier (BSS) according to an embodiment of the invention.

Figure 15 is a diagram illustrating impedances of a Balanced Single Ended Single

Ended Amplifier (BSS) according to an embodiment of the invention.

Figure 16 illustrates a power amplifier according to an embodiment of the invention.

Figure 17A is a diagram illustrating voltage swing (drain voltage/ output voltage) of an amplifier according to an embodiment of the invention.

Figure 17B is a diagram illustrating efficiency (%) versus back-off (dB) of a Balanced

Single Ended Doherty Amplifier (BSD) according to an embodiment of the inven-tion.

Figure 18 is a diagram illustrating impedances/ output voltage of a Balanced Single

Ended Doherty Amplifier (BSD) according to an embodiment of the invention.

Figure 19A is a diagram illustrating voltage swing (drain voltage/ output voltage) of a

Figure 19B is a diagram illustrating efficiency (%) versus back-off (dB) of a Balanced

Figure 20A is a diagram illustrating real part of the impedances versus normalised output voltage of a Balanced Single Ended Chireix Amplifier (BSC) according to an embodiment of the invention.

Figure 20B is a diagram illustrating imaginary part of the impedances versus normalised output voltage of a Balanced Single Ended Chireix Amplifier (BSC) according to an embodiment of the invention.

Figure 21 is a flow chart illustrating a method for ramping up output power of a power amplifier, according to an embodiment.

Figure 22A illustrates a power amplifier arrangement according to an embodiment.

Figure 22B illustrates a power amplifier arrangement according to yet an embodiment.

DETAILED DESCRIPTION

Embodiments of the invention described herein are defined as a power amplifier, a method in a power amplifier, a computer program, a power amplifier arrangement, and a driving circuitry, which may be put into practice in the embodiments described below. These embodiments may, however, be exemplified and realised in many different forms and are not to be limited to the examples set forth herein; rather, these illustrative examples of embodiments are provided so that this disclosure will be thorough and complete.

Still other objects and features may become apparent from the following detailed description, considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the herein disclosed embodiments, for which reference is to be made to the appended claims. Further, the drawings are not necessarily drawn to scale and, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.

Due to high peak to average ratio in mobile telecom standards signals such as e.g. Long Term Evolution (LTE), close to 9 dB, the amplifier size should be eight times bigger than the power that the power amplifier will in average deliver to the antenna load. This make it difficult to implement a high efficiency, low power consumption, power amplifier.

Several power amplifier architectures have been proposed to improve efficiency at low power level, i.e. at back off. Basically these architectures are based on two main techniques: Voltage modulation and Load modulation.

Voltage modulation techniques are mainly limited by the modulator signal bandwidth capability and by modulator efficiency: both at maximum power and at back off power.

Load modulation techniques are limited by Efficiency versus Bandwidth trade-off for high load pull ratio requirements.

The herein described solutions focus on the second group of techniques based on load modulation and improves the Efficiency versus Bandwidth trade-off by reducing the demand of load pull ratio of the devices used in the power amplifier implementation.

Figure 3 is a schematic illustration over a power amplifier 300, according to an implementation. The illustrated power amplifier 300 comprises a balanced amplifier 310 and a main amplifier 320. The balanced amplifier 310 is connected using a hybrid combiner 330. The hybrid combiner 330 may comprise a quadrature hybrid combiner such as e.g. a 90° quadrature hybrid combiner. The hybrid combiner 330 may have four ports.

An isolated port of the hybrid combiner 330 is connected to the main amplifier 320. Power is delivered at an output port of the hybrid combiner 330.

The balanced amplifier 310 may comprise at least a first amplifier 312 and a second amplifier 314. The first amplifier 312 and the second amplifier 314 may comprise one or several transistors. Further, the first amplifier 312 may be connected to a first connection port 311 of the hybrid combiner 330. The second amplifier 314 may be connected to a second connection port 313 of the hybrid combiner 330. A third connection port 321 of the hybrid combiner 330 may be configured for output. Thus, the third connection port 321 , or output port, may be operatively connected to a load either directly or via some other component. The main amplifier 320 comprises at least one third amplifier 322. The third amplifier 322 may comprise one or several transistors. The third amplifier 322 of the main amplifier 320 may be connected to a fourth connection port 323 of the hybrid combiner 330, connected via an impedance modifying structure 324. The illustrated embodiment of Figure 3, may be referred to as a Balanced Single Ended Single Ended Amplifier (BSS). The main amplifier 320 may alternatively, in other embodiments, be implemented as Doherty (BSD) or Chireix (BSC) amplifiers. Thanks to the made implementation, the power amplifier 300 will not experience any load pull ratio, thereby solving many of the problems of the prior art solutions.

The switching may be implemented, not only in the balanced amplifier 310, but also in the 5 main amplifier 320, by using especial driving signals. This improve the trade-off between back off and load pull ratio solving the problems of prior art. Additionally, this add an extra maximum of efficiency which make the overall back off efficiency more flat.

The especial driving together with right dimensioning of the size of the different power 10 amplifiers will allows to maximise the voltage swing of the balanced amplifier 310. Thereby, the balanced amplifier will operate at maximum efficiency from the lowest power level until the maximum power level, unlike the situation of previously known solutions.

In some embodiments, the main amplifier 320 may have further back off efficiency of the 15 power amplifier 300, thereby increasing the back off efficiency of the power amplifier 300.

Further, in some embodiments, the total back of the power amplifier 300 may in some embodiments be equal the sum of the back off of the main amplifier 320 and a threshold value of 1/ 9 of the output power of the power amplifier 300, where the balanced amplifier 20 310 is switched on.

The power amplifier 300 may in some embodiments comprise a balanced amplifier 310, comprising at least a first transistor 312 and a second transistor 314. Further, the power amplifier 300 may comprise the main amplifier 320, comprising at least one third transistor

25 322. The power amplifier 300 may also comprise the quadrature hybrid combiner 330.

Further, the first transistor 312 of the balanced amplifier 310 may be connected to the first connection port 31 1 of the quadrature hybrid combiner 330. Also, the second transistor 314 of the balanced amplifier 310 may be connected to the second connection port 313 of the quadrature hybrid combiner 330. The third connection port 321 of the quadrature hybrid

30 combiner 330 may be configured for output. The third transistor 322 of the main amplifier 320 may be connected to the fourth connection port 323 of the quadrature hybrid combiner 330, connected via an impedance modifying structure 324.

The impedance modifying structure 324 may in turn be realised by a transformer, as 35 illustrated in Figure 3, Figure 5 and/ or Figure 7 or may be integrated as a combination of matching networks and some combiner structure as is illustrated in Figure 16.

Figure 4A and 4B illustrates the operation of a power amplifier in accordance with some embodiments described herein is depicted. In Figure 4A, the solid lines illustrate the driving signal characteristics of the main amplifier 320, e.g. as illustrated in Figure 3. Further, the dashed lines illustrate the driving signal of the balanced amplifier 310. Figure 4A depicts amplitude driving currents while Figure 4B illustrates phase driving currents.

As can be seen in Figure 4A and Figure 4B, at low output power only the main amplifier 320 is fed with a driving signal. When the main amplifier 320 is saturated and cannot provide more output power, the balance amplifier 310 is fed with a driving signal to supplement the output from the main amplifier 320. The output of the balanced amplifier 310 may then be increased linearly with respect to the output voltage, while the output power of the main amplifier 320 is decreased down to zero, or to another predefined or configurable low value. Further, when the output of the balance amplifier 310 reaches its maximum value, the main amplifier 320 is again fed with a driving signal, linearly with the output voltage up to its maximum.

Figure 5 illustrates a Balanced Single ended Doherty amplifier (BSD), according to an embodiment.

Figure 6A and 6B illustrates driving signals of the Balanced Single ended Doherty amplifier. Figure 6A illustrates amplitude driving currents while Figure 6B illustrates phase driving currents. The continuous lines illustrate driving signal of the main amplifier 320, the dash lines illustrate the Peak (DHT) and the dot lines illustrate the driving signal of the balanced amplifier 310. Figure 7 illustrates a Balanced Single ended Chireix amplifier (BSC), according to an embodiment.

Figure 8A and 8B illustrates driving signals of the Balanced Single ended Chireix amplifier, according to an embodiment.

Figure 8A illustrates amplitude driving currents while Figure 8B illustrates phase driving currents. The continuous lines illustrate driving signal of the Chireix pair, while the dash lines illustrate the driving signal of the balanced amplifier 310. The main advantages of the proposed circuit together with the proposed driving signals comprises eliminating the load pull ratio of the main amplifier 320: in BSS, single ended; in BSD, Doherty and in BSC, Chireix. This allows to achieve better trade-off efficiency versus bandwidth than previously known solutions. By introducing switching of the main amplifier 320 and the balance amplifier 310 will further improve the back off achievable for a given bandwidth compared with previously known solutions. In conventional solutions, the peak amplifier is not working to full efficiency. According to embodiments herein, the balanced amplifier 310 working as peak amplifier works in maximum swing from the lowest to the highest back off. In previously known solutions, the balanced amplifier 310 is operating at maximum possible efficiency but is never switched off. The special driving of the main amplifier 320 introduces an extra maximum of efficiency achieving a flatter efficiency, in comparison with previously known solutions.

A further advantage of this architecture is the possibility to combine more devices which will be an advantage, in comparison with previously known solutions. Further, high power will be easy to achieve if more devices are used. In addition, smaller devices will be used for the same output power which will simplify the use of the amplifier 300 over wider signal bandwidth.

Figure 9 illustrates a quadrature hybrid combiner 330 and a Z matrix. The Z matrix has off- diagonal entries that are less than or equal to zero.

Figure 10 illustrates yet an embodiment of the present BSS amplifier 300.

To understand the origin of the power amplifier 300, the quadrature hybrid combiner 330 and its Z parameters matrix as is shown in Figure 9 may be reviewed. In one implementation of the present power amplifier 300 will assume that the third port 321 is the output port; the first port 31 1 and the second port 313 are the ports where the balanced amplifier 310 is connected and the fourth port 323 is the port where the main amplifier 320 (which may be implemented in several different ways), is connected.

To fulfil that the voltage of the balanced amplifier 310 is equal to the maximum voltage swing, here depicted as Vdd, the following equations may be verified, according to the first and second equation of the Z matrix:

[Equation 1 ]

The currents h and , which corresponds to the currents of the balanced amplifier, are zero. The first equation fixes the value of the output power (I3, the load is Zo) at which the balanced amplifier 310 will start and the second equation fixes the power level of the main amplifier 320 (U, the load is Zo) at the position where the balanced amplifier 310 will start. Because these two values are identical this means that at the total power will be supplied by the main amplifier 320 as was expected. These two equation will define the value of the characteristic impedance of the quadrature hybrid combiner 330.

The impedance modifying structure 324 may in some embodiments be implemented by a transformer.

According to some embodiments, a driving signal is provided, where the main amplifier 320 is also switched on/ off, for that reason the output voltage/ power range is divided in 3 regions, see Figure 11 , which is illustrating power distribution for the proposed driving the power amplifier 300.

In a first region where the balanced amplifier 310 is off and main amplifier 320 is increasing its output power until it reaches its maximum power. This region may cover approximately the first 1 /3 of the output voltage, or 1 /9 of the output power.

In a second region where the balanced amplifier 310 starts to deliver power to the load ramping up and the main amplifier 320 reduces its output power level until completely switches off. This region may cover from approximately 1 / 3 to 2/ 3 of the output voltage or from about 1 / 9 to 4/ 9 of the output power, according to some embodiments.

In a third region where the main amplifier 320 increases its output power level until it reach its maximum power and the balanced amplifier 310 continue to grow its output power until its maximum power level. This region may cover from about 21 3 of the output voltage to maximum output voltage or from about 4/ 9 of the output power to maximum output power or Peak Envelop Power (PEP).

The BSS amplifier 300 driven in this way will achieve maximum voltage swing of the balanced amplifiers 310 from the start point. To utilise the maximum swing of the main amplifier 320 will be necessary to complement the hybrid coupler 330 with a transformer connected to the main amplifier 320 to basically double the impedance that the main amplifier 310 will obtain. This may be deduced from the equation 1 (see Figure 12 for reference): [Equation 2]

Figure 12 illustrates a transformer 324 according to an embodiment.

5 The BSS amplifier 300 using the driving signals with the three described regions, see Figure 1 1 , will result in a maximise voltage swing for the balanced amplifier 310 at all the power levels. The main amplifier 320 will be also reach at maximum power the maximum swing twice in the whole power range see Figure 14. Observe that the phase of the main amplifier driving signal suffer an inversion when entering in region 3, this will be a characteristic of the 10 herein described power amplifiers 300 according to different embodiments.

Figure 13A and 13B illustrates BSS driving signals. The continuous solid lines illustrate the driving signal of the main amplifier 320 while the Dash/ Dash-dot lines illustrate the driving signal of the balanced amplifier 310. Figure 13A depicts amplitude driving currents while 15 Figure 13B illustrates phase driving currents.

A further advantage is the extra efficiency top at about 4/ 9 of PEP which is 3.52 dB back-off due to the switching off of the main amplifier 320 keeping the balanced amplifier 310 to maximum swing. This can be observed in Figure 14, where the drain efficiency of a BSS 20 amplifier 300 is plotted.

Figure 15 illustrates impedances of the power amplifier 300.

It can also be observed the impedance of the main amplifier 320 and the balanced amplifier 25 310 in Figure 15. As expected the main amplifier 320 sees a constant impedance and the balanced amplifier 310 works like a peak amplifier, however the efficiency characteristic looks like a 3-way Doherty thanks to the switching off of the main amplifier 320, which behaves dually like a peak and like a main amplifier.

30 Figure 16 illustrates a general embodiment of a power amplifier 300 according to an embodiment.

Where the size of the main power amplifier 320 may be 1/ 9 of the PEP and the balanced amplifier size may be calculated as: 2^* 4/ 9 of the maximum output power or PEP. (i.e. for a 35 720 W PEP amplifier the Balanced amplifier 310 will be 640 W = 2x 320 W amplifiers in balanced configuration and the main power amplifier 320 may be 80W which could be implemented as single ended 80 W power amplifier (BSS) or as Chireix pair with 2x40 W power amplifiers (BSC) or in the Doherty case the summa of the power of the Doherty main and the Doherty peak will be equal to 80 W (BSD), in different embodiments.

Because the main power amplifier 320 will reach its maximum power at 1/ 9 of PEP (-9.54 dB) if the main power amplifier 320 may be implemented with a Doherty amplifier the relative size of Main and Peak will define the first tent of efficiency of the whole BSD amplifier. If for example to achieve a first efficiency peak at 12 dB back-off will be necessary to design a DHT with -2.46 dB back off. A symmetrical DHT achieve -6 dB back-off pulling the load of the main device by 2 times. In this case the size of the main amplifier 320 may be bigger than the peak amplifier 3.15 times bigger in power and the load of the main amplifier 320 will be pulled by 1 .15 times, achieving a back-off of 12 dB. This is a clear advantage which can be used to design wideband power amplifiers or high efficiency narrow band high power amplifiers.

The impedance modifying structure 324 may comprise a combiner 1610 and a first matching network 1620, and a second matching network 1630. Figure 17A illustrates a voltage swing BSD main amplifier 320 (solid line) and balanced amplifier 310 (Dash line). Figure 17B illustrates efficiency of BSD amplifier versus back-off (dB).

In Figure 17A it may be seen how a 12 dB back off BSD amplifier achieves the maximum swing of the balanced amplifier 310 in the whole range and how the back-off is extended thanks to the Doherty main power amplifier 320 from the 9.54 dB to 12 dB. In Figure 17B the efficiency versus output voltage shows up to 6 peaks of efficiency double than the BSS case which helps to improve the flatness of the efficiency versus back off. Figure 18 illustrates BSD impedances. The solid line depicts the Main Doherty (DHT), the dot line illustrates the peak Doherty and the dot and dot-dash line illustrates the balanced amplifier 310.

In Figure 18, the output impedance presented to every transistor is plotted. It may be noticed the small load pull ratio applied to the Doherty Main amplifier 320. The peak amplifier suffers some load pull ratio but because the size difference with the main amplifier 320 and balanced amplifier 310 affects very few to the total efficiency. The balanced amplifier 310 suffers some load pull but because it follows a maximum voltage swing trajectory across all its back off will still show its maximum possible achievable efficiency.

Because the main power amplifier 320 will reach its maximum power at 1/ 9 of PEP (-9.54 dB) if the main amplifier is implemented with a Chireix amplifier the required back-off of the Chireix pair may be much smaller for a given back-off than previously known solutions. For example, to achieve a first efficiency peak at 12 dB back off may be made to design a Chireix with -2.46 dB back-off. This may imply that to achieve 12 dB back-off, load pull of the load of every transistor in the Chireix pair by: 1 .76 times this value may be small enough to be able to achieve wide bandwidths high efficiency power amplifier designs. Alternatively, one could allow more load pull and increase the back off achieving higher average efficiencies for narrow band designs.

Figure 19A illustrates drain voltages and output voltage of a BSC Main amplifier (solid line) and balanced amplifier (Dash line). Figure 19B illustrates efficiency versus back off of a BSC amplifier.

In Figure 19A B it may be observed how the BSC amplifier achieves a very flat efficiency plateau over almost 5 dB range which will allow to achieve a high average efficiency when signal Peak to Average Ratio (PAR) will be around 9 dB. Furthermore, this range is achieved with a low load pull ratio which guarantee the possibility to implement this architecture and driving signals for wide band power amplifiers.

Figure 20A illustrates impedances. The solid line depicts a real part of impedance of the CHX pair while the dash line depicts a real part of impedance of the balanced amplifier 310. In Figure 20B, the solid line depicts an imaginary part of impedance of the CHX pair while the dash line depicts an imaginary part of impedance of the balanced amplifier 310.

In Figure 20A B it may be observed the impedances for the Chireix pair and for the balanced amplifier 310. It may also be noticed that the load pull ratio at 12dB BO is small 1 .76 times as it was expected. The herein presented architectures: BSS, BSD and/ or BSC may be regarded as some examples of implementations of the power amplifier 300. However, it may be noted that other power amplifier architectures may be used as main amplifier 320 still following the same concept as the herein described. The presented architecture of the power amplifier 300 combined with the new driving methodology improve the trade-off between load pull ratio and back off efficiency. Comparing with previously known solutions based on 3-Way Doherty, for the same back off 12 dB 3- Way DHT requires 2.49 dB load pull ratio and BSD presented here only needs 1 .21 dB load pull ratio.

Comparing embodiments of the power amplifier 300 with the previously known solutions based on Chireix Doherty for the same back-off 12 dB Chireix Doherty requires 9 dB load pull ratio while BSC presented here only needs 2.45 dB. Comparing embodiments of the power amplifier 300 with other previously known solutions, the introduction of the different driving regions with the switching of the balanced amplifier and the switching of the main amplifier 320 introduces further improvement of efficiency at higher back-off. A further advantage of this architecture plus driving signals is the high voltage swing of the balanced amplifiers over the whole back-off range. This may be achieved thanks to the dimensioning of the different power amplifiers combined in this architecture and thanks to the special driving methodology. These advantages can be used in wideband designs to design 40% bandwidth high efficiency high power (more devices are combined than in previously known solutions). These advantages may also be used to design narrow band very efficient power amplifiers 300.

Figure 21 illustrates an example of a method 2100 according to an embodiment. The method 2100 aims at ramping up output power of a power amplifier 300, from zero to maximum power level of the power amplifier 300. The power amplifier 300 comprises a balanced amplifier 310 and a main amplifier 320, which are connected via a hybrid combiner 330.

In order to correctly be able to ramping up output power of the power amplifier 300, the method 2100 may comprise a number of steps 2101 -2105. However, some of the described steps 2101 -2105 may be performed in a somewhat different chronological order than the numbering suggests. The method 2100 may comprise the subsequent steps:

Step 2101 comprises switching on the main amplifier 320. Step 2102 comprises increasing output power of the main amplifier 320 linearly up to a maximum power level of the main amplifier 320, or a predefined or configurable power level, while keeping the balanced amplifier 310 switched off.

Step 2103 comprises switching on the balanced amplifier 310.

Step 2104 comprises linearly increasing output power of the balanced amplifier 310, while decreasing the output power of the main amplifier 320 down to a defined minimum value such as e.g. zero. Step 2105 comprises increasing output power of the main amplifier 320 linearly with the output voltage up to the maximum main amplifier power level while continuing increasing the output power of the balanced amplifier 310 up to the maximum balanced amplifier power level.

Thereby, a family of high efficiency wideband power amplifiers 300 are provided: BSX, i.e. BSS, BSD and/ or BSC. A quadrature hybrid 330 is utilised to isolate the main amplifier 320 which could be implemented in different ways.

A special driving technique where all the amplifiers used are at some back-off switched off, this add extra maximums of efficiency at some back-off levels.

The special driving ramp down and up the main amplifier 320 twice in the whole dynamic range of operation. Dimensioning the main amplifier 320 to provide 1/ 9 of the total output power. This together with the special driving may allow to maximise the voltage swing of the balanced amplifier 310 in the whole back-off range.

The special driving and the dimension of the power amplifiers 300 allows to further increase the back-off range if the main amplifier 320 is implemented with an enhanced efficiency power amplifier 300. The back off efficiency may start at 9.54 dB (1/ 9 of the total power) or at any other defined back-off in other embodiments and therefore the efficiency enhanced mode amplifier used as the main amplifier 320 may only not require too much load pull ratio to achieve higher back-off levels. The low Load Pull Range (LPR) respect to back off can be used to design wideband amplifiers when the LPR is limited to minimise impedance dispersion.

The good trade-off between LPR and back-off can be used to design narrow band high efficiency power amplifiers using back-off levels not possible according to previously known solutions.

A computer program comprising program code for performing the method 2100 according to any of the method steps 2101 -2105, may perform the method 2100 for ramping up output power of the power amplifier 300, from zero to maximum power level of the power amplifier 300 when loaded into a computer.

Figure 22A illustrates a driving circuitry 2200 with a driver DRB of a balanced amplifier 310, 5 according to an embodiment. DM 1 and DM 2 are the drivers of the main amplifier 320. The three inputs may be generated following an algorithm. Thus, the driving circuitry 2200 comprises three input ports and four output ports being connected to drive each of the balanced amplifier 310 and the main amplifier 320, respectively. The driving circuitry 2200 is configured for digital signal decomposition SD. Thereby, full control is achieved, of amplitude 10 and phase.

Figure 22B illustrates yet an embodiment of a driving circuitry 2200 with a driver DRB of a balanced amplifier 310 and a driver DRM of a main amplifier 320 according to an embodiment. The signal decomposition SD may implement analogue signal splitting for the 15 Chireix or Doherty in some embodiments such as BSD and/ or BSC. According to the illustrated embodiment, the driving circuitry 2200 has two input ports and four output ports being connected to drive each of the balanced amplifier 310 and the main amplifier 320, respectively, and an analogue signal decomposition SD.

20 The driving circuitry 2200 is configured to drive the power amplifier 300. The driving circuitry 2200 is configured to provide a driving signal to switch on the main amplifier 320. Further, the driving circuitry 2200 is configured to increase output power of the main amplifier 320 up to a maximum main amplifier power level, while keeping the balanced amplifier 310 switched off. In addition, the driving circuitry 2200 is also configured to switch on the balanced amplifier

25 310. The driving circuitry 2200 is additionally configured to increase output power of the balanced amplifier 310, while decreasing the output power of the main amplifier 320 down to a defined minimum value. In further addition, the driving circuitry 2200 is configured to increase output power of the main amplifier 320 up to the maximum main amplifier power level while continuing increasing the output power of the balanced amplifier 310 up to the

30 maximum balanced amplifier power level.

Hereby an efficient driving of a power amplifier 300 having a main amplifier 320 and a balanced amplifier 310 is provided wherein both the main amplifier 320 and the balanced amplifier 310 may be switched on/ off when driving the power amplifier 300.

35

The terminology used in the description of the embodiments as illustrated in the accompanying drawings is not intended to be limiting of the described method 2100, power amplifier 300, computer program, power amplifier arrangement 2210, a driving circuitry 2200. Various changes, substitutions and/ or alterations may be made, without departing from the invention as defined by the appended claims.

As used herein, the term "and/ or" comprises any and all combinations of one or more of the associated listed items. The term "or" as used herein, is to be interpreted as a mathematical OR, i.e., as an inclusive disjunction; not as a mathematical exclusive OR (XOR), unless expressly stated otherwise. In addition, the singular forms "a", "an" and "the" are to be interpreted as "at least one", thus also possibly comprising a plurality of entities of the same kind, unless expressly stated otherwise. It will be further understood that the terms "includes", "comprises", "including" and/ or "comprising", specifies the presence of stated features, actions, integers, steps, operations, elements, and/ or components, but do not preclude the presence or addition of one or more other features, actions, integers, steps, operations, elements, components, and/ or groups thereof. A single unit such as e.g. a processor may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. A computer program may be stored/ distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms such as via Internet or other wired or wireless communication system.

Claims

1 . A power amplifier (300) comprising:

a main amplifier (320);

a balanced amplifier (310) connected using a hybrid combiner (330), wherein an isolated port of the hybrid combiner (330) is connected to the main amplifier (320), wherein power is delivered at an output port of the hybrid combiner (330); which power amplifier (300) is configured to, when ramping up output power from zero to maximum power level of the power amplifier (300):

firstly, switch on the main amplifier (320) and increase the main amplifier output power up to a maximum power level of the main amplifier (320), while keeping the balanced amplifier (310) switched off;

secondly, switch on power of the balanced amplifier (310) and increase the balanced amplifier output power, while decreasing the output power of the main amplifier (320) down to a defined minimum value; and

thirdly, increase the output power of the main amplifier (320) up to the maximum main amplifier power level while continuing increasing the output power of the balanced amplifier (310) up to the maximum balanced amplifier power level.

2. The power amplifier (300) according to claim 1 , wherein:

the balanced amplifier (310), comprises at least a first amplifier (312) and a second amplifier (314);

the main amplifier (320) comprising at least one third amplifier (322); and wherein the first amplifier (312) of the balanced amplifier (310) is connected to a first connection port (31 1 ) of the hybrid combiner (330);

the second amplifier (314) of the balanced amplifier (310) is connected to a second connection port (313) of the hybrid combiner (330);

a third connection port (321 ) of the hybrid combiner (330) is configured for output; and

the third amplifier (322) of the main amplifier (320) is connected to a fourth connection port (323) of the hybrid combiner (330) connected via an impedance modifying structure (324).

3. The power amplifier (300) according to any one of claim 1 or claim 2, wherein

the main amplifier (320) has further back-off efficiency of the power amplifier (300).

4. The power amplifier (300) according to any one of claims 1 -3, wherein total backoff of the power amplifier (300) is equal to the sum of the back-off of the main amplifier (320) and a threshold value defined by the output power of the power amplifier (300), where the balanced amplifier (310) is switched on.

5. The power amplifier (300) according to any one of claims 1 -4, wherein the main amplifier (320) is single ended.

6. The power amplifier (300) according to any one of claims 1 -4, wherein the main amplifier (320) comprises a Doherty amplifier.

7. The power amplifier (300) according to any one of claims 1 -4, wherein the main amplifier (320) comprises a Chireix amplifier.

8. The power amplifier (300) according to any one of claims 1 -7, wherein the impedance modifying structure (324) comprises a matching network (1620, 1630) and a combiner (1610).

9. The power amplifier (300) according to any one of claims 1 -7, wherein the impedance modifying structure (324) is implemented by a transformer.

10. A method (2100) for ramping up output power of a power amplifier (300), from zero to maximum power level of the power amplifier (300); which power amplifier (300) comprises a balanced amplifier (310) and a main amplifier (320), which are connected via a hybrid combiner (330); wherein the method (2100) comprises:

switching on (2101 ) the main amplifier (320);

increasing (2102) output power of the main amplifier (320) up to a maximum power level of the main amplifier (320), while keeping the balanced amplifier (310) switched off; switching on (2103) the balanced amplifier (310);

increasing (2104) output power of the balanced amplifier (310), while decreasing the output power of the main amplifier (320) down to a defined minimum value; and

increasing (2105) output power of the main amplifier (320) up to the maximum main amplifier power level while continuing increasing the output power of the balanced amplifier (310) up to the maximum balanced amplifier power level.

1 1 . A computer program comprising program code for performing a method (2100) according to claim 10, when the computer program runs on a computer.

12. A power amplifier arrangement (2210) comprising:

the power amplifier (300) according to any one of claims 1 -9;

a driving circuitry (2200), comprising three input ports and four output ports being connected to drive each of the balanced amplifier (310) and the main amplifier (320), respectively; which driving circuitry (2200) is configured for digital signal decomposition.

13. A power amplifier arrangement (2210) comprising:

5 the power amplifier (300) according to any one of claims 1 -9;

a driving circuitry (2200), having two input ports and four output ports being connected to drive each of a balanced amplifier (310) and a main amplifier (320), respectively; and an analogue signal decomposition.

10 14. A driving circuitry (2200), for driving a power amplifier (300), which driving circuitry (2200) is configured to provide a driving signal to:

switch on the main amplifier (320);

increase output power of the main amplifier (320) up to a maximum main amplifier power level, while keeping the balanced amplifier (310) switched off;

15 switch on the balanced amplifier (310);

increase output power of the balanced amplifier (310), while decreasing the output power of the main amplifier (320) down to a defined minimum value; and

increase output power of the main amplifier (320) up to the maximum main amplifier power level while continuing increasing the output power of the balanced amplifier (310) up 20 to the maximum balanced amplifier power level.