WO2019085912A1 - 通信终端及其通信方法、存储介质 - Google Patents

通信终端及其通信方法、存储介质 Download PDF

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Publication number
WO2019085912A1
WO2019085912A1 PCT/CN2018/112799 CN2018112799W WO2019085912A1 WO 2019085912 A1 WO2019085912 A1 WO 2019085912A1 CN 2018112799 W CN2018112799 W CN 2018112799W WO 2019085912 A1 WO2019085912 A1 WO 2019085912A1
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Prior art keywords
core processor
radio frequency
communication terminal
signal
fpga
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Application number
PCT/CN2018/112799
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English (en)
French (fr)
Inventor
唐彦波
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捷开通讯(深圳)有限公司
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Publication of WO2019085912A1 publication Critical patent/WO2019085912A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/401—Circuits for selecting or indicating operating mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a communication terminal, a communication method thereof, and a storage medium.
  • DSPs digital signal processors
  • the embodiment of the invention provides a communication terminal, a communication method thereof and a storage medium, which can solve the improvement of the processing capability and flexibility of the communication terminal.
  • an embodiment of the present invention provides a communication terminal, where the communication terminal is based on a general-purpose processor, including: an interconnected baseband card and a radio frequency board, the baseband board includes a multi-core processor, and the radio frequency board includes interconnected a radio frequency transceiver and a field programmable gate array FPGA, wherein the radio frequency transceiver is used for signal transmission and reception; the FPGA includes a channel decoding unit, and the channel decoding unit is used for usage of the multi-core processor The signal received by the radio frequency transceiver is subjected to channel decoding processing when the value is set.
  • a general-purpose processor including: an interconnected baseband card and a radio frequency board, the baseband board includes a multi-core processor, and the radio frequency board includes interconnected a radio frequency transceiver and a field programmable gate array FPGA, wherein the radio frequency transceiver is used for signal transmission and reception; the FPGA includes a channel decoding unit, and the channel decoding unit is used for usage of
  • the radio frequency transceiver has a single channel bandwidth of at least 80 MHz.
  • the radio frequency transceiver is an AD9371.
  • the multi-core processor is an 8-core processor.
  • the baseband card comprises a first sub-baseband card and a second sub-baseband card, the first sub-baseband card and the second sub-baseband card being connected by the data bus;
  • the first sub-baseband The board includes the multi-core processor, and the second sub-baseband card includes a second FPGA.
  • the second FPGA includes a channel decoding unit, and the channel decoding unit is configured to perform channel decoding processing on a signal received by the radio frequency transceiver when a usage rate of the multi-core processor exceeds a set value;
  • the FPGA on the radio frequency board is configured to process the signal received by the radio frequency transceiver when the usage rate of the multi-core processor exceeds a set value.
  • the FPGA on the radio frequency board is specifically configured to perform fast Fourier transform or inverse fast Fourier transform processing on the received signal when the usage rate of the multi-core processor exceeds a set value.
  • the baseband board and the radio frequency board are connected by a data bus.
  • the digital signal protocol stack running by the multi-core processor is an LTE or 5G protocol stack.
  • the baseband board and the radio frequency board are connected by wireless.
  • the multi-core processor includes a PCIE interface, a CPU, a double-rate synchronous dynamic random access memory, and a bus.
  • the double-rate synchronous dynamic random access memory electrically connects to the PCIE interface, acquires and stores information from the data bus through the PCIE interface, and doubles the rate.
  • the synchronous dynamic random access memory electrically connects to the bus; the CPU acquires and processes the information stored in the double rate synchronous dynamic random access memory through the bus.
  • the radio frequency transceiver is provided with a signal transmitting end and a signal receiving end.
  • an embodiment of the present invention provides a communication method of a communication terminal, where the communication terminal is based on a general-purpose processor, including a baseband card and a radio frequency board connected to each other, and the baseband card includes a multi-core processor, and the radio frequency board includes each other.
  • the connected radio frequency transceiver and the field programmable gate array FPGA the communication method of the communication terminal includes: the communication terminal receives a signal through the radio frequency transceiver; and determines whether the current usage rate of the multi-core processor of the communication terminal exceeds The value is set; if the current usage rate of the multi-core processor exceeds the set value, the signal is processed by the field programmable gate array FPGA.
  • the baseband card comprises a first sub-baseband card and a second sub-baseband card, the first sub-baseband card and the second sub-baseband card being connected by the data bus;
  • the first sub-baseband The board includes the multi-core processor, and the second sub-baseband card includes a second FPGA; if the current usage rate of the multi-core processor exceeds the set value, the field through the radio frequency board may be
  • the step of programming the gate array FPGA to process the signal specifically includes:
  • the multi-core processor If the current usage rate of the multi-core processor exceeds the set value, performing channel decoding processing on the signal by using the second FPGA; and using an FFT module of the field programmable gate array FPGA of the radio frequency board
  • the signal is subjected to fast Fourier transform processing or fast inverse Fourier transform processing.
  • the radio frequency transceiver has a single channel bandwidth of at least 80 MHz.
  • the radio frequency transceiver is an AD9371.
  • the multi-core processor is an 8-core processor.
  • the baseband board and the radio frequency board are connected by a data bus.
  • the digital signal protocol stack running by the multi-core processor is an LTE or 5G protocol stack.
  • an embodiment of the present invention provides a storage medium storing a plurality of instructions, the instructions being adapted to be loaded by a processor and performing the following steps:
  • the communication terminal receives a signal through the radio frequency transceiver; wherein the communication terminal is based on a general-purpose processor, the communication terminal includes an interconnected baseband card and a radio frequency board, and the baseband card comprises a multi-core processor and a radio frequency board.
  • the card includes an interconnected RF transceiver and a field programmable gate array FPGA;
  • the signal is processed by the field programmable gate array FPGA if the current usage of the multi-core processor exceeds the set value.
  • the baseband card comprises a first sub-baseband card and a second sub-baseband card, the first sub-baseband card and the second sub-baseband card being connected by the data bus;
  • the first sub-baseband The board includes the multi-core processor, and the second sub-baseband card includes a second FPGA; if the current usage rate of the multi-core processor exceeds the set value, the field through the radio frequency board may be
  • the step of programming the gate array FPGA to process the signal specifically includes:
  • the multi-core processor If the current usage rate of the multi-core processor exceeds the set value, performing channel decoding processing on the signal by using the second FPGA; and using an FFT module of the field programmable gate array FPGA of the radio frequency board
  • the signal is subjected to fast Fourier transform processing or fast inverse Fourier transform processing.
  • the invention adopts a communication terminal based on a general processor architecture, the baseband board of the communication terminal has a multi-core processor, and when the usage rate of the multi-core processor exceeds a set value, the channel decoding function is sunk to the communication terminal.
  • the FPGA on the RF board is processed.
  • the invention decomposes the physical layer part of the processor on the AMC board and distributes it to other modules for collaborative processing, which brings about an improvement in processing capability and flexibility, and also improves user experience.
  • FIG. 1 is a schematic structural diagram of a communication terminal according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a communication terminal according to another embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a communication method of a communication terminal according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a communication terminal according to an embodiment of the present invention.
  • This embodiment provides a communication terminal, including: a baseband card 101 and a radio frequency card 102.
  • the baseband card 101 and the radio frequency card 102 are connected by a data bus PCIE 103.
  • the baseband card 101 and the radio frequency board are connected.
  • Card 102 can communicate information over a wireless connection.
  • the baseband card 101 is provided with a multi-core processor 104 based on a general-purpose processor architecture and capable of processing real-time baseband signals and operating a large number of digital signal processing algorithms used in mobile communications.
  • the multi-core processor 104 can be an 8-core processor, such as an Intel i7 8 core processor, or more core processors, such as 16 cores, or 32 cores, etc., as long as the mobile communication technology can be realized.
  • a large number of digital signal processing algorithms used in the present invention can complete the real-time processing of communication signals, which is not limited herein.
  • the digital signal protocol stack operated by the multi-core processor 104 is a protocol stack of LTE or 5G.
  • the multi-core processor 104 includes a PCIE interface 108, a CPU 105, a double rate synchronous dynamic random access memory 106, and a bus 107, and the processor is coupled to the data bus 103 via a PCIE interface 108.
  • the double rate synchronous dynamic random access memory 106 is electrically coupled to the PCIE interface 108, through which information is acquired and stored from the data bus 103, and the double rate synchronous dynamic random access memory 106 is electrically coupled to the bus 107.
  • the CPU 105 acquires and processes the information stored in the double rate synchronous dynamic random access memory 106 via the bus 107.
  • the multi-core processor 104 can be other general-purpose processor-based processors, as long as it can process real-time baseband signals and run a large number of digital signal processing algorithms used in mobile communications, and support the fifth generation. Even multi-core processors with higher generation mobile communication technologies, such as i9, AMD Ryzen 7 processors, etc.
  • the RF card 102 is provided with a field programmable gate array FPGA 109 and a radio frequency transceiver 110, and the field programmable gate array FPGA 109 and the RF transceiver 110 are electrically connected.
  • the field programmable gate array FPGA 109 is provided with a PCIE interface 111 and a channel decoding unit 112.
  • the PCIE interface 111 is electrically coupled to the channel decoding unit 112 and the data bus 103.
  • the channel decoding unit 112 is configured to perform decoding processing on the signal received by the multi-core processor 104 through the radio frequency transceiver 110 when the usage rate of the multi-core processor 104 exceeds a set value.
  • the present embodiment selects a Xilinx-based processor ZYNQ, which not only has digital up-conversion and filtering processing functions, but also includes a channel decoding unit 112, which can be used for a multi-core processor.
  • the channel transmitted through the data bus 203 performs channel decoding processing.
  • processors that have not only digital up-conversion and filtering processing functions but also channel decoding processing on signals transmitted by the multi-core processor 104 may be selected.
  • the RF transceiver 110 is provided with a signal transmitting end 113 and a signal receiving end 114.
  • the single-channel bandwidth of the radio frequency transceiver 110 is at least 80 MHz. Therefore, the AD9371 chip with the baseband real-time processing capability of 1200 MHz and the single chip supporting dual-issue and dual-receiver is used as the radio frequency transceiver. 110.
  • a signal transceiver device with a single channel bandwidth greater than 80 MHz is selected as the radio frequency transceiver.
  • the communication terminal may be a base station or an intelligent terminal supporting a general-purpose processor architecture.
  • the base station is taken as an example to describe the function of the communication terminal by receiving and transmitting the 5G signal by the base station.
  • the communication terminal is a base station
  • the multi-core processor 104 on the baseband card 101 is an Intel i7 8 core processor
  • the RF transceiver 110 on the RF board 102 is an AD9371
  • the FPGA 109 is based on Xilinx processing. ZYNQ.
  • the signal receiving end 114 on the RF transceiver 110 receives the analog signal
  • the RF transceiver 110 converts the analog signal into a digital signal and transmits it to the FPGA 109.
  • the FPGA 109 digitally up-converts and filters the received digital signal.
  • the FPGA 109 transmits the processed signal to the data bus 103 through the PCIE interface 111.
  • the multi-core processor 104 receives the signal transmitted by the data bus 103 through the PCIE interface 108, and the multi-core processor 104 processes the received signal according to the 5G protocol stack.
  • the multi-core processor 104 may sink the signal decoding portion of the 5G protocol stack to the FPGA 109 for processing. Specifically, when the usage rate exceeds the set value, the multi-core processor 104 transmits the signal received through the radio frequency transceiver 110 to the FPGA 109 through the data bus 103, and the channel decoding unit 112 on the FPGA 109 performs channel decoding processing on the signal, and The processed signal is transmitted to the multi-core processor 104 via the data bus 203.
  • the multi-core processor 104 achieves the purpose of quickly processing the received signals through secondary interaction with the FPGA 109 on the RF board 102.
  • the communication terminal is a base station
  • the multi-core processor 104 is an Intel
  • the i7 8-core processor, RF transceiver 110 is the AD9371
  • the FPGA 109 is the Xilinx-based processor ZYNQ.
  • the multi-core processor 104 located on the baseband card 101 processes the signal according to the 5G protocol stack, and transmits the processed signal to the data bus 103 through the PCIE interface 108.
  • the FPGA 109 receives the signal transmitted by the data bus 103 through the PCIE interface 111, and the FPGA 109 The signal is not processed and transmitted directly to the radio frequency transceiver 110, and the radio frequency transceiver 110 transmits the received signal through the signal transmitting end 113.
  • the usage setting value of the multi-core processor can be set according to actual conditions. For example, when the usage rate of the multi-core processor exceeds 80%, the temperature of the processor easily exceeds the safe temperature, which may cause the device to age. The problem of poor heat dissipation, etc., in this case, the set value can be set to 80%. In other cases, the set value can be set to a range in which the communication terminal can operate safely and quickly.
  • the multi-core processor can also sink other parts of the 5G protocol stack to the FPGA on the RF board for processing.
  • the invention has the beneficial effects that, different from the prior art, the present invention adopts a communication terminal based on a general-purpose processor architecture, the baseband board of the communication terminal has a multi-core processor, and the usage rate of the multi-core processor exceeds When the value is set, the channel decoding function is sunk to the FPGA on the radio frequency board of the communication terminal for processing.
  • the invention decomposes the physical layer part of the processor on the AMC board and distributes it to other modules for collaborative processing, which brings about an improvement in processing capability and flexibility, and also improves user experience.
  • FIG. 2 is a schematic structural diagram of a communication terminal according to an embodiment of the present invention.
  • the embodiment provides a communication terminal, including: a first sub-baseband card 201, a second sub-baseband card 202, and a radio frequency card 204, a first sub-baseband card 201, a second sub-baseband card 202, and a radio frequency.
  • the boards 204 are connected by the data bus PCIE 203.
  • the first sub-baseband card 201, the second sub-baseband card 202, and the radio frequency card 204 can also transmit information in a wireless manner.
  • the first sub-baseband card 201 is provided with a multi-core processor 205 based on a general-purpose processor architecture and capable of processing real-time baseband signals and operating a large number of digital signal processing algorithms used in mobile communications.
  • the multi-core processor 205 can be an 8-core processor, such as an Intel i7 8 core processor, or more core processors, such as 16 cores, or 32 cores, etc., as long as the mobile communication technology can be implemented.
  • a large number of digital signal processing algorithms used in the present invention can complete the real-time processing of communication signals, which is not limited herein.
  • the digital signal protocol stack operated by the multi-core processor 205 is a protocol stack of LTE or 5G.
  • the multi-core processor 205 includes a PCIE interface 209, a CPU 206, a double rate synchronous dynamic random access memory 207, and a bus 208, and the processor is coupled to the data bus 203 via a PCIE interface 209.
  • the double rate synchronous dynamic random access memory 207 is electrically coupled to the PCIE interface 209, through which information is acquired and stored from the data bus 203, and the double rate synchronous dynamic random access memory 207 is electrically coupled to the bus 208.
  • the CPU 206 acquires and processes the information stored in the double rate synchronous dynamic random access memory 207 via the bus 208.
  • the multi-core processor 104 can be other general-purpose processor-based processors, as long as it can process real-time baseband signals and run a large number of digital signal processing algorithms used in mobile communications, and support the fifth generation. Even multi-core processors with higher generation mobile communication technologies, such as i9, AMD Ryzen 7 processors, etc.
  • the second baseband board 202 is provided with a second FPGA 210.
  • the second FPGA 210 includes a PCIE interface 211 and a channel decoding unit 212, and the PCIE interface 211 and the channel decoding unit 212 are electrically connected.
  • the PCIE interface 211 is connected to the data bus 203 through which the second baseband card 202 acquires information transmitted by the multi-core processor 205.
  • the channel decoding unit 212 is configured to perform decoding processing on the signal received by the multi-core processor 205 through the radio frequency transceiver 220 when the usage rate of the multi-core processor 205 exceeds a set value.
  • the present embodiment selects a Xilinx-based processor ZYNQ, which not only has digital up-conversion and filtering processing functions, but also includes a channel decoding unit 212, which can be used for a multi-core processor.
  • the signal transmitted by 205 is subjected to channel decoding processing.
  • other processors that can perform channel decoding processing on signals transmitted by the multi-core processor 205 may be selected.
  • the RF board 204 is provided with a field programmable gate array FPGA 213 and a radio frequency transceiver 220.
  • the field programmable gate array FPGA 213 and the RF transceiver 220 are electrically connected.
  • the field programmable gate array FPGA 213 includes a PCIE interface 214 and an FFT module 216 and an IFFT module 215.
  • the PCIE interface 214 is connected to the data bus 203 through which the RF board 204 acquires or transmits information from the data bus 203.
  • the FFT module 216 is configured to perform fast Fourier transform processing on the FPGA 213 after receiving the signal received by the RF transceiver 220.
  • the IFFT module 215 is configured to: after the FPGA 213 receives the signal transmitted by the multi-core processor 205 through the data bus 203. Inverse Fast Fourier Transform processing.
  • the present embodiment selects a Xilinx-based processor ZYNQ, which not only has digital up-down conversion and filtering processing functions, but also includes an FFT module 216 and an IFFT module 215.
  • the signal can be subjected to fast Fourier transform processing and fast Fourier transform processing.
  • other processors having digital up-conversion and filtering processing functions, and performing fast Fourier transform processing and fast Fourier transform processing on the signal may be selected.
  • the RF transceiver 220 is provided with a signal transmitting end 218 and a signal receiving end 219.
  • the single-channel bandwidth of the radio frequency transceiver 220 is at least 80 MHz. Therefore, in this embodiment, the ADI's support baseband real-time processing capability is 1200 MHz, and the single chip supports the dual-issue dual-receiving AD9371 chip as the radio frequency transceiver. 220.
  • a signal transceiver device with a single channel bandwidth greater than 80 MHz is selected as the radio frequency transceiver.
  • the communication terminal may be a base station or an intelligent terminal supporting a general-purpose processor architecture.
  • the base station is taken as an example to describe the function of the communication terminal by receiving and transmitting the 5G signal by the base station.
  • the communication terminal is a base station
  • the multi-core processor 205 on the first sub-substrate 201 is an Intel i7 8 core processor
  • the radio frequency transceiver 220 on the radio frequency board 203 is an AD9371, respectively located in the second sub-baseband.
  • the second FPGA 210 and the FPGA 213 on the board 202 and the RF board 203 are both Xilinx-based processors ZYNQ.
  • the signal receiving end 219 on the RF transceiver 220 receives the analog signal
  • the RF transceiver 220 converts the analog signal into a digital signal and transmits it to the FPGA 213.
  • the FPGA 213 performs digital up-conversion processing and filtering processing on the received digital signal.
  • the FPGA 213 transmits the processed signal to the data bus 103 via the PCIE interface 214.
  • the multi-core processor 205 receives the signal transmitted by the data bus 203 through the PCIE interface 209, and the multi-core processor 205 processes the received signal according to the 5G protocol stack.
  • the multi-core processor 104 may sink the signal decoding portion in the 5G protocol stack to the second FPGA 210 on the second sub-substrate 202 for processing, and The fast Fourier transform portion of the 5G protocol stack sinks to the FFT module 216 in the FPGA 213 for processing.
  • the radio frequency transceiver 220 receives the analog signal through the signal receiving terminal 219, converts the analog signal into a digital signal, and then transmits the digital signal to the FPGA 213, and the FPGA 213 transmits the received digital signal.
  • the FFT module 216 in the FPGA 213 performs fast Fourier transform processing on the received signal
  • the FPGA 213 transmits the processed signal to the data bus 203 through the PCIE interface 214
  • the multi-core processor 205 passes the PCIE.
  • Interface 209 receives the signals transmitted by data bus 203.
  • the multi-core processor 205 transmits the signal received through the RF transceiver 220 to the second FPGA 210 through the data bus 203
  • the second FPGA 210 performs channel decoding processing on the signal
  • the multi-core processor 205 achieves the purpose of quickly processing the received signals by the FPGA 213 on the RF board 204 and the second interaction with the second FPGA 210 on the second sub-board 202.
  • the communication terminal is a base station
  • the multi-core processor 205 on the first sub-baseband card 201 is an Intel i7 8 core processor
  • the RF transceiver 220 is an AD9371, which are respectively located in the second sub-baseband board 202.
  • the second FPGA 210 and the FPGA 213 on the RF board 203 are both Xilinx-based processors ZYNQ.
  • the multi-core processor 205 located on the first sub-baseband card 201 processes the signal according to the 5G protocol stack, and transmits the processed signal to the data bus 203 through the PCIE interface 209.
  • the FPGA 213 receives the data bus 203 through the PCIE interface 214.
  • the signal, FPGA 213 does not process the signal and transmits it directly to the radio frequency transceiver 220, and the radio frequency transceiver 220 transmits the received signal through the signal transmitting end 218.
  • the multi-core processor 205 allocates an operation of performing fast inverse Fourier transform processing on the signal in the 5G protocol stack to the FPGA 213 on the radio frequency board 204.
  • the multi-core processor 104 transmits the signal to be processed to the FPGA 213 through the data bus 103, and the IFF module 215 on the FPGA 213 performs inverse fast Fourier transform processing on the signal, and processes the signal.
  • the subsequent signal is transmitted to the RF transceiver 220.
  • the RF transceiver 220 converts the received signal into an analog signal and transmits it through the signal transmitting terminal 218.
  • the usage setting value of the multi-core processor can be set according to actual conditions. For example, when the usage rate of the multi-core processor exceeds 80%, the temperature of the processor easily exceeds the safe temperature, which may cause the device to age. In the case of poor heat dissipation, the set value can be set to 80%. In other cases, the set value can be set as a range in which the communication terminal can operate safely and quickly.
  • the multi-core processor can partially process the other parts of the 5G protocol stack by performing an inverse fast Fourier transform process on the signal in the 5G protocol stack and sinking it to the FPGA on the RF board.
  • the FPGA is processed on the RF board and the second sub-baseband board, and the sinking of each part of the 5G protocol stack can be allocated according to the usage rate or processing capability of the multi-core processor.
  • the invention has the beneficial effects that, different from the prior art, the present invention adopts a communication terminal based on a general-purpose processor architecture, the baseband board of the communication terminal has a multi-core processor, and the usage rate of the multi-core processor exceeds When the value is set, the channel decoding function is sunk to the FPGA on the radio frequency board of the communication terminal for processing.
  • the invention decomposes the physical layer part of the processor on the AMC board and distributes it to other modules for collaborative processing, which brings about an improvement in processing capability and flexibility, and also improves user experience.
  • FIG. 3 is a schematic flowchart of a communication method of a communication terminal according to an embodiment of the present invention.
  • the communication method of the communication terminal of the present embodiment includes the following steps:
  • the communication terminal receives a signal through the radio frequency transceiver.
  • the communication terminal is a base station
  • the multi-core processor on the baseband board is an Intel i7 8-core processor
  • the RF transceiver on the RF board is an AD9371
  • the FPGA is a Xilinx-based processor ZYNQ.
  • the signal receiving end of the RF transceiver receives the analog signal
  • the RF transceiver converts the analog signal into a digital signal and transmits it to the FPGA.
  • the FPGA performs digital up-conversion processing and filtering processing on the received digital signal.
  • the FPGA transmits the processed signal to the data bus through the PCIE interface
  • the multi-core processor receives the signal transmitted by the data bus through the PCIE interface, and the multi-core processor processes the received signal according to the 5G protocol stack.
  • the communication terminal is a base station
  • the multi-core processor on the first sub-substrate is an Intel i7 8 core processor
  • the radio frequency transceiver on the radio frequency board is an AD9371, respectively located on the second sub-baseband board and
  • the second FPGA and FPGA on the RF board are both Xilinx-based processors ZYNQ.
  • the signal receiving end of the RF transceiver receives the analog signal, and the RF transceiver converts the analog signal into a digital signal and transmits it to the FPGA.
  • the FPGA performs digital up-conversion processing and filtering processing on the received digital signal.
  • the FPGA transmits the processed signal to the data bus through the PCIE interface
  • the multi-core processor receives the signal transmitted by the data bus through the PCIE interface
  • the multi-core processor processes the received signal according to the 5G protocol stack.
  • S302 Determine whether the current usage rate of the multi-core processor of the communication terminal exceeds a set value.
  • the multi-core processor When the multi-core processor processes the signal, it detects its usage rate in real time and determines whether it exceeds the set value.
  • the usage setting value of the multi-core processor can be set according to actual conditions. For example, when the usage rate of the multi-core processor exceeds 80%, the temperature of the processor easily exceeds the safe temperature, which may cause the device to age. The problem of poor heat dissipation, etc., in this case, the set value can be set to 80%. In other cases, the set value can be set to a range in which the communication terminal can operate safely and quickly.
  • the signal decoding portion of the 5G protocol stack is sunk to the FPGA for processing.
  • the multi-core processor transmits the signal received by the radio frequency transceiver to the FPGA through the data bus, and the channel decoding unit on the FPGA performs channel decoding processing on the signal, and transmits the processed signal to the multi-core processor through the data bus.
  • the multi-core processor achieves the purpose of quickly processing the received signal through secondary interaction with the FPGA on the RF board.
  • the multi-core processor may sink the signal decoding portion of the 5G protocol stack to the second FPGA on the second sub-substrate for processing. And the fast Fourier transform part of the 5G protocol stack is sunk to the FFT module in the FPGA for processing.
  • the RF transceiver receives the analog signal through the signal receiving end, converts the analog signal into a digital signal, and then transmits the digital signal to the FPGA on the RF board, and the FPGA performs digital up-conversion processing on the received digital signal.
  • the FFT module in the FPGA performs fast Fourier transform processing on the received signal
  • the FPGA transmits the processed signal to the data bus through the PCIE interface
  • the multi-core processor receives the signal transmitted by the data bus through the PCIE interface.
  • the multi-core processor transmits the signal received by the RF transceiver to the second FPGA through the data bus
  • the second FPGA performs channel decoding processing on the signal, and transmits the processed signal to the multi-core processor through the data bus.
  • the multi-core processor achieves the purpose of rapidly processing the received signal by performing fast Fourier transform on the signal on the FPGA on the RF board 204 and secondary interaction with the second FPGA on the second sub-substrate.
  • the multi-core processor can partially process the other parts of the 5G protocol stack by performing an inverse fast Fourier transform process on the signal in the 5G protocol stack and sinking it to the FPGA on the RF board.
  • the FPGA is processed on the RF board and the second sub-baseband board, and the sinking of each part of the 5G protocol stack can be allocated according to the usage rate or processing capability of the multi-core processor.
  • the invention has the beneficial effects that, different from the prior art, the present invention adopts a communication terminal based on a general-purpose processor architecture, the baseband board of the communication terminal has a multi-core processor, and the usage rate of the multi-core processor exceeds When the value is set, the channel decoding function is sunk to the FPGA on the radio frequency board of the communication terminal for processing.
  • the invention decomposes the physical layer part of the processor on the AMC board and distributes it to other modules for collaborative processing, which brings about an improvement in processing capability and flexibility, and also improves user experience.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Telephone Function (AREA)
  • Transceivers (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

本发明公开了一种通信终端及其通信方法，包括：相互连接的基带板卡以及射频板卡，基带板卡包括多核处理器，射频板卡包括相互连接的射频收发器和现场可编程门阵列FPGA，射频收发器用于信号的发送和接收；FPGA包括信号信道解码单元，信道解码单元用于在多核处理器的使用率超过设定值时对射频收发器接收到的信号进行信道解码处理。

Description

通信终端及其通信方法、存储介质
本申请要求于2017年10月31日提交中国专利局、申请号为201711055622.4、发明名称为“通信终端及其通信方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域，特别是涉及通信终端及其通信方法、存储介质。
 背景技术
目前全球关于5G的技术研究正如火如荼的开展，但是3GPP标准化也还在同步进行，迄今为止还没有一个定型的版本。多数从事5G研究的厂商一致认为，到2020年前后，5G 才能逐步进入商用阶段，并在全球范围内走进人们的生活。
基于5G协议的不确定性，对测试终端的软件架构设计提出了挑战。与传统的基于 FPGA、专用芯片或DSP的系统不同，基于通用处理器(GPP)实现的纯软件架构的开放式5G无线系统可以方便地使用各种成熟的软件工程方法，提高软件开发效率与开发质量。
尽管数字信号处理器(DSP)近年来在架构、性能和功耗上都取得了很多进步，为基于软件实现的移动通信基站提供了更多的选择，但是由于不同厂家甚至同一厂家的各种 DSP在向后兼容性上不一致，而且所支持的实时操作系统也不尽相同，因此业界目前缺少统一的平台和标准。与此同时，随着通用处理器相关技术的迅速发展，通用处理器逐渐可以满足数字信号处理等具有高数据负荷运算的要求，为软件实现数字信号处理提供了新的选择。
尽管采用通用处理器完成基带信号处理在系统费用、容量和灵活性等方面都显示出传统专用硬件所没有的优势，但是，采用通用处理器处理实时基带信号也带来了新的挑战，首当其冲的就是对于移动通信中使用的大量数字信号处理算法，由于其高实时性的要求，传统基站和终端设计都是主要在硬件平台上以数字信号处理器的方式进行实现。
因此，现有技术还有待于改进和发展。
 技术问题
本发明实施例提供一种通信终端及其通信方法、存储介质，能够解决提高通信终端的处理能力和灵活性。
 技术解决方案
第一方面，本发明实施例提供一种通信终端，该通信终端基于通用处理器，包括：相互连接的基带板卡以及射频板卡，基带板卡包括多核处理器，射频板卡包括相互连接的射频收发器和现场可编程门阵列FPGA，其中，所述射频收发器用于信号的发送和接收；所述FPGA包括信道解码单元，所述信道解码单元用于在所述多核处理器的使用率超过设定值时对所述射频收发器接收到的信号进行信道解码处理。
其中，所述射频收发器单通道频带带宽至少为80MHZ。
其中，所述射频收发器为AD9371。
其中，所述多核处理器为8核处理器。
其中，所述基带板卡包括第一子基带板卡和第二子基带板卡，所述第一子基带板卡和第二子基带板卡通过所述数据总线连接；所述第一子基带板卡包括所述多核处理器，所述第二子基带板卡包括第二FPGA，
所述第二FPGA包括信道解码单元，所述信道解码单元用于在所述多核处理器的使用率超过设定值时对所述射频收发器接收到的信号进行信道解码处理；
所述射频板卡上的FPGA用于在所述多核处理器的使用率超过设定值时对所述所述射频收发器接收到的信号进行处理。
其中，所述射频板卡上的FPGA具体用于在所述多核处理器的使用率超过设定值时对所述接收的信号进行快速傅里叶变换或快速傅里叶逆变换处理。
其中，所述基带板卡和所述射频板卡通过数据总线连接。
其中，所述多核处理器运行的数字信号协议栈为LTE或5G的协议栈。
其中，所述基带板卡和射频板卡通过无线连接。
其中，所述多核处理器包括PCIE接口、CPU、双倍速率同步动态随机存储器以及总线，双倍速率同步动态随机存储器电连接PCIE接口，通过PCIE接口从数据总线获取并存储信息，并且双倍速率同步动态随机存储器电连接总线；CPU通过总线获取双倍速率同步动态随机存储器存储的信息并对其进行处理。
其中，所述射频收发器上设有信号发送端和信号接收端。
第二方面，本发明实施例提供一种通信终端的通信方法，该通信终端基于通用处理器，包括相互连接的基带板卡以及射频板卡，基带板卡包括多核处理器，射频板卡包括相互连接的射频收发器和现场可编程门阵列FPGA，该通信终端的通信方法包括：所述通信终端通过所述射频收发器接收信号；判断所述通信终端的多核处理器当前的使用率是否超过设定值；如果所述多核处理器当前的使用率超过所述设定值，通过所述现场可编程门阵列FPGA对所述信号进行处理。
其中，所述基带板卡包括第一子基带板卡和第二子基带板卡，所述第一子基带板卡和第二子基带板卡通过所述数据总线连接；所述第一子基带板卡包括所述多核处理器，所述第二子基带板卡包括第二FPGA；所述如果所述多核处理器当前的使用率超过所述设定值，通过所述射频板卡的现场可编程门阵列FPGA对所述信号进行处理的步骤具体包括：
如果所述多核处理器当前的使用率超过所述设定值，通过所述第二FPGA对所述信号进行信道解码处理；通过所述射频板卡的现场可编程门阵列FPGA的FFT模块对所述信号进行快速傅里叶变换处理或快速傅里叶逆变换处理。
其中，所述射频收发器单通道频带带宽至少为80MHZ。
其中，所述射频收发器为AD9371。
其中，所述多核处理器为8核处理器。
其中，所述基带板卡和所述射频板卡通过数据总线连接。
其中，所述多核处理器运行的数字信号协议栈为LTE或5G的协议栈。
第三方面，本发明实施例提供一种存储介质，其存储有多条指令，所述指令适于由处理器加载并执行如下步骤：
所述通信终端通过所述射频收发器接收信号；其中，所述通信终端基于通用处理器，所述通信终端包括相互连接的基带板卡以及射频板卡，基带板卡包括多核处理器，射频板卡包括相互连接的射频收发器和现场可编程门阵列FPGA；
判断所述通信终端的多核处理器当前的使用率是否超过设定值；
如果所述多核处理器当前的使用率超过所述设定值，通过所述现场可编程门阵列FPGA对所述信号进行处理。
其中，所述基带板卡包括第一子基带板卡和第二子基带板卡，所述第一子基带板卡和第二子基带板卡通过所述数据总线连接；所述第一子基带板卡包括所述多核处理器，所述第二子基带板卡包括第二FPGA；所述如果所述多核处理器当前的使用率超过所述设定值，通过所述射频板卡的现场可编程门阵列FPGA对所述信号进行处理的步骤具体包括：
如果所述多核处理器当前的使用率超过所述设定值，通过所述第二FPGA对所述信号进行信道解码处理；通过所述射频板卡的现场可编程门阵列FPGA的FFT模块对所述信号进行快速傅里叶变换处理或快速傅里叶逆变换处理。
 有益效果
本发明采用了基于通用处理器架构的通信终端，该通信终端的基带板卡上有多核处理器，且在多核处理器的使用率超过设定值时，将信道解码功能下沉到该通信终端的射频板卡上的FPGA进行处理。本发明通过将AMC板卡上的处理器物理层部分功能分解，并分配到其他模块协同处理，带来处理能力的提高和灵活性的提升，也提高使用者的体验度。
 附图说明
图1是本发明实施例提供的通信终端的结构示意图；
图2是本发明另一实施例提供的通信终端的结构示意图；
图3是本发明实施例提供的通信终端的通信方法的流程示意图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，均属于本发明保护的范围。
请参阅图1，图1是本发明实施例提供的通信终端的结构示意图。
本实施例提供了一种通信终端，包括：基带板卡101和射频板卡102，基带板卡101和射频板卡102通过数据总线PCIE 103连接，在其他场景中，基带板卡101和射频板卡102可无线连接传递信息。
其中，基带板卡101上设置有多核处理器104，该多核处理器104基于通用处理器架构，且可以处理实时基带信号以及运行移动通信中使用的大量数字信号处理算法。在本实施例中，该多核处理器104可以为8核处理器，如Intel i7 8核处理器，或更多核处理器，如16核，或32核等等，只要能实现运行移动通信技术中使用的大量数字信号处理算法，完成通信信号的实时处理均可，在此不做限定。
具体地，多核处理器104运行的数字信号协议栈为LTE或5G的协议栈。在一个可选的实施方式中，该多核处理器104包括PCIE接口108、CPU105、双倍速率同步动态随机存储器106以及总线107，且该处理器通过PCIE接口108连接数据总线103。双倍速率同步动态随机存储器106电连接PCIE接口108，通过该接口从数据总线103获取并存储信息，并且双倍速率同步动态随机存储器106电连接总线107。CPU105通过总线107获取双倍速率同步动态随机存储器106存储的信息并对其进行处理。
可选的，在其他实施例中，多核处理器104可以为其他基于通用处理器架构的处理器，只要能处理实时基带信号以及运行移动通信中使用的大量数字信号处理算法，且支持第五代甚至更高代移动通信技术的多核处理器即可，如i9、AMD Ryzen 7处理器等。
其中，射频板卡102上设置有现场可编程门阵列FPGA109和射频收发器110，现场可编程门阵列FPGA109和射频收发器110之间电连接。其中现场可编程门阵列FPGA109上设有PCIE接口111和信道解码单元112。PCIE接口111电连接信道解码单元112和数据总线103。信道解码单元112用于在多核处理器104的使用率超过设定值时对多核处理器104通过射频收发器110收到的信号进行解码处理。为分担多核处理器104的数字信号处理工作，本实施例选用基于Xilinx的处理器 ZYNQ，该处理器不仅具有数字上下变频和滤波处理功能，而且包括信道解码单元112，该单元可以对多核处理器104通过数据总线203传输的信号进行信道解码处理。
可选的，在其他实施场景中，可选用其他不仅具有数字上下变频和滤波处理功能，而且可对多核处理器104传输的信号进行信道解码处理的处理器。
射频收发器110上设有信号发送端113和信号接收端114。为支持第五代移动通信技术，射频收发器110的单通道带宽至少为80MHZ，因此，本实施方式选用ADI的支持基带实时处理能力为1200MHZ且单芯片支持双发双收的AD9371芯片作为射频收发器110。可选的，在其他实施方式中，选用单通道带宽大于80MHZ的信号收发装置作为射频收发器。
在上述实施例中，通信终端可以是基站或支持通用处理器架构的智能终端，现以基站为例，通过基站对5G信号的接收和发送对通信终端的功能进行说明。
在一个具体的实施场景中，通信终端为基站，基带板卡101上的多核处理器104为Intel i7 8核处理器，射频板卡102上的射频收发器110为AD9371，FPGA109为基于Xilinx的处理器ZYNQ。位于射频收发器110上的信号接收端114接收到模拟信号，射频收发器110将该模拟信号转为数字信号，并将其传输给FPGA109，FPGA109对接收的数字信号进行数字上下变频处理和滤波处理。并且FPGA109将处理后的信号通过PCIE接口111传送给数据总线103，多核处理器104通过PCIE接口108接收数据总线103传输的信号，多核处理器104根据5G协议栈对接收的信号进行处理。
可选的，在多核处理器104的使用率超过设定值时，多核处理器104可将5G协议栈中的信号解码部分下沉到FPGA109进行处理。具体的，在使用率超过设定值时，多核处理器104将通过射频收发器110接收的信号通过数据总线103传输给FPGA109，FPGA109上的信道解码单元112对该信号进行信道解码处理，并将处理后的信号通过数据总线203传输给多核处理器104。多核处理器104通过与射频板卡102上的FPGA109的二次交互实现了快速处理接收的信号的目的。
在另一个具体的实施场景中，通信终端为基站，多核处理器104为Intel i7 8核处理器、射频收发器110为AD9371，FPGA109为基于Xilinx的处理器ZYNQ。位于基带板卡101上的多核处理器104根据5G协议栈对信号进行处理后，通过PCIE接口108将处理后的信号传输给数据总线103，FPGA109通过PCIE接口111接收数据总线103传输的信号，FPGA109对信号不做处理将其直接传输给射频收发器110，射频收发器110将接收到的信号通过信号发送端113发送出去。
在上述实施场景中，多核处理器的使用率设定值可根据实际情况进行设定，如在多核处理器的使用率超过80%时，处理器的温度容易超过安全温度，会引起器件老化，散热不畅等问题，在这种情况下可将设定值定为80%。在其他情况下，可将设定值定为通信终端可以安全快速运行的范围。
在其他实施场景中，多核处理器也可以将5G协议栈中的其他部分下沉到射频板卡上的FPGA进行处理。
本发明的有益效果是：区别于现有技术的情况，本发明采用了基于通用处理器架构的通信终端，该通信终端的基带板卡上有多核处理器，且在多核处理器的使用率超过设定值时，将信道解码功能下沉到该通信终端的射频板卡上的FPGA进行处理。本发明通过将AMC板卡上的处理器物理层部分功能分解，并分配到其他模块协同处理，带来处理能力的提高和灵活性的提升，也提高使用者的体验度。
请参阅图2，图2是本发明实施例提供的通信终端的结构示意图。
本实施例提供了一种通信终端，包括：第一子基带板卡201、第二子基带板卡202和射频板卡204，第一子基带板卡201、第二子基带板卡202、射频板卡204均通过数据总线PCIE 203连接，在其他场景中，第一子基带板卡201、第二子基带板卡202、射频板卡204之间也可以无线连接的方式传输信息。
其中，第一子基带板卡201上设置有多核处理器205，该多核处理器205基于通用处理器架构，且可以处理实时基带信号以及运行移动通信中使用的大量数字信号处理算法。在本实施例中，该多核处理器205可以为8核处理器，如Intel i7 8核处理器，或更多核处理器，如16核，或32核等等，只要能实现运行移动通信技术中使用的大量数字信号处理算法，完成通信信号的实时处理均可，在此不做限定。
具体地，多核处理器205运行的数字信号协议栈为LTE或5G的协议栈。在一个可选的实施方式中，该多核处理器205包括PCIE接口209、CPU206、双倍速率同步动态随机存储器207以及总线208，且该处理器通过PCIE接口209连接数据总线203。双倍速率同步动态随机存储器207电连接PCIE接口209，通过该接口从数据总线203获取并存储信息，并且双倍速率同步动态随机存储器207电连接总线208。CPU206通过总线208获取双倍速率同步动态随机存储器207存储的信息并对其进行处理。
可选的，在其他实施例中，多核处理器104可以为其他基于通用处理器架构的处理器，只要能处理实时基带信号以及运行移动通信中使用的大量数字信号处理算法，且支持第五代甚至更高代移动通信技术的多核处理器即可，如i9、AMD Ryzen 7处理器等。
其中，第二基带板卡202上设有第二FPGA210，第二FPGA210包括PCIE接口211和信道解码单元212，且PCIE接口211和信道解码单元212之间电连接。PCIE接口211连接数据总线203，第二基带板卡202通过该接口获取多核处理器205传输的信息。信道解码单元212用于在多核处理器205的使用率超过设定值时对多核处理器205通过射频收发器220收到的信号进行解码处理。为分担多核处理器205的数字信号处理工作，本实施例选用基于Xilinx的处理器 ZYNQ，该处理器不仅具有数字上下变频和滤波处理功能，而且包括信道解码单元212，该单元可以对多核处理器205传输的信号进行信道解码处理。可选的，在其他实施场景中，可选用其他可对多核处理器205传输的信号进行信道解码处理的处理器。
其中，射频板卡204上设置有现场可编程门阵列FPGA213和射频收发器220。现场可编程门阵列FPGA213和射频收发器220之间电连接。其中，现场可编程门阵列FPGA213包括PCIE接口214和FFT模块216和IFFT模块215，PCIE接口214连接数据总线203，射频板卡204通过该接口从数据总线203获取或传输信息。FFT模块216用于在FPGA213接收到射频收发器220接收的信号后对其进行快速傅氏变换处理，IFFT模块215用于在FPGA213接收到多核处理器205通过数据总线203传输的信号后对其进行快速傅里叶逆变换处理。为分担多核处理器205的数字信号处理工作，本实施例选用基于Xilinx的处理器 ZYNQ，该处理器不仅具有数字上下变频和滤波处理功能，还包括FFT模块216和IFFT模块215，这两个模块可以对信号进行快速傅氏变换处理和快速傅氏逆变换处理。可选的，在其他实施场景中，可选用其他具有数字上下变频和滤波处理功能，且可以对信号进行快速傅氏变换处理和快速傅氏逆变换处理的处理器。射频收发器220上设有信号发送端218和信号接收端219。为支持第五代移动通信技术，射频收发器220的单通道带宽至少为80MHZ，因此，本实施方式选用ADI的支持基带实时处理能力为1200MHZ且单芯片支持双发双收的AD9371芯片作为射频收发器220。可选的，在其他实施方式中，选用单通道带宽大于80MHZ的信号收发装置作为射频收发器。
在上述实施例中，通信终端可以是基站或支持通用处理器架构的智能终端，现以基站为例，通过基站对5G信号的接收和发送对通信终端的功能进行说明。
在一个具体的场景中，通信终端为基站，第一子基板201上的多核处理器205为Intel i7 8核处理器、射频板卡203上的射频收发器220为AD9371，分别位于第二子基带板卡202和射频板卡203上第二FPGA210和FPGA213均为基于Xilinx的处理器ZYNQ。位于射频收发器220上的信号接收端219接收到模拟信号，射频收发器220将该模拟信号转为数字信号，并将其传输给FPGA213，FPGA213对接收的数字信号进行数字上下变频处理和滤波处理。FPGA213将处理后的信号通过PCIE接口214传送给数据总线103，多核处理器205通过PCIE接口209接收数据总线203传输的信号，多核处理器205根据5G协议栈对接收的信号进行处理。
可选的，在多核处理器205的使用率超过设定值时，多核处理器104可将5G协议栈中的信号解码部分下沉到第二子基板202上的第二FPGA210进行处理，并且将5G协议栈中的快速傅里叶变换部分下沉到FPGA213中的FFT模块216进行处理。具体地，在使用率超过设定值时，射频收发器220通过信号接收端219接收到模拟信号，并将模拟信号转为数字信号，然后将数字信号其传输给FPGA213，FPGA213对接收的数字信号进行数字上下变频处理和滤波处理，且FPGA213中的FFT模块216对接收的信号进行快速傅里叶变换处理，FPGA213将处理后的信号通过PCIE接口214传送给数据总线203，多核处理器205通过PCIE接口209接收数据总线203传输的信号。同时，多核处理器205将通过射频收发器220接收的信号通过数据总线203传输给第二FPGA210，第二FPGA210对该信号进行信道解码处理，并将处理后的信号通过数据总线203传输给多核处理器205。多核处理器205通过射频板卡204上的FPGA213和与第二子基板202上的第二FPGA210的二次交互实现了快速处理接收的信号的目的。
在另一个具体的场景中，通信终端为基站，第一子基带板卡201上的多核处理器205为Intel i7 8核处理器、射频收发器220为AD9371，分别位于第二子基带板卡202和射频板卡203上第二FPGA210和FPGA213均为基于Xilinx的处理器ZYNQ。位于第一子基带板卡201上的多核处理器205根据5G协议栈对信号进行处理后，通过PCIE接口209将处理后的信号传输给数据总线203，FPGA213通过PCIE接口214接收数据总线203传输的信号，FPGA213对信号不做处理将其直接传输给射频收发器220，射频收发器220将接收到的信号通过信号发送端218发送出去。可选的，在多核处理器205的使用率超过设定值时，多核处理器205将5G协议栈中的对信号进行快速傅里叶逆变换处理的工作分配给射频板卡204上的FPGA213。具体地，在使用率超过设定值时，多核处理器104将需要处理的信号通过数据总线103传输给FPGA213，FPGA213上的IFF模块215对该信号进行快速傅里叶逆变换处理，并将处理后的信号传输给射频收发器220。射频收发器220将接收到的信号转换为模拟信号，并通过信号发送端218发送出去。
在上述实施场景中，多核处理器的使用率设定值可根据实际情况进行设定，如在多核处理器的使用率超过80%时，处理器的温度容易超过安全温度，会引起器件老化，散热不畅等问题，在这种情况下可将设定值定为80%，在其他情况下可将设定值定为通信终端可以安全快速运行的范围。
在其他实施场景中，多核处理器除了将5G协议栈中的对信号进行快速傅里叶逆变换处理部分下沉到射频板卡上的FPGA进行处理，也可以将5G协议栈中的其他部分下沉到射频板卡和第二子基带板卡上的FPGA进行处理，5G协议栈各部分下沉可根据多核处理器的使用率或处理能力需要进行分配。
本发明的有益效果是：区别于现有技术的情况，本发明采用了基于通用处理器架构的通信终端，该通信终端的基带板卡上有多核处理器，且在多核处理器的使用率超过设定值时，将信道解码功能下沉到该通信终端的射频板卡上的FPGA进行处理。本发明通过将AMC板卡上的处理器物理层部分功能分解，并分配到其他模块协同处理，带来处理能力的提高和灵活性的提升，也提高使用者的体验度。
基于同一发明构思，本发明还提供了一种通信终端的通信方法，请参阅图3，图3是本发明实施例提供的通信终端的通信方法的流程示意图。本实施方式的通信终端的通信方法包括如下步骤：
S301：所述通信终端通过所述射频收发器接收信号。
在一个具体的实施场景中，通信终端为基站，基带板卡上的多核处理器为Intel i7 8核处理器，射频板卡上的射频收发器为AD9371，FPGA为基于Xilinx的处理器ZYNQ。位于射频收发器上的信号接收端接收到模拟信号，射频收发器将该模拟信号转为数字信号，并将其传输给FPGA，FPGA对接收到的数字信号进行数字上下变频处理和滤波处理。并且FPGA将处理后的信号通过PCIE接口传送给数据总线，多核处理器通过PCIE接口接收数据总线传输的信号，多核处理器根据5G协议栈对接收的信号进行处理。
在另一个具体的场景中，通信终端为基站，第一子基板上的多核处理器为Intel i7 8核处理器，射频板卡上的射频收发器为AD9371，分别位于第二子基带板卡和射频板卡上第二FPGA和FPGA均为基于Xilinx的处理器ZYNQ。位于射频收发器上的信号接收端接收到模拟信号，射频收发器将该模拟信号转为数字信号，并将其传输给FPGA，FPGA对接收的数字信号进行数字上下变频处理和滤波处理。FPGA将处理后的信号通过PCIE接口传送给数据总线，多核处理器通过PCIE接口接收数据总线传输的信号，多核处理器根据5G协议栈对接收的信号进行处理。
S302：判断所述通信终端的多核处理器当前的使用率是否超过设定值。
多核处理器在对信号进行处理时，会实时检测其使用率，并判断是否超过设定值。
在上述实施场景中，多核处理器的使用率设定值可根据实际情况进行设定，如在多核处理器的使用率超过80%时，处理器的温度容易超过安全温度，会引起器件老化，散热不畅等问题，在这种情况下可将设定值定为80%。在其他情况下，可将设定值定为通信终端可以安全快速运行的范围。
S303：如果所述多核处理器当前的使用率超过所述设定值，通过所述现场可编程门阵列FPGA对所述信号进行处理。
在一个具体的实施场景中，多核处理器确定其使用率超过设定值时，将5G协议栈中的信号解码部分下沉到FPGA进行处理。具体的，多核处理器将通过射频收发器接收的信号通过数据总线传输给FPGA，FPGA上的信道解码单元对该信号进行信道解码处理，并将处理后的信号通过数据总线传输给多核处理器。多核处理器通过与射频板卡上的FPGA的二次交互实现了快速处理接收的信号的目的。
在另一个具体的实施场景中，多核处理器确定其使用率超过设定值时，多核处理器可将5G协议栈中的信号解码部分下沉到第二子基板上的第二FPGA进行处理，并且将5G协议栈中的快速傅里叶变换部分下沉到FPGA中的FFT模块进行处理。具体地，射频收发器上通过信号接收端接收到模拟信号，并将模拟信号转为数字信号，然后将数字信号其传输给射频板卡上的FPGA，FPGA对接收的数字信号进行数字上下变频处理和滤波处理，且FPGA中的FFT模块对接收的信号进行快速傅里叶变换处理，FPGA将处理后的信号通过PCIE接口传送给数据总线，多核处理器通过PCIE接口接收数据总线传输的信号。同时，多核处理器将通过射频收发器接收的信号通过数据总线传输给第二FPGA，第二FPGA对该信号进行信道解码处理，并将处理后的信号通过数据总线传输给多核处理器。多核处理器通过射频板卡204上的FPGA对信号进行快速傅里叶变换以及与第二子基板上的第二FPGA的二次交互实现了快速处理接收的信号的目的。
在其他实施场景中，多核处理器除了将5G协议栈中的对信号进行快速傅里叶逆变换处理部分下沉到射频板卡上的FPGA进行处理，也可以将5G协议栈中的其他部分下沉到射频板卡和第二子基带板卡上的FPGA进行处理，5G协议栈各部分下沉可根据多核处理器的使用率或处理能力需要进行分配。
本发明的有益效果是：区别于现有技术的情况，本发明采用了基于通用处理器架构的通信终端，该通信终端的基带板卡上有多核处理器，且在多核处理器的使用率超过设定值时，将信道解码功能下沉到该通信终端的射频板卡上的FPGA进行处理。本发明通过将AMC板卡上的处理器物理层部分功能分解，并分配到其他模块协同处理，带来处理能力的提高和灵活性的提升，也提高使用者的体验度。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种通信终端，其中，所述通信终端基于通用处理器，包括相互连接的基带板卡以及射频板卡，基带板卡包括多核处理器，射频板卡包括相互连接的射频收发器和现场可编程门阵列FPGA，其中，所述射频收发器用于信号的发送和接收；所述FPGA包括信道解码单元，所述信道解码单元用于在所述多核处理器的使用率超过设定值时对所述射频收发器接收到的信号进行信道解码处理。
  2. 根据权利要求1所述的通信终端，其中，所述射频收发器单通道频带带宽至少为80MHZ。
  3. 根据权利要求1所述通信终端，其中，所述射频收发器为AD9371。
  4. 根据权利要求1所述通信终端，其中，所述多核处理器为8核处理器。
  5. 根据权利要求1所述的通信终端，其中，所述基带板卡包括第一子基带板卡和第二子基带板卡，所述第一子基带板卡和第二子基带板卡通过所述数据总线连接；所述第一子基带板卡包括所述多核处理器，所述第二子基带板卡包括第二FPGA，
    所述第二FPGA包括信道解码单元，所述信道解码单元用于在所述多核处理器的使用率超过设定值时对所述射频收发器接收到的信号进行信道解码处理；
    所述射频板卡上的FPGA用于在所述多核处理器的使用率超过设定值时对所述所述射频收发器接收到的信号进行处理。
  6. 根据权利要求5所述的通信终端，其中，所述射频板卡上的FPGA具体用于在所述多核处理器的使用率超过设定值时对所述接收的信号进行快速傅里叶变换或快速傅里叶逆变换处理。
  7. 根据权利要求1所述的通信终端，其中，所述基带板卡和所述射频板卡通过数据总线连接。
  8. 根据权利要求1所述的通信终端，其中，所述多核处理器运行的数字信号协议栈为LTE或5G的协议栈。
  9. 根据权利要求1所述的通信终端，其中，所述基带板卡和射频板卡通过无线连接。
  10. 根据权利要求1所述的通信终端，其中，所述多核处理器包括PCIE接口、CPU、双倍速率同步动态随机存储器以及总线，双倍速率同步动态随机存储器电连接PCIE接口，通过PCIE接口从数据总线获取并存储信息，并且双倍速率同步动态随机存储器电连接总线；CPU通过总线获取双倍速率同步动态随机存储器存储的信息并对其进行处理。
  11. 根据权利要求1所述的通信终端，其中，所述射频收发器上设有信号发送端和信号接收端。
  12. 一种通信终端的通信方法，其中，所述通信终端基于通用处理器，所述通信终端包括相互连接的基带板卡以及射频板卡，基带板卡包括多核处理器，射频板卡包括相互连接的射频收发器和现场可编程门阵列FPGA，通信方法包括：
    所述通信终端通过所述射频收发器接收信号；
    判断所述通信终端的多核处理器当前的使用率是否超过设定值；
    如果所述多核处理器当前的使用率超过所述设定值，通过所述现场可编程门阵列FPGA对所述信号进行处理。
  13. 根据权利要求12所述的通信方法，其中，所述基带板卡包括第一子基带板卡和第二子基带板卡，所述第一子基带板卡和第二子基带板卡通过所述数据总线连接；所述第一子基带板卡包括所述多核处理器，所述第二子基带板卡包括第二FPGA；所述如果所述多核处理器当前的使用率超过所述设定值，通过所述射频板卡的现场可编程门阵列FPGA对所述信号进行处理的步骤具体包括：
    如果所述多核处理器当前的使用率超过所述设定值，通过所述第二FPGA对所述信号进行信道解码处理；通过所述射频板卡的现场可编程门阵列FPGA的FFT模块对所述信号进行快速傅里叶变换处理或快速傅里叶逆变换处理。
  14. 根据权利要求12所述的通信方法，其中，所述射频收发器单通道频带带宽至少为80MHZ。
  15. 根据权利要求12所述的通信方法，其中，所述射频收发器为AD9371。
  16. 根据权利要求12所述的通信方法，其中，所述多核处理器为8核处理器。
  17. 根据权利要求12所述的通信方法，其中，所述基带板卡和所述射频板卡通过数据总线连接。
  18. 根据权利要求12所述的通信方法，其中，所述多核处理器运行的数字信号协议栈为LTE或5G的协议栈。
  19. 一种存储介质，其存储有多条指令，所述指令适于由处理器加载并执行如下步骤：
    所述通信终端通过所述射频收发器接收信号；其中，所述通信终端基于通用处理器，所述通信终端包括相互连接的基带板卡以及射频板卡，基带板卡包括多核处理器，射频板卡包括相互连接的射频收发器和现场可编程门阵列FPGA；
    判断所述通信终端的多核处理器当前的使用率是否超过设定值；
    如果所述多核处理器当前的使用率超过所述设定值，通过所述现场可编程门阵列FPGA对所述信号进行处理。
  20. 根据权利要求19所述的存储介质，其中，所述基带板卡包括第一子基带板卡和第二子基带板卡，所述第一子基带板卡和第二子基带板卡通过所述数据总线连接；所述第一子基带板卡包括所述多核处理器，所述第二子基带板卡包括第二FPGA；所述如果所述多核处理器当前的使用率超过所述设定值，通过所述射频板卡的现场可编程门阵列FPGA对所述信号进行处理的步骤具体包括：
    如果所述多核处理器当前的使用率超过所述设定值，通过所述第二FPGA对所述信号进行信道解码处理；通过所述射频板卡的现场可编程门阵列FPGA的FFT模块对所述信号进行快速傅里叶变换处理或快速傅里叶逆变换处理。
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