WO2019080852A1 - 一种数据处理方法、数据处理电路和网络设备 - Google Patents

一种数据处理方法、数据处理电路和网络设备

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Publication number
WO2019080852A1
WO2019080852A1 PCT/CN2018/111557 CN2018111557W WO2019080852A1 WO 2019080852 A1 WO2019080852 A1 WO 2019080852A1 CN 2018111557 W CN2018111557 W CN 2018111557W WO 2019080852 A1 WO2019080852 A1 WO 2019080852A1
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Prior art keywords
channel
operand
data
command
operation code
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PCT/CN2018/111557
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English (en)
French (fr)
Inventor
李忠星
何贵洲
朱小婷
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华为技术有限公司
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Publication of WO2019080852A1 publication Critical patent/WO2019080852A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

Definitions

  • the present application relates to the field of communications, and in particular, to a data processing method, a data processing circuit, and a network device.
  • Atomic operations are an independent and inseparable operation.
  • An existing processor may be a single core processor with a single processor core or a multi-core processor with multiple cores.
  • a single machine instruction can be thought of as an atomic operation.
  • multiple instruction streams are parallel. When one core executes an instruction, the instructions executed by other cores may operate the same storage unit, resulting in data competition.
  • the lock mechanism is often used to solve data race problems.
  • the operation method of multi-checking the same storage space is as follows: Assume that the multi-core device includes four cores, namely core1, core2, core3, and core4.
  • core1 processes the data of the storage space A, it first queries the lock state of the storage space A. If the lock is idle, the lock of the storage space A is preempted, the data is read from the storage space A, and the lock is released after the reading is completed.
  • Other processing cores (such as core2, core3, or core4), if they want to access storage space A, need to wait for core1 to release the lock before competing for the lock. If not idle, the loop locks the lock state until the lock is idle, so that the lock can be preempted and subsequent operations are performed.
  • the present application provides a data processing method, a data processing circuit, and a network device, which can solve the data competition problem by using a queuing mechanism and an atomic operation, thereby improving data processing performance of the multi-core network device.
  • the first aspect provides a data processing method, including: receiving an instruction sent by a processor core, acquiring an operation code according to the instruction; storing the operation code in a command channel, storing the operand included in the instruction into the data channel; and reading from the command channel
  • the opcode reads the operand from the data channel; performs atomic operations based on the opcode and operands, and sets the state of the state machine to an uninterruptible state during atomic operations.
  • the data processing circuit can store instructions issued by multiple cores in the command channel and the data channel, and then execute in the order of the instructions, and implement atomic operations in hardware instead of the lock mechanism, thereby solving the simultaneous execution of multiple instructions.
  • the formed data competition avoids the waste of data processing capability caused by other core loops.
  • the acquiring the operation code according to the instruction is specifically: determining, according to the correspondence between the preset address and the address segment, the target address segment corresponding to the target address; The correspondence between the address segment and the operation code and the target address segment obtain the operation code.
  • command channels and data channels can be selected for opcodes and operands for storage. In this way, a large number of instructions are executed through the multi-channel and queuing mechanism, which can avoid the waste of data processing capability caused by other core loops when a core occupies storage space.
  • determining the command channel corresponding to the operation code is: determining the target address segment corresponding to the target address according to the correspondence between the preset address and the address segment;
  • the command channel corresponding to the target address segment is determined as the command channel corresponding to the operation code according to the preset relationship between the address segment and the command channel;
  • the data channel corresponding to the determined operand is specifically: according to the preset address segment and the data channel Relationship: Determine the data channel corresponding to the target address segment as the data channel corresponding to the operand.
  • the operation code can be stored in the corresponding command channel according to the address segment to which the address belongs, and the operand is stored in the corresponding data channel. This provides a way to store opcodes and operands into the channel.
  • determining the command channel corresponding to the operation code is specifically: determining, according to a preset correspondence between the data block size and the channel number, a channel number corresponding to the operand; determining, according to the channel number, an operation code corresponding to the channel number
  • the command channel; determining the data channel corresponding to the operand is specifically: determining the data channel corresponding to the operand according to the channel number.
  • the data processing circuit can store the operation code into the corresponding command channel according to the data block size, and store the operand into the corresponding data channel. This provides another way to store and the implementation of the solution is more flexible.
  • determining the command channel corresponding to the operation code is specifically: hashing the target address to obtain a hash value, and using the hash value and the channel of the command channel
  • the number is modulo operation to obtain the channel number, and the command channel corresponding to the operation code is determined according to the channel number;
  • the data channel corresponding to the determined operand is specifically: the data channel corresponding to the operand is determined according to the channel number.
  • a second aspect provides a data processing circuit comprising: a communication interface, a controller, a command channel, a data channel, a memory, and a state machine, wherein the controller is respectively connected to the communication interface, the command channel, the data channel, the memory, and the state machine through the circuit;
  • the controller acquires the operation code according to the instruction; stores the operation code in the command channel, and stores the operand included in the instruction into the data channel; then, the operation code is read from the command channel, and the data is read from the command channel.
  • the channel reads operands; performs atomic operations in memory based on opcodes and operands, and sets the state of the state machine to an uninterruptible state during atomic operations.
  • the command channel is used to store the opcode; the data channel is used to store the operand.
  • a controller is a combinational logic controller, also known as a hard-wired controller.
  • the controller when the instruction includes the target address, is specifically configured to determine, according to the preset correspondence between the address and the address segment, the target address segment corresponding to the target address; according to the preset address segment The operation code is obtained by the correspondence with the command channel and the target address segment.
  • the controller is further configured to determine a command channel corresponding to the operation code, and determine the operand corresponding to the Data channel.
  • the controller is specifically configured to determine, according to the correspondence between the preset address and the address segment, the target address segment corresponding to the target address; according to the preset address
  • the corresponding relationship between the segment and the command channel determines that the command channel corresponding to the target address segment is the command channel corresponding to the operation code.
  • the data channel corresponding to the target address segment is determined to be the operand corresponding to the operand. Data channel.
  • the controller is specifically configured to determine, according to a preset correspondence between the data block size and the channel number, a channel number corresponding to the operand; and determine, according to the channel number, a command channel corresponding to the operation code; The channel number determines the data channel corresponding to the operand.
  • the controller when the instruction includes the target address, is specifically configured to perform a hash operation on the target address to obtain a hash value, and perform a modulo operation on the hash value and the channel number of the command channel.
  • the channel number is obtained, and the command channel corresponding to the operation code is determined according to the channel number; the data channel corresponding to the operand is determined according to the channel number.
  • a third aspect provides a chip system including a plurality of processor cores for supporting a network device to implement the functions involved in the above aspects.
  • the chip system further includes a memory for storing necessary program instructions and data of the network device.
  • the chip system can be composed of chips, and can also include chips and other discrete devices.
  • the instruction sent by the processor core receives the operation code according to the instruction; the operation code is stored in the command channel, and the operand included in the instruction is stored in the data channel; the operation code is read from the command channel, The data channel reads the operand; performs atomic operations based on the opcode and operands, and sets the state of the state machine to an uninterruptible state during atomic operations.
  • the instructions issued by each core are stored in the channel, and then the instruction execution is sequentially read, so that the overhead of multiple core loops to query the lock state can be avoided, and other operations can be performed during this period.
  • the data processing circuit can maintain the atomic operation state by controlling the state of the state machine, and implement atomic operations through hardware, so that multiple instructions can be executed separately, thereby solving data competition generated when multiple instructions are parallel.
  • FIG. 1 is a schematic diagram of a data processing circuit in an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a data processing method in an embodiment of the present application.
  • FIG. 3 is another schematic diagram of a data processing method in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a network device in an embodiment of the present application.
  • an embodiment of the data processing circuit 100 provided by the present application includes:
  • the communication interface 101, the controller 102, the command channel 103, the data channel 104, the memory 105, and the state machine 106 are respectively connected to the communication interface 101, the command channel 103, the data channel 104, the memory 105, and the state machine 106 through a circuit;
  • a communication interface 101 configured to receive an instruction sent by a processor core, where the instruction includes an operand
  • the controller 102 is configured to obtain an operation code according to the instruction, determine a command channel corresponding to the operation code, and determine a data channel corresponding to the operand; store the operation code in the command channel, and store the operand in the data channel;
  • a command channel 103 for storing an operation code
  • a data channel 104 for storing operands
  • Controller 102 is also operative to read an opcode from command channel 103, read an operand from data channel 104, perform an atomic operation in memory 105 based on the opcode and operand, and state the state machine 106 during atomic operations. Set to uninterruptible state.
  • the controller refers to a combination logic controller, also known as a hard wiring controller.
  • the controller 102 can convert the instruction sent by the processor core into an actually executed operation instruction, the operation instruction includes an operation code and an operand, and the operation code indicates an operation type corresponding to the operation instruction.
  • the operand represents the source of the data needed to perform the operation.
  • the operand can be an immediate or an address.
  • Both the command channel and the data channel are hardware-implemented First Input First Output (FIFO) channels.
  • First in, first out refers to accessing the opcode of the command channel in sequence, and accessing the operand of the data channel.
  • the number of command channels and data channels is the same and corresponds.
  • the operation code is add, and the operand is 2, the operation code add enters the command channel 1, and the operand 2 enters the data channel 1.
  • the opcode and the operand are respectively enqueued and dequeued according to the order of the instructions.
  • the operation code enqueue and the operand enqueue of one operation instruction are synchronized, and the operation code dequeue and the operand dequeue of one operation instruction are also synchronized, so that It is possible to guarantee the integrity of an operation instruction.
  • an embodiment of a data processing method provided by the present application includes:
  • Step 201 Receive an instruction sent by a processor core.
  • Step 202 Acquire an operation code according to the instruction.
  • Step 203 Store the operation code into the command channel.
  • Step 204 Store the operands into the data channel.
  • the instructions may include an opcode and an operand, or the instructions include a target address and an operand.
  • the instruction includes the operation code and the operand
  • the operation code of the instruction is directly obtained, and the operation code included in the instruction is directly stored in the command channel, and the operand is directly stored in the data channel.
  • the opcode can be obtained from the target address. Then steps 203 and 204 are performed.
  • Step 205 Read an operation code from the command channel.
  • Step 206 Read an operand from the data channel.
  • the accesses of the operation code and the operand are synchronous, that is, the operation code and the operand corresponding to one instruction are simultaneously stored, and the operation code and the operand corresponding to one instruction are simultaneously read.
  • Step 207 Perform an atomic operation in the memory according to the opcode and the operand, and set the state of the state machine to an uninterruptible state during the atomic operation.
  • the operation code may include various types such as an addition operation, a subtraction operation, and a storage operation.
  • Corresponding atomic operations also include multiple types, such as atomic addition operations, atomic subtraction operations, and atomic storage operations.
  • the state of the state machine is set to an uninterruptible state. This ensures that an atomic operation is not interrupted, so that different instructions are executed independently.
  • the state machine When the atomic operation is over, the state machine is set to the idle state. In this way, the controller can read the next opcode from the command channel, read the next operand from the data channel, and then perform the next atomic operation based on the read opcode and operand.
  • the instruction is executed in the order of the instruction, thereby avoiding waste of data processing capability caused by multi-core loop stealing.
  • the command channel is used to store the opcode
  • the data channel is used to store the operands
  • the atomic operations are implemented by hardware, so that different instructions can be executed separately and independently, thereby solving the data competition generated when the multi-core is issued.
  • atomic operations in hardware can speed up instruction execution.
  • the instructions include a target address
  • Step 202 is specifically: determining a target address segment corresponding to the target address according to the correspondence between the preset address and the address segment; and acquiring the operation code according to the correspondence between the preset address segment and the operation code and the target address segment.
  • the controller stores a correspondence between the address segment and the operation code.
  • the controller determines that it belongs to the first address segment, and according to the correspondence between the address segment and the operation code, the corresponding operation code can be determined as an addition operation.
  • the add operation is then stored in the command channel and the operand is stored in the data channel. It can be understood that the correspondence between the address segment and the operation code is not limited to the above examples.
  • FIG. 3 another embodiment of the data processing method provided by the present application includes:
  • Step 301 Receive an instruction sent by a processor core.
  • Step 302 Acquire an operation code according to the instruction.
  • Step 303 Determine a command channel corresponding to the operation code.
  • Step 304 Determine a data channel corresponding to the operand.
  • Step 305 Store the operation code into the command channel.
  • Step 306 Store the operand into the data channel.
  • Step 307 Read an operation code from the command channel.
  • Step 308 Read an operand from the data channel.
  • the operation code and the operand are synchronously accessed, that is, the operation code and the operand corresponding to one instruction are simultaneously stored, and the operation code and the operand corresponding to one instruction are simultaneously read.
  • Step 309 Perform an atomic operation in the memory according to the opcode and the operand, and set the state of the state machine to an uninterruptible state during the atomic operation.
  • the steps 301 to 302 are similar to the steps 201 to 202 in the embodiment shown in FIG. 2, and the steps 305 to 309 are similar to the steps 203 to 207 in the embodiment shown in FIG. 2.
  • the data processing circuit includes a plurality of command channels and a plurality of data channels.
  • the instructions include a target address
  • Step 303 is specifically: determining a target address segment corresponding to the target address according to the correspondence between the preset address and the address segment; determining the command channel corresponding to the target address segment as the operation code according to the correspondence between the preset address segment and the command channel Corresponding command channel;
  • Step 304 is specifically: determining, according to the correspondence between the preset address segment and the data channel, the data channel corresponding to the target address segment as the data channel corresponding to the operand.
  • the controller stores a correspondence between the address segment and the command channel and the data channel.
  • the correspondence between the address segment and the command channel, and the address segment and the data channel can be as shown in Table 2:
  • the controller determines that it belongs to the first address segment, and further determines that the command channel corresponding to the operation code is command channel 1, and the data channel corresponding to the operand is data channel 1. It can be understood that the correspondence between the address segment and the command channel, or the correspondence between the address segment and the data channel is not limited to the above example.
  • Step 303 is specifically: determining, according to a preset correspondence between the data block size and the channel number, a channel number corresponding to the operand; and determining, according to the channel number, a command channel corresponding to the operation code;
  • Step 304 is specifically: determining a data channel corresponding to the operand according to the channel number.
  • the controller stores a correspondence between a data block size and a command channel and a data channel.
  • the data block size and command channel can be as shown in Table 3:
  • Block size Command channel Data channel 16 Command channel 1 Data channel 1 32 Command channel 2 Data channel 2 64 Command channel 3 Data channel 3
  • the controller determines that the corresponding command channel is the command channel 2, and the corresponding data channel is the data channel 2.
  • the interleave mode can be used to store the opcode and the operand into the corresponding channel.
  • the correspondence between the data block size and the command channel, or the correspondence between the data block size and the data channel is not limited to the above example.
  • the instructions include a target address
  • Step 303 is specifically: performing a hash operation on the target address to obtain a hash value, performing a modulo operation on the hash value and the channel number of the command channel to obtain a channel number, and determining a command channel corresponding to the operation code according to the channel number;
  • Step 304 is specifically: determining a data channel corresponding to the operand according to the channel number.
  • the number of channels of the command channel is the same as the number of channels of the data channel.
  • the algorithm used for the hash operation may be CRC32, or a Message Digest Algorithm such as MD2, MD4, MD5, or a Secure Hash Algorithm such as SHA1.
  • the command channel includes command channel 1, command channel 2, ..., command channel 8, and the data channel includes data channel 1, data channel 2, ..., data channel 8. It is assumed that the target address is hashed, and the channel number obtained by performing the modulo operation with 8 is 3, then the command channel corresponding to the operation code is determined as command channel 3, and the data channel corresponding to the operand is data channel 3.
  • the 8 cores included in the network device are core1, core2, ..., core8. Assume that core1 and core2 issue instruction 1 and instruction 2, and the statistics corresponding to instruction 1 and instruction 2 are the number of messages; in instruction 1, the address is 0x2FD80100, and the immediate value is 1. In instruction 2, the address is 0x2FD80100 and the immediate value is 2.
  • the correspondence between the preset address segment and the operation code is as shown in Table 1.
  • the correspondence between the address segment and the channel is as shown in Table 2.
  • the data processing circuit determines that the address belongs to the first address segment, and the corresponding operation code is addition. Operation, the corresponding command channel is command channel 1, and its corresponding data channel is data channel 1.
  • the controller first stores "add” corresponding to instruction 1 into command channel 1, and stores “1" corresponding to instruction 1 into data channel 1. Then, the "add” corresponding to the instruction 2 is stored in the command channel 1, and the “2" corresponding to the instruction 2 is stored in the data channel 1. Then, according to the "add” and “1” corresponding to the instruction 1, the atomic operation is performed, and the number of the first message obtained by the execution of the instruction 1 is 1. During this time, the state of the state machine is set to an uninterruptible state. When the execution of the instruction 1 is completed, the state of the state machine period is set to the idle state.
  • the "add" corresponding to the instruction 2 is read from the command channel 1
  • the "2" corresponding to the instruction 2 is read from the data channel 1
  • the number of the second packets obtained by performing the atomic operation is 3, that is, the number of the second packets is equal to
  • the number of first messages is +2.
  • the state of the state machine is set to an uninterruptible state.
  • the addition operation is performed on the number of packets obtained by the execution of the previous instruction.
  • core2 can perform other operations without looping the lock, thereby improving the data processing capability of the network device.
  • the command channel is used to store the opcode
  • the data channel is used to store the operand
  • the atomic operation is implemented by hardware. This enables the instruction 1 and the instruction 2 to be executed independently, thereby solving the data competition problem when the multi-instruction is parallel in the multi-core system.
  • an embodiment of the network device 400 provided by the present application includes:
  • the multi-core processor 401 includes a plurality of processor cores 4011.
  • Data processing circuit 402 is the data processing circuit of the embodiment or alternative embodiment shown in FIG.
  • the data processing circuit 402 can execute the data processing method provided by the above embodiments.
  • the network device of the present application may be a user equipment, an access network device, or a core network device.
  • User equipment refers to mobile phones, tablets, personal digital assistants, car computers, wearable devices, and the like.
  • An access network device refers to a base station, an evolved base station, an access point, and the like.
  • the core network device refers to a Mobile Switching Center (MSC), a router, or a switch.
  • MSC Mobile Switching Center

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Abstract

一种数据处理方法，包括：接收处理器核心发送的指令，指令包括操作数；根据指令获取操作码；将操作码存入命令通道，将操作数存入数据通道；从命令通道读取操作码，从数据通道读取操作数；根据操作码和操作数在存储器中执行原子操作，以及在原子操作期间将状态机的状态设为不可打断状态。本申请能够利用排队机制和原子操作解决数据竞争问题，提高网络设备的数据处理性能。本申请还提供一种能够实现上述方法的数据处理电路和网络设备。

Description

一种数据处理方法、数据处理电路和网络设备
本申请要求于2017年10月24日提交中国专利局、申请号为201711001602.9、发明名称为“一种数据处理方法、数据处理电路和网络设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种数据处理方法、数据处理电路和网络设备。
背景技术
原子操作是指一个独立不可分割的操作。现有处理器可以是具有单个处理器核心(core)的单核处理器，或具有多个core的多核处理器。在单核系统中，单个机器指令可以看成是原子操作。在多核设备中多指令流是并行的，一个核在执行一个指令时，其他核同时执行的指令有可能操作同一存储单元，从而出现数据竞争现象。
在多核设备中，通常使用锁机制来解决数据竞争问题。多核对同一个存储空间的操作方法大致如下：假设多核设备包括4个core，分别为core1、core2、core3和core4。core1处理存储空间A的数据时，首先查询存储空间A的锁状态，若锁空闲，则抢占存储空间A的锁，从存储空间A读取数据，读取完成后释放锁。而其他处理核心(如core2、core3或core4)在此期间如果要访问存储空间A，需要等待core1释放锁后才能竞争锁。若不空闲，则循环查询锁状态，直至锁空闲，才能抢占锁，执行后续操作。
当锁被一个core占用时，其他core循环判断锁状态，而不能执行其他操作，以至于core的数据处理能力没有得到合理利用，导致多核设备的数据处理效率很低。
发明内容
有鉴于此，本申请提供一种数据处理方法、数据处理电路和网络设备，能够利用排队机制和原子操作解决数据竞争问题，从而提高多核网络设备的数据处理性能。
第一方面提供一种数据处理方法，包括：接收处理器核心发送的指令，根据指令获取操作码；将操作码存入命令通道，将指令包括的操作数存入数据通道；从命令通道读取操作码，从数据通道读取操作数；根据操作码和操作数执行原子操作，以及在原子操作期间将状态机的状态设为不可打断状态。
依此实施，数据处理电路能够将多个core下发的指令，存储在命令通道和数据通道中，然后按照指令顺序执行，以及通过硬件实现原子操作代替锁机制，从而解决多个指令同时执行时形成的数据竞争，避免了其他core循环抢锁造成的数据处理能力的浪费。
在一种可能的实现方式中，在指令包括目标地址的情况下，根据指令获取操作码具体为：根据预设的地址与地址段的对应关系，确定目标地址对应的目标地址段；根据预设的地址段与操作码的对应关系和目标地址段，获取操作码。依此实施，只需要向数据处理电路提供地址，就能快速确定地址对应的操作码。这样无需在程序的指令中写入操作码，能够统一操作接口，可以避免因错误操作码导致的程序故障，提高了程序的可靠性。
在另一种可能的实现方式中，在命令通道的数量为多个，数据通道的数量为多个的情况下，在将操作码存入命令通道，将操作数存入数据通道之前，确定操作码对应的命令通道，以及，确定操作数对应的数据通道。依此实施，在多个命令通道和数据通道的情况下，可以为操作码和操作数选择命令通道和数据通道进行存储。这样通过多通道和排队机制执行大量指令，可以避免一个core占用存储空间时，其他core循环判断造成的数据处理能力的浪费。
在另一种可能的实现方式中，在指令包括目标地址的情况下，确定操作码对应的命令通道具体为：根据预设的地址与地址段的对应关系，确定目标地址对应的目标地址段；根据预设的地址段与命令通道的对应关系，确定目标地址段对应的命令通道为操作码对应的命令通道；确定操作数对应的数据通道具体为：根据预设的地址段与数据通道的对应关系，确定目标地址段对应的数据通道为操作数对应的数据通道。依此实施，数据处理电路获取指令包括的地址后，可以根据地址所属的地址段将操作码存入相应的命令通道，以及将操作数存入相应的数据通道。这样提供了一种将操作码和操作数存入通道的方法。
在另一种可能的实现方式中，确定操作码对应的命令通道具体为：根据预设的数据块大小与通道号的对应关系，确定操作数对应的通道号；根据通道号，确定操作码对应的命令通道；确定操作数对应的数据通道具体为：根据通道号，确定操作数对应的数据通道。依此实施，数据处理电路能根据数据块大小，将操作码存入相应的命令通道，以及将操作数存入相应的数据通道。这样能够提供了另外一种存储方式，方案实施更具灵活性。
在另一种可能的实现方式中，在指令包括目标地址的情况下，确定操作码对应的命令通道具体为：将目标地址进行哈希运算得到哈希值，将哈希值与命令通道的通道数进行取模运算得到通道号，根据通道号确定操作码对应的命令通道；确定操作数对应的数据通道具体为：根据通道号确定操作数对应的数据通道。这样提供了另外一种存储方式，方案实施更具灵活性。
第二方面提供一种数据处理电路，包括：通信接口、控制器、命令通道、数据通道、存储器和状态机，控制器分别通过电路与通信接口、命令通道、数据通道、存储器和状态机相连；通信接口接收处理器核心发送的指令后，控制器根据指令获取操作码；将操作码存入命令通道，将指令包括的操作数存入数据通道；然后，从命令通道读取操作码，从数据通道读取操作数；根据操作码和操作数在存储器中执行原子操作，以及在原子操作期间将状态机的状态设为不可打断状态。其中，命令通道用于存储操作码；数据通道用于存储操作数。控制器是指组合逻辑控制器，又称硬布线控制器。
在一种可能的实现方式中，在指令包括目标地址的情况下，控制器具体用于根据预设的地址与地址段的对应关系，确定目标地址对应的目标地址段；根据预设的地址段与命令通道的对应关系和目标地址段，获取操作码。
在另一种可能的实现方式中，在命令通道的数量为多个，数据通道的数量为多个的情况下，控制器还用于确定操作码对应的命令通道，以及，确定操作数对应的数据通道。
在另一种可能的实现方式中，在指令包括目标地址的情况下，控制器具体用于根据预设的地址与地址段的对应关系，确定目标地址对应的目标地址段；根据预设的地址段与命 令通道的对应关系，确定目标地址段对应的命令通道为操作码对应的命令通道；根据预设的地址段与数据通道的对应关系，确定目标地址段对应的数据通道为操作数对应的数据通道。
在另一种可能的实现方式中，控制器具体用于根据预设的数据块大小与通道号的对应关系，确定操作数对应的通道号；根据通道号，确定操作码对应的命令通道；根据通道号，确定操作数对应的数据通道。
在另一种可能的实现方式中，在指令包括目标地址的情况下，控制器具体用于将目标地址进行哈希运算得到哈希值，将哈希值与命令通道的通道数进行取模运算得到通道号，根据通道号确定操作码对应的命令通道；根据通道号确定操作数对应的数据通道。
第三方面提供一种芯片系统，该芯片系统包括多个处理器核心，用于支持网络设备实现上述方面中所涉及的功能。在一种可能的设计中，所述芯片系统还包括存储器，所述存储器，用于保存网络设备必要的程序指令和数据。该芯片系统，可以由芯片构成，也可以包括芯片和其他分立器件。
从以上实施例可以看出，接收处理器核心发送的指令，根据指令获取操作码；将操作码存入命令通道，将指令包括的操作数存入数据通道；从命令通道读取操作码，从数据通道读取操作数；根据操作码和操作数执行原子操作，以及在原子操作期间将状态机的状态设为不可打断状态。在多个core下发指令的情况下，各core下发的指令存储在通道中，然后依次读取指令执行，这样可避免多个core循环查询锁状态的开销，在此期间可以执行其他操作，从而提升多核设备的数据处理性能。并且，数据处理电路可以通过控制状态机的状态，维护原子操作状态，通过硬件实现原子操作，以使得多个指令能够分开执行，从而解决多指令并行时产生的数据竞争。
附图说明
图1为本申请实施例中数据处理电路的一个示意图；
图2为本申请实施例中数据处理方法的一个示意图；
图3为本申请实施例中数据处理方法的另一个示意图；
图4为本申请实施例中网络设备的一个示意图。
具体实施方式
首先对本申请应用的数据处理电路进行介绍，请参阅图1，本申请提供的数据处理电路100的一个实施例包括：
通信接口101、控制器102、命令通道103、数据通道104、存储器105和状态机106，控制器102分别通过电路与通信接口101、命令通道103、数据通道104、存储器105和状态机106相连；
通信接口101，用于接收处理器核心发送的指令，指令包括操作数；
控制器102，用于根据指令获取操作码；确定操作码对应的命令通道，以及，确定操作数对应的数据通道；将操作码存入命令通道，将操作数存入数据通道；
命令通道103，用于存储操作码；
数据通道104，用于存储操作数；
控制器102，还用于从命令通道103读取操作码，从数据通道104读取操作数；根据操作码和操作数在存储器105中执行原子操作，以及在原子操作期间将状态机106的状态设为不可打断状态。
其中，控制器是指组合逻辑控制器，又称硬布线控制器。
其中，控制器102可以将处理器核心发送的指令转换成实际执行的操作指令，操作指令包括操作码和操作数，操作码表示操作指令对应的操作类型。操作数表示执行操作所需要数据的来源。操作数可以是立即数或者地址。
命令通道和数据通道均为由硬件实现的先入先出队列(First Input First Output，FIFO)通道。先入先出是指按照先后顺序，存取命令通道的操作码，以及存取数据通道的操作数。命令通道和数据通道的数量相同且对应。例如在操作指令中，操作码为add，操作数为2，则操作码add进入命令通道1，操作数2进入数据通道1。操作码和操作数分别按照指令顺序入队和出队，一个操作指令的操作码入队和操作数入队是同步的，一个操作指令的操作码出队和操作数出队也是同步的，这样就可以保证一个操作指令的完整性。
基于以上提供的数据处理电路，下面对本申请的数据处理方法进行介绍。请参阅图2，本申请提供的数据处理方法的一个实施例包括：
步骤201、接收处理器核心发送的指令。
步骤202、根据指令获取操作码。
步骤203、将操作码存入命令通道。
步骤204、将操作数存入数据通道。
本实施例中，指令可以包括操作码和操作数，或者指令包括目标地址和操作数。
在指令包括操作码和操作数的情况下，直接获取指令的操作码，将指令包括的操作码直接存入命令通道，将操作数直接存入数据通道。
在指令包括目标地址和操作数的情况下，可以根据目标地址获取操作码。然后执行步骤203和步骤204。
步骤205、从命令通道读取操作码。
步骤206、从数据通道读取操作数。
需要说明的是，操作码和操作数的存取是同步的，即同时存入一个指令对应的操作码和操作数，同时读取一个指令对应的操作码和操作数。
步骤207、根据操作码和操作数在存储器中执行原子操作，以及在原子操作期间将状态机的状态设为不可打断状态。
其中，操作码可以包括多种类型，例如加法操作、减法操作和存储操作。相应的原子操作也包括多种类型，例如原子加法操作、原子减法操作和原子存储操作。在原子操作期间，将状态机的状态设为不可打断状态。这样能够保证一个原子操作不被打断，以使得不同指令分开独立执行。
当原子操作结束后，将状态机设为空闲状态。这样控制器可以分别从命令通道中读取 下一个操作码，从数据通道中读取下一个操作数，然后根据读取的操作码和操作数执行下一个原子操作。
本实施例中，以通道存储指令后，按照指令顺序执行指令，避免了多core循环抢锁造成的数据处理能力的浪费。
其次，用命令通道存储操作码，用数据通道存储操作数，通过硬件实现原子操作，使不同指令能够分开独立执行，从而解决多核下发指令时产生的数据竞争。并且，以硬件实现原子操作可以加快指令执行效率。
在一个可选实施例中，指令包括目标地址；
步骤202具体为：根据预设的地址与地址段的对应关系，确定目标地址对应的目标地址段；根据预设的地址段与操作码的对应关系和目标地址段，获取操作码。
具体的，控制器存有地址段与操作码的对应关系。
举例来说，地址段与操作码的对应关系可以如表1所示：
地址段 起始地址 终点地址 操作码 说明
第一地址段 0x2FD80000 0x2FEDFFFF add 加法操作
第二地址段 0x2FE00000 0x2FE5FFFF sub 减法操作
… … … … …
第八地址段 0x2FF00000 0x2FF5FFFF write/read 存储操作
表1
若指令包括的地址为0x2FD80100，控制器确定其属于第一地址段，根据地址段与操作码的对应关系可以确定其对应的操作码为加法操作。然后将加法操作存入命令通道，以及将操作数存入数据通道。可以理解的是，地址段与操作码的对应关系不限于以上举例。
这样只需要向数据处理电路提供地址，数据处理电路的控制器就能快速确定地址对应的操作码。这样无需用户在程序的指令中写入各种操作码，能够统一操作接口，可以避免因错误操作码导致的程序故障，提高了程序的可靠性。
在实际应用中可以设置多个命令通道和数据通道，以存储多个core下发的大量指令。下面对指令存储在通道的方法进行详细介绍。请参阅图3，本申请提供的数据处理方法的另一个实施例包括：
步骤301、接收处理器核心发送的指令。
步骤302、根据指令获取操作码。
步骤303、确定操作码对应的命令通道。
步骤304、确定操作数对应的数据通道。
步骤305、将操作码存入命令通道。
步骤306、将操作数存入数据通道。
步骤307、从命令通道读取操作码。
步骤308、从数据通道读取操作数。
需要说明的是，本实施例采用操作码和操作数同步存取，即同时存入一个指令对应的操作码和操作数，同时读取一个指令对应的操作码和操作数。
步骤309、根据操作码和操作数在存储器中执行原子操作，以及在原子操作期间将状态机的状态设为不可打断状态。
具体的，步骤301至步骤302与图2所示实施例中步骤201至步骤202相似，步骤305至步骤309与图2所示实施例中步骤203至步骤207相似。
本实施例中，数据处理电路包括多个命令通道和多个数据通道。将多个操作码存入多个命令通道，以及，将多个操作数存入多个数据通道有多种方式。请参阅以下实施例：
在一个可选实施例中，指令包括目标地址；
步骤303具体为：根据预设的地址与地址段的对应关系，确定目标地址对应的目标地址段；根据预设的地址段与命令通道的对应关系，确定目标地址段对应的命令通道为操作码对应的命令通道；
步骤304具体为：根据预设的地址段与数据通道的对应关系，确定目标地址段对应的数据通道为操作数对应的数据通道。
具体的，控制器存有地址段与命令通道和数据通道的对应关系。
举例来说，地址段与命令通道，和地址段与数据通道的对应关系可以如表2所示：
地址段 起始地址 终点地址 命令通道 数据通道
第一地址段 0x2FD80000 0x2FEDFFFF 命令通道1 数据通道1
第二地址段 0x2FE00000 0x2FE5FFFF 命令通道2 数据通道2
… … … … …
第八地址段 0x2FF00000 0x2FF5FFFF 命令通道8 数据通道8
表2
若指令包括的地址为0x2FD80100，控制器确定其属于第一地址段，进而确定操作码对应的命令通道为命令通道1，操作数对应的数据通道为数据通道1。可以理解的是，地址段与命令通道的对应关系，或者地址段与数据通道的对应关系不限于以上举例。
在另一个可选实施例中，
步骤303具体为：根据预设的数据块大小与通道号的对应关系，确定操作数对应的通道号；根据通道号，确定操作码对应的命令通道；
步骤304具体为：根据通道号，确定操作数对应的数据通道。
具体的，控制器存有数据块大小与命令通道和数据通道的对应关系。
举例来说，数据块大小与命令通道，和数据块大小与数据通道的对应关系可以如表3所示：
数据块大小 命令通道 数据通道
16 命令通道1 数据通道1
32 命令通道2 数据通道2
64 命令通道3 数据通道3
表3
本实施例中，若操作数的数据块大小为32，则控制器确定其对应的命令通道为命令通道2，其对应的数据通道为数据通道2。
可以理解的是，除了按照数据块大小存取操作码和操作数之外，还可以采用间插模式将操作码和操作数存入对应的通道。数据块大小与命令通道的对应关系，或者数据块大小与数据通道的对应关系不限于以上举例。
在另一个可选实施例中，指令包括目标地址；
步骤303具体为：将目标地址进行哈希运算得到哈希值，将哈希值与命令通道的通道数进行取模运算得到通道号，根据通道号确定操作码对应的命令通道；
步骤304具体为：根据通道号确定操作数对应的数据通道。
具体的，命令通道的通道数和数据通道的通道数相同。哈希运算采用的算法可以是CRC32，或者，消息摘要算法(Message Digest Algorithm)，如MD2、MD4、MD5，或者，安全哈希算法(Secure Hash Algorithm)，如SHA1。
举例来说，命令通道包括命令通道1，命令通道2，…，命令通道8，数据通道包括数据通道1，数据通道2，…，数据通道8。设将目标地址进行哈希运算，再和8进行取模运算得到的通道号为3，则确定操作码对应的命令通道为命令通道3，操作数对应的数据通道为数据通道3。
为便于理解，下面以一个具体应用场景对本申请实施例中的数据处理方法进行介绍：
网络设备包括的8个core为core1，core2，…，core8。假设core1和core2下发指令1和指令2，指令1和指令2对应的统计项均为报文数量；在指令1中，地址为0x2FD80100，立即数为1。在指令2中，地址为0x2FD80100，立即数为2。
预设的地址段和操作码的对应关系如表1所示，地址段与通道的对应关系如表2所示，则数据处理电路确定该地址属于第一地址段，其对应的操作码为加法操作，其对应的命令通道为命令通道1，其对应的数据通道为数据通道1。
控制器先将指令1对应的“add”存入命令通道1，将指令1对应的“1”存入数据通道1。然后，将指令2对应的“add”存入命令通道1，将指令2对应的“2”存入数据通道1。再先根据指令1对应的“add”和“1”，执行原子操作，指令1执行完成得到的第一报文数量为1。在此期间将状态机的状态设为不可打断状态。当指令1执行完成后，将状态机时段的状态设为空闲状态。然后，从命令通道1读取指令2对应的“add”，从数据通道1读取指令2对应的“2”，执行原子操作得到的第二报文数量为3，即第二报文数量等于第一报文数量+2，。在此期间将状态机的状态设为不可打断状态。
可以理解的是，若有后续指令对应的统计项也是报文数量，且操作码为加法操作，则在前一指令执行完成得到的报文数量上执行加法操作。
在指令1的执行期间，core2将指令发送给数据处理电路后，core2无需循环抢锁，可以执行其他操作，从而提高网络设备的数据处理能力。同时，用命令通道存储操作码，用数据通道存储操作数，通过硬件实现原子操作，这样能够使指令1和指令2分开独立执行，从而解决多核系统中多指令并行时的数据竞争问题。
以上对本申请的数据处理电路和数据处理方法进行了介绍，下面对本申请的网络设备进行介绍。请参阅图4，本申请提供的网络设备400的一个实施例包括：
多核处理器401和数据处理电路402；
多核处理器401包括多个处理器核心4011。
数据处理电路402如图1所示实施例或可选实施例中的数据处理电路。
其中，数据处理电路402可以执行以上实施例提供的数据处理方法。
本申请的网络设备可以是用户设备、接入网设备或核心网设备等。用户设备是指手机、平板电脑、个人数字助理、车载电脑、可穿戴设备等。接入网设备是指基站、演进型基站或接入点等。核心网设备是指移动交换中心(Mobile Switching Center，MSC)、路由器或交换机等。
以上所述并不用以限制本发明，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (13)

  1. 一种数据处理方法，其特征在于，包括：
    接收处理器核心发送的指令，所述指令包括操作数；
    根据所述指令获取操作码；
    将所述操作码存入所述命令通道，将所述操作数存入所述数据通道；
    从所述命令通道读取所述操作码，从所述数据通道读取所述操作数；
    根据所述操作码和所述操作数在存储器中执行原子操作，以及在原子操作期间将状态机的状态设为不可打断状态。
  2. 根据权利要求1所述的方法，其特征在于，所述指令还包括目标地址；
    所述根据所述指令获取操作码包括：
    根据预设的地址与地址段的对应关系，确定所述目标地址对应的目标地址段；
    根据预设的地址段与操作码的对应关系和所述目标地址段，获取操作码。
  3. 根据权利要求1所述的方法，其特征在于，所述命令通道的数量为多个，所述数据通道的数量为多个；
    在所述将所述操作码存入所述命令通道，将所述操作数存入所述数据通道之前，所述方法还包括：
    确定所述操作码对应的命令通道，以及，确定所述操作数对应的数据通道。
  4. 根据权利要求3所述的方法，其特征在于，所述指令还包括目标地址，
    所述确定所述操作码对应的命令通道包括：根据预设的地址与地址段的对应关系，确定所述目标地址对应的目标地址段；根据预设的地址段与命令通道的对应关系，确定所述目标地址段对应的命令通道为所述操作码对应的命令通道；
    所述确定所述操作数对应的数据通道包括：根据预设的地址段与数据通道的对应关系，确定所述目标地址段对应的数据通道为所述操作数对应的数据通道。
  5. 根据权利要求3所述的方法，其特征在于，
    所述确定所述操作码对应的命令通道包括：根据预设的数据块大小与通道号的对应关系，确定所述操作数对应的通道号；根据所述通道号，确定所述操作码对应的命令通道；
    所述确定所述操作数对应的数据通道包括：根据所述通道号，确定所述操作数对应的数据通道。
  6. 根据权利要求3所述的方法，其特征在于，所述指令还包括目标地址，
    所述确定所述操作码对应的命令通道包括：将所述目标地址进行哈希运算得到哈希值，将所述哈希值与所述命令通道的通道数进行取模运算得到通道号，根据所述通道号确定所述操作码对应的命令通道；
    所述确定所述操作数对应的数据通道包括：根据所述通道号确定所述操作数对应的数据通道。
  7. 一种数据处理电路，其特征在于，包括：
    通信接口、控制器、命令通道、数据通道、存储器和状态机，所述控制器分别通过电路与所述通信接口、命令通道、数据通道、存储器和状态机相连；
    通信接口，用于接收处理器核心发送的指令，所述指令包括操作数；
    控制器，用于根据所述指令获取操作码；将所述操作码存入所述命令通道，将所述操作数存入所述数据通道；
    所述命令通道，用于存储所述操作码；
    所述数据通道，用于存储所述操作数；
    所述控制器，还用于从所述命令通道读取所述操作码，从所述数据通道读取所述操作数；根据所述操作码和所述操作数在所述存储器中执行原子操作，以及在原子操作期间将状态机的状态设为不可打断状态。
  8. 根据权利要求7所述的数据处理电路，其特征在于，所述指令还包括目标地址；
    所述控制器具体用于根据预设的地址与地址段的对应关系，确定所述目标地址对应的目标地址段；根据预设的地址段与命令通道的对应关系和所述目标地址段，获取操作码。
  9. 根据权利要求7所述的数据处理电路，其特征在于，所述命令通道的数量为多个，所述数据通道的数量为多个；
    所述控制器还用于确定所述操作码对应的命令通道，以及，确定所述操作数对应的数据通道。
  10. 根据权利要求9所述的数据处理电路，其特征在于，所述指令还包括目标地址；
    所述控制器具体用于根据预设的地址与地址段的对应关系，确定所述目标地址对应的目标地址段；根据预设的地址段与命令通道的对应关系，确定所述目标地址段对应的命令通道为所述操作码对应的命令通道；根据预设的地址段与数据通道的对应关系，确定所述目标地址段对应的数据通道为所述操作数对应的数据通道。
  11. 根据权利要求9所述的数据处理电路，其特征在于，
    所述控制器具体用于根据预设的数据块大小与通道号的对应关系，确定所述操作数对应的通道号；根据所述通道号，确定所述操作码对应的命令通道；根据所述通道号，确定所述操作数对应的数据通道。
  12. 根据权利要求9所述的数据处理电路，其特征在于，所述指令还包括目标地址；
    所述控制器具体用于将所述目标地址进行哈希运算得到哈希值，将所述哈希值与所述命令通道的通道数进行取模运算得到通道号，根据所述通道号确定所述操作码对应的命令通道；根据所述通道号确定所述操作数对应的数据通道。
  13. 一种网络设备，其特征在于，包括：
    多个处理器核心和数据处理电路；
    所述处理器核心，用于向所述数据处理电路发送指令；
    所述数据处理电路为权利要求7至12中任一项所述的数据处理电路。
PCT/CN2018/111557 2017-10-24 2018-10-24 一种数据处理方法、数据处理电路和网络设备 WO2019080852A1 (zh)

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