WO2019066891A1

WO2019066891A1 - Systems, methods, and apparatuses for implementing failure prediction and process window optimization in chromeless phase lithography

Info

Publication number: WO2019066891A1
Application number: PCT/US2017/054266
Authority: WO
Inventors: Hyungjin MA; Ashish V. SANGWAI; Diwakar Agarwal
Original assignee: Intel Corporation
Priority date: 2017-09-29
Filing date: 2017-09-29
Publication date: 2019-04-04

Abstract

Predicting a failure mode in a negative and positive focus including patterning a wafer using a test mask at each of a plurality of varied focus steps to expose a plurality of features of the test mask into the wafer at each of the plurality of varied focus steps; capturing images of the plurality of features exposed; identifying any location where one or more of the plurality of features fails to expose correctly; and creating a predictor for each failure mode by correlating the location at which the respective feature failed to expose correctly into the wafer and the focus step at which the feature failed to correctly expose into the wafer. Feedback from predictor is applied via Optical Proximity Correction to the output mask by fine-tuning output mask shape or with negative Sub-Resolution Assisting Features (SRAFs) to align center focus for overall process window improvement.

Description

SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING FAILURE PREDICTION AND PROCESS WINDOW OPTIMIZATION IN CHROMELESS

PHASE LITHOGRAPHY

TECHNICAL FIELD

Semiconductor and electronics manufacturing, and more particularly, to systems, methods, and apparatuses for implementing failure prediction and process window optimization in chromeless phase lithography.

BACKGROUND

As circuit feature sizes shrink with Moore's Law scaling, defect and yield control have become more challenging because process margin is getting squeezed due to increasingly tight tolerances and a greater density of features within a given space. More than ever, high resolution and high contrast are required during lithography since extreme ultraviolet (EUV) lithography and multi-patterning lithographic processes are relatively extremely costly.

For advanced process nodes in semiconductor manufacturing, one of the major challenges is to control defects and yield to a level that is viable for high volume

manufacturing (HVM). To maintain the density scaling and reduce cell footprint, process margins are tightening which in turn causes systematic and random process variations resulting in the processes being more prone to defects.

One such source of process variation is the result of insufficiently accurate model prediction of lithographic processes or changes in the overall depth of focus (DOF), which impacts the optical proximity correction (OPC) of mask design.

The accuracy of these measurements and the accuracy of the model is of utmost importance because deficiency of the OPC model translates to a variation of dimensions on the final semiconductor chips produced.

When the physical dimensions of the manufactured semiconductors were greater, such inaccuracies and uncertainty were manageable due to the greater margins. However, as the physical size of these manufactured semiconductors is reduced further into the nanometer realm of manufacturing, it becomes necessary to operate using increasingly accurate models if manufacturing yields are to remain economically viable.

Chrome-less phase lithography (CPL) is an advanced method of resolution enhancement using phase shifted masks (PSM). It offers superior resolution and contrast at the argon fluoride (ArF) wavelength and may be utilized to reduce the quantity of multi- patterning operations necessary for a given silicon fabrication. Unfortunately, one of the challenges is to control overall depth of focus (DOF), because Chrome-less phase lithography processes are highly sensitive to main feature optical proximity correction (OPC) and Sub- Resolution Assisting Feature (SRAF) fashion. Consequently, certain features may have shifted focus and therefore translate to defects such as missing features or scumming of the resist, each of which is capable of causing yield fallout and therefore increase the cost of manufacturing.

The present state of the art may therefore benefit from the systems, methods, and apparatuses for implementing failure prediction and process window optimization in chromeless phase lithography as described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example, and not by way of limitation, and will be more fully understood with reference to the following detailed description when considered in connection with the figures in which:

Figure 1 depicts a Scanning Electron Microscope (SEM) image capture having varying focus steps from negative to positive in accordance with described embodiments;

Figure 2 depicts a Scanning Electron Microscope (SEM) image capture having varying focus steps from negative to positive in accordance with described embodiments;

Figure 3 depicts an exemplary sudden falloff in critical dimension (CD) at positive defocus resulting in a "missing feature" defect in accordance with described embodiments;

Figure 4 depicts various failure modes at each of positive and negative focus biases in accordance with described embodiments;

Figure 5 depicts an OPC correction scheme utilizing new metrics in accordance with described embodiments;

Figure 6 depicts an OPC correction scheme providing fine control of the center focus shift in accordance with described embodiments;

Figure 7 is a schematic of a computer system in accordance with described embodiments;

Figure 8 illustrates a semiconductor device (or an interposer) that includes one or more described embodiments;

Figure 9 illustrates a computing device in accordance with one implementation of the invention;

Figure 10 is a flow diagram illustrating a method for implementing failure prediction and process window optimization in chromeless phase lithography in accordance with described embodiments; and

Figure 11 is a flow diagram illustrating another method for implementing failure prediction and process window optimization in chromeless phase lithography in accordance with described embodiments.

DETAILED DESCRIPTION

Described herein are systems, methods, and apparatuses for implementing failure prediction and process window optimization in chromeless phase lithography. For instance, in accordance with one embodiment, there are means described for predicting a failure mode in a negative and positive focus, in which the method includes: creating a test mask via a lithography process, in which the test mask defines a plurality of features; patterning a physical silicon wafer using the test mask at each of a plurality of varied focus steps, in which the patterning exposes the plurality of features as defined by the test mask into the physical silicon wafer at each of the plurality of varied focus steps; capturing Scanning Electron Microscope (SEM) images of the plurality of features exposed into the physical silicon wafer; identifying from the SEM images any location where one or more of the plurality of features fails to expose correctly from the test mask at any one or more of the plurality of varied focus steps; and creating a predictor for each failure mode by correlating the location at which the respective feature failed to expose correctly into the physical silicon wafer and the focus step at which the feature failed to correctly expose into the physical silicon wafer.

According to yet another embodiment, there are means described for performing Optical Proximity Correction (OPC) to align features of a mask to a center of focus, in which the method includes: receiving a predictor as input for each of features corresponding to a failure mode within a test mask, in which the predictor identifies (i) a location at which the respective feature might fail to expose correctly into a physical silicon wafer exposed via the test mask, (ii) a focus step at which the respective feature failed to correctly expose into the physical silicon wafer, and (iii) whether a failure occurred within a top portion of a photoresist of the physical silicon wafer or within a bottom portion of the photoresist;

identifying a center of focus for each of the plurality of features having failed to expose correctly into the physical silicon wafer; and adjusting the features toward the identified center of focus by (i) positively biasing features associated with a failure mode within a positive focal depth range to move the respective features toward the identified center of focus and by further (ii) negatively biasing features associated with a failure mode within a negative focal depth range to move the respective features toward the identified center of focus.

Masks which employ OPC correction through OPC models require high accuracy of prediction in those models. The greater the accuracy, the more useful and accurate the resulting photomask will be for the semiconductor manufacturing processes.

The methodologies described herein provide both failure prediction of failure modes undetectable to prior methodologies as well as provide improved input parameters for OPC correction via improved OPC models which is then applied to semiconductor fabrication via Chromeless Phase Lithography (CPL).

As circuit feature sizes shrink to enable continued Moore's Law scaling, the accuracy requirements for the placement and size of individual wafer features continue to tighten. A critical determiner of this wafer feature scaling is ensuring broad depth of focus for feature negatively and positively biased focuses which are necessary for proper feature sizing on the product photomasks. The size of mask features is directly determined by the OPC (Optical Proximity Correction) as determined by the OPC lithography model. As the Edge Placement Error (EPE) requirements tighten for next generation node manufacturing, such as 10- nanometer (nm) node and beyond, improvements are needed in OPC modeling accuracy to enable both efficient process development cycles, and ultimately to enable correct feature sizes on product wafers to so as to attain proper circuit function.

The existing modeling software for OPC is deficient in terms of the accuracy when new lithographic systems having tighter margins and dimensions are utilized, resulting in unworkable errors inhibiting the newer technologies from being successfully scaled to high volume manufacturing. Previously utilized techniques simply cannot predict failure modes such as T-topping and footing failure modes with sufficient accuracy and consistency to enable precise photolithographic processing of smaller feature sizes and geometries needed for next generation semiconductor manufacturing.

In the following description, numerous specific details are set forth such as examples of specific systems, languages, components, etc., in order to provide a thorough

understanding of the various embodiments. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the embodiments disclosed herein. In other instances, well known materials or methods have not been described in detail in order to avoid unnecessarily obscuring the disclosed embodiments.

In addition to various hardware components depicted in the figures and described herein, embodiments further include various operations which are described below. The operations described in accordance with such embodiments may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the operations. Alternatively, the operations may be performed by a combination of hardware and software.

Any of the disclosed embodiments may be used alone or together with one another in any combination. Although various embodiments may have been partially motivated by deficiencies with conventional techniques and approaches, some of which are described or alluded to within the specification, the embodiments need not necessarily address or solve any of these deficiencies, but rather, may address only some of the deficiencies, address none of the deficiencies, or be directed toward different deficiencies and problems which are not directly discussed.

Implementations of embodiments of the invention may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention.

A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors

(MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the invention, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the invention may also be carried out using nonplanar transistors.

Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si0₂) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an MOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some implementations of the invention, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si0₂), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as

silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

Figure 1 depicts a Scanning Electron Microscope (SEM) image 100 capture having varying focus steps 105 from negative to positive.

More particularly, there may be observed negative focus steps 105 on the left, a neutral focus step F0 in the center, and then positive focus steps 105 on the right.

At the bottom left of the SEM image 100 there is a block of features exhibiting insufficient exposure 110 at the most extreme left negative focus step. Conversely, at the upper right, there is depicted missing features 115 at the most extreme right positive focus step. Notably, the features are not aligned to center focus 120 and there is little common depth of focus.

As can be seen in the center portion of the SEM image 100 there is a region of overlap 125 within which the features are adequately exposed and correctly developed, although this common depth of focus is narrow and thus highly restrictive.

It is important to the manufacturing process to have accurate indicators to predict failures as a function of focus shift so as to identify process margin and to drive the OPC solution to maximize the process margin and thus improve yields and reduce the cost of manufacture.

With Chrome-less phase lithography (CPL) a significant factor in determining depth of focus (DOF) is not only a change to critical dimension (CD) of approximately 10% but also the sudden failures, such as the missing features 115 depicted at the upper right of the

SEM image, at the extreme edges of depth of focus (DOF).

Chromeless Phase Lithography or CPL utilizes phase shifting technology to provide multi-layer enabling by applying chromeless features on the mask to define patterns that have a nearly 100% transmission and are phase shifted by 180 degrees. The phase shift is created by etching the quartz substrate to a depth that is dependent on the wavelength of the imaging system and using the etched quartz to induce a phase shift, making it possible to build the desired 100% transmission phase structures for any given wavelength using standard chrome on quartz substrates.

While the application of Chromeless Phase Lithography techniques provides clear benefits to the semiconductor manufacturing processes, there is problematically an inability to accurately identify and determine the presence of such sudden failures, such as missing features or insufficiently exposed features.

By predicting the failures, overall depth of focus may be greatly improved and predicted with greater accuracy. For instance, through the use of improved metrics, techniques for mask modification enable a continuous shift of center focus which can then be controlled for each feature to maximize the common DOF of the entire mask corresponding to the region of overlap 125 as depicted at the bottom of the SEM image 100. Through the use of such techniques, increased fabrication operating margins as well as improved yields for semiconductor manufacturing processes may be realized when using Chromeless Phase Lithography based masks.

The depth of focus is a metric for process margin of the scanner. Each photomask, often from a larger set of photomasks, defines a pattern layer for the integrated circuit fabrication process. The photomask is fed into a photolithography scanner (sometimes called a stepper) selected for exposure.

Unfortunately, the scanner may exhibit process variation such that when a wafer is exposed, there is some very small variation resulting in small process windows, which can, in turn, result in defects and present problems during the fabrication process due to reduced yields.

Intentionally placing the silicon wafer at different focus depths via the varying offsets shown here, there is a range for the resulting depth of focus.

At some focus steps 105, the features are exposed adequately and are thus well formed, whereas at other focus steps 105, the features are insufficiently exposed, such as the insufficient exposure 110 denoted in the lower left corner at the extreme negative focus edge or resulting in entirely missing features 115 as denoted by the upper right corner at the extreme positive focus edge.

The overlap between the three columns of boxes forming the region of overlap 125 or the common depth of focus is of extreme importance to the process because within that region of overlap, variation of process can be accommodated while still attaining correctly exposed features on the silicon wafer.

As can be seen, features within the region of overlap 125 are correctly exposed, however, certain features are malformed, missing, or otherwise defective at both the left (negative) and right (positive) focus edges, due to excessive process variation.

Figure 2 depicts a Scanning Electron Microscope (SEM) image 200 capture having varying focus steps 205 from negative to positive.

Unlike the features from Figure 1 described above, the features of Figure 2 have been aligned to center 210 thus resulting in an increased region of overlap 225. More particularly, it may now be observed that the common depth of focus (DOF) is now extended from three blocks wide at Figure 1 to double the region of overlap 225 at six blocks wide as depicted by the SEM image 200 of Figure 2.

Depth of focus prediction utilizes model intensity based image metrics which are calibrated to predicted physical failure modes, such as resist footing and T-topping. These calibrated metrics are then used to drive correction and/or validation. Unlike previous techniques which relied on a single intensity metric to capture all failure modes, practice of the disclosed embodiments creates and utilizes many more physical metrics.

For instance, through practice of the described techniques, T-topping failure modes are predicted with a positive focus metric while resist footing is predicted with a negative focus metric. By employing these two approaches independently in conjunction with many more physical metrics, the accuracy of DOF predictions improve significantly.

The region of overlap 225 or the common depth of focus may be maximized by changing the mask so as to yield a nearly continuous center focus shift through a combination of dot negative SRAFs and varying sawtooth depths as described in greater detail below at Figures 5 and 6.

More specifically, the final mask shape may be optimized through OPC correction using the above described techniques to align the center focus of all features, thus

maximizing the overall depth of focus and providing a significantly greater region of overlap 225.

In the absence of accurate depth of focus prediction metrics, previously known techniques suffered from generally small and non-optimal depth of focus with a restricted and very narrow region of overlap, such as that which is depicted by the smaller region of overlap 125 of Figure 1.

For instance, laboratory results demonstrate that application of previously known techniques for a given mask resulted in a highly restrictive and narrow 30 nm of common (e.g., overlapping) depth of field.

Conversely, after characterization of the mask utilizing the improved methodologies as described herein, including applying the techniques for predicting failures modes and providing a mask manipulation scheme to maximize the depth of focus, the resulting overlapping region of interest was more than doubled, increasing the common depth of field from approximately 30 nm (e.g., as approximated by the three block wide region at Figure 1) to more than 60 nm of common depth of field (e.g., as approximated by the six block wide region at Figure 2).

Maximizing or increasing the region of overlap 225 does not eliminate process variation, as there may still be certain focus steps where features are not satisfactory, however, by increasing the area of overlap, here doubling the area of overlap or the common focus depth to a six-wide region, there is a significantly larger range of satisfactory foci meaning that a greater amount of process variation can be accommodated while maintaining equivalent yields or increasingly tight tolerances may be accommodated without increasing the likelihood of defects due to such variation when the scanner exposes the wafer's photoresist to the mask.

Chromeless Phase Lithography offers improved resolution but has a trade off due to a smaller process window overlap and a smaller depth of focus overlap, which, if not accommodated properly, results in the defects described above.

Maximizing the overlapping depth of focus and thus having a greater region of overlap 225 therefore permits utilizing of the stricter Chromeless Phase Lithography process with greater variance in the scanners and, because we can operate with more variance in the scanners while maintaining a satisfactory yield, or attaining a larger yield due to the larger accommodation of process variation windows had the increased region of overlap 225 not been realized.

Improved yields and accommodation of greater process variation when operating the scanners thus in turn contributes to lower operating costs and enables a lower cost to manufacture and thus a lower cost to customers for the resulting product.

Figure 3 depicts an exemplary sudden falloff 300 in critical dimension (CD) at positive defocus resulting in a "missing feature" defect.

More particularly, the observed features in the SEM image 315 are depicted with the focus steps progressing from negative (on the left) to positive (on the right) as depicted by element 305.

Though derived from the same mask, notably there is a missing center feature 310 in the rightmost extreme positive edge of the depth of focus, causing a defect or a failure mode for the functional silicon under manufacture.

Also depicted are the simulated features in an optical model 320 with the simulated missing feature due to the lack of intensity 325 again being depicted in the center of the simulated image.

Fabrication failures at defocus are predicted utilizing new metrics in comparison to previously known Chromeless Phase Lithography solutions which relied upon either contour based metrics or a single intensity metric for fabrication failures at defocus. Unfortunately, such a process is prone to missing critical failures such as the missing center feature 310 depicted here, due to the fact that model contours at defocus are not sufficient to accurately predict all failures at defocus conditions.

The sudden falloff in critical dimension (CD) depicted here at positive defocus is referred to as a "missing feature" defect. Use of model contours or a single intensity (on- target) metric fails to predict the "missing feature" defect exemplified here whereas application of a separate metric calibration, using a positive defocus here specifically for such defect, predicts and captures the failure mode effectively.

Failure modes including a "missing feature" and also "resist footing" are described in greater detail below with respect to Figure 4.

According to one embodiment, application of the described methodologies enables a prediction of what defects will occur, such as the missing features or the insufficiently exposed features. With such a prediction, it is then possible for the OPC modeling to comprehend the necessary corrections so as to compensate for and therefore eliminate those failure modes at the silicon wafer.

Prior techniques simply could not reliably predict such failure modes, and therefore, means are provided in accordance with one embodiment to enable a much more reliable and more accurate prediction of what will actually occur for a given feature at each depth of focus, both on the left (negative) and the right (positive) sides of the depth of focus continuum.

Stated differently, such predictions describe how large the region of overlap or the common depth of focus will be for a given mask, within which all the features are reliably formed, without moving into a region of the depth of focus that is too negatively biased or too positively biased that some features are missing, defective, or malformed.

Having made such predictions and established the acceptable overlapping depth of focus, it is then possible to correct the pattern of the mask via OPC modeling in such a way as to correct for those defects by aligning features to the center of focus to permit for a greatest possible range of process variation while realizing correctly formed defect free features within the resulting silicon wafer.

According to one embodiment, output of a semi-physical model renders the simulated cross sections 420 and 421 as depicted at Figure 4 as well as the simulated features within the optical model as depicted at here at element 320, with the different intensities presented with respect to the wafer plane. With the optical electromagnetic field intensity at the wafer plane as provided by an optical model the intensities are correlated to the respective features defined by the mask and as represented by the semi-physical model, from which it is then derived where failure modes are predicted to occur. For instance, the missing center feature 310 is represented within the simulated image output by the optical model in which it may be observed the simulated missing feature is predicted due to a lack of intensity 325 at that location, effectively resulting in a missing feature predicted as output from the semi-physical model due to weak intensity at that location, despite the feature being defined by the mask.

As shown here, the center feature is formed correctly at negative focus steps but fails to form correctly at positive focus steps, meaning that if the process deviation biases to the right (positive) then such a defect are predicted to occur.

Calibrating for such predicted failures permits alignment of the features defined by the mask to center focus so as to reduce or eliminate the occurrence of such failures by permitting for greater process variation through the increased overlapping depth of focus, due to the center aligned features as opposed to the non-corrected left and right biased (e.g., negatively and positively biased) features prior to OPC correction which is described in greater detail below at Figure 4.

Figure 4 depicts various failure modes 400 at each of positive and negative focus biases in accordance with described embodiments. The focus steps from negative at the top to positive at the bottom as represented by the key at element 405.

More particularly, there is depicted on the left a feature intensity profile 415 showing a failure mode at a positive focus bias, with the extreme positive edge of the focus depth clearly depicting an uneven and insufficient exposure due to a lack of intensity, resulting in a "missing feature" as the top portion of the resist that is not adequately opened. From far negative focus steps through approximately on focus or slightly positive focus steps, the feature is opened correctly. The simulated cross section 420 similarly depicts the "missing feature" as a missing feature in the center of the simulated image corresponding to the positive end of the feature intensity profile 415.

Similarly, the feature intensity profile 410 depicts the failure mode at a negative focus bias, here resulting in a resist footing failure mode at the extreme negative edge of the depth focus where the bottom-most portion of the resists is insufficiently exposed due to a lack of intensity, resulting in a "resist footing" failure mode. The simulated cross section 425 similarly depicts the "resist footing" failure mode as extra unwanted resist which has remained after exposure and etching as predicted by the simulated cross section image 425.

The effect of a "missing feature" is highly dependent on the geometry and SRAF fashion used in correction. Observations such as "missing feature" occur when a resist top is not opened at positive defocus due to weak image contrast at the resist top portion. Similarly, "resist footing" occurs at negative defocus due to weak image contrast at the resist bottom. Corrections therefore must ensure an appropriate balance of negative and positive defocus intensities so as to provide a healthy image on both sides of the center focus.

Unfortunately, previously utilized methodologies are simply incapable of comprehending and therefore unable to predict the occurrence of such failures modes and therefore cannot address such faults through subsequent OPC correction.

However, as depicted here, the simulated cross section correctly predicts and captures both "missing feature" and "resist footing" failure modes effectively at different defocus conditions.

For a given mask shape, CDSEM images measured at the wafer level, represented by the feature intensity profiles 410 and 415 for the negative and positive focus biases respectively and a numerical simulation of intensity profiles inside the resist (xz plane) are plotted, as represented by the simulated cross sections 425 (positive bias) and 420 (negative bias).

Fabrication failures at negative and positive defocus show distinctive signatures such as resist T-topping as depicted at the feature intensity profile 415 at far positive focus step, and footing as depicted at the right feature intensity profile at far negative focus step, each of which can be induced by intensity at the top and bottom locations respectively through defocus.

As shown here, contour critical dimension (CD) would meet target critical dimension (CD) for both cases and they look similar on focus, however, their respective Bossung plots are very different. Depending on where the center focus of process resides, such focus-shifted structures may fail at negative defocus or positive defocus, which creates yield issues.

According to one embodiment, a silicon wafer is exposed, developed, and etched, so as to realize the pattern of the mask on the wafer, which is then brought into the laboratory for analysis. For instance, measurements are taken from the wafer via a Scanning Electron Microscope resulting in the representative (actual SEM images are not shown) feature intensity profiles 410 and 415 as shown here.

By intentionally creating a focus bias it is possible to observe when the scanner is operating at 0 focus (fO) and what those patterns look like at zero focus. Rather than mimicking an actual manufacturing process where some small variations are known to occur within the process window, the exposure is instead induced to be zero focused such that the resulting patterns may be observed, measured, and then from that measurement data, predictions of the failure modes may be rendered as depicted by the simulated cross sections 420 and 425 showing the T-topping and resist footing failure modes.

Once the failure is understood from the observed wafer and the measurement data, it is then possible to correlate the failure to the corresponding areas of the OPC model and then render OPC model corrections, such as contour adjustments, so as to provide a new OPC corrected mask, from which new silicon wafers may be exposed without the defects due to the accommodation for a larger process variation.

The OPC model is correlated to the prediction from the simulations. A semi-physical model is derived from the mask, the predicted defects are correlated to feature sites within the mask, those locations are then OPC corrected, and then a new mask is fabricated that embodies the corrections to accommodate the predicted failure modes by permitting for a greater process variation window due to the features of the mask being center focus aligned as described in greater detail below at Figure 5 (coarse center alignment) and Figure 6 (fine center alignment).

According to one embodiment, calibration is performed based on measurements taken from SEM images of the mask patterns at different focus depths, for instance, focus depths ranging from an extreme negative focal edge through less extreme negative focal stops, through fO and then through positively biased focal stops and ultimately through, by way of example only, the extreme positive focal edge.

As the focus depth is changed from negative to positive, the center feature depicted at

Figure 3, element 315, will become smaller and smaller within the actual SEM images of the exposed silicon wafer, until ultimately disappearing and resulting in a missing center feature 310 of Figure 3 at the most extreme positive focus steps.

The simulated cross sections 420 and 425 shown here represent the predicted failure mode of that center feature as output by the optical model within a simulated cross section of the resist. Consequently, it is known that at the extreme negative focal edge, there will be a very dark region in the middle representing a feature through the resist (as depicted at the top portion of the positive feature intensity profile 415), as desired, whereas the feature becomes less pronounced and ultimately disappears as the focal steps progress from negative to positive, ultimately disappearing entirely at far positive focus steps (as depicted at the bottom portion of the positive feature intensity profile 415).

From the intensity profiles created by the purposefully varying focus depths, it is then possible to correlate the failure mode to the predicted intensity what that failure is expected to occur, such as the missing feature at the top of the resist when exposed at the extreme positive focal edge or the resist footing which results at the extreme negative focal edge.

By correlating the SEM image measurements indicating the failure modes with specified focal depths with the intensities at which those failures occur at two different depths, including the top portion of the resist and the bottom portion of the resist as depicted here, it is then possible to combine the two calibrated intensity metrics with the simulated cross sections for the top (cross section of 420) and bottom (cross section of 425) portions of the resist to find the failures at the positive focus extremities and the failures at the negative focus extremities and thus predict where those failures will occur. Stated differently, with the two calibrated intensity metrics it is possible to predict which features of the mask will fail and at what location and at what focal depths those features will fail. For instance, with these metrics, it is possible to know at what focal depths the features are no longer acceptable, and such data may then be utilized to improve the OPC correction by center aligning the various features (e.g., by left or right positive or negatively biasing those features to center) such that the scanner may operate with a greater permissible range of variation so as to improve yields and reduce costs of manufacture.

With such metrics, it can be understood where the acceptable region of overlap resides (e.g., the common depth of focus for all features) as well as how large that region of overlap is. By then center aligning the features, the region of overlap may be expanded to permit for greater process variation.

Figure 5 depicts an OPC correction scheme 500 utilizing new metrics in accordance with described embodiments.

In particular, there is depicted the original feature placement 505 on the left, with respective features 550 and 555. As shown here, new metrics enable designing masks with matched center focus for all features on the mask, maximizing the process window. For instance, according to certain embodiments, two components of OPC correction include (i) the placement of negative Sub -Re solution Assisting Features (SRAFs) to perform coarse shifting of the center focus as depicted here in which the focus elements 510 and 515 correspond to features which are not aligned to center as represented by element 530. The OPC correction is then followed by (ii) fine versus jagged correction, by applying a sawtooth manipulation to perform a fine shift of the center focus as described in greater detail below at Figure 6.

For the coarse shifting, negative Sub-Resolution Assisting Features (SRAF) are added to shift the center focus in a positive direction, thus providing the coarse or gross alignment of the features to the center.

The feature placement 550 on the left is offset from the feature placement 555 and therefore, feature placement 555 is shifted favorably towards the positive relative to feature placement 550.

By determining where the left and right (negative and positive) focus extremities reside for any given mask, the center of focus may then be derived and the feature placements 505 may then be shifted so as to better align to center. By aligning the features to the center point, the area of overlapping focus depth is thus increased providing for a much greater process variation.

With such information, the patterns as defined by the mask are then modified on the mask itself in such a way as to better align the feature placements 505 to center such that they are strongest or most intense at that center focal point, while permitting positive or negative focus variation to occur to a greater extent while still attaining the desired and specified features at the correct locations of the resulting patterned silicon wafer as defined by the modified mask.

Stated differently, having determined the prediction of where the failures will occur for the various features and by knowing where the left and right (negative and positive) acceptable focus extremities reside, OPC correction of the mask may be applied to shift the features as defined by the mask, resulting in a new mask to be fabricated pursuant to the OPC corrected feature positions which are now aligned to center.

The two curves for feature placements 510 and 515 represent that the features and how they will appear on the patterned wafer in terms of their critical dimension (CD). The range of acceptable focus depth for each feature remains the same but is shifted left or right (e.g., biased negative or positive) so as to be aligned to the center of focus, with certain individual features requiring left shift (negative biasing) and other individual features requiring right shift (positive biasing) and other features requiring no adjustment or only fine adjustment left or right.

Because individual features may be moved left to right via the OPC correction process, it is possible to align all of the features to the same center of focus. For instance, the non-aligned features 120 of Figure 1 depicted at the top row have a risk of failure in the positive extremities. Consequently, the first row may be moved so as to be heavier on the right, effectively aligning itself with the second row and the third row. Therefore, if a particular feature is predicted to have a right bias failure mode, then such a feature will be shifted to the left and visa versa so as to maximize or increase the total overlap of all the features.

By patterning negative SRAF(s) defining exposed portions in the mask pattern to the right of the original feature placement 550, the feature 550 which is left or negatively biased is shifted right toward the center by a large value, thus providing a coarse or large alignment.

Because the negative SRAF(s) are physically defined within the mask they induce a shift to the focus toward the positive bias for the original feature placement of feature 550, however, because the negative SRAF physically defined within the mask are sufficiently small, they do not print onto or pattern the wafer. In such a way, the features may be biased left or right by defining very small negative SRAF in the mask to the left or right of the feature in question without actually creating unwanted patterning or unwanted features within the silicon wafer itself.

Though the negative SRAF(s) defined with the mask are very small, they nevertheless shift the focus toward center by a large amount, resulting in the coarse adjustment toward center.

Finer adjustments are also utilized as discussed in greater detail below with respect to Figure 6

Figure 6 depicts an OPC correction scheme 600 providing fine control of the center focus shift in accordance with described embodiments.

As shown here, iterative sawtooth fine adjustments 635 (e.g., via modifications to the mask) are performed using sawtooth patterns 650, 655, and 660.

Fine control of center focus shift is attained by modulating the sawtooth providing a smoothness of correction for the mask. As the mask becomes smoother, the center focus shifts towards negative focus. Contrary to that, as the sawtooth in the mask becomes more pronounced, the center focus shifts towards positive focus effectively providing an ability to control placement of the center focus. Correction is modified while monitoring center focus with continuous feedback from weak image metrics as discussed above, thus achieving matched center focus for the different features, where Bossung curves corresponding to 610, 620, and 615 show how center focus can be fine-tuned towards desired direction.

While the large adjustment process via the negative SRAF(s) as discussed with respect to Figure 5 is inducing larger focus shifts to align the features to center the sawtooth formations may be utilized to smoothly fine tune the features to the center of focus as depicted here.

Unlike the coarse adjustment process where negative SRAF(s) are defined in the mask, effectively using features of opposite polarity within the mask to bias features left or right toward center focus alignment, the fine tuning process changes the shape of the features (e.g., by producing sawtooth shapes or other contour adjustments to the features) so as to bias the feature alignment toward center by small amounts without altering the critical dimension of such features within the final patterning of the silicon.

By exaggerating the sawtooth features within the newly defined mask, the features in question will be smoothly shifted or biased in the relevant direction so as to improve alignment to focus of all features. A series of test masks may further be utilized to test or validate the adjustments applied via the OPC correction process until the desired alignment is attained at which point a final new mask may then be fabricated for use in production of the final silicon wafer. Therefore, even for the strictest of tolerances or features which correspond to the most problematic yield issues, the coarse and fine tuning adjustments may be iteratively applied through a series of OPC corrected test masks until the requisite yield and calibration of feature placement to center is attained, at which point the final mask may be produced and used for production purposes.

Where intervening test masks are utilized, SEM imagery may be captured and measurements take to re-calibrate in the manner described above with regard to an original mask, so as to iteratively improve upon the alignment of features until satisfactory yields are attained through a larger accommodation for process vacation of the newly fabricated OPC corrected mask.

Figure 7 is a schematic of a computer system 700 in accordance with described embodiments. The computer system 700 (also referred to as the electronic system 700) as depicted can embody means for implementing failure prediction and process window optimization in chromeless phase lithography, according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure. The computer system 700 may be a mobile device such as a net-book computer. The computer system 700 may be a mobile device such as a wireless smartphone or tablet. The computer system 700 may be a desktop computer. The computer system 700 may be a hand-held reader. The computer system 700 may be a server system. The computer system 700 may be a supercomputer or high-performance computing system.

In accordance with one embodiment, the electronic system 700 is a computer system that includes a system bus 720 to electrically couple the various components of the electronic system 700. The system bus 720 is a single bus or any combination of busses according to various embodiments. The electronic system 700 includes a voltage source 730 that provides power to the integrated circuit 710. In some embodiments, the voltage source 730 supplies current to the integrated circuit 710 through the system bus 720.

Such an integrated circuit 710 is electrically coupled to the system bus 720 and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit 710 includes a processor 712 that can be of any type. As used herein, the processor 712 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor 712 includes, or is coupled with, electrical devices having gradient encapsulant protection, as disclosed herein.

In accordance with one embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit 710 are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit 714 for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. In an embodiment, the integrated circuit 710 includes on- die memory 716 such as static random-access memory (SRAM). In an embodiment, the integrated circuit 710 includes embedded on-die memory 716 such as embedded dynamic random-access memory (eDRAM).

In accordance with one embodiment, the integrated circuit 710 is complemented with a subsequent integrated circuit 711. Useful embodiments include a dual processor 713 and a dual communications circuit 715 and dual on-die memory 717 such as SRAM. In accordance with one embodiment, the dual integrated circuit 710 includes embedded on-die memory 717 such as eDRAM.

In one embodiment, the electronic system 700 also includes an external memory 740 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 742 in the form of RAM, one or more hard drives 744, and/or one or more drives that handle removable media 746, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory 740 may also be embedded memory 748 such as the first die in a die stack, according to an embodiment.

In accordance with one embodiment, the electronic system 700 also includes a display device 750 and an audio output 760. In one embodiment, the electronic system 700 includes an input device 770 such as a controller that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 700. In an embodiment, an input device 770 is a camera. In an embodiment, an input device 770 is a digital sound recorder. In an

embodiment, an input device 770 is a camera and a digital sound recorder.

As shown herein, the integrated circuit 710 can be implemented in a number of different embodiments, including means for implementing failure prediction and process window optimization in chromeless phase lithography for a semiconductor substrate package, according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a package substrate or a semiconductor package having therein means for implementing failure prediction and process window optimization in chromeless phase lithography, according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art- recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed package substrates and semiconductor packages having means for implementing failure prediction and process window optimization in chromeless phase lithography for semiconductor substrate package embodiments and their equivalents. A foundation substrate 798 may be included, as represented by the dashed line of Figure 7. Passive devices 799 may also be included, as is also depicted in Figure 7.

Figure 8 illustrates a semiconductor device 800 (or an interposer) that includes one or more described embodiments. The interposer 800 is an intervening substrate used to bridge a first substrate 802 to a second substrate 804. The first substrate 802 may be, for instance, an integrated circuit die. The second substrate 804 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 800 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 800 may couple an integrated circuit die to a ball grid array (BGA) 806 that can subsequently be coupled to the second substrate 804. In some embodiments, the first and second substrates 802/804 are attached to opposing sides of the interposer 800. In other embodiments, the first and second substrates 802/804 are attached to the same side of the interposer 800. And in further embodiments, three or more substrates are interconnected by way of the interposer 800.

The interposer 800 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further

implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 808 and vias 810, including but not limited to through-silicon vias (TSVs) 812. The interposer 800 may further include embedded devices 814, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 800. In accordance with described embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 800.

Figure 9 illustrates a computing device 900 in accordance with one implementation of the invention. The computing device 900 houses a board 902. The board 902 may include a number of components, including but not limited to a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations the at least one communication chip 906 is also physically and electrically coupled to the board 902. In further implementations, the communication chip 906 is part of the processor 904.

Depending on its applications, computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 906 enables wireless communications for the transfer of data to and from the computing device 900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 900 may include a plurality of communication chips 906. For instance, a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.

In further implementations, another component housed within the computing device

900 may contain an integrated circuit die that includes one or more devices, such as MOS- FET transistors built in accordance with implementations of the invention.

In various implementations, the computing device 900 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 900 may be any other electronic device that processes data.

Figure 10 is a flow diagram illustrating a method 1000 for implementing failure prediction and process window optimization in chromeless phase lithography in accordance with described embodiments. Some of the blocks and/or operations listed below are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from method 1000 may be utilized in a variety of combinations.

At block 1005, the method 1000 for predicting a failure mode in a negative and positive focus operates via the following processes.

At block 1010, the method includes creating a test mask via a lithography process, wherein the test mask defines a plurality of features. At block 1015, the method includes patterning a physical silicon wafer using the test mask at each of a plurality of varied focus steps, wherein the patterning exposes the plurality of features as defined by the test mask into the physical silicon wafer at each of the plurality of varied focus steps.

At block 1020, the method includes capturing Scanning Electron Microscope (SEM) images of the plurality of features exposed into the physical silicon wafer.

At block 1025, the method includes identifying from the SEM images any location where one or more of the plurality of features fails to expose correctly from the test mask at any one or more of the plurality of varied focus steps.

At block 1030, the method includes creating a predictor for each failure mode by correlating the location at which the respective feature failed to expose correctly into the physical silicon wafer and the focus step at which the feature failed to correctly expose into the physical silicon wafer.

Figure 11 is a flow diagram illustrating another method 1100 for implementing failure prediction and process window optimization in chromeless phase lithography in accordance with described embodiments. Some of the blocks and/or operations listed below are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from method 1100 may be utilized in a variety of combinations.

At block 1105, the method 1100 for performing Optical Proximity Correction (OPC) to align features of a mask to a center of focus operates via the following processes.

At block 1110, the method includes receiving a predictor as input for each of features corresponding to a failure modes within a test mask, wherein the predictor identifies (i) a location at which the respective feature failed to expose correctly into a physical silicon wafer exposed via the test mask, (ii) a focus step at which the respective feature failed to correctly expose into the physical silicon wafer, and (iii) whether the failure occurred within a top portion of a photoresist of the physical silicon wafer or within a bottom portion of the photoresist.

At block 1115, the method includes identifying a center of focus for each of the plurality of features having failed to expose correctly into the physical silicon wafer.

At block 1120, the method includes adjusting the features toward the identified center of focus. Such an adjustment is performed by the following sub-operations:

At block 1125, the method includes positively biasing features associated with a failure mode within a positive focal depth range to move the respective features toward the identified center of focus.

At block 1130, the method includes negatively biasing features associated with a failure mode within a negative focal depth range to move the respective features toward the identified center of focus.

While the subject matter disclosed herein has been described by way of example and in terms of the specific embodiments, it is to be understood that the claimed embodiments are not limited to the explicitly enumerated embodiments disclosed. To the contrary, the disclosure is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the disclosed subject matter is therefore to be determined in reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

It is therefore in accordance with the described embodiments, that:

According to one embodiment there is a method for implementing failure prediction and process window optimization in chromeless phase lithography. For instance, according to one embodiment, there is a method for predicting a failure mode in a negative and positive focus, in which the method includes: patterning a wafer (e.g., physical silicon wafer) using the test mask at each of a plurality of varied focus steps, wherein the patterning exposes a plurality of features of the test mask as defined by the test mask into the wafer at each of the plurality of varied focus steps; capturing images (e.g., Scanning Electron Microscope (SEM) images) of the plurality of features exposed into the wafer; identifying from the images any location where one or more of the plurality of features fails to expose correctly from the test mask at any one or more of the plurality of varied focus steps; and creating a predictor for each failure mode by correlating the location at which the respective feature failed to expose correctly into the wafer and the focus step at which the feature failed to correctly expose into the wafer.

According to another embodiment of the method, patterning the wafer using the test mask at each of the plurality of varied focus steps includes patterning the wafer using the test mask at each of the plurality of focus steps ranging from a positive depth of focus to a negative depth of focus. According to another embodiment of the method, creating the predictor further includes: creating the predictor to predict, via simulation, predicted failure modes for each of the plurality of features and the focus step at the positive focus or negative focus at which the feature is predicted to fail.

According to another embodiment of the method, creating the predictor further includes: creating the predictor to further predict, via simulation, whether the failure is predicted to occur within the top portion of a photoresist or within a bottom portion of the photoresist.

According to another embodiment of the method, creating the predictor via the simulation includes predicting at what location the predicted failure mode is to occur and whether the failure is predicted to occur within the top portion of a photoresist or within a bottom portion of the photoresist and at which of the varied focus steps the failure is predicted to occur based on intensity of photolithographic exposure of the failed feature at each of the varied focus steps.

According to another embodiment of the method, creating the predictor further includes: creating a feature intensity profile from the captured images (e.g., SEM images) of one of the plurality features having failed to expose correctly into the wafer, at any one of the plurality of varied focus steps in which the failure mode for the feature having failed to expose correctly into the wafer is identified within either the top portion of a photoresist or within a bottom portion of the photoresist or at both the top and bottom portions of the photoresist at one or more of the varied focus steps within either the positive focus or within the negative focus; and creating a predictor for the failure mode of the feature having failed to expose correctly into the wafer by correlating (i) the location at which the respective feature failed to expose correctly into the wafer, (ii) the focus step at which the feature failed to correctly expose into the wafer, and (iii) whether the failure is predicted to occur within the top portion of the photoresist or within the bottom portion of the photoresist, or within both the top and the bottom portions of the photoresist.

According to another embodiment of the method, creating the predictor for each failure mode includes one or more of: predicting, via simulation, a T-topping type failure mode within a top portion of a photoresist; predicting, via simulation, a resist footing type failure mode within a bottom portion of the photoresist; predicting, via simulation, scumming or residue at a top surface of a wafer after photolithographic exposure, development, and etch processing; and predicting, via simulation, a "missing feature" type failure mode within the photoresist. According to another embodiment, the method further includes: outputting the predictor for each failure mode to an Optical Proximity Correction (OPC) base model;

performing OPC correction based on the predictors received at the OPC model to generate a new semi-physical model; and fabricating a new photolithographic mask from the new semi- physical model.

According to another embodiment, the method further includes: identifying a center of focus for each of the plurality of features having failed to expose correctly into the wafer; positively biasing features associated with a failure mode within one or more of the varied focus steps within a positive focal depth range to move the respective features toward the identified center of focus; and negatively biasing features associated with a failure mode within one or more of the varied focus steps within a positive focal depth range to move the respective features toward the identified center of focus.

According to another embodiment, the method further includes: identifying a center of focus for each of the plurality of features having failed to expose correctly into the wafer; fine tuning features associated with a failure mode within one or more of the varied focus steps within a positive focal depth range or a negative focal depth range to fine tune the respective features toward the identified center of focus by adjusting a contour of the respective feature to form a sawtooth pattern within the respective feature.

According to another embodiment of the method, adjusting mask shape at the respective feature to form the sawtooth pattern further includes: applying adjustments to the mask shape of the respective feature forming the sawtooth pattern; and evaluating, via simulation, whether the respective feature moves in the correct direction toward the center of focus based on the predictor; and iteratively making different adjustments to mask shape and re-evaluating, via the simulation, whether the respective feature moves in the correct direction toward the center of focus based on the predictor until the respective feature is correctly biased toward the center of focus within the simulation according to the predictor for the respective feature.

According to another embodiment, the method further includes: identifying a center of focus for each of the plurality of features having failed to expose correctly into the wafer; performing coarse adjustment of features associated with a failure mode within one or more of the varied focus steps within a positive focal depth range to shift the respective features toward the identified center of focus by introducing negative Sub-Resolution Assisting Features (SRAFs) to positively bias the respective feature in the direction of the center of focus; in which the negative Sub-Resolution Assisting Features (SRAFs) in the new mask is of a size which permits an insufficient amount of light through the mask during a photolithographic exposure to pattern any feature into a photoresist exposed through the new mask.

According to another embodiment, the method further includes: determining a center of focus for each of the plurality of features having failed to expose correctly into the wafer by identifying at which of the varied focus steps within a positive focus depth range and a negative focus depth range the failure occurs; and identifying a range of focus steps through the positive focus depth range and the negative focus depth range where the feature exposes correctly; and selecting a position in the center of the range of focus steps within which the feature exposed correctly as the center of focus for that respective feature.

According to yet another embodiment, there is a method for performing Optical Proximity Correction (OPC) to align features of a mask to a center of focus, in which the method includes: receiving a predictor as input for each of features corresponding to a failure modes within a test mask, in which the predictor identifies (i) a location at which the respective feature failed to expose correctly into a wafer (e.g., physical silicon wafer) exposed via the test mask, (ii) a focus step at which the respective feature failed to correctly expose into the wafer, and (iii) whether the failure occurred within a top portion of a photoresist of the wafer or within a bottom portion of the photoresist; identifying a center of focus for each of the plurality of features having failed to expose correctly into the wafer; and adjusting the features toward the identified center of focus by (i) positively biasing features associated with a failure mode within a positive focal depth range to move the respective features toward the identified center of focus and by further (ii) negatively biasing features associated with a failure mode within a negative focal depth range to move the respective features toward the identified center of focus.

According to another embodiment of the method, adjusting the features toward the identified center of focus further includes: fine tuning features associated with a failure mode within the positive focal depth range or within the negative focal depth range to shift the respective features toward the identified center of focus by adjusting a mask shape of a sawtooth pattern in the respective feature.

According to another embodiment of the method, adjusting mask shape of the respective feature by forming the sawtooth pattern within the respective feature further includes: applying iterative correction to the mask shape of the sawtooth pattern in the respective feature; and evaluating, via simulation, whether the respective feature moves in the correct direction toward the center of focus based on the predictor; and iteratively making different adjustments to the respective feature and re-evaluating, via the simulation, whether the respective feature moves in the correct direction toward the center of focus based on the predictor until the respective feature is correctly biased toward the center of focus within the simulation according to the predictor for the respective feature.

According to another embodiment of the method, adjusting the features toward the identified center of focus further includes: performing coarse adjustment of features associated with a failure mode within a positive focal depth range to shift the respective features toward the identified center of focus by introducing negative Sub-Resolution Assisting Features (SRAFs) to positively bias the respective feature in the direction of the center of focus; and in which the negative Sub-Resolution Assisting Features (SRAFs) in the new mask is of a size which permits an insufficient amount of light through the mask during a photolithographic exposure to pattern any feature into a photoresist exposed through the new mask.

According to another embodiment of the method, identifying the center of focus for each of the plurality of features includes identifying at which of a plurality of varied focus steps within a positive focus depth range and a negative focus depth range a failure occurred for a respective feature; identifying a range of focus steps through the positive focus depth range and the negative focus depth range where the feature exposes correctly; and selecting a position in the center of the range of focus steps within which the feature exposed correctly as the center of focus for that respective feature.

According to another embodiment, the method further includes: creating a semi- physical model of the test mask using physical parameters of the lithography process used to create the test mask by capturing optical intensity values from a light source shone through the test mask, in which the semi-physical model specifies the optical intensity values representing the plurality of features of the test mask as captured from the light source when shone through the test mask; in which the semi-physical model specifies optical intensity values representing the plurality of features of the mask; in which adjusting the features toward the identified center of focus includes performing the Optical Proximity Correction (OPC) to align features of a mask to a center of focus within a simulation of the test mask derived from the semi-physical model; and fabricating a new photolithographic mask from the OPC corrected semi-physical model.

According to yet another embodiment, there is a system for predicting a failure mode in a negative and positive focus, in which the system includes: a mask created via a lithography process, in which the test mask defines a plurality of features; a wafer (e.g., physical silicon wafer) having been patterned using the test mask at each of a plurality of varied focus steps, in which the patterning of wafer exposes the plurality of features as defined by the test mask into the wafer at each of the plurality of varied focus steps; storage to capture images (e.g., Scanning Electron Microscope (SEM) images) of the plurality of features exposed into the wafer; an analysis unit to identify from the SEM images any location where one or more of the plurality of features has failed to expose correctly from the test mask at any one or more of the plurality of varied focus steps; and the analysis unit to create a predictor for each failure mode by correlating the location at which the respective feature failed to expose correctly into the wafer and the focus step at which the feature failed to correctly expose into the wafer.

According to another embodiment of the system, the wafer is patterned using the test mask at each of the plurality of focus steps ranging from a positive focus to a negative focus.

According to another embodiment of the system, the predictor is to predict, via simulation, predicted failure modes for each of the plurality of features and the focus step at the positive focus or negative focus at which the feature is predicted to fail and whether the failure is predicted to occur within the top portion of a photoresist or within a bottom portion of the photoresist; and in which the predictor is to suggest mask shape adjustments to the features and negative Sub-Resolution Assisting Features (SRAFs), in which the output mask shape adjustments are to be applied to a new semi-physical model via Optical Proximity Correction (OPC); in which the analysis unit is to perform OPC correction on the features where the negative SRAFs are applied; and in which the system further includes a new photolithographic mask fabricated from the new semi-physical model.

According to a particular embodiment, there is non-transitory computer readable storage media having instructions stored thereupon that, when executed by a processor, the instructions cause the processor to perform operations for predicting a failure mode in a negative and positive focus, in which the operations include: patterning a wafer (e.g., a physical silicon wafer) using a test mask at each of a plurality of varied focus steps, in which the patterning exposes a plurality of features of the test mask into the wafer at each of the plurality of varied focus steps; capturing images (e.g., Scanning Electron Microscope (SEM) images) of the plurality of features exposed into the wafer; identifying from the images any location where one or more of the plurality of features fails to expose correctly from the test mask at any one or more of the plurality of varied focus steps; and creating a predictor for each failure mode by correlating the location at which the respective feature failed to expose correctly into the wafer and the focus step at which the feature failed to correctly expose into the wafer.

According to another embodiment of the non-transitory computer readable storage media, patterning the wafer using the test mask at each of the plurality of varied focus steps includes patterning the wafer using the test mask at each of the plurality of focus steps ranging from a positive focus to a negative focus.

According to another embodiment of the non-transitory computer readable storage media, the instructions cause the processor to perform operations which further include creating the predictor to predict, via simulation, predicted failure modes for each of the plurality of features and the focus step at the positive focus or negative focus at which the feature is predicted to fail and whether the failure is predicted to occur within the top portion of a photoresist or within a bottom portion of the photoresist.

Claims

CLAIMS What is claimed is:

1. A method for predicting a failure mode in a negative and a positive focus, wherein the method comprises:

patterning a wafer using a test mask at each of a plurality of varied focus steps, wherein the patterning exposes a plurality of features of the test mask into the wafer at each of the plurality of varied focus steps;

capturing images of the plurality of features exposed into the wafer;

identifying from the images any location where one or more of the plurality of features fails to expose correctly from the test mask at any one or more of the plurality of varied focus steps; and

creating a predictor for each failure mode by correlating the location at which the respective feature failed to expose correctly into the wafer and the focus step at which the feature failed to correctly expose into the wafer.

2. The method of claim 1, wherein patterning the wafer using the test mask at each of the plurality of varied focus steps comprises patterning the wafer using the test mask at each of the plurality of focus steps ranging from a positive focus to a negative focus.

3. The method of claim 2, wherein creating the predictor further comprises:

creating the predictor to predict, via simulation, predicted failure modes for each of the plurality of features and the focus step at the positive focus or negative focus at which the feature is predicted to fail.

4. The method of claim 3, wherein creating the predictor further comprises:

creating the predictor to further predict, via simulation, whether the failure is predicted to occur within the top portion of a photoresist or within a bottom portion of the photoresist.

5. The method of claim 3, wherein creating the predictor via the simulation comprises: predicting at what location the predicted failure mode is to occur and whether the failure is predicted to occur within the top portion of a photoresist or within a bottom portion of the photoresist and at which of the varied focus steps the failure is predicted to occur based on intensity of photolithographic exposure of the failed feature at each of the varied focus steps.

6. The method of claim 2, wherein creating the predictor further comprises:

creating a feature intensity profile from the simulated optical intensity from semi- physical model of one of the plurality features having failed to expose correctly into the wafer, at any one of the plurality of varied focus steps,

wherein the failure mode for the feature having failed to expose correctly into the wafer is identified within either the top portion of a photoresist or within a bottom portion of the photoresist or at both the top and bottom portions of the photoresist at one or more of the varied focus steps within either the positive focus or within the negative focus; and

creating a predictor for the failure mode of the feature having failed to expose correctly into the wafer by correlating (i) the location at which the respective feature failed to expose correctly into the wafer, (ii) the focus step at which the feature failed to correctly expose into the wafer, and (iii) whether the failure is predicted to occur within the top portion of the photoresist or within the bottom portion of the photoresist, or within both the top and the bottom portions of the photoresist.

7. The method of claim 1, wherein creating the predictor for each failure mode comprises one or more of:

predicting, via simulation, a T-topping type failure mode within a top portion of a photoresist;

predicting, via simulation, a resist footing type failure mode within a bottom portion of the photoresist;

predicting, via simulation, scumming or residue at a top surface of a wafer after photolithographic exposure, development, and etch processing; and

predicting, via simulation, a "missing feature" type failure mode within the photoresist.

8. The method of claim 1, further comprising:

outputting the predictor for each failure mode to an Optical Proximity Correction (OPC) base model;

performing OPC correction based on the predictors received at the OPC model to generate new mask shapes that comply with the criteria from the predictors; and fabricating a new photolithographic mask with the new mask shapes that avoid perceived failures as predicted by the predictor.

9. The method of claim 1, further comprising:

identifying a center of focus for each of the plurality of features having failed to expose correctly into the wafer;

positively biasing features associated with a failure mode within one or more of the varied focus steps within a positive focal depth range to move the respective features toward the identified center of focus; and

negatively biasing features associated with a failure mode within one or more of the varied focus steps within a negative focal depth range to move the respective features toward the identified center of focus.

10. The method of claim 1, further comprising:

identifying a center of focus for each of the plurality of features having failed to expose correctly into the wafer; and

fine tuning features associated with a failure mode within one or more of the varied focus steps within a positive focal depth range or a negative focal depth range toward the identified center of focus by adjusting a shape of the mask to form a sawtooth pattern.

11. The method of claim 10, wherein adjusting shape of the mask to form the sawtooth pattern further comprises:

applying iterative algorithms to adjust the depth and shape of the sawtooth for respective feature; and

evaluating, via simulation, whether the respective feature moves in the correct direction toward the center of focus based on the predictor; and

iteratively making different adjustments to the mask shape of the respective feature and re-evaluating, via the simulation, whether the respective feature moves in the correct direction toward the center of focus based on the predictor until the respective feature is correctly biased toward the center of focus within the simulation according to the predictor for the respective feature.

12. The method of claim 1, further comprising:

performing coarse adjustment of features associated with a failure mode within one or more of the varied focus steps within a positive focal depth range to shift the respective features toward the identified center of focus by introducing negative Sub-Resolution Assisting Features (SRAFs) to positively bias the respective feature in the direction of the center of focus.

13. The method of claim 1, further comprising:

performing coarse adjustment of features associated with a failure mode within one or more of the varied focus steps within a positive focal depth range to shift the respective features toward the identified center of focus by forming a negative SRAF(s) within a new mask, wherein the negative SRAF(s) in the new mask positively biases the respective feature toward the center of focus within a simulation according to the predictor for the respective feature; and

wherein the negative SRAF(s) in the new mask is of a size which permits an insufficient amount of light through the mask during a photolithographic exposure to pattern any additional feature into a photoresist exposed through the new mask.

14. The method of claim 1, further comprising:

determining a center of focus for each of the plurality of features having failed to expose correctly into the wafer by identifying at which of the varied focus steps within a positive focus depth range and a negative focus depth range the failure occurs; and identifying a range of focus steps through the positive focus depth range and the negative focus depth range where the feature exposes correctly; and

selecting a position in the center of the range of focus steps within which the feature exposed correctly as the center of focus for that respective feature.

15. A method for performing Optical Proximity Correction (OPC) to align features of a mask to a center of focus, wherein the method comprises:

receiving a predictor as input for each of features corresponding to a failure modes within a test mask, wherein the predictor identifies (i) a location at which the respective feature failed to expose correctly into a wafer exposed via the test mask, (ii) a focus step at which the respective feature failed to correctly expose into the wafer, and (iii) whether the failure occurred within a top portion of a photoresist of the wafer or within a bottom portion of the photoresist;

adjusting the features toward the identified center of focus by (i) positively biasing features associated with a failure mode within a positive focal depth range to move the respective features toward the identified center of focus and by further (ii) negatively biasing features associated with a failure mode within a negative focal depth range to move the respective features toward the identified center of focus.

16. The method of claim 15, wherein adjusting the features toward the identified center of focus further comprises:

fine tuning features associated with a failure mode within the positive focal depth range or within the negative focal depth range to shift the respective features toward the identified center of focus by adjusting a mask shape of a sawtooth pattern in the respective feature.

17. The method of claim 16, wherein adjusting a contour of the respective feature by forming the sawtooth pattern within the respective feature further comprises:

applying iterative correction to the mask shape of the sawtooth pattern in the respective feature; and

iteratively making different adjustments to the respective feature and re-evaluating, via the simulation, whether the respective feature moves in the correct direction toward the center of focus based on the predictor until the respective feature is correctly biased toward the center of focus within the simulation according to the predictor for the respective feature.

18. The method of claim 15, wherein adjusting the features toward the identified center of focus further comprises:

performing coarse adjustment of features associated with a failure mode within a positive focal depth range to shift the respective features toward the identified center of focus by introducing negative Sub-Resolution Assisting Features (SRAFs) to positively bias the respective feature in the direction of the center of focus; and

19. The method of claim 15, wherein identifying the center of focus for each of the plurality of features comprises:

identifying at which of a plurality of varied focus steps within a positive focus depth range and a negative focus depth range a failure occurred for a respective feature;

identifying a range of focus steps through the positive focus depth range and the negative focus depth range where the feature exposes correctly; and

20. The method of claim 15, further comprising:

creating a semi-physical model of the test mask using physical parameters of the lithography process used to create the test mask by capturing optical intensity values from a light source shone through the test mask, wherein the semi-physical model specifies the optical intensity values representing the plurality of features of the test mask as captured from the light source when shone through the test mask;

wherein the semi-physical model specifies optical intensity values representing the plurality of features of the mask;

wherein adjusting the features toward the identified center of focus comprises performing the Optical Proximity Correction (OPC) to align features of a mask to a center of focus within a simulation of the test mask derived from the semi-physical model; and

fabricating a new photolithographic mask from the OPC corrected semi-physical model.

21. A system for predicting a failure mode in a negative and positive focus, wherein the system comprises:

a wafer having been patterned using a test mask at each of a plurality of varied focus steps, wherein the patterning of wafer exposes plurality of features defined by the test mask into the wafer at each of the plurality of varied focus steps;

storage to capture images of the plurality of features exposed into the wafer;

an analysis unit to identify from the images any location where one or more of the plurality of features has failed to expose correctly from the test mask at any one or more of the plurality of varied focus steps; and the analysis unit to create a predictor for each failure mode by correlating the location at which the respective feature failed to expose correctly into the wafer and the focus step at which the feature failed to correctly expose into the wafer.

22. The system of claim 21, wherein the wafer is patterned using the test mask at each of the plurality of focus steps ranging from a positive focus to a negative focus.

23. The system of claim 22:

wherein the predictor is to predict, via simulation, predicted failure modes for each of the plurality of features and the focus step at the positive focus or negative focus at which the feature is predicted to fail and whether the failure is predicted to occur within the top portion of a photoresist or within a bottom portion of the photoresist; and

wherein the analysis unit is to output mask shape adjustments to the features and negative Sub-Resolution Assisting Features (SRAFs) based on the predictor, wherein the output mask shape adjustments are to be applied via Optical Proximity Correction (OPC); wherein the system further comprises a new photolithographic mask fabricated from the new semi-physical model.

24. Non-transitory computer readable storage media having instructions stored thereupon that, when executed by a processor, the instructions cause the processor to perform operations for predicting a failure mode in a negative and positive focus, wherein the operations comprise:

capturing images of the plurality of features exposed into the wafer;

25. The non-transitory computer readable media of claim 24, wherein patterning the wafer using the test mask at each of the plurality of varied focus steps comprises patterning the wafer using the test mask at each of the plurality of focus steps ranging from a positive focus to a negative focus.

26. The non-transitory computer readable media of claim 25, wherein the instructions cause the processor to perform operations further comprising:

creating the predictor to predict, via simulation, predicted failure modes for each of the plurality of features and the focus step at the positive focus or negative focus at which the feature is predicted to fail and whether the failure is predicted to occur within the top portion of a photoresist or within a bottom portion of the photoresist.